DE2842023C2 - - Google Patents

Description

The invention is based on a digital control device DE-OS 25 46 529, at which, however, suddenly changes when the vehicle speed changes the new setpoint is specified. Because the driving speed reacting relatively slowly, there is a risk of Control oscillations after at least some periods Continue to reach the new setpoint. To one To reduce overshoot it is from DE-OS 25 37 415 known to use a controller with PD behavior. At  such a PD or P controller is different Loads and variable play in the actuator linkage the regulated speed after the setting process inaccurate. if an I controller is used, however you get worse comfort.

From JP-OS 33 207/73 is a method for accelerating one Turbine known, wherein in the acceleration phase of the rev a linearly increasing setpoint and the slope of the setpoint when a predetermined one is reached The speed value given by the actual speed is small nere increase to the smooth transition to the target turbine speed enables. When this target speed is reached by the current one Turbine speed, the turbine is braked to the prescribed Maintain speed.

Advantages of the invention

The device according to the invention with the features of the main saying has the compared to the known cruise control Advantage that ver when converting the actual value to one of them different setpoint by changing the controller leading A good transition behavior with improved driving comfort is achieved. There is a jump at the beginning of the control process formal change of the setpoint compared to the actual value and then the target through a time-varying ramp value changed, the ramp with at least two slope values is selected, with an earlier increase in amount in terms of amount is specified. The ramp is changed until the actual value corresponds to the target value corresponding to the driver's request.

By the measures listed in the subclaims are advantageous developments and improvements to facility specified in the main claim possible. Especially ders advantage is the use of a ramp with two different gradients, one in terms of amount initially a larger slope into a smaller one Slope at the end of the ramp, or the Verwen of a ramp with a continuously decreasing Pitch. This will make an even smoother transition achieved the new driving speed.

An optimal realization can be achieved by using a microcomputer, preferably a 1-chip micro calculator. The digital control device is based on this Way very simple and inexpensive with small Bauvo lumen to realize.  

drawing

Two embodiments of the invention are in the drawing shown and in the description below explained in more detail. It shows

Fig. 1 shows a circuit configuration of the first embodiment even with a control loop,

Fig. 2 is a diagram for explaining an effected via the control device acceleration operation,

Fig. 3 is a diagram for explaining the process of transferring the vehicle speed to a previously stored target value. The embodiment of FIGS. 1 to 3 with a corresponding description is the subject of the older, according to published patent application 28 31 238.

Fig. 4 is a TIC practical embodiment displays the second game without Ausführungsbei actuator control circuit,

Fig. 5 is a diagram according to FIG. 3 for the second embodiment,

Fig. 6 shows an illustrative diagram of the same operation for the case of a road slope,

Fig. 7 is a circuit even from a guiding direction formed as a pulse control Stellvor,

Fig. 8 is a diagram for explaining the effect of the impulse control shown in Fig. 7 and Fig. 9 is a circuit configuration of an initialization device.

Description of the embodiments

In the embodiment shown in FIG. 1, a terminal 10 , at which there is a positive potential, is connected via a main switch 11 for switching on the voltage supply to five switching devices 12 to 16 which are preferably designed as pushbutton switches. The switches 12 and 13 are ausgebil det as a brake or clutch switch and are closed when the mechanically related ver brake or clutch of the motor vehicle is actuated. Both switches 12, 13 are each connected to an input of an OR gate 17 , the output of which is connected both to an input of a further OR gate 18 and to the reset input R of a flip-flop 19 . The switches 14 to 16 are the command circuit for the control device. The first switch 14 is switched as a recovery switch, ie when it is actuated, a previously stored target driving speed is resumed. The second switch 15 is switched as a delay switch and the third switch 16 is switched as an acceleration switch, ie, a deceleration or acceleration process takes place during actuation of one of these switches. In addition, these switches 15, 16 serve for a brief actuation of the storage and maintenance of the current driving speed.

The switches 14 to 16 are each connected to an input of an OR gate 20 as well as to three AND gates 21 to 23 , where an AND gate 21 to 23 is assigned to each switch 14 to 16 . The outputs of the three AND gates 21 to 23 are connected via an OR gate 24 both to the set input S of the flip-flop 19 and to a further input of the OR gate 18 . The main switch 11 is connected via an inverter 25 to a further input of the OR gate 17 and also directly to a further input of the OR gate 18 , the output of which is connected to a terminal 26 . This terminal 26 is connected in a manner not shown to the reset inputs of all memory devices (e.g. flip-flops and counters) with the exception of the actual and setpoint memory, which will be described in more detail later.

The outputs of the AND gates 22, 23 are also connected via an OR gate 27 to an input of an OR gate 28 , the output of which is connected to the set input S of a flip-flop 29 and the second input of which is connected to the output of the AND gate 21 and the set input of a further flip-flop 30 is connected. The output from the OR gate 27 is connected via a delay element 31 acting on the trailing edge of a signal and via an OR gate 32 connected in series to the reset input R of the flip-flop 29 . Furthermore, the output of the OR gate 27 is connected via an inverter 33 to an input of an AND gate 34 , the second input of which is connected to the output of the flip-flop 29 and the third input of which is connected to a terminal 35 to which a clock frequency f 1 is created. Finally, the output of the OR gate 27 is still connected to an input of an AND gate 36 , the second input of which is connected to a terminal 37 carrying a second clock frequency f 2 . The output of the flip-flop 30 is connected to an input of an AND gate 38 , the second input of which is connected to a terminal 39 carrying a third clock frequency f 3 .

The outputs of the AND gates 34, 36, 38 are connected via an OR gate 40 to the clock input C of a digital counter 41 used as an auxiliary setpoint storage device. The output of the OR gate 24 is via a z. B. out as a monostable switching stage formed timer 42 for generating a short setting pulse connected to the set input S of the counter 41 . The output of the AND gate 23 is connected via an OR gate 43 to the count direction input U / D (up / down) of the counter 41 .

The outputs of the AND gates 22, 23 are also connected via a NOR gate 44 to the trigger input of a further timing element 45 , which is used to generate a short setting signal for a digital counter 46 connected to the output of the timing element 45 . This counter 46 is connected as a setpoint memory.

A speed sensor 47 is used to generate a speed proportional frequency and consists of a rotatable disc 48 coupled to a vehicle wheel, which has a plurality of ferromagnetic marks 49 on the circumference. These ferromagnetic marks are guided past an inductive pickup 50 and each induce a pulse there. The output frequency of the speed sensor 47 is converted into a data word, in particular a binary number, in a frequency-number converter 51 and, as such, fed to a digital counter 52 , which is connected as an actual value storage device and continuously stores the applied actual values. A frequency number converter is e.g. B. from US-PS 39 28 797, but - as for the speed sensor - various known principles and embodiments can be used.

The number outputs of the actual value memory 52 are connected via a terminal arrangement 53 to number inputs of the following components: the auxiliary setpoint memory 41 , the setpoint memory 46 , the inputs B of a first digital comparator 54 , the inputs B of a second digital comparator 55 , the inputs B of a third digital comparator 56 , the inputs A of a fourth digital comparator 57 , a subtracting stage 58 (preferably implemented as an adding stage), a digital counter 59 and a control comparison point 60 (usually implemented as an adding stage). The number outputs of the auxiliary setpoint value storage device 41 are also connected to the control comparison point 60 , the outputs of which are connected via a control stage 61 to a further control comparison point 62 . Depending on the desired control properties, this control stage 61 can have P -, I -, D -, behavior or combined behavior. In the prior art specified at the outset, a PD controller is used and described for a control device for the driving speed of a motor vehicle.

The number outputs of the setpoint storage device 46 are connected to the number inputs of the following components: the inputs A of the first digital comparator 54 , the subtraction stage 58 , the inputs A of a fifth digital comparator 63 , a read-only memory (ROM) 64 , the outputs of which to the Control reference junction 62 are connected. The numerical outputs of the counter 59 are connected to the inputs B of both the fourth digital comparator 57 and the fifth digital comparator 63 and furthermore via a read-only memory (ROM) 65 to the inputs A of the third digital comparator 56 . The outputs of the comparators 57, 63 , at which a signal is generated when the number applied to the inputs A is greater than the number applied to the inputs B , are via an AND gate 66 and an OR gate connected in series therewith 68 connected to the set input S of the counter 59 . The output of the OR gate 20 is also connected to an input of the OR gate 68 of the counter 59 via a timing element 67 .

A numerical value is applied to the number inputs A of the second digital comparator 55 via a terminal arrangement 69 , preferably by means of fixed wiring, which specifies the threshold for a minimum driving speed Vmin below which the control device is switched off. The outputs of the digital comparators 55, 56 , at which an output signal is generated when the numerical value applied to the inputs A is smaller than the numerical value applied to the inputs B , are via a NOR gate 70 to a further input of the OR gate 17 connected. Furthermore, this output of the second digital comparator 55 is connected to a further input of the AND gates 21 to 23 .

An output of the first digital comparator 54 , at which an output signal is generated when the numerical value applied to the inputs A is greater than the numerical value applied to the inputs B , is connected to a further input of the OR gate 43 . A second output of this comparator 54 , at which an output signal is generated when the input number values are of the same size, is connected to a further input of the OR gate 32 . The number outputs of the subtracting stage 58 are connected to number inputs A of a sixth digital comparator 71 . Via a terminal arrangement 72 , a numerical value is applied to the numerical inputs B of the comparator 71 , preferably by fixed wiring, which is proportional to a speed difference which specifies the breakpoint of the ramp gradient during the resumption process. The output of the sixth digital comparator 71 , at which an output signal is generated when the numerical values at the input are the same size, is connected to the reset input R of the flip-flop 30 .

The number outputs of the second control comparison point 62 are connected to number inputs A of a seventh digital comparator 73 and to number inputs B of an eighth digital comparator 74 . A terminal 75 is preferably a fixed value by fixed wiring to the number inputs B of the comparator 73 , which corresponds to a maximum manipulated variable Smax , which should not be exceeded. Via a terminal 76 , the numerical inputs A of the comparator 74 are preferably supplied with numerical values by fixed wiring, which corresponds to a minimum manipulated variable Smin , which should not be undercut. The outputs of the comparators 73, 74 , at which an output signal is generated when the number at the number inputs A is greater than the number at the number inputs B , are via a NOR gate 77 to a further input of the AND gate 36 connected.

Furthermore, the number outputs of the second control comparison point 62 are fed to a control loop 78 which has an actuator 79 which, for. B. can be designed as an actuator or solenoid. By means of this actuating drive 79 , an element 80 influencing the speed of the motor vehicle is movable, which in FIG. 1 is designed as a throttle valve in an intake manifold 81 of the internal combustion engine. Other elements influencing the speed of a motor vehicle are e.g. B. the ignition point, or the ignition at all, or in the case of an injection motor, the position of the control rod of the injection pump or the switching time of the injection valves. Adjustment loops with actuators are known from the state of the art at the outset and have also been proposed in digital form by DE-OS 27 46 445. A lock input for the control loop or the actuator is connected to the output of the flip-flop 19 .

The three used and connected to the terminals 35, 37, 39 clock frequencies f 1 to f 3 can preferably be generated by a clock frequency generator (not shown), different frequencies being generated by frequency division. The four clock frequencies used do not have to be different in every case with the exception of the two frequencies for generating the different ramp slopes.

The operation of the embodiment shown in Fig. 1 will be explained below with reference to the diagrams shown in FIGS. 2 and 3. First, assume that the vehicle is moving at a certain speed and that the main switch 11 is closed. The vehicle should now be accelerated by means of the control device. For this purpose, the acceleration switch 16 is actuated, whereby the flip-flop 29 is set. At the same time, the flip-flop 19 is set via the OR gate 24 , as a result of which the locking of the control loop 78 or of the actuator 79 is released. At the same time, as already described, the memory device is initialized via the OR gate 18 and the terminal 26 . Due to the short pulse of the timer 42 , the counter 41 is loaded with the memory content of the actual value memory 52 . While (from time t 1 ) the signal U 16 is present when the switch 16 is actuated, the AND gate 34 is blocked by the O signal at the output of the inverter 33 . However, the AND gate 36 is opened by this signal U 16 and the clock frequency f 2 can reach the clock input C of the counter 41 and counts upwards from the number corresponding to the actual value, since the signal U 16 at the output of the OR gate 43 there is a 1 signal which causes the up-counting process. At the control comparison point 60 , this counting up has the effect of a change in the target value, which in turn is noticeable at the control comparison point 62 as an apparent reduction in the actual value. The resulting manipulated variable causes the control circuit 78 and the internal combustion engine to increase the power and thus the actual actual value, that is to say an increase in the numerical value in the actual value memory 52 . This enlargement continues until the switch 16 is opened again, or the button 16 formed as a button scarf is released at time t 2 . The AND gate 36 blocks the clock frequency f 2 and the lower clock frequency f 1 can now reach the clock input C of the counter 41 via the AND gate 34, at the same time by the signal at the output of the AND gate 23 via the OR gate 43 an inversion of the counting direction, which is determined by the output signal of the comparator 54 . Finally, at the time t 2, the timing element 45 is triggered by the trailing edge of the signal U 16 via the NOR gate 44, the short output pulse of which causes the setpoint value memory 46 to be set with the current actual value. At the control comparison point 62 there is now a setpoint, which is formed by means of the stored value in the setpoint memory 46 on the basis of the working characteristic of the control device by the read-only memory 64 . The numbers stored in the setpoint memory 46 form the addresses for the read-only memory 64 . As a result of the unavoidable inertia of a control system, the actual value after the time t 2 exceeds the target value by a small amount. The feedback is supported by the falling ramp due to the clock frequency f 1 . If the stored setpoint at time t 3 is equal to the stored actual value, a reset signal for the flip-flop 29 is generated at the output " A = B " of the comparator 54 , by means of which the counting process in the counter 41 is ended.

If the vehicle moves with the set speed and now z. B. due to a dangerous situation, the brake or the clutch of the vehicle is actuated, one of the two switches 12, 13 is actuated, which leads to an initialization of the memory devices, as well as to a reset of the flip-flop 19 via the terminal 26 . By this, the control loop 78 , or the actuator 79 is returned to the idle position and the vehicle is no longer influenced by the control device. If the resumption switch is now actuated, the three flip-flops 19, 29, 30 are set, whereby the locking of the actuator 79 is released and the clock frequencies f 1 and f 3 are simultaneously fed to the clock input C of the counter 41 . These processes are shown in FIG. 3 and start at time t 4 . The counter 41 is set to the value of the actual value memory 52 present at this point in time. Since the setpoint at inputs A of comparator 54 is greater than the actual value at inputs B at this time, a signal is generated at output " A < B ", which causes OR gate 43 to count up in counter 41 . This upward counting process lasts until the difference between the target value and the actual value, which is present at the output of the subtracting stage 58 , has reached the value Δ v , which, for. B. can be three kilometers per hour. If this equality is sufficient, the flip-flop 30 is reset by the output of the comparator 71 , as a result of which the AND gate 38 is blocked. From this point in time t 5 , counting in counter 41 only takes place by frequency f 1 , which results in a flatter ramp increase. This flatter ramp increase leads the actual value slowly to the setpoint, where the operating point adjustment is carried out. If the actual value reaches the target value at the time t 6 , the flip-flop 29 is reset as described above by the output " A = B " of the comparator 54 . The counting process in the counter 41 has ended.

The processes described above function accordingly in the opposite direction, ie when the resume button 14 is pressed at an actual speed above the target speed, the counting processes run in the reverse counting direction, since the condition " A < B " no longer exists is, and a 0 signal is supplied to the counting direction input U / D of the counter 41 via the comparator 54 . The same applies to a delay caused by the control device by actuating the delay switch 15 . Again, the first part of the ramp runs in the reverse of Fig. 2 with a negative slope, while the second, shallower portion of the ramp having a positive slope, as by the resulting, low overshoot of the actual value below the desired value by releasing the button on the output " A < B " of the comparator 54 generates a 1-count direction signal for the positive count direction.

The timer 31 prevents the adjustment process from being switched off when the keys 16 or 15 are released , since at this moment there is equality between the setpoint and the actual value. Thereby, the comparator 54 would ter via the OR Gat 32 to reset the flip-flop 29th Since the vehicle is now accelerating, equality is removed and the adaptation process is regulated.

If one of the keys 15, 16 is briefly actuated, a short counting process takes place in the positive or negative direction in the counter 41 , as shown in FIG. 2, but this has little effect, since with this slight change in the counter reading a readjustment as shown in FIG takes place. 2,. In practice, the instantaneous actual value of the driving speed is saved and maintained in the event of such a brief actuation.

In order to prevent the manipulated variable from being changed by the control device to values that can no longer be realized by the control circuit or the actuator, the comparators 73, 74 have provided a limitation of the manipulated variable. If either the maximum manipulated variable Smax applied to the comparator 73 is exceeded by the actual manipulated variable or the minimum manipulated variable Smin applied to the comparator 75 is undershot , the corresponding comparator 73, 74 generates an output signal by means of which the AND gate 36 is blocked and another counting process in the case of acceleration and deceleration is ended in the counter 41 .

In order to prevent the control device from being switched on accidentally at low speeds, in particular when maneuvering the motor vehicle, when reversing or in the event of the speed sensor failing , the comparator 55 specifies a minimum driving speed Vmin below which the AND gates 21 to 23 are constantly blocked . A permanent reset signal for the flip-flop 19 is formed via the NOR gate 70 and the OR gate 17 , by means of which the actuator 79 is blocked.

Since all processes are controlled via ramps during control, the deviation between the setpoint minus the actual value is small and can be used as a safety function. If the difference between the setpoint minus the actual value has exceeded a certain value, this indicates a malfunction, e.g. B. the interruption of the signal line from the brake or clutch, the signal should lead to a shutdown. In this case, the controller should be switched off automatically. The actual value is constantly present at the counter 59 . If the setpoint exceeds the actual value currently present in counter 59 , a constant set signal for counter 59 is generated via comparator 63 and AND gate 66 , provided that the value stored in counter 59 is at the same time smaller than the actual actual value. This second condition is specified by the comparator 57 . The peak value of the actual value is thus constantly stored in counter 59 as long as the setpoint remains above the actual value. If the vehicle becomes slower under this condition, the actual value decreases, but the value stored in the counter 59 is retained. A function is now stored in the read-only memory 65 which indicates the threshold below which an auxiliary shutdown is to take place. This function is e.g. B .:

Za = 0.75Ze + Z 10

(Za = output numerical value, Ze = input numerical value, Z 10 = numerical value which corresponds to a speed of 10 kilometers per hour). So if the actual value drops to three quarters of its value plus 10 kilometers per hour, the 1 signal at the output of the comparator 56 changes to a 0 signal, by means of which the flip-flop 19 is reset via the NOR gate 70 and the OR gate 17 and switches off the actuator. Due to the function entered in the read-only memory, the switch-off threshold can be variably specified as a function of the speed.

When the main switch 11 is opened, the inverter 25 and the OR gate 17 likewise issue a return command to the idle position for the actuator 79 .

The second exemplary embodiment shown in FIG. 4 again contains the regions framed in FIG. 1 with a broken line, which contain the components 10 to 26, 44 to 57, 59 and 65 to 70 . These components are interconnected identically and are therefore not shown in detail again. An important difference of the second embodiment compared to the first embodiment is that no control loop 78 is used, that is, there is no separate control circuit for the actuator 79 . Such a control circuit 78 , as used in the first exemplary embodiment, requires an encoder for position feedback for the position of the actuator 79 , for. B. a potentiometer. In the second exemplary embodiment, the actuator 79 is operated by a pulse control 100 , as a result of which the position feedback and thus the associated encoder are unnecessary.

The terminals 101 to 103 are connected to the outputs of the AND gates 21 to 23 . The terminal 101 is connected to the set input S of a flip-flop 104 , the output of which is connected via an OR gate 105 to an input of an AND gate 106 . The output of the AND gate 106 provides the clock signals for the clock input C of the counter 41 used as a ramp value memory. As in the first exemplary embodiment, both the output of the AND gate 23 (via the terminal 103 ) and the output " A < B " of the digital comparator 54 (via the terminal 107 ) via the OR gate 43 control the counting direction input U / D of counter 41 . The terminals 101 to 103 are connected via an OR gate 108 to a first, dynamic trigger input of a timing element 109 , the output of which is connected both to the set input S of the counter 41 and to an input of an AND gate 110 . This first trigger input of the timing element 109 can be triggered by a positive pulse edge. Terminal 102 is connected to a further, inverting input of AND gate 110 , as well as to a further, dynamic trigger input of timing element 109 , which can be triggered by a negative signal edge. The terminals 102, 103 are also connected via an OR gate 111 to the command input " A = O " of a digital comparator 112 . The output " A = B " is connected to the reset input R of the flip-flop 104 . The output of the OR gate 111 is additionally connected both to an input of an OR gate 113 and to a further input of the OR gate 105 . The output of the flip-flop 104 is connected via the OR gate 113 to the switching input of a switching device 114, which is preferably designed as a multiplexer.

The voltage applied to the clamping order of 53 actual value is applied to the inputs B of the adder 115 to the number of inputs of a digital counter 116, the number B inputs of a subtractor 117, to the address inputs of a read only memory (ROM) 118 as well as to the actual-value inputs of a regulation -Comparison 119 created. The setpoint applied via the outputs of the counter 46 to a terminal arrangement 120 is applied once to the number inputs B of the comparator 112 and furthermore to the first number inputs of the switching device 114 . The value of the ramp leading count outputs of the counter 41 are connected to inputs A number of the comparator 112, input numbers A of the subtracter 117, and with second on of the switching device 114 connected gears. Number outputs " B - A " of the comparator 112 are connected to number inputs of a number-frequency converter 121 , the sen variable output frequency f 4 is applied to a further input of the AND gate 106 . The number outputs " A - B " of the subtractor 117 are connected to number inputs B of a comparator 122 , to the number inputs A of which a fixed binary number Δ Y is applied. The output " A greater than B " is connected to a further input of the AND gate 106 .

The fixed binary number Δ X is applied to the number inputs A of the adder 115 . The number outputs " A + B " are fed to the numerical inputs of the counter 41 .

The output of the AND gate 110 , the terminal 107 and a terminal 123 connected to the output of the flip-flop 19 are connected to inputs of an AND gate 124 , the output of which is connected to the set input S of the counter 116 and to the set input of a flip-flop 125 . A clock frequency f 5 is supplied to the clock input C of the counter 117 via a terminal 126 . The overflow output CO (carry out) of the counter 116 is connected to the reset input R of the flip-flop 125 , the output of which is connected via a terminal 127 to an input of the pulse controller 100 . An advantageous, circuit-based configuration of such a pulse control 100 is described in conjunction with FIG. 7 in more detail. Terminal 123 is also connected to an input of pulse controller 100 via terminal 128 .

The number outputs of the switching device 114 are connected to actual value inputs of the control comparison point 119 , the outputs of which are connected to inputs A of a digital multiplier 129 . The number outputs of the read-only memory 118 are connected to number inputs B of this multiplier 129 . The number outputs " A × B " are connected via the P (ID) controller 61 and a terminal arrangement 130 to inputs of the pulse control 100 . A signal dependent on the sign of the system deviation is also fed to the pulse controller 100 via a terminal 131 .

The operation of the Regelein direction shown in Fig. 4 will be explained in the following, inter alia, with reference to FIGS. 5 and 6. First, the resumption process of a speed previously stored in the target value storage device 46 will be described. By pressing the resume button 14 , a corresponding signal U 14 appears at the terminal 101 . This signal sets the counter 41 to a value via the OR gate 108 and the timing element 109 which corresponds to the actual value plus the fixed numerical value Δ X. Wei further, the flip-flop 104 is set so that clock pulses f 4 can reach the clock input of the counter 41 and are counted up as a result of the 1 signal present at terminal 107 . The ramp value accordingly increases according to the broken line shown in FIG. 5. The frequency f 4 depends on the difference between the setpoint minus the ramp value. Is the difference z. B. greater than 10 km / h, so f 4 by appropriate dimen sionation of the number-frequency converter 121 constant accordingly the desired maximum acceleration is set. Therefore, the closer the ramp value approaches the target value, the lower the frequency f 4 . This is done by activating the number-frequency converter 121 through the output " BA " of the comparator 112 . The ramp value is thus continuously and flatly brought up to the setpoint. The same happens with the actual value, which follows the ramp value with some delay. This slow approach of the actual value prevents overshoot and very good comfort is achieved. If the ramp value reaches the desired value, a 1 signal is generated at the output " A = B " of the comparator 112 , by means of which the flip-flop 104 is reset. The AND gate 106 thereby prevents further counting processes. Furthermore, the switching device 114 is actuated via the OR gate 113 , so that now instead of the ramp value from the counter 41 , the setpoint from the terminal 120 of the control comparison point 119 is available. The value of the control deviation is multiplied in multiplier 129 by an actual value-dependent factor in order to achieve improved stability in small speed ranges. This means e.g. B. that at higher speeds the multiplier factor is 1, while at lower speeds this factor z. B. 0.3, so as to reduce the gain of the controller at lower speeds. This factor can be reduced practically continuously by the read-only memory 118 , in that corresponding addresses are addressed by the actual value of the driving speed. A certain multiplication factor can thus be assigned to each actual speed value. This multiplied control deviation controls the pulse control 100 via the controller 61 , as will be explained in more detail in relation to FIG. 7.

If at the same time the stored setpoint is greater than the actual value (signal at terminal 107 ), flip-flop 19 is reset as a result of pressing one of the buttons 14 to 16 (signal at terminal 123 ) and button 15 is not pressed (signal at the output of the AND gate 110 ), then a set signal for the counter 116 and the flip-flop 115 is generated at the output of the AND gate 124 . The counter 116 accepts the current actual value. This actual value is counted down by the clock signals f 5 . At the zero crossing, a reset signal is generated for the flip-flop 125 , so that a 1 signal is present at the terminal 127 during the countdown. The length of this signal is dependent on the actual value and controls the actuating device 79 - as it is explained in more detail in relation to FIG. 7 - in an actual value-dependent position. Since the actuating device 79 is returned to the zero position (0 signal at the terminal 123 ) after each actuation of the brake, the clutch or the switching off of the control device, this approaching of the actual value by the actuating device 79 accelerates the reaching of the desired speed value. This actual value is approached with the greatest possible positioning speed, regardless of the control deviation. The logic of the AND gate 124 does this in the following cases:
When you press the acceleration button 16 (signal at terminal 103 ), when you press the resume button 14 (signal at terminal 101 ), when the speed value to be started is higher than the actual value, and finally when you release the deceleration button 15 (signal Trailing edge at terminal 102 ).

In Fig. 6 the case is shown that after pressing the resume button 14 , z. B. due to an incline of the road, the actual value cannot follow the changing ramps value. Too large a difference between these values would result in the ramp being able to move any distance from the actual value. If the load now disappears, the vehicle experiences too much acceleration (full throttle). This is prevented by the fact that in the event of a deviation < Δ Y, the comparator 122 generates a 0 signal on the output side, by means of which the AND gate 106 is blocked for clock signals f 4 . The ramp is stopped briefly as a result, but continues to run immediately when the difference Δ Y is again fallen below due to the actual value, which continues to increase. By switching the counting frequency f 4 for the ramp on and off, its slope is reduced and runs parallel to the actual value. This adaptation of the ramp gradient to the actual value gradient also results in a smooth transition to the setpoint speed on gradients.

The acceleration case due to actuation of the acceleration button 16 runs essentially according to FIG. 2. Differences result from the fact that once the starting value in the counter 41 in turn, the actual value plus Δ X is taken over. As a result of a signal at the output of the OR gate 111 , the numerical inputs A are set to the value 0 in the comparator 112 , so that the greatest possible difference " B - A " is generated. This in turn generates the highest possible ramp frequency f 4 . If the key 16 is released, then according to the first exemplary embodiment, the actual value currently present is transferred to the target value storage device 46 . In contrast to the first exemplary embodiment, the ramp value present at this point in time remains in the counter 41 . However, this is no longer important, since at the same time the switching device 114 is switched to the setpoint value storage device 46 .

The circuit of FIG. 7 shows an advantageous guidance of the pulse from controller 100. A clock frequency f 6 leads to both the set input of a counter 151 and the set input of a flip-flop 152 via a terminal 150 . Another, higher-frequency clock frequency f 7 , z. B. the frequency of the speed sensor 47 is fed via a terminal 153 to the clock input C of the counter 151 . The number outputs of the controller 61 are connected to the number inputs of the counter 151 via the terminal arrangement 130 . The overflow output C 0 of the counter 151 is connected to the reset input of the flip-flop 152 , the output of which is connected to an input of two AND gates 154, 155 . Terminal 131 is connected to a second input of AND gate 154 and to a second inverting input of AND gate 155 . The output of the AND gate 154 is connected via an OR gate 156 to an input of an AND gate 157 , the output of which controls the advance V of the actuator 79 . The output of the AND gate 155 is connected via an AND gate 158 to an input of an AND gate 159 , the output of which controls the return R of the actuator 79 via an OR gate 160 . Terminal 127 is connected to a further input of OR gate 156 and to a further inverting input of AND gate 158 . The terminal 128 is connected once to an inverting input of the AND gates 157, 159 and finally via a timing element 161 to a further input of the OR gate 160 .

The operation of the pulse control 100 shown in FIG. 7 consists in the conversion of a binary number present at the terminal arrangement 130 into a pulse sequence whose pulse duty factor is proportional to this binary number. It is essential that the pulses of these output pulses are integer multiples of the period or half periods of the input pulse train. This is particularly important when implementing the control device using a microcomputer, since parallel processing is not possible there. After each calculation cycle - during the measuring phase - the motor is controlled with a number of speed sensor periods (or half periods) determined by the calculation. A changing binary number Z 130 is shown in the diagram in FIG. 8. With each rising edge of the signal sequence f 6 , the binary number present at this time is transferred to the counter 151 . The flip-flop 152 is set at the same time. This adopted numerical value is counted down in time with the higher-frequency clock frequency f 7 and the flip-flop 152 is reset in the event of an overflow pulse. This creates a signal sequence U 152 at the output of the flip-flop 152 , the duty cycle of which is proportional to the binary number Z 130 . Corresponding to the signal present at terminal 131 for determining the direction of adjustment, this signal sequence U 152 is present at one of the outputs of AND gates 154, 155 . If there is a 0 signal at terminal 127 (the actuator 79 does not advance to the actual value) and there is a 1 signal at terminal 128 (the actuator is not switched off due to braking, for example), the outputs of the AND Gates 154, 155 alternatively depending on the setting direction of one of the outputs V or R of the pulse controller 100 . The pulse train U 152 affects either the forward or the return of the actuator 79 . If, according to the description of FIG. 4, a lead signal for the actuator 79 to the actual value is generated at the terminal 127 , the AND gate 158 is blocked and this signal has a direct effect on the output V.

If a 1 signal is applied to terminal 128 as a result of a switch-off process (for example braking), the AND gates 157, 159 are blocked and the pulse train U 152 can no longer reach the actuator 79 . The timing element 161 is triggered with this 1 signal, as a result of which a return signal is generated at the output R for the actuator 79 during the holding time of this timing element. The actuator 79 is returned to the 0 position by this return signal.

Of course, the actuator 79 cannot be controlled directly by the outputs of the gates 157, 160 , but amplifier stages must be connected in between. Such a power amplifier arrangement is e.g. B. known from DE-OS 26 09 842. Furthermore, instead of the frequency f 7 , the output frequency of the speed sensor 47 can also be used before.

An initialization circuit for the storage devices (e.g. flip-flops and counters) is shown in FIG . As in the first exemplary embodiment, the inputs of the OR gate 17 are connected to devices which are intended to cause an initialization, that is to say a reset of the memory devices. The main switch 11 is however now connected to a dynamic input of this OR gate 17 . The output terminal 26 is in turn connected to all the storage devices with the exception of the actual value storage device 52 , the setpoint storage device 46 and the ramp value storage device 41 and resets these storage devices to an initial signal of the OR gate 17 in their basic position. The terminal 26 is connected via a NOR gate 170 to the trigger input of a timer 171 , the output of which is connected both to the reset inputs of the memory devices 41, 46, 52 and to the set input of a working memory (RAM) 172 . The numbers outputs of this memory 172 are connected to number inputs A of a comparator 173 , the output " A = B " is connected to a further input of the NOR gate 170 . A fixed binary number Z is applied to the number inputs B of the comparator 173 and the number inputs of the working memory 172 .

The mode of operation of the initialization circuit shown in FIG. 9 is that due to the dynamic input of the OR gate 17 when the main switch 11 is closed , that is to say when the system is switched on, after a short 1 signal at the output of the OR gate 17 again a 0 signal appears. Since the condition " A = B " in the comparator 173 is initially not met, the timer 171 is triggered and resets the memory devices 41, 46, 52 . At the same time, the binary number Z is taken into the working memory 172 , so that the condition " A = B " is now fulfilled and the NOR gate 170 remains blocked for any further type of signals at the terminal 26 . Further resetting of the memory devices 41, 46, 52 is no longer possible, not even due to an interference pulse on the gear side. Resetting these memory devices 41, 46, 52 is only possible again when the power supply was switched off and the main switch 11 was closed again.

The functions of the devices described above can NEN preferably realized by a microcomputer the, especially a 1-chip microcomputer, as in Trade is available. This leads to a simple and cheap implementation with a small footprint. The one before Functions described are such a microcomputer  as a program in a manner familiar to the person skilled in the art given.

In the following he should be in a table in the trade available components are listed, which, for. B. in the specified circuit can be used. The construction parts are marked with their type number. The in Manufacturer specified in brackets serves as an example and must not the only manufacturer for the respective component be:

Claims (27)

1. Digital control device for the driving speed of a force vehicle with an actual value transmitter, a storage device for a setpoint proportional to the desired driving speed, the actual value when at least one switching device is actuated is transferable to the setpoint storage device with a Comparison device for carrying out an actual value setpoint ver equally and with a controllable by the difference of these values Device based on the speed of the motor vehicle influencing element acts with a circuit arrangement that by actuating the at least one switching device Control of the setpoint influences the control device in such a way that the speed change of the motor vehicle from a previous one Driving speed to a new driving speed with constant Change speed and smooth transition to the new driving speed takes place, the setpoint of the digital rule device is changed such that when the at least a switching device the setpoint by supplying a default value is formed for the current actual value, so that the Difference when the at least one switching device is actuated first takes a step, and the setpoint in following is changed in such a way that this changes over time equitable ramp and its rate of change at least takes two values, the earlier value in terms of amount is bigger.   2. Device according to claim 1, characterized in that at a stored setpoint in the setpoint storage device ( 46 ) and actuation of the resumption of control causing the first switching device ( 14 ) essentially the instantaneous actual value with a default value and in the second storage device ( 41 ) is taken over that this accepted value is changed by the ramp until the actual value deviates from the target value by a fixed amount ( Δ V) and that from this point in time the smaller ramp gradient becomes effective until the actual value corresponds to the target value. 3. Device according to claim 1, characterized in that at a stored setpoint in the setpoint storage device ( 46 ) and actuation of the resumption of control causing the first switching device ( 14 ) essentially the instantaneous actual value with a default value and applied to the second Storage device ( 41 ) is taken over that this adopted value is changed by the ramp until it corresponds to the stored setpoint, the ramp slope depending on the difference between the ramp value and the stored ramp value being continuously smaller. 4. Device according to one of the preceding claims, characterized in that when actuating one of the further switching devices ( 15 or 16 ) for triggering a positive or negative acceleration process, the instantaneous actual value is acted upon with a default value and taken into the second memory device ( 41 ) is that this value taken over by the ramp accordingly the duration of actuation of the further switching device ( 15 or 16) is changed and that immediately afterwards the actual value in the setpoint storage device ( 46 ) is accepted. 5. Device according to claim 4, characterized in that after the end of the actuation of one of the further Schaltvor devices ( 15 or 16 ) the smaller ramp slope with the opposite sign is effective until the actual value corresponds to the target value. 6. Device according to claim 4, characterized in that the circuit unit ( 112, 121 ) for determining a variable ramp slope has a control device ( 111 , input A = 0 of 112 ), by one of the further switching devices during operation ( 15 or 16 ) the ramp slope can be set to a maximum value. 7. Device according to one of claims 4 to 6, characterized in that when one of the further switching devices ( 15 or 16 ) is actuated, the actual value is also taken over into the setpoint value storage device ( 46 ), so that the instantaneous actual value as a further setpoint when briefly actuated - Enter the speed value before. 8. Device according to one of the preceding claims, characterized in that a switch-off device ( 73, 74, 77 ) is provided for stopping the ramps, which can be triggered by reaching at least one predeterminable final value (Smin or Smax) . 9. Device according to one of the preceding claims, characterized in that a circuit unit means ( 117 ) for detecting the difference between the ramp value and the actual value is provided and that a threshold value detection ( 122 ) is provided, by a further change when a maximum permissible difference is exceeded the ramp value can be prevented. 10. Device according to one of the preceding claims, characterized in that the setpoint stored in the setpoint storage device ( 46 ) with the aid of a read-only memory (ROM) ( 64 ) according to the working characteristic of the internal combustion engine and the control device can be modified. 11. Device according to one of the preceding claims, characterized in that the control has a P - and / or an I - and / or a D behavior. 12. Device according to one of the preceding claims, characterized in that when the value falls below a predeterminable value (Vmin) by the actual value, the control device is switched off. 13. Device according to one of the preceding claims, characterized in that when a pre is exceeded value that can be given by the difference peak value (max value) minus the actual value a shutdown of the control device is effected.   14. The device according to claim 13, characterized in that the predeterminable value by addressing a fixed value memory ( 65 ) is dependent on the driving speed. 15. Device according to one of the preceding claims, characterized in that the occurrence of disturbing the scheme before gears in the motor vehicle, especially brake or clutch processes causes the control device to be switched off. 16. Device according to one of the preceding claims, characterized in that by actuating one of the switching device ( 14, 15, 16 ) a locking of the actuating device ( 78, 100 ) can be canceled to influence the speed of the motor vehicle. 17. Device according to one of the preceding claims, characterized in that the actual value transmitter ( 50 ) is assigned an actual value memory ( 52 ) in which the current actual value is constantly stored. 18. Device according to one of the preceding claims, characterized in that upon actuation of one of the switching devices ( 14, 15, 16 ) and / or when a process causing the shutdown of the control device occurs, a reset of all storage devices with the exception of the setpoint storage device ( 46 ) the actual value storage device ( 52 ) and preferably the ramp value storage device ( 41 ) can be triggered. 19. Device according to one of the preceding claims, characterized in that when the supply voltage is switched on all storage devices are reset and that a locking device ( 170 to 173 ) is provided by the subsequent signals, the storage devices ( 52, 46, 41 ) no longer can reset. 20. Device according to one of the preceding claims, characterized in that a switching device ( 114 ) for switching between setpoint storage device ( 46 ) and ramp value storage device ( 41 ) is provided, the setpoint for controlling the actuating device ( 78, 100 ) Contents of the ramp value storage device ( 41 ) is switched through until there is equality between the ramp value and the setpoint value or while one of the further switching devices ( 15 or 16 ) is actuated. 21. Device according to one of the preceding claims, characterized in that a circuit unit ( 118, 129 ) for multiplication of the control difference with an actual value-dependent factor are provided. 22. Device according to one of the preceding claims, characterized in that an adjusting control circuit ( 78 ) is provided as the adjusting device. 23. Device according to one of claims 1 to 22, characterized in that a pulse control ( 100 ) is provided as an actuator, in which the manipulated variable is converted into a pulse voltage with manipulated variable-dependent Tastver ratio. 24. The device according to claim 23, characterized in that the pulse control ( 100 ) contains a counting device ( 151 ), in which the actuating variable present as a binary number is adopted in time with a first clock frequency (f 6 ), that the adopted values in Clock of a second, higher frequency (f 7 ) are counted, the counting time specifying the pulse width of the signals of the pulse voltage. 25. The device according to claim 24, characterized in that the higher frequency (f 7 ), the output frequency of the rotary encoder ( 47 ) is provided and that the actuation of the actuator ( 79 ) takes place during a measuring phase of this frequency (f 7 ). 26. Device according to one of the preceding claims, characterized in that the actuator is also directly switchable by a control device ( 116, 125, 156, 158 ) through which the actuator ( 79 ) when actuating at least one of the switching devices ( 14 to 16 ) can be moved into a position corresponding to the current actual value. 27. Device according to one of the preceding claims, characterized by training as a microcomputer, ins especially as a 1-chip microcomputer.