DE2840325A1 - ARRANGEMENT FOR BOOKING PRE-DETERMINED SAME UNITS - Google Patents

Description

- 4- patent attorneys 2 8 4 O ο 2 O

Dipl.-Ing. Dipl.-Chem. Dipl.-Ing.

E. Prince - Dr. G. Hauser - G. Leiser

Ernsbergerstrasse 19

8 Munich 60

September 14, 1978

COMPAGFIE INTERNATIONAL POUR L'INFORMATIQUE CII- HONEYWELL BITLL

94 “Avenue Gambetta

75020 PARIS / France

Our drawing: C 3199

Arrangement for booking predetermined similar units

The invention relates to an arrangement for booking predetermined similar units with the aid of a Information carrier and with the help of external devices for reaming and / or using the information, and in particular to an arrangement of this type, as described in the earlier patent application P 28 14 003.6.

Arrangements of this type consist of an information carrier which contains an initial quantity and which is intended to do so is to register quantities that correspond to the services received or provided, a device for registering the Initial amount in the information carrier, a device with which the available amount in the information carrier Can be changed to a size that the desired or

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service received, the provision of which is carried out by the device is released, and a connection system between the information carrier and these devices.

The purpose of such orders is to create documents for transactions or for registration, which can register whole values of units and for the acquisition and booking of the data of the carried out To serve transaction or registration.

In the arrangement described in the aforementioned earlier patent application, the information carrier is in particular for example, formed by a card on which a certain amount of desired in coded form Achievements in the form of a certain number of equal separate Units is recorded.

At the point in time at which the user procures a card, it will have one in its memory certain credit, which can be changed in the course of use and thus from the initial value to the value zero goes.

Since the memory of the card is not reusable, once the card is empty, it can no longer be used. and it must be returned by the user when he gets a new card.

If the card is to be sufficient for a large number of services, the initial value written in the number become very large, which requires a significant investment when purchasing the card.

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So that the card is more profitable and more accessible it is therefore desirable to provide the option of making it valid in sections.

The object of the invention is to provide an arrangement which allows such "filling" and yet guarantees a very high level of security against possible fraud.

According to the invention is an arrangement for booking predetermined similar units with the aid of a Information carrier and with the help of external facilities for writing and / or using the information, wherein the information carrier comprises a memory, circuits for controlling the memory and devices for the temporary coupling of the information carrier with the registration and / or usage devices, which are formed by means for reading and writing data in the memory, the memory of the information carrier in coded form information about the use for which the information carrier is intended, about the unit in which the operations carried out are booked and the number of units available contains, and wherein the writing and / or reading devices contain devices that are used in the Memory of the information carrier the number of times used by the owner inscribe the information carrier desired or received units, characterized in that, that the memory is divided into three parts, namely a part in which the information about the units and the serial number of the card are stored, a price field which can be accessed by a predetermined one Has key contained in the information carrier and only through the writing and reading devices of the memory

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of the information carrier is accessible, and a third part, which is allocated to the storage of the units and is divided into zones that can be released individually.

With the arrangement according to the invention, the information carrier can be released for one or more zones, and it can then be released for new zones until later the total storage capacity of the information carrier is exhausted.

Because in the course of the service life of an information carrier it is possible to release further zones of the memory, therefore attempts at fraud must be prevented, which would consist in further zones of the store outside the single-ear reaming devices intended for this purpose to release. The key provided in the information carrier serves this purpose.

Further features and advantages of the invention emerge from the following description of an exemplary embodiment, which is shown in the drawing. In the drawing show:

Pig. 1 the organizational scheme of the information content of an information carrier in the arrangement according to the invention,

Pig. 2 the general logic diagram on the information carrier attached circuits and part of the circuits of the devices for writing and / or use of the information carrier,

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Pig. Figure 3 is a more detailed logic diagram of the address generator of the Tig array. 2,

Pig. 4 a more detailed logic diagram of the circuits of the information carrier,

Pig. 5 a. more precise logic scheme of the key generator the arrangement of Pig. 2,

Pig. Figure 6 is a more detailed logic diagram of the address generator of the Pig array. 4,

Pig. 7 Diagrams of the cycle signals for reaming or reading the information content of the information carrier,

Pig. 8 diagrams of the phase signals for the intervention or reading of the information content of the information carrier and

Pig. 9 the subdivision of a zone, which makes it possible to assign different values to each bit.

Pig. 1 shows the scheme of the organization of the information content of an information carrier, for example one Map. The information content is in binary form.

At the top of the card, the identification code group of the card is written at 1, which the use of the card in suitable evaluation devices enabled. At 2, the code group is written, which for a given type of use the identification of the credit unit assigned Value enables.

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At 3 a service or serial number is recorded, which allows identification of the card.

These three code groups 1, 2 and 3 are immutable, i.e. they must not be manipulable in order to create a certain code group recognized by an evaluation device to another code group that is also recognized by the device, but of a different type of Services is assigned.

For this purpose, fields of η bits are used for these code groups, in which the transition from a state each bit in the other state is irreversible.

] for more detailed information on such coding reference may be made to the aforementioned earlier patent application.

At 4 there is a release field for the release a certain number of zones numbered from 1 to Z

In the release field 4, Z bits are combined, which are numbered from 1 to Z and each one of the zones 1 to Z. correspond.

The irreversible transition of one of the bits in the enable field 4 to state 1 results in the corresponding zone Approved. To make the use of the card more versatile, the bits of the various zones 1 to Z have not the same values.

For example, the bit can have different unit values in a zone adopt, depending on its function in the zone;

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According to FIG. 9, a bit in sub-zone 1 has the value U, one bit in sub-zone 2 has the value 5U, one bit in the Subzone 3 the value 1OU, one bit in subzone 4 the value 2OU, one bit in subzone 5 the value 5OU and a bit in sub-zone 6 has the value 100U.

The release field 4 has the task of the usage machine indicate for the map the zone or zones (1 to Z) to be used, with the expression "Use a zone "means that one or more bits of the zone in question are under the control of the use of B-mascliine be brought from state 0 to state 1.

As with the arrangement according to the previously mentioned earlier patent application, the bits transition to the changeable ones Zone or zones of the memory of the card when using the card in an irreversible manner from state 0 to the state 1.

When the changeable zones are exhausted, the map can be made usable again by using is permitted by one or more other remaining zones on the card; This process takes place because the card is thus inserted into a suitable registered machine or credit machine.

In order to prevent any possibility of fraud, the address of the authorization bit of the card is sent to the card by the credit machine in encrypted form, whereby the encryption is carried out using a key that is identical to the key remaining in the card. This The key can be found in one of the crediting machines Memory that is protected by the service or order number at position 3.

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Pig. Figure 2 shows the general logic diagram of the arrangement. The card contains a programmable memory 10 of the type PROM (programmable read-only memory), which by a cyclic address generator 11 is addressed, which receives synchronization signals from a clock generator (signal H) in the writing machine or Usage machine for the card is located.

The memory 10 protrudes with the external circuits an input terminal EM and an output terminal SM in connection.

The EM input receives what comes from the Masohine Signal S, which is also applied to a non-equivalence circuit 12 whose second input is connected to the output of a circulating shift register 15 that does the job has to deliver a coding key C.

The output of the non-equivalence circuit 12 is to the address generator 11 connected.

The output SM of the memory 10 is connected to the address generator 11 and connected via a connection block 24 to the line that connects the card to the Masohine connects and the signals E and S leads, where E is the output from the card and for the (registered or Use) machine specific signal is.

To the address generator 11 is a generator 14 for Cycle and phase signals (control signals) are connected, which will be explained later.

In addition to the circuits intended for writing and reading the card, the machine contains circuits that are not shown are, but with those in the earlier mentioned older

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The circuits shown and described in the patent application are identical, a circulating shift register 15, which is used for this purpose is intended to assign a key M in accordance with the information provided by the service or order number 3 of the card produce. This shift register 15 is connected to an antivalence circuit 16, of which a second input receives the addresses formed by the machine and connects its output to the line carrying the signals E and S. is. The machine also includes a memory 67 connected to line E / S for storage the information read on the card for each transaction is determined. That for the synchronization The clock signal H required for the exchange of information between the card and the machine is provided by a clock generator delivered.

Pig. 3 shows a more detailed circuit diagram of the address generator 11 by Pig. 2.

The address generator contains a comparator 17 'which the output signals of a register 18 for the effective Address and a register 19 for the incoming address. ·

The register 18 is connected to the output SM of the memory 10, and the register 19 is connected to the non-equivalence circuit 12 connected.

The output of the comparator 17 is connected to a selector 20, which also has the output signal of the register receives and generates the Aäressen Aq to A ^ q.

Pig. Figure 4 shows a more detailed logic diagram of the circuitry of the Pig card. 2

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This circuit diagram again shows the memory 10, the address generator 11, the key generator 21, the cycle and phase signal generator 14 and a circuit block 22, the supply voltage Y ^ for the digital circuits of the tender and the supply voltage V ₂ for the memory 10 and the reset signal RAZ supplies, which is converted by an inverter 23 into a signal RAZ.

The generator 14 is formed by a shift register which supplies the cycle signals 01 to C5 (Pig 7) and the phase signals φϊ , <p2, ψ3, <p4- and ψ7 (FIGS. 7 and 8), while the phase signals φ 5 and ψβ are generated by the address generator 11 (Fig. 6).

The output SM of the memory 10 is connected to the connecting line carrying the signals E and S via an AND circuit 24 connected by the cycle signals 01, C3 and C5 is released.

The memory 10 has a write control input CE which is connected to a latch block 25 which contains an AND latch 26 and two NAND latches 27 and 28 which receive the signals C4, ψΊ and 02, φ 5, respectively.

The key generator 21 receives the signals <? 1, <p3, 02, H and RAZ, and the address _{generator 11 receives the signals φ} 1, φ2, _Ψ 3, <p4, C2, H, RAZ and RAZ as well as that from the (write-in - and use) machine-derived signal S; In addition to the address bits _{Aq to A 10, it} outputs the signal φ5.

Fig. 5 shows a more detailed logic diagram of the key generator 21 of Fig. 4. The key generator includes a circuit block 30 which controls the digital state of the terminals A, B, 0, D determined by two shift registers 31 and 32 which define the key 0.

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The key generator is controlled by a NAND circuit 33, which receives the signals 02 and φΛ, and by an OR circuit 34, which sends the signals C2, tp3 and H via an UKD circuit 35 and the output signal of the NAHD circuit 33 Receives via an inverter 36 and an UlCD-Sohaltung 37 released by the clock signal H.

Fig. 6 shows a more detailed logic diagram of the address generator 11 of Pig. 1. The address generator includes a counter which is formed by the registers 41, 42, 43 and has the task to generate the addresses to Aq A _10th

The holding blocks 44, 45 and 46 are registers which have the task of receiving the effective address of the bit to be released on the one hand and the incoming address formed by the comparator 51 on the other hand. The comparator 17 of FIG. 3 corresponds to the two bistable multivibrators 47 and 48, which control the counter 41, 42, 43 via an AND circuit 49 which is enabled by the signal C2. The flip-flop 47 is controlled by a non-equivalence so-holding 50, which is connected on the one hand to the output Q _{c of} the register 46 and on the other hand to the output of a further non-equivalence circuit 51, which receives the signal applied to the input EM of the memory 10 and from Key signal C is released.

The output signal of the exclusive OR circuit 51 controls also registers 44 to 46.

The flip-flop 48 is controlled by an AND circuit 52 which receives the signals H, C2 and φ4. The flip-flops 47 and 48 are formed by an AND circuit

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reset to zero, released by the signal RAZ and receives the output signal of an AND circuit 54, at whose inputs the signals <p1 and C2 are applied are.

The registers 44 to 46 are reset to zero by the signal RAZ, and the resetting of the counters 41 to 43 to zero is carried out by an AND circuit 55 which receives the signal RAZ and the output of an AND latch to which the signals H and ψβ are applied.

The transfer of the contents of the registers 44 to 46 into the counter registers 41 to 43 is controlled by a series of OR circuits 57, which are enabled by the AND gate, and under the control of a NAND circuit 58 which signals 02 and ψ5 are applied.

The port switching of the bits in the shift registers 44 to 46 is controlled by an OR circuit 59 which, on the one hand, receives the output signal of an AND latch 56, to which the signals 02, φ 3 and H are applied, and, on the other hand, the output signal of an AND Circuit 61 which is enabled by the signal H and receives the (inverted) output signal of a NAND circuit 62 which is enabled by the signals G2 and φ2 and receives the output signal from the output SM of the memory after inversion.

The output of the NAND circuit 62 is also used for charging the registers 44 to 46.

Finally, the address generator 11 generates the phase signals φ 5 and φ 6 with the aid of two flip-flops 63 and 64 under the control of the signals 02 and (/ '4.

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8 shows the phase signals?> 1 to <p6, the clock signal H being the signal supplied by the (write-in or use) masohine, as described in the earlier patent application mentioned.

Pig. 7 shows the cycle signals CM to C5 and the phase signal ψΐ.

The arrangements shown and described above operate in the following manner, regardless of whether it is the Writing to the card (writing the credit in the memory of the card) or to use the card (Entering a load in the memory), the operations being carried out in five cycles C1 to C5.

The memory 10 of the card is read in cycle C1, the entire memory being read in the course of this cycle including the non-shared zones.

Reaming into the release zone takes place in cycle C2 (Release field for zones 1 to Z).

When a credit is to be placed in one or more zones of the card's memory, one or more Bits of enable field 4 from state O to state 1 brought.

If, for example, zones 1, 2, 3 and 4 are to be used, the writing machine brings the first four bits of field 4 to state 1.

If, on the other hand, the card is to be charged, the usage machine brings the bits corresponding to the value to be charged in the available (changeable) zone or zones to the value 1.

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The address of the bit to be written is determined by the (write or use) Masehine sent. This address is not sent in plain text, but after encryption by the key generator 15 (Pig · 2).

In the card (FIG. 3) the address is deciphered (in 12) and (comparator 17) compared with the address of the bit to be written (register 18). If the two addresses are identical, the bit is written (selector 20), and if they are different, the last bit of the memory is written. This anomaly is later discovered by the usage machine, which causes the card to be rejected.

Cycle 03 is a read cycle that is the same as cycle C1 is.

Cycle 04 is a write cycle in the course of which fields 1, 2, 3 and 4 are protected and only zones 1 to Z are accessible.

Finally, cycle 05 is a read cycle that corresponds to the Cycle G1 is the same.

The process of writing a certain credit into the card will now be described in detail.

After the card is inserted and the connections have been made, cycle 01 becomes through the appearance of the signal RAZ (Fig. 7) triggered. It extends over a complete cycle (2048 bits) of addressing of the memory 10 of the card (reading the card).

All read data (signal E) are transmitted to the credit machine. If any abnormality is found, the card is rejected.

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Ea aei now assume that the card is already in use so that their fields 1, 2, 3 have already been described and that they should be "refilled".

At the end of cycle G1, signal C2 appears (Fig. 7 and 8). The cycle G2 is a short cycle of 141 periods of the clock signal H for writing in the enable field 4 of the memory of the card.

This registered mail is possible because the machine knows the serial number 3 that you received from the card in the process of cycle C1 has been notified. This serial number gives the key to be used.

The incoming signal has the purpose? the map, after comparison with the signal from the key generator 21 to indicate the address of the next enable bit to be included in the Release field 4 is to be written.

If the signal <p2 appears, the release field 4 is read. The detection of the first bit with the value zero in this field 4 causes the entry of the address of this bit in the registers 44-46.

During phase φ3 of cycle 02, the card receives the address of the enable bit to be written, with the reception taking the highest priority.

If no difference is detected during phase φ 3, flip-flop 47 remains in state 0. If a difference is detected, flip-flop 47 goes into state 1.

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If the Kippsohaltung 47 is in the O state in the phase ψ 4, the toggle circuit 48 remains in the O state; on the other hand, if flip-flop 47 is in state 1, flip-flop 48 also goes into state 1. During phase ψ 3, the content of registers 31-32 is shifted eleven times in a circle. This circular shift generates the key C which is sent to the address generator 11.

During phase ψ5 , the contents of registers 44 to 46 in counter 41 to 43 are copied when flip-flop 48 is in the 0 state. If, on the other hand, the flip-flop 48 is in the state 1, the counter 41 to 43 is loaded with 11 bits of the value 1.

During the phase ψβ the counter 41 to 43 is reset to zero.

If, during phase <p3, the comparison between the real address of the bit to be written and the address supplied by the machine results in a difference, the last bit of the memory is brought to 1 during phase φ5. This is shown in the upper part of FIG. 8 at the level of the clock signals H and the memory addresses. In the case of correct addressing, the 67th bit of the enable field of the memory is addressed (for example). In the event of incorrect addressing, the 2047th bit is addressed.

The addressing of the 2047th bit thus expresses an attempt at fraud which is easily discovered by the usage machine will. Since the probability for a fraudster (who does not know the key C), a release bit is correct is set to 1: 2048, the system has a high level of security against attempted fraud.

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The end of cycle 02 triggers cycle 03, which is a Read cycle is.

During cycle 04, fields 1, 2, 3 and 4 of the card are protected and only zones 1 to Z are accessible when phase φ 7 appears. At this moment the bits of the affected zones are set to 1.

If the entire memory of the card is at the end of cycle 04 has been addressed, the cycle C5> appears, which is a read cycle.

Once the memory has been completely read, the cycle of operations is complete.

The lending machine can have serial numbers 3 of the on this Way to register credit cards; this possibility allows the control of certain dubious cards. to for this purpose it contains a non-volatile memory (65 in Pig. 2), to which the operator can use a at 66 (Pig. 2) synchronized identification code group Has access. When this memory is addressed with the serial number of a card, it delivers to the key register 15 of the loan machine the key to be used.

Once the card has been properly credited, it can they can be used in any suitable machine.

After inserting the card and making the connections the same cycles 01 to 05 run as with the loan machine.

The task of the usage machine is to debit the card, i.e. to bring the bits that correspond to the value to be debited to 1 in the usage zone or zones.

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The memory of the card is read in cycle C1.

During cycle 02, the usage measure requires h.ine the writing of digits O in the release field of the Memory of the card at the relevant bit addresses, and no longer the writing of digits 1, as in JTaIl of credit. This enrollment requirement does not have any Effect on the memory, since the bits that have already been set to the value 1 are irreversible and those are already in the state O bits can only remain in this state. The addresses given by the machine can therefore be arbitrary.

Cycle 03 is a read cycle that is the same as cycle C1 is.

During cycle 04, which is a write cycle, Fields 1, 2, 3 and 4 are protected and only the zones or sub-zones authorized by the release field 4 are for the debit machine accessible, which then writes digits 1.

Finally, cycle 05 is a read cycle that corresponds to the Cycle 01 is the same.

In the event of attempted fraud, as previously seen, the last bit of the card's memory is in has been brought to state 1. When such a card is inserted into a usage machine, the first Read cycle C1 in memory 67 determines that the last bit of memory is 1 and the card is rejected.

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Claims (6)

Patent attorneys Dipl.-Ing. 2840325 Dipl.-Ing. Dipl.-Chem. G. Quieter E. Prince Dr. G. Hauser Ernsbergerstrasse 19 8 Munich 60 September 14, 1978 GOMPAGNIE IHTERNATIOFAItE POUR L ¹ INPORMATIQUE CII- HONEIWELI. BULL 94-, Avenue Gambetta 75020 PARIS / France . Our reference: G 3199 Claims he Arrangement for posting predetermined similar items Units with the help of an information carrier and with the help of external devices for reaming and / or using the information, the information carrier being a memory, circuits for controlling the Memory and devices for the temporary coupling of the information carrier with the inscribing and / or Contains usage facilities, which are carried out by facilities for reading and writing data in the memory are formed, the memory of the information carrier in coded Porm information about the use for which the information carrier is intended, about the unit, in which the operations carried out are recorded, and contains the number of units available, and where the writing and / or reading devices included, which are used to store in the memory of the information carrier the number of the owner of the information carrier to register the units requested or received, 909813/0931 ORIGINAL INSPECTED Lei / Gl characterized in that the memory is divided into three parts is divided, namely a part in which the information about the units and the serial number of the Card are stored, a price field that can be accessed by a predetermined key, the contained in the information carrier iat and only duroh the Writing and reading devices of the memory of the information carrier is accessible, and a third Part that is assigned to the storage of the units and is divided into zones that are released individually can be. 2. Arrangement according to claim 1, characterized in that at least one of the zones in which the information about The units stored are divided into several sub-zones, one of which is elementary units and the other sub-zones of multiples or submultibles associated with the elementary units, and that each of these sub-zones has a release zone inside of the release field. 3. Arrangement according to claim 1 or 2, characterized in that that the information carrier contains an address generator, which is connected to the memory of the information carrier and to a control signal generator that the Address generator information on the one hand from the write and read devices of the memory and on the other hand receives from a key generator contained in the information carrier, and that the writing and Readers also contain a key generator, who is able to reconstruct the key of the information carrier and who has the task of to encode the information intended for the information carrier. 909813/0931 4. Arrangement according to claim 3, characterized in that the address generator has an address register for incoming Contains addresses that with the key generator of the information carrier and connected to the input of the memory, an address register for effective addresses, which is connected to the output of the memory, a comparator which is connected to the two address registers is, and a selector which is connected to the comparator and is adapted to make the connection between the output of the address register for incoming addresses and the address inputs of the memory can. 5. Arrangement according to claim 3 or 4, characterized in that that in the event of a mismatch between the effective address and that of the writing devices of the "The address generator's received address last cell of memory addressed. 6. Arrangement according to one of claims 1 to 5 »characterized in that that the writing devices contain a memory for storing the key the information carrier is determined. 109813/0931