DE2835282C2 - Tax rate for a self-commutated inverter - Google Patents

Description

- The clock generator (1) is followed by a frequency divider (2) with a division ratio of 2: 1, which only with a rising or only a falling edge, the pulse of the clock (1) switches;

- The clock generator (1) is also followed by a memory (3) in parallel with the frequency divider (2), which is used when the inverter is switched on is in the reset state and that is set in the other tendril of the pulses of the clock generator (1) will;

- The outputs (2t £ Ie, 3c) of the frequency divider (2) and memory (3) are connected to the inputs (22a, 23a. 226, 236; . -set memory (3), _{the J0} control signals for the inverter being present at the outputs (22c 23c) of this first locking stage (22, 23).

2. Steuer * jtz for an inverter according to claim 1. that the pulse-pause ratio dps clock generator (1) adjustable _J5

3. A tax rate according to claim 1 or 2, characterized in that the reset input (3b) of the memory (3) is connected to a limit value transmitter (6) which monitors the supply voltage (U ') of the tax rate. wherein the memory (3) is reset as soon as the supply voltage (U ') of the tax rate is below a limit value and the setting of the memory (3) is enabled. as soon as the supply voltage (U) exceeds this limit value.

4. Tax rate according to one of claims I to 3, characterized in that the frequency divider (2) has two complementary outputs (2c /, Ie) Tw control at least one thyristor each (9, 10) and that the outputs of the frequency divider (2) a pulse converter stage is connected downstream, which delays the beginning of each output signal of the frequency divider (2).

5. Tax rate according to claim 4, characterized in that the two outputs (2c /, 2e) of the frequency divider (2) with the set or reset input (life. 1IcV of a / K memory element (11) are connected that at least one input (Wb) go and one output (Lindes / K memory element (11) are connected to a comparison stage (12) which is connected to the clock input (Wa) of the / K memory element via a delay stage (13) (11) is connected, with a signal on the clock input (Wa) of the y / C memory element (Wa) of the y / C memory element ( 11) is given, and that the / K-Speichergleid (11) is followed by a third locking stage (4, 5 ) which blocks the output signals when the signal changes at the inputs (Wb, Wc) of the JK storage element (11) until the The signal change at the outputs has been reproduced

The invention relates to a control unit for a self-commutated inverter according to the preamble of Claim 1.

When an inverter is switched off, the inverter transformer is usually approximately demagnetized, since power supplies and consumers are usually switched off almost at the same time while the control of the inverter's thyristors is still pending for a certain period of time can. During operation, the inverter transformer's magnetic induction is powered by a maximum negative operating induction changed to a maximum positive operating induction. Against it If the inverter is switched on again after it has been switched off, induction can be reduced only change from zero to saturation induction. Since the operating induction close to the saturation induction the inverter transformer would saturate with a full half-wool when switched on go and thus absorb very high inrush currents. If when switching off the inverter a commutation short-circuit occurs, the inverter transformer can remain in a remanence that is only slightly below the maximum Operation induction lies. Because it is unpredictable. whether this remanence is positive or negative. must with it be expected that the magnetic induction of the inverter transformer at the first switch-on pulse only in the relatively small range from the Remanence to induction of saturation can end. In order to In this case, the inrush current peaks become even higher.

Various methods are used to suppress the inrush current peaks. From the DE-AS 14 88 911 it is known to have the transformer via a Pre-magnetize auxiliary thyristor and a resistor in a defined manner before switching on. In order to can be assured that when switching on change the magnetic induction in a range between positive and negative saturation induction can and thus the transformer is not controlled in the saturation range.

inverters are commercially available that are im Idle can be switched on via series resistors, which are short-circuited after start-up. Aurh this can reduce the inrush current peaks.

Both of these methods have the disadvantage that for the switch-on additional elements must be provided in the power circuit, which must be dimensioned accordingly and losses in the Condition performance group.

Tax rates for self-commutated inverters according to the preamble of claim 1 are in the following form known: With inverters available in the market, it is known to cut the inverter with one to half The switch-on pulse is shortened to its normal length

to start up. This becomes the voltage of the time area of the switch-on pulse halved and thus TQr prevents most operating cases that the transformer goes into saturation and impermissibly high inrush current peaks occur. As a clock are so-called Saturation clocks are used, but they are quite complex. The frequency of the saturation clock is set via the supply voltage, the stability of which is therefore subject to high requirements. at The start-up and operation of the saturation clock generator can cause asymmetries. Furthermore, there is no defined one Impulse release possible. Rather, the length of the switch-on pulse is set to a quarter wave

From DE-OS 25 16 934 is a tax rate for one known from antiparallel thyristors existing AC power controller with full wave control, in which when using a transformer as a load in the first half-wave of each full-wave packet, a gate control is carried out. For this purpose there is a bistable multivibrator with whose output signal the thyristors controlling high-frequency push-pull oscillator is switched on or off, followed by a delay stage, by which the output signal and dpmit the switching on of the push-pull oscillator compared to the Zero crossing of the alternating voltage is delayed. In the case of inverters, a delay stage would be used to shorten the switch-on pulse quite expensive, since the delay stage to the clock generator would have to be synchronized in order to achieve a defined pulse shortening.

The object of the invention is to provide a tax rate for a self-commutated inverter of the above designed so that the length of the switch-on pulse with good symmetry of the entire Inverter control can be specified in a defined manner.

This object is achieved according to the invention by the characterizing features of claim I.

With the circuit arrangement it is achieved that the switch-on pulse of the tax rate compared to the following Pulses is shortened by a period of time. which is defined by the pulse edge spacing of the clock generator. The length of the first pulse depends on the pulse-pause ratio of the clock generator. The pulse-pause ratio the clock can be adjustable.

The reset input of the memory can according to the features of claim 3 with a die Be connected to the supply voltage of the limit indicator monitoring the tax rate. This becomes a Automatic start-up and shutdown of the inverter depending on the supply voltage. In the event of a drop in the supply voltage, the inverter is automatically switched on and off again gone.

A pulse converter stage can be connected downstream of the outputs of the frequency divider Delayed start of each output signal of the frequency divider. This ensures that the second Thyristor only switches on when the first one blocks. One Such a pulse converter stage can be designed in accordance with the features of claim 5.

A tax rate designed according to the invention is shown in FIG. 1 shown as an example as a block diagram. Of the The power circuit of the inverter is only indicated schematically. One pole of a direct current source 25 is connected to the center cap of the primary winding 26a of a transformer 26. The second pole the direct current source 25 is via a thyristor 9 each

or to connected to the ends of the primary winding 26a. A commutation capacitor 27 is used to delete one thyristor when switching over. The schematically indicated thyristors 9 and 10 are alternately switched to the conductive state by the control set. This causes the core of the transformer 26 is constantly reversed and an alternating voltage is induced in the secondary winding 266

The switching of the thyristors 9 and 10 is controlled by a clock generator 1. The output a of the clock generator 1 is connected to the clock input of a / K flip-flop 2. Set input 26 and reset input 2c of the / K flip-flop 2 are connected to “!” Potential. The / K flip-flop 2 therefore acts as a frequency divider with a division ratio of 2: 1, with the signal change taking place when the output signal of the clock generator 1 has a negative edge. The outputs 2d and 2e of the / K-flip-flop 2 therefore alternate with »! «Signal on. These output signals are fed to the set input 116 or the reset input lic of a further / K flip-flop 11. Each output Hc / or. He of the y / C flip-hop 11 is connected to an input 46 or 56 of an AND gate 4 or 5, which act as a locking stage. The outputs 4c and 5c are connected to the inputs 22a and 23a of a further locking stage consisting of AND gates 22 and J 23.

The output 2tf of the // C-FHp-flop 2 and the output j le of the / K flip-flop 11 are also connected to inputs 12a and 126 of an EXCLUSIVE-OR stage i2. The output 12c of this stage is connected to two further inputs 4a and 5a of the AND gates 4 and 5 and to the input 13a of a pulse generator 13. The pulse generator 13 is connected in such a way that it delivers a pulse at the output 136 in the event of a negative signal edge at the input 13a. The output signal of the output 136 is sent to the clock input Hades / K flip-flops 11, which also switches over when there is a negative signal flank at input 11a.

The control record also contains a signal memory 3, the reset input 36 of which is switched to invert and is connected to a limit value stage 6. delivers the "!" signal as soon as a supply voltage U 'of the control rate applied to input 6a exceeds a certain limit value. The supply voltage U 'of the control set is obtained from the supply voltage U of the inverter by smoothing with an RC-GWeA 30, 31 and stabilization with a Zener diode 32. The input 3a of the signal memory 3 is connected to the output 21c of an AND gate 21, to which the output signal of the limit value stage 6 and the output signal of a pulse generator 20 are fed. The input 20a ilsg Imp-des.-Frjrs 20 is connected to the clock generator 1, the pulse generator 20 then supplies a pulse at the output 206 when the output of the "IAV tgebers 1 of" 0 "changes to" 1 ". The output 3c of the latch 3 is connected to the inputs 226 and 236 of the AND gates 22 and 23, respectively.

The output signals of AND gates 22 and 23 are through pulse amplifiers 18 and 19 respectively Thyristors 9 and 10 respectively supplied.

The function of the circuit according to FIG.] Is explained below with reference to the pulse diagrams in FIG. Dobei are the individual momentum diagrams numbered according to the inputs and outputs of the components.

The first pulse diagram la shows the output signals of the clock generator 1. These output signals are with the frequency divider 2 converted into signals with half the frequency, which are at the outputs 2a and 2e pending and also in F i g. 2 are shown. As - already mentioned, the signal change takes place on the Outputs on the negative signal edge of the output signals of the clock generator I.

The output signals of the frequency divider 2 are not suitable for direct control of the thyristors, n net, since the switch-on process would possibly take place with a full pulse and thus from the input For reasons explained, a high inrush current peak would occur. It must also be ensured that that the second thyristor can only switch on when the first thyristor is safely switched off, d. H. the pulses for different thyristors must have so-called respect distances from one another.

The outputs 2rf and 2 of the divider 2 are connected to the set input 1 \ b or> n to the reset input Hc of the JK flip-flop 11 to form a respectful distance. A signal change at the outputs 2d or 2 of the frequency divider 2 is only reproduced at the outputs Wd or Iiedes / K flip-flops 11 when a negative>·> signal change occurs at the clock input 11a of the JK flip-flop 11. To form a clock signal for the / K flip-flop 11, the input signal at the input 11 b and comparing the output signal at output Hein an EXCLUSIVE-OR gate 12 to one another. This EXCLUSIVE-OR gate 12 supplies the _{"!" Signal at the) n} output 12c as long as the output signals of the JK flip-flop 11 match the input signals at the set or reset input. As soon as a signal change occurs at the inputs 116 or Hc, the output signal at the output 12c of the 3, EXCLUSIVE-OR gate 12 goes to "0", since the outputs of the / K flip-flop 11 do not initially follow this signal change. The transition of the output signal of the EXCLUSIVE-OR gate 12 triggers the pulse generator stage 13, which thereby delivers the pulse of a certain duration shown in FIG. 2 at output 13f. This pulse is fed to the clock input 11a of the JK flip-flop 11. Since the clock input acts on negative tendrils, the output signals of the JK flip-flop 11 are switched over according to the input signals as soon as the pulse of the pulse generator 13 has ended. The signals at the outputs 11 t / and lledes JK flip-flops 11 are thus shifted relative to the input signals by the width of a pulse from the pulse generator 13, as FIG. 2 shows. The output signals at the outputs Wd and lie do not yet have a respectful distance from one another. This respect distance is achieved by feeding the output signals at the outputs lic / and He to an AND gate 4 and 5, respectively, with a further input of the AND gate 4 brw. 5 is connected to the output 12c of the EXCLUSIVE-OR gate 12. By UN D linking these input signals, the outputs 4c and 5c of AND gates 4 and 5 have the output signals shown in FIG of the pulse generator 13 are shifted. The signals at the outputs 4c and 5c thus have the desired to respect distances.

It must now be ensured that the inrush current peaks of the inverter are suppressed. For this purpose it should be ensured that the first pulse fed to the inverter is only half the length and thus only half the voltage-time area of the remaining pulses. The output signals of AND gates 4 and 5 are therefore fed to a further locking stage, which consists of AND gates 22 and 23. The AND gates are enabled as soon as output 3c of memory 3 has an "I" signal. Output 3c of the memory 3 is switched to the "!" State via the AND gate 21 as soon as the supply voltage U 'of the control unit has reached a limit value. exceeded and the clock 1 emits a positive pulse, which is transmitted to the AND gate 21 with de :: j pulse generator 20. It is thus achieved! That the output signals of AND gates 4 and 5 are released as soon as the first positive pulse edge of the clock generator 1 occurs when the supply voltage of the control unit is sufficient. The frequency divider 2 which supplies the control signals, however, responds to negative pulse edges. The first pulse begins with a negative pulse edge of the clock generator 1, but is only released with the next positive pulse edge of the clock generator 1. In the example given, the pulses are symmetrical and the division ratio of the frequency divider 2 is 2: 1, so that the output pulses of the frequency divider 2 are half as long as the pulses of the clock 1. This means that the first pulse is only half the length of the has other pulses. In the example according to FIG. 2, the first half-length pulse is available at the output 23c of the AND gate 23.

The supply voltage U 'of the control set follows the supply voltage U of the inverter with a delay because of the smoothing element 30, 31. By releasing the control pulses with the output signal of the limit value transmitter 6 it is achieved that the inverter is automatically started up with a delay after its supply voltage L / is switched on and is shut down again with a delay when its supply voltage U is switched off.

The ones at the outputs 22c and 23c of the AND gates 22 and 23 pending impulses therefore have a stock of respect and the starting process is with a quarter-wave is initiated, so that these pulses after amplification to control the thyristors 9 and 10 can be used.

With the circuit explained, the requirements for a control rate for an inverter are met are to be provided, namely start-up with a shortened pulse, if necessary while maintaining a respectful distance between the impulses, in a simple manner. In particular, the inverter can be started without a Inadmissibly high current peaks are reached without additional elements being provided in the power circuit have to. It should be pointed out that, in contrast to known circuits, this circuit the length of the first impulse on start-up can be freely selected by adjusting the pulse-pause ratio of the clock 1 changed. If you z. B. makes the pulse-pause ratio smaller, occurs relative to entire period the positive edge that enables the control signal, only later, so that the first Impulse becomes shorter.

Since the clock generator is independent of the downstream stages to shorten the first pulse and works to create a respectable community, can this very easily and with high frequency stability

being constructed. It is possible in a simple manner to have a voltage that is independent of the supply voltage To achieve frequency. The tax rate is released with a delay after the inverter supply voltage has been established. Likewise, the Tax rate switched off with a delay when the inverter supply voltage drops.

For this purpose 2 sheets of drawings

Claims (1)

Patent claims: 1. Tax rate for a self-commutated inverter with a transformer alternately fed via at least two thyristors and magnetized alternately in one and the other direction, with a clock generator that determines the frequency of the inverter’s ignition pulses and with a device for shortening the duration of the first pulse of the output voltage in the exchange _{| 0} selrichters after power gekennzeichne tdurch following features: