DE2832269C2 - Monolithic integrated circuit for the horizontal deflection of television sets and their operating circuit - Google Patents

Description

The invention relates to a monolithically integrated circuit for the horizontal deflection of television sets according to the preamble of claim 1.

State of the art

In the journal "IEEE Transactions on Consumer Electronics", August 1977, pp. 311-325, one is monolithic integrated circuit for vertical deflection in televisions described, in which the vertical tilting pulse not, as has long been the case, from the mixture of horizontal and vertical synchronizing pulses contained in the broadcast television signal is obtained, but from a line-frequency signal by frequency doubling and subsequent frequency division is generated, the divider being equal to the number of lines of a full image is (CCIR standard 625 lines, American Standard: 525 lines). The advantage of this type of vertical tilting pulse generation is in particular the better insensitivity to noise with weakly incident transmitters and in the better temporal mutual fixation of the two fields of a full image, which is due to the frequency doubling mentioned is due.

Also in DE-OS 24 49 534 and DE-OS 26 57 940 such, also as digital vertical synchronization systems designated arrangements described. From a preliminary data sheet from Mullard from February 1977 for the monolithic Integrated circuit TDA 2571 with the designation "Horizontal Synchronization and Vertical Divider" goes Finally, it emerges that the generation of the signal mentioned with twice the line frequency is also already in an integrated circuit for the horizontal deflection of television signals can be included.

In the technology of radio receivers it has been known for a long time, the so-called silent voting to apply, d. H. during the tuning process the sound channel for the incoming more or to block less noisy signals, including generally one taken from the demodulator DC voltage is used, see H. Pitsch "Textbook of radio reception technology", 3rd edition, Batid II, Leipzig 1960. pp. 843-851.

According to a request by the German Federal Post Office, this type of breastfeeding coordination should now be used in particular TV sets suitable for cable television are provided so that noisy signals, but especially those received signals that are not television signals do not result in sound reproduction to lead. This requirement is based on the fact that in the frequency ranges intended for cable television there are also channels that are not kept by cable TV stations but are subject to mutual secrecy Radio services are busy.

There are also conventional televisions on the market that already have the mentioned breastfeeding adjustment is built in, for which the term »muting« is common.

task

The object of the invention defined in claim 1 is that from the mentioned data sheet

to train known monolithic integrated circuit in such a way that the intended inclusion of the known muting circuit does not have an additional output connection of the monolithic integrated circuit requires, since the number of such output connections is known due to the predetermined Crystal surface and edge length as well as aes provided standardized housing type is limited

Presentation of the invention

to

The invention will now be explained together with exemplary embodiments and advantageous configurations the figures of the drawing explained in more detail

F i g. 1 shows the block diagram of the monolithic integrated circuit according to the invention,

F i g. 2 shows the operating circuit for the monolithically integrated circuit according to FIG. 1 and their further interconnection with the circuit parts of the sound channel and the vertical deflection circuit of a Television set,

F i g. 3 shows the course of the blocking signal and the signal with twice the line frequency,

F i g. 4 shows a first advantageous embodiment for the superimposition circuit,

5 shows a second advantageous embodiment for the superimposition circuit, and

F i g. 6 shows a third advantageous embodiment for the superimposition circuit.

In Fig. 1, the monolithic integrated circuit 1 is schematically indicated by the double border, and these are essential for the invention Circuit parts within this border are indicated in a block diagram. It goes without saying that, without deviating from the basic idea of the invention, still further required for television sets Circuit parts can be included in the monolithic integrated circuit 1. On the representation Such circuit parts are, however, dispensed with since they are familiar to every television specialist.

The so-called image blanking synchronous signal mixture is supplied to the monolithically integrated circuit 1 via the terminal 11, So the BAS signal is fed in, which in the case of color televisions also has the Contains color information and is referred to there as a composite signal. This arrives at connection II BAS / FBAS signal to the amplitude filter 2, by means of which the horizontal-vertical synchronous pulse mixture is won. This is on the one hand the output 12 and on the other hand the phase comparison circuit 3 supplied, which together with the voltage-controlled oscillator 4 is a conventional phase-locked Loop (in English: phase-locked loop) forms.

The output signal of the voltage-controlled oscillator has the required line frequency Iz (CCIR standard: fz = 15.625 kHz) and is supplied on the one hand to the output terminal 14 of the monolithic integrated circuit 1 and on the other hand to the frequency doubler circuit 6. Instead of a frequency doubler circuit, an independent ω oscillator can of course also be used. Jie generates the required double line frequency 2fz. The course of the output signal i / 6 of the frequency doubler circuit 6 is shown in FIG. 3b shown.

The monolithically integrated circuit 1 also contains the circuit 5 known per se, the so-called muting circuit, which generates the blocking signal US for the audio channel. The "" blocking signal US is fed together with the signal i / 6 with twice the line frequency 2fz to the superimposition circuit 7, the output signal of which is fed to the output terminal 17 as a total signal U 7 Oscillator 4 and the pulses occurring at the output of the amplitude filter 2 and that generates the two DC voltage levels i / 51 (level for playback mode of the audio channel) and i / 52 (level for muting the audio channel) having blocking signal US , see F i g. 3a.

The F i g. 2 shows the operating circuit specified in claim 2 for the monolithic integrated circuit 1 and schematically the further interconnection with the circuit parts of the audio channel 9 and the vertical deflection circuit 8. The output terminal 17 for the total signal t / 7 is on the one hand via the diode D. connected to the input 912 of the audio channel IF amplifier 91 serving for blocking and, on the other hand, coupled to the input 82 of the vertical deflection circuit 8. In addition, the output connection 12 is connected to its image pulse trigger input 81, and the image deflection coils or the output amplifier connected upstream thereof can be connected to its output 89.

When the diode D is operated in the forward direction, the forward voltage i / 3 drops. In FIG. 2 it is assumed that the monolithic integrated circuit 1, the vertical deflection circuit 8 and the sound channel 9 operate with at least one positive operating voltage. Therefore, the anode of the diode D is connected to the output terminal 17 and its cathode is coupled to the blocking input 912 of the audio channel IF amplifier 91, while its signal input 911 is via the conventional ceramic filter 10 to filter out the audio carrier frequency (CCIR standard: 5.5 MHz) from the BAS / FBAS signal is connected to the terminal 11 of the monolithic integrated circuit 1. The input 912 serving for blocking, at which the operating point potential UO is set in the unblocked state via the negative feedback resistor 915 and which is blocked in terms of AC voltage via the capacitor 102. is finally connected to the ceramic filter 10 via the resistor 101 and to the circuit zero point via the capacitor 102.

The structure of the sound channel 9 shown in FIG. 2 is of a conventional type and is only shown for the sake of completeness. The already mentioned audio channel IF amplifier 91, which is a differential amplifier or operational amplifier, especially if the audio channel 9 consists of a monolithically integrated circuit, feeds with its output the demodulator 92, whose output signal is amplified by means of the audio amplifier 93 and the loudspeaker 94 is supplied. The operating point potential i / 0 present at the input 912 serving for blocking in the unblocked state is shifted by the total signal U 7 in such a way that it is no longer amplified, that is to say blocked.

A first preferred embodiment of the superimposition circuit 7 is shown in FIG. It contains the reference voltage source 70 for emulating the operating point potential UO of the audio channel IF amplifier 91, which is present in the unlocked state, the first transistor 71 controlled by the locking signal i / 5, the second transistor 72 controlled by the signal i / 6 at twice the line frequency 2fz, the Emitter follower transistor 73, which with the operating voltage U

connected first constant current source 75 and serving as the emitter resistor of the emitter follower second Constant current source 76.

The emitter of the first transistor 71 is at the circuit node, and the collector is connected to the reference voltage source 70 formed from the series connection of two diodes, the connection of which is remote from the collector via the first constant current source 75 to the operating voltage source U and directly to the collector of the second transistor 72 and is at the base of the emitter follower transistor 73. The emitter of the second transistor 72 is connected to the circuit zero point.

The transistor 71 is switched on and off by the blocking signal i / 5, that is, the level (751 according to FIG. 3a blocks the transistor and the level £ 752 makes it conductive first transistor 71 no current, so that the reference potential LO cannot develop at the end of the reference voltage source 70 facing away from the collector. In this case, the first constant current source 75 thus acts as a working resistance of the second transistor 72, and its collector potential, which, around the base-emitter The voltage drop of the emitter follower transistor 73 is reduced, also appears at the output terminal 17 as a total signal (77, jumps depending on the signal (76 with twice the line frequency Kz between the collector-emitter saturation voltage of the second transistor 72 and that reduced by the voltage drop at the first constant current source 75 Value of the operating voltage t / back and forth, in Fig. 4b these both correspond n values correspond to levels U 70 or (7 72.

If, however, the level (752 of the blocking signal (75) is at the base of the first transistor 71, this is Transistor conductive, and it can be the reference voltage (70 form, on which now the collector of the second transistor 72 and the base of the emitter follower transistor 73 held, i.e. clamped. Depending on the signal (76, the Collector voltage of the second transistor 72 only between its collector-emitter saturation voltage and the reference voltage (70 back and forth. Which two voltages in Fig. 4b the levels (770 and (771 correspond.

Thus, the level (771 ( "non-silent level") at the output terminal 17 of the monolithic integrated circuit 1 is present, the diode g in the operating circuit of F i. 2 locked D and the sound channel 9 in its unlocked state. If, however, at ÄusgangsanschiuS Yi the level i / 72 ("Siummpegei"), the diode Din F i g. 2 is conductive, and the current required to shift the operating point potential of the audio channel IF amplifier 91 into the blocking range flows.

In Fig. 5, another preferred embodiment for the overlay circuit 7 is shown as at the arrangement according to FIG. 4a are the first transistor

71, the second transistor 72, the emitter foiger transistor

72, the reference voltage source 70 and the second constant current source 76 are provided. The first constant current source 75 according to FIG. 4a is missing, however. The collector of the second transistor 72 is inconsistent with the Base of the emitter follower transistor 73 connected, but it is connected to the input of the resistor 77 Current translator circuit 78, which is preferably a conventional current mirror circuit, the output with the emitter of the transistor 79 complementary to the transistors 71, 72, 73 is connected. The base this complementary transistor is connected to the reference voltage (70 and via the further constant current source 80 at circuit zero, while its collector with the base of the emitter follower transistor 73 is connected.

The current translator circuit 78 consists of the transistor 781, the collector of which is connected to its base, and the transistor 782, the base-emitter path of which is connected in parallel with that of the transistor 781, the two emitters being connected to the operating voltage U. The ratio of input to output current can be determined in such current converter circuits by appropriate

set measurement of the base-emitter-PN-junction of the two transistors; in the case of the current mirror circuit with a transmission ratio of 1: 1, these areas are therefore equal to one another. the Transistors 781,782 are also complementary to transistors 71,72,73.

When the first transistor 71 is blocked, again no reference voltage (70 can develop at the base of the complementary transistor 79. In this case, when the second transistor 72 is blocked by the signal (76 with twice the line frequency 2fz) , no current flows in the current translator circuit 78 and therefore also does not flow in the complementary transistor 79 and to the base of the emitter follower transistor 73, so that the total signal (77 at the output terminal 17 is kept practically at the potential of the circuit zero point by the second constant current source 76. On the other hand, if the second transistor 72 is made conductive, then current flows in the current translator circuit 78, and the complementary transistor 79 is driven into saturation, as a result of which its collector potential is practically equal to the operating voltage (/ (only reduced by the collector-emitter saturation voltage) the bas is-emitter forward voltage of the emitter follower transistor 73 is reduced. Thus, the output voltage (77 with the first transistor 71 blocked, as in the arrangement according to FIG. 4a, assumes the two levels (/ 70, (7 72.

If, on the other hand, the first transistor 71 is made conductive by the level (752 of the blocking signal (75), then forms at the base of the complementary transistor 79, the reference voltage (70 from, so that when conducting second transistor 72 the collector voltage of the complementary transistor 79 no longer up to almost Operating voltage (7 can shift, but only up to the reference voltage (70 plus base-emitter voltage of complementary transistor 79 minus collector-emitter saturation voltage of this Transistor. The output voltage t / 7 thus again assumes the level (771 according to FIG. 4b Constant current source 80 ensures that the complementary transistor 79 in the absence of a reference voltage (70 is supplied with base current in its conductive state.

In Fig. 6 is a third preferred embodiment of the overlay circuit 7, with special parts also in the embodiments according to FIGS. 4a and 5 can be used. Thus, the reference voltage source 70 does not consist of a chain of diodes connected in series (the number of two diodes shown in FIGS. 4a and 5 is not mandatory), but from a circuit known per se with which

the base-emitter voltage of a transistor can be multiplied, so to speak. For this purpose, the two resistors 702, 703 are assigned to the transistor 701 in such a way that, on the one hand, they form a voltage divider and, on the other hand, are connected in parallel to the base-collector path and the base-emitter path. The voltage at the collector of this transistor is thus equal to the product of the base-emitter voltage and the quotient of the total voltage divider resistance and the base-emitter parallel resistance 703. This reference voltage source can thus also be used in the arrangements according to FIGS. 4a and 5 can be used instead of the diodes shown there.

In Figure 6 it is also shown that instead of the emitter follower 73 also a complementary transistor 79 according to FIG. 5 comparable complementary transistor can be used as emitter follower transistor 73 in connection with the current converter circuit 78. The emitter of this transistor is in turn connected to the output of the current converter circuit 78, that is to say the collector of its transistor 782 , while the collector of the complementary transistor 73 is connected to the circuit zero point.

Since the output power of such complementary transistors, which are lateral PNP transistors when the operating voltage is positive in bipolar integrated circuits, is limited, FIG. 6 the further emitter follower transistor 74 is provided, the current gain of which is predetermined to a certain value in that it has two collectors, one of which is connected to its base. The further emitter follower transistor 74 is again of the same conductivity type as the transistors 71, 72 and 701. This further emitter follower transistor 74 can also be used in the embodiments according to FIGS. 4a and 5 can be provided either instead of the emitter follower transistor 73 or in addition to it, if necessary. Finally, in the embodiment according to FIG. 6, the first constant current source 75 according to FIG. 4a is again provided. The mode of operation of the circuit according to FIG. 6 corresponds essentially to that of the arrangement according to FIG. 5 with the only difference that the base of the additional emitter follower 74 is now connected to the emitter of the complementary transistor 73 and thus follows the potential occurring there, while in the Arrangement according to FIG. 5 the base of the emitter follower transistor 73 is connected to the collector of the complementary transistor 79.

The three preferred exemplary embodiments according to FIGS. 4a, 5 and 6 for the superposition circuit 7 has in common that the superposition circuit 7 contains a reference voltage source 70 for the simulation of the existing in the unlocked state working point potential UO of the audio channel IF amplifier 91, which via the collector-emitter path of one of the blocking signal US controlled first transistor 71 is connected to the circuit zero point, that the superimposition circuit 7 also contains a second transistor 72 controlled by the signal t / 6 with twice the line frequency 2 />, the emitter of which is connected to the circuit zero point and whose collector is connected to the output of the Reference voltage source 70 coupled base of an emitter follower transistor 73 is coupled in such a way that this base is dependent on the levels t / 51, C / 52; L / 61, U 62 of the blocking signal U5 and the signal t / 6 with twice the line frequency Kz is applied to the potential of the circuit zero point or to the reference voltage UO or approximately to the operating voltage U.

For this purpose 3 sheets of drawings

Claims (4)

Patent claims: 1. Monolithic integrated circuit for the horizontal deflection of television sets, which contains a stage for the generation of a circuit for the vertical deflection supplied signal with twice the line frequency, characterized in that a known circuit (5) ("muting"), the a blocking signal (US) for the audio channel (9) in the case of very noisy television signals or in the case of such received signals that are not television signals, is included in the monolithic integrated circuit (1) that the blocking signal (U 5) and the signal ( U 6) are fed to a superimposition circuit (7) at twice the line frequency (2 / z) and that its output signal is the overall signal! (U 7) is fed to an output terminal (17) of the monolithic integrated circuit (1). 2. Operating circuit for a monolithically integrated circuit according to claim 1, characterized in that the output connection (17) for the overall signal ( U7) via a diode (D) to the input (912) of the audio channel IF amplifier (91) serving for blocking ) and is coupled to an input (82) of the vertical deflection circuit (8). 3. Monolithic integrated circuit according to claim 1 for an operating circuit according to claim 2, characterized in that the level (UTi) of the overall signal (U7) when the audio channel (9) is unlocked is selected such that the diode (D) in the direction of the blocking Serving input (912) of the audio channel IF amplifier (91) is blocked so that the level (U7 \) of the total signal (U7) with the audio channel blocked is greater than the sum of the operating point potential (UO) of the audio channel IF in the unlocked state Amplifier (91) and the forward voltage (U3) of the diode (D) and that the mean current flowing to the input (912) serving for blocking is greater than or equal to that direct current which is the operating point potential (UO) of the audio channel IF amplifier (91) moves into its restricted area. 4. Monolithic integrated circuit according to claim 3, characterized in that the superimposition circuit (7) contains a reference voltage source (70) for the simulation of the operating point potential (UO) of the audio channel IF amplifier (91) present in the unlocked state, which is via the collector -Eitter path of a first transistor (71) controlled by the blocking signal (US) is connected to the circuit zero point, so that the superimposition circuit (7) also has a second transistor (72) controlled by the signal (U6) at twice the line frequency (2 / z) whose emitter is connected to the circuit zero point and whose collector is coupled to the base of an emitter follower transistor (73) coupled to the output of the reference voltage source (70) in such a way that this base depends on the levels (t / 51, U52; L / 61, U62) of the blocking signal (U5) and the signal (U6) with twice the line frequency (2 />) to the potential of the circuit zero point or to the reference voltage (UO) or approximately to the operating voltage (U) ge \ eg \ . 2. Monolithic integrated circuit according to claim 4, characterized in that the emitter follower transistor (73) another emitter follower transistor (74) with two collectors is connected downstream, one of which is connected to the base.