DE2828388C2 - Method and device for digital control of an m-phase pulse-width modulated thyristor DC converter - Google Patents

Description

that the counting unit for clock pulses contains a single clock counter (2), the outputs of which are connected to the inputs of a decoder (7) for undelayed pulse trains, that the switching unit contains a single reversing counter (9),

dal3 the output of each decoder (3,4,5 and 6) the door delayed pulse trains is also connected to one of the m information inputs (13, to 13 ,,,) an adaptation unit (14), whose control inputs m to the m control outputs (19, to 19 ,,,) of the reversing / a'hlers (9) are connected, and that the adaptation unit (14) m groups (15, 16, 17, 18) each with m AND gates (15, -15 ,; 16, -16 ,; 17, -17 .; 18, -18,) contains.

- one input of each AND element of a group (15-18) is connected to a control output (2Ο1-2Ο4) of the reversing counter (9) (first control _{output (2O 1} ) to the first (15), second control output (20 _; ) to the second group (I61 etc.).

- The outputs (13 | -13 ₄ ) of the decoders (3-6) are connected to the other inputs of the AND elements (first decoder (3) to the first AND elements (15, -18,) of each group Decoder (4) with the second AND _{gates (IS 2 -Ie 2} ) etc.) and the outputs of the AND gates of _{the first group (15, -15 4} ) directly the outputs (19, -19j) which control the thyristors Represent adjustment unit (14), and

- the outputs of the further group (16-18) being connected cyclically to these outputs (19, -19.,) (first AND element (16 |) of the second group (16) to / «- th output ( 19j at m = 4), second AND element (16 _{:) of} the second group (16; to the first output (19,). M-ies AND element of the second group (16) to the (ml) -th output etc., first AND element (17,) of the third group (17) to the (ml) -th output, second AND element (17 _{:) of} the third group to the m-th output etc.).

The invention relates to a method and a device for digitally controlling a w-phasigcn Pulse width modulated thyristor DC converter of the known from SU-PS 4 24 290, in the generic term of claims 1 to 2 described type.

As is well known, in order to control the thyristors of thyristor direct current controllers, the first and main thyristors of each phase must be supplied with undelayed and delayed sleuer pulse trains, which is why the pulse width t of the main thyristors corresponding to the current carrying time changes. In the case of multiphase DC choppers, in order to reduce the pulsations of the current in the supply source and the load, at the same time as the generation of delayed and undelayed pulse trains, the use of each subsequent phase of an m-phase thyristor DC chopper is shifted by - T compared to the previous phase, where m

III

the number of phases and T the pulse period of the controller.

From "DC pulse converter". »Energie» publishing house. Moscow, 1974, is a method for digital control an m-phase pulse-width modulated thyristor DC converter known, in which the pulse width of the thyristors of each phase in the entire setting range by supplying delayed and ungorted pulse trains from the corresponding control channel simultaneous delay in the use of each phase

by - T is changed.

The setting range Φ is the time period during which the pulse width 1 of the thyristors or the duty cycle γ is adjusted, which is equal to the ratio of the pulse width 1 of the thyristor / ur CuIs period T , namely

^y Τ '

The maximum setting range is equal to O < Φ <T. The delayed and undelayed pulse sequences are generated by changing the state of the flip-flops of each control channel. Each control channel changes the pulse width / thyristor of a phase in the entire setting range, which is why each channel also generates a pulse of a certain duration

a time shift by - T is repeated.

HI

Each control channel ensures control of the pulse width ι in the actuating zone ψ, which represents a time during which the current lead time is controlled by a channel. With the method mentioned, the setting / one φ of each control channel is equal to the setting range Φ. With this control method it is necessary to generate all possible combinations of the states of the flip-flops in each channel.

each of the device known from SU-PS 4 24 290 with which the method described can be carried out. the switching unit contains m reversing counter; their control inputs are connected to the control outputs of the control unit. The total unit of clock pulse counter, decoder and reversing counter represents a control channel.

In the known device, the decoders. Clock and reversing counters for all control channels, the generation of a pulse train in the entire setting range ensure, d. H. all combinations of the states of the circuit elements allow what an increase in the number of elements in the decoders, clock and reversing counters, and thus the reliability and reduces the efficiency of the control unit and reduces the power requirements and dimensions enlarged.

The invention is based on the object of developing the generic method and the generic device so that the adjustment zone of each control channel without narrowing the adjustment range door the transmission time or pulse width t of the thyristors by a corresponding switchover of the control channels from one phase to the other using a lower one Number of clock and reversing counters and a smaller number of decoding elements for different pulse trains can be reduced.

According to the invention, this object is achieved by the characterizing features of claim 1 b / w. 2 solved.

The invention ensures an increase in reliability and efficiency, a reduction the power consumption, the dimensions and the costs and an improvement in the control quality Reduction of the influence of the parameter spread of elements, the number of which is reduced.

The exemplary embodiments shown in the drawing are explained below. It shows

1 shows a block diagram of a device for digitally controlling the thyristors of an m-phase pulse-width modulated Thyristor DC converter,

Hg. 2 is a basic circuit diagram of a decoder for a delayed pulse train,

lig. 3 is a basic circuit diagram of a decoder for another delayed pulse train,

I i ü 4 timing diagrams for the states of the elements egg linrichlung and

I ig. 5 is a diagram for connecting the control cannula to the phases of an m-phase controller.

I ig 1 / like a block diagram of a device for the digital control of an m-phase (m = 4) pulse-width-modulated thyristor DC converter, in which a clock generator 1 representing a relaxation generator is connected to a counting unit for clock pulses in the form of a single clock counter 2. The outputs of the clock counter 2, the number of which is equal to In (n - number of digits of the clock counter 2), are connected to the logic inputs of a decoder 3 for a first delayed pulse train, a decoder 4 for a second delayed pulse train, and a decoder 5 for a third delayed pulse train Pulse train and a decoder 6 for a fourth delayed pulse train and connected to the inputs of a decoder 7 for undelayed pulse trains, the outputs 8 to 8 ". (in = 4i. The decoder 7 is used to generate a sequence of undelayed pulses by separating off from each other shifted by - T and determined, in in

Clock counter 2 written code combinations corresponding pulses. The outputs 8, to 8 _; of the decoder 7 are connected to the main thyristors of the respective phases of an m-phase controller, not shown. The outputs of a reversing counter 9 serving as a sound unit are connected to the information inputs of the decoders 3, 4, 5 and 6, which are used to select binary code combinations that correspond to the first, second, third or fourth shifted pulse train, the entirety of which is an entire pulse train on Represents the output of the clock generator 1. In addition, the decoders 3, 4, 5 and 6 are provided for comparing code combinations arriving at their information and logical inputs.

The summation input 10 and the subtraction input U of the reversing counter 9 are connected to the sleuer outputs of a control unit 12 designed, for example, in accordance with SU-PS 3 10 895. The information inputs 13, 13 to 13 ″, (m = 4) of an adaptation unit 14 are each to the outputs of the decoders 3, 4, 5 and 6 of the first, second, third b / w. fourth shifted pulse train connected.

The clock generator 1, the clock counter 2, the decoder 7 and one of the decoders 3, 4, 5 or 6 together constitute a control channel. Each control channel has two outputs: in the first channel the outputs 8 and the decoder 7 are used for an undelayed pulse train and the output of the decoder 3 for the first delayed pulse train, in the second channel the output 8 _: and the output of the decoder 4 for the second delayed pulse train, while in the third and fourth channels as outputs of the outputs, and the output of the Decoder 5 b / w. the output 8 ₄ and the output of the decoder 6 are used.

To ensure a time-shifted - T

When the control channels are connected to the respective phases of the m-phase controller, the adaptation unit 14 is provided, the m groups 15, 16, 17 and 18 each with m AND gates 15, up to IS ₄ , 16, up to 16 ₄ , 17, up to 17 , and 18, to I84 (m = 4).

The adaptation unit 14 has m outputs (19, to 19j) which are connected to the quenching thyristors of the corresponding phases of an m-phase controller. The m control inputs of the adaptation unit 14 are connected to the control outputs 20 to 20 _{4 of} the reversing counter 9.

One of the inputs of the / th AND element of each group is connected to the output of the decoder of the / th

10

20th

shifted pulse train connected (/ = 1,2

/Hi. So are /. B. one of the inputs of the logical AND gates 15 |. 16 ,. 17, and 18, at the output of the decoder 3 door, the first shifted pulse train and one of the inputs of each of the AND elements 15 ₂ , 16 .. 17 .. 18 ^, one of the inputs of each of the AND elements 15., 16, 17, and 18, as well as one of the inputs of each of the AND gates 15 ₄ , 16 ₄ , 17 ₄ and 18 _{4 are connected} to the outputs of the decoders 4, 5 and 6, respectively. The other inputs of the AND gates 15 to 15 _{4 of} the first group 15, the AND gates 16, to 16 _{4 of} the / broad group 16, the AND gates 17, to 17 _{4 of} the third group 17 and the AND gates 18 to 18 _{4 of} the fourth group 18 are at the first, second, third b / w. fourth control output 20, connected to 2O _{4 of} the Revcrsicr / counter 9.

In the first group 15, the / th AND element 15 is on the menu output 191 of the adaptation unit 14 is connected. The total number of outputs 19 of the adaptation unit 14 is equal to / h, that is to say in the case in question four. The output of the first AND gate 16, 17, and 18, in the / vth of the remaining groups 16, 17 and 18 Table I.

(/ »2. 3 in) represents the (m - ρ + 2) -th output 19

of the adaptation unit 14. The AND element 16, the / broad group 16 is therefore connected to the fourth output 19 _{4 of} the adaptation unit 14, the AND element 17, the third group 17 to the third output 19i and the AND element 18, the fourth group 18 to the second output 19 _: connected.

In the /> - th of the remaining groups 16, 17 and 18 are the m-th, ie the fourth AND elements 16 ₄ , 17 ₄ , 18 ₄ at the (w - /)) th output 19 "," the adaptation unit 14 connected, ie in the second group i6 the output of the AND element 16 _{4 is} the third output 19 of the adaptation unit 14, while in the third group 17 and in the fourth group 18 the outputs of the AND elements 17 ₄ and 18 ₄ serve as outputs 19 and 19 of the adaptation unit 14.

In addition, in the second group 16 the outputs of the AND elements 16 and 16 serve as outputs 191 and 19 _{2 of} the adaptation unit 14 and in the third group 17 the outputs of the NAND elements 17 and 17 serve as outputs 19 , and 19 _{4 of} the adaptation unit 14.

The output of the m-th AND element in the /? Th group represents the (mp + D-th output of the unit 14, in the m-th group the output of the / v-th AND element occurs as (k + l) -th output of the matching unit 14, while in the λ, -th group, the outputs of the / -th and the./ -th AND element the {in + i - k + iHen or (j - k + ij-icfi represent the output of the adaptation unit 14, where k = 2, 3, ...,

mean.

In I-ig. 2 shows a basic circuit diagram of the decoder 3 for the first delayed pulse sequence, the logic inputs of which are connected to the outputs of the clock counter 2 and the information inputs of which are connected to the information outputs of the reversing counter 9. The decoder 3 is designed in the form of an OR element 21, the inputs of which are connected to the outputs of a decoding matrix 22 designed for m- 4 and π = 4, where η is the number of flip-flops 23 and 24 of the clock counter 2 and the Reversing counter 9 is. The decoding matrix 22 provides for a change in the

Pulse width t of the thyristor within the limits 0 <t <- T, ie in the setting zone φ ,.

The rails 3, 3 ₍ , 3 _? And 3-, which are referred to as Yeriikalschienen, are to the /. Outputs of the respective flip-flops 23 of the clock counter 2 and the 0 outputs of the same flip-flops 23 are to the vertical rails 3 ₃ , 3 ₄ , 3 "and 3" connected. The number of hori / ontalschicnen 3 to

2 "

3i, | is equal - that is, in the given case four, what the m

four setting stages of the flip-flops 23 and 24 corresponds. The vertical rails 3 ". 3 | ,, 3,., And 3, <are to the L outputs of the flip-flops 24 of the reversing counter 9 and the vertical rails 3 "" 3, _: , 3 "and 3," to the 0 outputs of the same flip -Flops 24 connected. The horizontal rail 3 | 7 is the clock to the counter 2 and the reverse counter 9 connected to the vertical rails 3 ,, 3j, 3 ₆ and 3 or _S 3 ', _3;, 3, ₄ and 3 ". via diodes 25, which corresponds to the first state recorded in the known transition table I.

State Flip flops 23 or 24 III iv nummcr 1 Il 0 0 0 0 0 0 0 1 1 0 0 0 2 0 1 0 ü 3 1 1 1 0 4th 0 0 1 0 5 1 0 1 0 6th 0 1 1 0 7th 1 1 0 I. 8th 0 0 0 1 9 1 0 0 1 10 0 1 0 1 11th I. 1 1 1 12th 0 0 1 1 13th 1 0 1 1 14th 0 1 1 1 15th 1 1 0 (.1 16 0 0

The horizontal _{rails 3, 8} , 3,, and 3 _: "of the decoding matrix 22 are connected to the corresponding vertical rails (see FIG. 2) via diodes 25 _: -. 25, and 25 are connected in accordance with the second, third and fourth states of Table I.

The decoder 4 for the second delayed pulse train, the basic circuit diagram of which is shown in FIG. 3, is designed similarly to the decoder 3 described above with four setting stages. The adjustment zone φ created by the second control channel including this decoder 4 changes within the limits of 0.25 y <q> ₂ έ 0.5 γ.

The vertical rails 4 ₉ to 4, "from the reversing counter 9 are to the horizontal rails 4, - to 4 _; "Via the diodes 25 to 2S ₄ in the same way as when decoding (Fig. 2), ie corresponding to the states 1 to 4 of Table I and the vertical _{rails 4, to 4 S} from the clock counter 2 to the horizontal rails 4, - via the Diodes 25 to 25 _{4 are connected} according to the states 5, 6, 7, 8 of Table I.

7 8

The decoding matrix / s of the decoders 5 and 6 .. j ^ j- ■, _t * j * ■, ■ ι. ■ 1

(I, μ 1> are different from the above beschriebe- ^{addressed, the} decoder 3, 4, S and 6, ethene to 0 -

non decoding matrices 22 (Fig. 2 and 3) in that the (see diagrams 8, and 3.8 _: and 4.8; and 5 and 8, and 6

(not shown in Fig. 1) vertical rails of the deco (Fig. 4)) moved. When the first arrives, the

ilierers 5 from the clock / iihler 2 to the horizontal rails 5 beginning of the control of the leading Zuslandcs of the Th> -

according to the states 9, 10, 11, 12 of the table I ristors corresponding control pulse is to control

and the vertical rails of the decoder 6 from the clock output 20, the reversible counter 9 a potentiul

/ ahler 2 on the horizontal rails according to the signal (see diagram 20, in ed. 4). that one of the

States 13, 14, 15 and 16 of the table are long-closed inputs of each AND element 17, 17>. 17 _; and 17th the

are. The 10 first group 17 connected to the reversing counter 9 is supplied. At the other L-ingang

Venical circuits of the decoders 5 and 6 are connected to those of each of the same AND gates 17, 17 _; , 17th and

llori / ontal rails as well as in the decoding! 3 17 ₄ impulses come from the outputs of the Deeodie

isnd 4. d. H. in accordance with the states 1, rer3,4,5 and 6, which is why at the outputs 19 to 19.

2. 3 and 4 of Table 1 connected. , _. ,. ,. . .. , 1 _, _. , ",. , "

The setup works as follows. The clock pulse, 5 of the unit 14 in time at _T Hs. Diagrams 19 to 19.

follow with the frequency F = J- 2 " (where η is the number of pulses in Fig. 4) offset.

Flip-flops 23 (Fig. 2. 3) or 24 and / the Arbeitsfre- It is the first connection of the four control channels.

quen / the thyristors are) comes from the clock generator each has two outputs (see above) to which

lor I (see diagram in Fig. 4) to the input of the clock - corresponding phases of the m-phase thyristor-

/ selector 2 (Fig. 1). which is why the states of the flip-pulse converter 20 are guided via the adaptation unit 14

Flops 23 (FIGS. 2 and 3) of the clock counter 2 change. In the diagrams /, to ι- (Fig. 4) are the PuIs-

the outputs of the flip-flops 23 come the information width t of the main thyristors representing pulses glci-

lion in the form of a binary code to the logical input rather duration.

commonc the decoders 3.4, 5 and 6 (Fig. 1) and each of the control channels changes the pulse bridge / the

Decoder 7. The decoder? for the instantaneous 25 main thyristors of the corresponding phases in the

Pulse sequence separates ^G offset by 1 T ; ^en * ^{en v} ?? ° "'r ⁰ " ²⁵ *. ,

4 To the extent that the control pulses at the summa-

Pulses (see diagrams 8 |, 8;. 8, and 8 ₄ in Fig. 4). tion input 10 (Fig. 1) of the reversing counter 9 arrives

(Here and in the following, the number corresponds to the slide, if a change is made to the number in the flip-flops 24

gram of the position of the element in the drawing 30 (Fig. 2, 3) according to the table below

gen.) The first of the code combinations. The line point is shifted here the coincidence of the clock counter 2 and the

2 " . \. {21.4. \\ te reversing counter9 recorded code combinations

4 ⁺ '/ ^le · V 2' / temporally within the limits 0 < γ <0.25 of the setting _{zone Ψι} .

35 while the pulse width / thyristors through the

and the expression

40 is given, in which pulse is separated which has the same atomic number

having and in the flip-flops 23 of the clock counter 2 <5, the variable part of the pulse width / and

(Fig. I) written states of the table lent- t _k the commutation time (Umladczcii des Komrnu-

speak. The output condensers of the main thyristors hit the outputs S ₁ to 8 ₄

Pulses on the main thyristors of the w-phase Thy- 45

risior pulse converter. mean.

When a control pulse is fed into the sum, the pulse width is changed by changing the proportion <>

malionscingang 10 of the reversing counter 9 changes the adjusted, which is to any Zeilpunkt as first flip-flop of the reversing counter 9 its state,

what one thinks about the information inputs of the decoders 50 g _t = (.vv) —— (3)

rer3. 4. 5 and 6 incoming binary code 1000 correspond to- '2 "

speaks. is defined, where .v and ν are the numbers of the sum

The process of changing the states of the flip input 10 in the event of an enlargement of the pulse-flops (FIG. 3) of the clock counter 2 runs without undershoot t of the thyristor or is interrupted at the subtraction input 11. and the states of the Füp-Flops 23 change 55 in the event of a reduction in the pulse width f, of the Thyrisich, as already mentioned, with the frequency F. The stors of the reversing counter 9 received pulses change the states of the flip-flops 24 of the Reverse.

setting counter 9 takes place with a repetition frequency F; for the duty cycle} ■ each phase of the m-phase Stcl control pulses. Here, at a time toddlers accordance experiencing a change corresponding to the \ on the clock counter 2 and the reverse counter 9 einge- 60 α diagram of Fig. 5, where the diagrams a. Code combinations written b, t and d appear at which the changing laws for the duty cycle) · of the respective outputs of the first horizontal rails (see exemplary first, second, third and fourth phases, refer to FIGS. 2 and 3) of the decoding matrix 22 and thus illustrate. Because each control channel controls the outputs of the decoders 3, 4, 5 and 6, the conduction of the thyristors in the green

other umi-T-shifted pulses. With respect to the ⁶⁵ ^ n of the adjusting zone, ensures the entire ball region Ko 4 Φ φ in vierStellzoncn _{{, φ:} ψ and φ. under respective outputs 8, to 8 ₄ of the decoder 7 divides, where <p _{x, <p: <p:,} and ^ _4, the actuating zones of the first, occurring pulses, the pulses at the initial second, third and fourth control channel are .

Home! Strapping of the (—— Yten control pulse on

Summalionscingang 10 and after reaching a Tastvcrhiilinisscs y with a maximum value for the first control channel of 0.25, the constant voltage level present at the control output 20, (I-'ig. I) of the reversing counter 9 is switched off. At the same time, a direct voltage of the same level (see diagrams 2O ₁ and 2O _{2 in FIG. 4) is generated around control output 2O 2} and the reversing counter 9 is reset. From the io, control output 20, the constant level signal becomes one of the inputs of each AND element 18 | to 18 _; the / broad group 18 given. At the other input of each AND element 18 to 18 ₄ meet, as already mentioned. Pulses from the outputs of decoders 3, 4, 5 and 6, ie from one of the outputs of each control channel. As a result, occur at the outputs 19 to _19: the matching unit 14 also pulses on the order of arrival di: r pulses from the outputs of the decoder 6 to 6 to the exits 19 to 19, but the unit 14 differs from the above described from: namely, the pulses from the outputs of the decoders 3, 4, 5, 6 arrive at the outputs 19., 19i, 19 ·, or 19, (see diagram in Fig. 4 for 0.25 · 0.5) . The value of the duty cycle γ changes in the given case from 0.25 to OJ) because the time of the code combination written in the cycle counter 2 and in the reversing counter 9 changes. After reaching a pulse duty factor j of a maximum of 0.5 for the actuating zone φ ₂ (FIG. 5), the above-described process of resetting the reversing counter 9 takes place, at output 20 _: a potential signal occurs, while this signal occurs at output 2O ₂ disappears. In addition, the process of connecting the control channels via the adaptation unit 14 to the phases of the m-phase controller takes place in analogy to those described above. The impulses «in the setting zone φ-, (for a duty cycle of 0.5 < γ <0.75) from the outputs of the decoders ₃ , 4, 5 and 6 at the outputs 19 3, 19-“ 19j and 19, the adjustment unit 14. Within the limits of the adjusting zone φ ₄ (duty factor of 0.75 <:) * <1.0), the pulses coming from the outputs of the decoder 3, 4, 5 and 6 at the respective outputs _19: 19 ,, 19j or 19, the unit i4 at. The process of changing the pulse width ι of the main thyristors is shown in the diagrams / | to I ₁ (Fig. 4), where r ,, r _:. r _; and h is the Pulsbrcito ι the main thyristors of the first, second, third and fourth phase of the / n-phase adjuster mean

To reduce the pulse width / (to reduce the bag content>), the control pulses are sent from the control unit 12 (FIG. 1) to the subtraction input 11 of the reversing counter 9. Here, the pulse width t of the thyristors decreases by a value of rt with the arrival of each subsequent control pulse.

The use of the decoder 7 for undelayed pulse trains makes it possible. with the help of a single clock counter 2 for pulses m to generate undelayed pulse trains, while the execution of the decoders 3, 4, 5, 6 for delayed pulse trains according to the description allows the duty cycle γ for all phases with the help of a single clock counter 2 and one single reversing counter 9 to control. In addition, this embodiment requires the decoders 3, 4, 5

and 6 the inclusion of a by a factor of -

Hl smaller number of elements, d. H. with the enlargement of the The number of phases increases the effectiveness.

The decoding diaphragms 22 (FIG. 21 of the decoders 3, 4, 5 and 6) are used for delayed pulse trains only to enable the control of the key ratio y only in its own setting zone, ie in the general case from 0 to -γ , and not for Control in the »ι

Total range from 0 to 1.0> controlled. The latter leads to a reduction in the required elements and consequently to increase the reliability, the efficiency, to reduce the dimensions and the power consumed.

The described method and the device can jam with discrete elements (diodes! With integrated circuits can be realized, with all advantages being retained.

For this purpose 4 sheets of drawings

Claims (2)

Patent claims: 1. Method for the digital control of an m-phase Pulse-width modulated thyristor direct current sender, whose main and quenching thyristors each Phase with a time shift at - T BI (Γ - pulse period of a phase), for which a control channel for each phase generates delayed control pulses for the main thyristors and delayed control pulses for the quenching thyristors according to the required current carrying time of these main thyristors, with the following applies to the pulse width t \ s corresponding to the current carrying time: 0 < ι < Γ, so that the entire setting range for each phase is equal to T , characterized in that the entire setting range is subdivided into m setting zones (φ) that are equal in time, so that the pulse widths (O with their successive change over the entire setting range (7 ") each composed of two additive parts, with a time-fixed part being formed by the commutation time t _k (recharging time of the commutation capacitor) and an adjustable part (<5,) being limited by the width of an adjustment zone {φ) , including the phase-shifted delayed control pulses of the m control channels by cyclic swapping one after the other for each extinguishing thyristor j Either phase are fed, so that when changing the pulse width (r) from O to T z. B. in the first setting zone (p,) the thyristor of the first phase of the delayed control pulse of the first control channel, in the second setting zone (φ ₂ ) that of the / wide Slcuerkanals, in the / η-th setting zone (<p _m ) of the /? i-tcn control channel etc. and with decreasing pulse width (/) the reverse order applies accordingly. 2. Execution for performing the method according to claim 1, with a clock generator which is connected to the input of a counting unit for clock pulses -to, the outputs of which are connected to the logical inputs of each of m decoders for delayed pulse trains, each containing a decoding matrix , the outputs of which are connected to the inputs of an OR gate, while the information inputs of each decoder for a delayed pulse train are connected to the information outputs of a switching unit, the inputs of which are connected to the outputs of a control unit, characterized.