DE2825661A1 - ARRANGEMENT FOR LEVEL AND SPATIAL SOLID-CIRCUIT CIRCUITS OF HIGH INTEGRATION - Google Patents
ARRANGEMENT FOR LEVEL AND SPATIAL SOLID-CIRCUIT CIRCUITS OF HIGH INTEGRATIONInfo
- Publication number
- DE2825661A1 DE2825661A1 DE19782825661 DE2825661A DE2825661A1 DE 2825661 A1 DE2825661 A1 DE 2825661A1 DE 19782825661 DE19782825661 DE 19782825661 DE 2825661 A DE2825661 A DE 2825661A DE 2825661 A1 DE2825661 A1 DE 2825661A1
- Authority
- DE
- Germany
- Prior art keywords
- spatial
- chipa
- arrangement
- disks
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
Description
Anordnung für ebene und räumliche Festkörperschaltungen hoher IntegrationArrangement for planar and spatial solid-state circuits of high integration
Das Anwendungsgebiet der Erfindung sind digitale und analoge Schaltungen für komplette elektronische Geräte und Anlagen und deren elektronische Baugruppen.The field of application of the invention are digital and analog circuits for complete electronic devices and systems and their electronic assemblies.
Es ist bekannt, daß in der Monochiptechnik Schaltungen nur bis zu einem bestimmten Integrationsgrad ökonomisch herstellbar sind.It is known that in monochip technology, circuits can only be produced economically up to a certain degree of integration are.
Bei Überschreitung der Grenzen von 10 ... 10 Gatterfunktionen/ Baustein treten für die kommerzielle Technik nicht vertretbare Kosten auf. Multichiptechniken auf der Basis von Glas- oder Keramiksubtratunterlagen sind relativ aufwendige Technologien. Die dafür bekannten Verbindungstechniken sind teuer in der Herstellung und wegen der vielen Kontaktpunkte relativ unzuverlässig. If the limits of 10 ... 10 gate functions / The commercial technology incurs unreasonable costs. Multichip techniques based on glass or Ceramic substrates are relatively complex technologies. The connection techniques known for this are expensive in the Manufacture and relatively unreliable because of the many contact points.
Die bekannten Multichiptechniken ermöglichen nicht die vertikale Stapelung und räumliche Anordnung dieser Schaltungen.The known multichip technologies do not allow these circuits to be stacked vertically and spatially arranged.
Ziel der Erfindung ist eine Anordnung großintegrierter Pestkörperschaltungen auf der Basis serienmäßig hergestellter Chips in Mikroverbindungsbauweise.The object of the invention is an arrangement of large-scale integrated circuit boards on the basis of mass-produced chips in micro-connection design.
Die Aufgabe der Erfindung besteht darin, eine Anordnung für ebene und räumliche Pestkörperschaltungen hoher Integration mittels Substratscheiben und damit verbundener Chips zu schaffen, mit der eine sehr hohe Schaltungskonzentration erreicht wird. The object of the invention is to create an arrangement for planar and spatial plague circuits of high integration by means of substrate wafers and chips connected to them , with which a very high circuit concentration is achieved .
809884/0670 - 2 -809884/0670 - 2 -
Durch die erfindungagemäße Lösung soll ermöglicht werden, daß der Integrationsgrad optimal integrierter Bausteine um 3 bis 4 Zehnerpotenzen erhöht wird. Die Ablösung der bisherigen Leiterplattentechnik erbringt eine Einsparung an Masse und Raum elektrischer Geräte um 1 bis 2 Zehnerpotenzen. Durch den Wegfall von Kontaktstellen (Lötstellen) wird die Zuverlässigkeit um 2 bis 3 Zehnerpotenzen erhöht. Der Fertigungsaufwand im Herstellungsprozeß von Pestkörperschaltkreisen wird verringert, ebenso wird der Fertigungsaufwand durch die Ablösung der Leiterplatte und deren Montage (Bestücken und Verbinden) vermindert.The solution according to the invention is intended to enable that the degree of integration of optimally integrated components is increased by 3 to 4 powers of ten. The replacement of the previous Circuit board technology saves the mass and space of electrical devices by 1 to 2 powers of ten. By eliminating contact points (soldering points), reliability is increased by 2 to 3 powers of ten. The manufacturing effort in the manufacturing process of pest body circuits is Reduced, as well as the manufacturing effort due to the detachment of the circuit board and its assembly (equipping and connecting) reduced.
Weiterhin wird der Laufzeiteffekt durch die Miniaturisierung der Leiterwege verringert.Furthermore, the running time effect is increased by the miniaturization the ladder paths are reduced.
Erfindungsgemäß wird das dadurch erreicht, daß auf unstrukturierten oder strukturierten, Teilschaltungen enthaltenden, als Trägersystem fungierenden Substratscheiden Chips gleicher Dicke und gleicher Werkstoffpaarung wie die Substratscheiben implantiert sind, daß in diesen mechanisch, thermisch und elektrisch stabilen Systemen planansr Bauart die elektrische Verbindung der Chips untereinander und zur räumlichen Ebenen draht- und kontaktlos ausgeführt ist und daß diese großintegrierten Scheiben zu räumlichen Mehrebenensystemen gestapelt sind. Eine Ausgestaltung der Erfindung sieht vor, daß zur elektrischen Verbindung der Chips untereinander und zu räumlichen Ebenen über Mikrobohrungen zur Durchkontaktierung eine Bedampfungsschicht aufgebracht ist.According to the invention this is achieved in that on unstructured or structured substrate sheaths containing subcircuits and functioning as a carrier system, chips of the same thickness and the same material pairing as the substrate wafers are implanted in that mechanically, thermally and electrically stable systems planansr construction type the electrical connection of the chips to each other and to the spatial levels wired and is made contactless and that these large-scale integrated disks are stacked to form spatial multilevel systems. One embodiment of the invention provides that for the electrical connection of the chips to one another and to spatial levels via Microbores for through-hole plating a vapor deposition is applied.
Fig. 1 zeigt die erfindungsgemäße Anordnung in einer Ebene. Auf einer Grundplatte 3 sind die Substratscheiben 1 angeordnet, in welche die Chips 2 eingebracht und mittels Glaslot 4 verbunden sind.Fig. 1 shows the arrangement according to the invention in one plane. The substrate disks 1 are arranged on a base plate 3, in which the chips 2 are introduced and connected by means of glass solder 4.
- 3 80988A/0670 - 3 80988A / 0670
Darauf iat eine Paaaivierungaachicht 5 angebracht, in welcher aich die Anachlußkontaktpunkte bzw. darauf die Leiterzüge 6 befinden. Abgeachloaaen wird die Anordnung durch eine Deckeniaolation 7. Auf der Subatratacheibe 1 befindet aich weiterhin der Anachlußkontakt 8.A pairing layer 5 is then attached, in which aich the connection contact points or the conductor tracks 6 are located thereon. Abgeachloaen is the arrangement by a ceiling aolation 7. Aich is still on the subatratache disc 1 the connecting contact 8.
Die räumliche Anordnung in mehreren Ebenen iat in Fig. 2 dargeatellt. The spatial arrangement in several levels is shown in FIG.
In einem Gehäuse 11 aind die Subatratacheiben 1 übereinander angeordnet, jeweils durch die Zwiacheniaolation 9 getrennt bzw. durch die Mikrobohrung 10 elektriach verbunden.In a housing 11 the subatratache disks 1 are one above the other arranged, each separated by the Zwiacheniaolation 9 or electrically connected by the microbore 10.
Die Anordnung wird entaprechend den nachfolgend beachriebenen Schritten aufgebaut:The arrangement is set up according to the following steps:
Zur Anwendung kommen ala Trägeracheiben serienmäßig hergestellte Subatratacheiben, inabesondere Siliziumacheiben, die auch bereits Strukturen enthalten können.Series-produced carrier disks are used as carrier disks Subatrate disks, in particular silicon disks, which can also already contain structures.
In diese Scheiben werden Durchbrüche nach Größe und Geometrie der zu implantierenden Chips 2 eingearbeitet, wobei Ultrascballläpptechnik zur Anwendung kommen kann« Anschließend .werden die Chips 2, die aus gleichem Material wie die Substratscheiben 1 bestehen, in die Aussparungen eingesetzt und mit Glaslot 4 oder einer anderen Vergußmasse befeatigt. Danach erfolgt durch Oxidation das Aufbringen einer Passivierungsschicht 5 mittels eines Niedertemperaturverfahrens. Die Fenster für die Anschlußkontaktpunkte 6 der Mikroverbindung zum implantierten Chip 2 werden durch Fotolithographie hergestellt. Das Verbinden der Anschlußkontaktpunkte untereinander entsprechend der vorgegebenen Schaltung und Topologie erfolgt durch Bedampfen z.B. mit Aluminium oder Sputtering in einer Schichtdicke von 2 ... 3/um.Breakthroughs according to size and geometry are made in these disks incorporated into the chips 2 to be implanted, whereby ultrasound lapping technology can be used « The chips 2, which consist of the same material as the substrate wafers 1, are then inserted into the cutouts and attached with glass solder 4 or another potting compound. A passivation layer is then applied by means of oxidation 5 by means of a low temperature process. The windows for the connection contact points 6 of the micro-connection to the implanted Chip 2 are manufactured by photolithography. The connection of the connection contact points with each other accordingly The specified circuit and topology is done by vapor deposition, e.g. with aluminum or sputtering in a layer thickness of 2 ... 3 / um.
Daraus wird das Leiterbild (Mikroverbindungsachemen) auf fotolithographischem Weg gefertigt. Nach Hermetisierung der Scheiben mit den implantierten Chips und Leiterzügen durch Niedertemperaturoxidation entsteht die Deckenisolation 7. Die Anschlußkontakte 8 der großintegrierten Schaltung werden durch FotolithographieThis is used to create the conductive pattern (micro-connection issues) on a photolithographic basis Made away. After hermetically sealing the panes with the implanted chips and conductor tracks by means of low-temperature oxidation the ceiling insulation 7 is created. The connection contacts 8 of the large-scale integrated circuit are made by photolithography
809884/0670 - 4 -809884/0670 - 4 -
und Anscblußkontakfbedämpfung auf der Scheibe angebracht.and connection contact damping attached to the disk.
Wird eine höhere Schaltungsintegration gefordert, beginnt die räumliche Stapelung der gefertigten Scheiben. Im ersten Schritt werden die Verbindungskontaktpunkte von Scheibe zu Scheibe geoibet. Die Koordinaten für die Bohrungen in die Scheiben werden festgelegt und danach Mikrobohrungen 10 durch Ultraschallbohren angebracht. Danach wird die erste Scheibe in das Grundkörpergehäuse 11 eingelegt und eine Zwischenisolation 9 angefertigt, die zweite Scheibe nach festgelegten Koordinaten aufgebracht und mechanisch arretiert. Die zweite Scheibe und die Isolationszwischenlage sind bereits mit Bohrungen an den räumlichen Verbindungskoordinaten versehen.If a higher degree of circuit integration is required, the spatial stacking of the manufactured panes begins. In the first step, the connection contact points are mapped from pane to pane. The coordinates for the holes in the disks are fixed and then microbores 10 are made by ultrasonic drilling. After that the first disc inserted into the base body housing 11 and an intermediate insulation 9 made, the second disk according to fixed coordinates applied and mechanically locked. The second pane and the intermediate insulation layer are already drilled on the spatial Provide connection coordinates.
Die zweite Scheibe wird durchkontaktiert mittels Bedampfen und somit das Scheibenpaar elektrisch verbunden.The second pane is plated through by means of vapor deposition and thus the pair of panes is electrically connected.
Danach erfolgt schrittweise die weitere Stapelung von Scheibe 2 und Zwischenisolation 9 und Durchkontaktierung. Nach Fertigstellung der großintegrierten Schaltung wird das Grundkörpergehäuse 11 mit den η gestapelten Scheibe hermetisiert. Die Herstellung der Anschlußkontakte wird auf die injder Festkörperschaltkreistechnik bekannte Weise durchgeführt.The further stacking of pane 2 and intermediate insulation 9 and through-hole plating then takes place step by step. After completion of the large-scale integrated circuit, the base body housing 11 is hermetically sealed with the η stacked disks. The production of the connection contacts is carried out in the manner known in solid-state circuit technology.
809884/0670809884/0670
LeerseiteBlank page
Claims (2)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DD19992777 | 1977-07-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE2825661A1 true DE2825661A1 (en) | 1979-01-25 |
Family
ID=5509034
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE19782825661 Withdrawn DE2825661A1 (en) | 1977-07-07 | 1978-06-12 | ARRANGEMENT FOR LEVEL AND SPATIAL SOLID-CIRCUIT CIRCUITS OF HIGH INTEGRATION |
Country Status (3)
| Country | Link |
|---|---|
| DE (1) | DE2825661A1 (en) |
| FR (1) | FR2397068A1 (en) |
| GB (1) | GB2000909A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2153144A (en) * | 1984-01-13 | 1985-08-14 | Standard Telephones Cables Ltd | Circuit packaging |
| US5847448A (en) * | 1990-12-11 | 1998-12-08 | Thomson-Csf | Method and device for interconnecting integrated circuits in three dimensions |
-
1978
- 1978-06-12 DE DE19782825661 patent/DE2825661A1/en not_active Withdrawn
- 1978-07-05 FR FR7819978A patent/FR2397068A1/en not_active Withdrawn
- 1978-07-07 GB GB7829205A patent/GB2000909A/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| GB2000909A (en) | 1979-01-17 |
| FR2397068A1 (en) | 1979-02-02 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8139 | Disposal/non-payment of the annual fee |