DE2759040A1 - Multi-channel storage FET - has floating storage gate surrounded by insulator and has control and selector gates - Google Patents

Abstract

The n-channel storage field-effect transistor has a storage gate (G1) whose charge is reversed by the injection of electrons and which can be charged to a negative potential in relation to the uncharged state and can act upon the source-drain stage. A controllable control gate acts capactively on the storage gate. The storage gate and the channel (K) are influenced by the control gate (G2) which is connected to a selector gate (Ga2) which influences the furthr channel region (Ka) via a conductive junction (LV) made apart from an auxiliary regions (HS).

Description

n-channel memory FET

The invention relates to a development of one not previously published Main application / in the main patent P 27 44 113.0-33 specified subject matter and its Further training, all of which relate to a ventilated n-channel memory FET, and an n-channel memory FET with at least one gate, namely with one on all sides surrounded by an insulator, floating memory gate, in which the Storage gate the electron-injecting channel inJect - i.e. charge reversal by im own conductive channel strongly accelerated and thereby heated electrons, due to their heating by an electrical one acting in the source-drain direction Field to overcome the energy threshold to the conductivity band of the insulator and thereby get to the storage gate - is exploited with the task of sewer inspection for programming, i.e. charging the memory gate on one opposite the uncharged one State negative potential, so that the Storage gate after this charging by means of its negative charge by influencing the source-drain current acts inhibitory manner on the source-drain path, between the source and first an n-doped auxiliary region and the drain in series with its channel behind it another canal area with an influencing this further canal area, from this further channel area isolated, controllable selection gate are inserted and wherein it has an additional, one terminal, controllable control gate has, which acts capacitively on the memory gate.

The invention is particularly applicable to the program memories of a telephone switching system and suitable for storage in televisions, but also for storage in other facilities.

The n-channel Speioher-FHT described in the main application / main patent advantageously has a reduced reject rate in its manufacture, mainly because it may also be excessively erased, so that such an n-channel memory FET used as a 1-FGT memory cell within a large matrix-shaped memory as well as because its below-threshold current and also the risk of "punch-trought" is reduced, although quite simple processes are used to manufacture it can be.

DEOS 24 45 030 - VPA 74/6129 provides a method for manufacturing of a memory FET with a memory gate insulated on all sides and with a controllable control gate Known, whereby, due to its self-jesting during manufacture, edges of both Gates immediately adjoin the source and the drain in such a way that both guest with respect to these edges quite precisely are layered on top of each other. To the Forming the so layered gates and the substantial adjacent edges of the A single, tightly toleranced mask is required for the source and drain.

The invention has the task of reducing the reject rate in production of the n-channel memory FET, particularly by reducing requirements to the manufacture and effects of lines can be approved by the number of required to control the n-channel memory FET from the edge electronics coming, chip area required lines is made as small as possible.

The invention is based on the initially and in the preamble of Main claim cited subject matter of the main application / main patent. the The task of the n-channel memory FET according to the invention is achieved by the characteristics this main claim specified measure resolved.

The invention and further developments thereof are illustrated in the figures 1 to 3 illustrated exemplary embodiments, with FIG. 1 showing the cut surface a longitudinal section perpendicular to the substrate, and FIGS. 2 and 3 are each plan views show two different embodiments.

By using the same reference symbols as in the main application Main patent, the description above can essentially refer to the further education Features that relate to the invention and its developments restrict.

In the n-channel memory FET shown in Fig. 1, there are control gates G2 and a selection gate Ga2 attached, both of which are electrically conductive to one another are connected, for example by means of the conductive lines indicated only schematically in FIG Connection LV. As a result, these two guests are on the same potential as the indicated control gate connection AG2. It turned out to be too reliable Operation of the n-channel memory FiT generally always suffices, the control gate and to control the selection gate simultaneously and jointly through a single potential, that is led by the edge electrontk via a single, common control line will.

This compound VI. between both controllable gates can be by a metallic line as well as by a doped half-volt gate area be made. If it is made as a metallic wire, it can they as part of the production of all other contacts and all other metallic ones Lines of the chip are made. Below is a special manufacturing process are described in which such connections LV shared with the control gate G2 and the selection gate Ga2 are formed from a single, doped polysilicon layer will. By avoiding special contacts and metallic lines LV, the production of the n-channel storage FiT is particularly simple and so is the reject rate further reduced accordingly.

The measure according to the invention therefore does not prevent the n-channel memory FET to be able to program, read and, if necessary, delete as usual. In particular, this is allowed Storage gate because its electrical behavior corresponds to that in the application / patent P 25 13 207.4 corresponds to the behavior described.

Figures 2 and 3 show top views of two different embodiments, the structure of which essentially corresponds to the scheme shown in FIG.

Between the very broad areas of source 5 and auxiliary area HS lies the further channel region Ka, which is very wide here and which is covered by the selection gate Ga2 and is influenced. The channel K, which is comparatively only narrow, is used by the memory gate G1 and covered and influenced by the control gate G2. Between the control gate G2, the e.g. of doped polisilicon, and the selection gate Ga2, which is expediently is often made of the same material as the control gate G2 is in both examples a conductive connection LV inserted, which is conveniently often made of the same Material like the control gate G2.

The entire n-channel memory FET is surrounded by a thick oxide layer You, which is also shown in Fig. 1. In the exemplary embodiments shown in FIGS is the connection LV between the two controllable gates G2, Ga2 through this Thick oxide layer Du separated from the substrate, as is also indicated in FIG. 1. Through this this prevents unintentional LV on the Substrate HT can form a conductive additional channel, which is the source-drain path S-D unintentionally bridged and faked a conductive channel K.

The areas S, HS and D are here directly on the substrate surface appropriate. Between the substrate or channel parts on the one hand and the memory gate and the controllable gates on the other hand are respectively, as in Figures 1 and 2 indicated, in all of these exemplary embodiments parts of a thin first Insulating layer Ii or a thin second insulating layer 12.

The more or less schematically shown in the figures, a control gate Example of an embodiment having G2 can be produced in the following way: A thick oxide layer DU is initially grown on the p-conductive substrate HT. A window is then etched into the thick oxide roof DU along the entire surface and length GL of the actual source-drain path S-D of the n-e1ßpeicher-FIT1 so that the substrate HT is again openly accessible there. This also changes the shape the channel parts K and Ka set.

The area of the connection LV therefore does not create a window into the thick oxide layer You etched. If one uses the embodiment according to FIG. 3 instead of the execution example according to Fig. 2, the thick oxide Du in area V is only etched so far away that there the constriction V promoting the channel injection instead of the one shown in FIG constant channel width is created.

A first insulating layer, namely a thin oxide layer, is then left Ii arise on this entire area of the window, e.g. with a thickness of 600 Å.

A first polysilicon layer is then allowed to grow, which is then still doped and which is then etched away again with high permissible tolerances - with the exception of the too. Storage gate Gi belong to the layer area and the adjoining the memory gate G1 and protruding greatly beyond the later areas SH, D Edge layers G1 ', which are not yet etched away, and possibly with an exception a tab which is conductively connected to the memory gate and is not shown in the figures, the one to improve an electrically controlled discharge of the Storage gate can be attached. The memory gate G1 remains together with provisionally adjoining edge layers G1 'and possibly the conductively connected flap, these edge layers G1 'now parts of the later auxiliary area HS and the later cover drain D and do not have to have a certain size themselves. the Accordingly, the mask for carrying out this etching did not have to be narrow there Comply with tolerances. These protruding edge layers G1 'are only later, as will be described, etched away to finalize the memory gate G1.

Next, it is left on the first polysilicon layer thus formed and on the parts of the first insulating layer 11 that are still exposed, a second one thin insulating layer 12 arise, e.g. with a thickness of 500 i.

On this second insulating layer 12 or also on the thick oxide layer You can grow a second polysilicon layer, from which by etching away by means of a mask simultaneously the two controllable gates G2, Ga2 and possibly also the conductive connection LV formed on the thick oxide Du between these gates will. By using the same mask, you can also use those areas etch away the insulating layers 11, 12 and the protruding edge layers G11, which previously covered the later areas of drain D, source 5 and auxiliary area H5, so that the memory gate G1 and the control gate G2 now particularly exactly one above the other are stratified, which in itself reduces the reject rate.

One can then use, for example by means of ion implantation the second polysilicon layer and the thick oxide layer Du as a mask, the n-doping of the areas G2, Ga2, D, S'HS. At the same time, the polysilicon is used the connection VL of the control gate parts G2 and Ga2 n-doped and thus highly conductive.

Instead of using ion implantation, one can also use diffusion generate the n-doping of the regions D, S, Es in a manner known per se at the same time an n-doping of the parts of the polysilicon layer that form the areas G2, Ga2 and LV form is achieved. If ion implantation is used here, it is also sufficient in itself to use the mask in question to remove the edge layers Gi ' etch away, but at least remnants of the first insulating layer Ii, or even the whole The insulating layer In cannot be etched away, and the n-doping of the source S, the auxiliary region It and the drain D through these remnants of the first insulating layer II in the substrate To attach HT.

The figure largely shows the state of manufacture that has now been reached 1. The n-doped regions D, S, Es are produced in the p-conducting substrate HT. Between the selection gate Ga2 and the further channel region Ka consists of parts of the first and the second insulating layer Ii, 12 made insulator. Between the control gate G2 and the channel part K, a remaining part of each of the second lies one after the other Insulating layer 12, the first polysilicon layer G1 and the first insulating layer I1. The source-drain path S-D of this n-channel memory FET is made up of the thick oxide layer You surround.

A variety of such n-channel memory FETs can at the same time be made on the substrate HT and form a memory, with their sources 5 and / or drains D each also connected to one another, that is to say directly form n-doped regions that are conductively connected to one another without intermediate lines can. You then save a corresponding number of special contacts for these areas a. By utilizing the mask that forms the second polysilicon layer for Release of the source S, the auxiliary area HS and the drain D is as before mentioned, also achieved in an elegant way that the control gate G2 very precisely Above the Speicherga te G1 is attached, these two gates, as in Fig. 1 is shown, in this example are each of the same length, namely about 31u long.

On the entire disk with the state shown in FIG. 1, one can Let a first protective oxide layer grow out by means of a window Attaches contacts for areas 5 and D and for the steady gate G2. If you unlike the description above, no connection LV from the second polysilicon layer can now also be controlled on each of the two, previously electrically separated Gates G2, Ga2 attach such contacts in the first protective oxide layer. Afterward can be done by means of metal vapor deposition or a connecting line produced thereby subsequently establish the electrically conductive connection LV. By means of this metal vapor deposition you can also use other connecting lines of the block, and finally above also make a second protective solid layer.

To the thickness of the insulator between the select gate Ga2 and the further To make the channel area Ka smaller, the manufacturing process can be modified by that between the formation of the regions G1, Gi 'from the first polysilicon layer and the subsequent application of the second insulating layer 12, a further method step inserts, namely an etching away of all now exposed parts of the first insulating layer Ii, by means of G1, Gi 'and possibly also the mentioned cloth as a mask, or by means of the mask used to shape these parts. Then the insulator exists between the selection gate Ga2 and the further channel region Ka only from the second insulating layer 12, as a result of which the control potentials at the selection gate Ga2 in the rejects decreasing Way intensver can influence the further canal area Ka.

4 claims 3 figures Blank page

Claims (4)

Claims 1. n-channel memory FET with at least one gate, namely with a floating memory gate surrounded on all sides by an insulator, in the case of the electron-injecting channel injection for reloading the storage gate -th. Reloading through ii own conductive channel is greatly accelerated and as a result heated electrons, which because of their heating by a in the source-drain direction acting electric field the energy threshold 1. to the conductivity band of the insulator Overcome and thereby get to the storage gate - is exploited with the task of the channel injection for programming, i.e. charging the memory gate on an opposite the uncharged state negative potential, so that the memory gate after this charging by means of its negative charge by influencing the source-drain current acts inhibitory manner on the source-drain path, between the source and first an n-doped auxiliary region and the drain in series with its channel behind it another canal area with an influencing this further canal area, controllable selection gate isolated from this further channel area are inserted, wherein it has an additional controllable control gate having a connection, which has a capacitive effect on the memory gate, according to registration / patent P 27 44 113.0; 33, in particular for program memories of telephone systems, d a -d u r c h g e k e It is noted that the control gate (G2), which is the memory gate (G1) and the channel (K) influences, with the selection gate (Ga2), which the further channel area (ta) influenced, via a conductive connection (LV), which is away from the operating area (HS) is attached, is connected. 2. Method of manufacturing the n-channel memory FE? according to claim 1, g e k e n n n z e i c h n e t d u r c h the following process steps: a. On a p-conducting silicon wafer as a substrate (HT), a relatively thick Oxide layer (Du) applied, in which a continuous up to the substrate <HT) The window in which the source-drain path (S-D) will later lie is etched; b. a relatively thin first insulating layer (11) is produced in the window; c. A first polysilicon layer is deposited on the entire wafer, which is additionally endowed; d. the first polysilicon layer is made like this by etching away shaped that essentially the area of the memory gate (G1) - and ggr with the memory gate conductively connected, serving for discharging the memory gate Lobe - remains, however, initially adjacent to the memory gate (¢ 1) Another protruding edge layer (G1 ') over the later auxiliary area (HS) and areas located over the later drain (D) extends in; e. on the first Polysilicon layer, a relatively thin second insulating layer (12) is produced; f. a second polysilicon layer is deposited over the entire wafer; G. the second polysilicon layer is formed by etching away using a mask so that that areas of the control gate (G2), the selection gate and a conductive connection (LV) remain between these areas; this second layer of polysilicon can estl. to be or will be endowed already now; H. with that for forming the second polysilicon layer The mask used in method step g will cover the later auxiliary area (Es) and the later drain CD) extending into the outer layers (G1 ') of the first Polisilicon layer and the unneeded parts of the first and second insulating layers (I1, I2) etched away; i. a doping of the second polysilicon layer is ggr. now made up for; n-doping of the substrate (HT) on its exposed surfaces to produce the source (5), the auxiliary region (HS), and the drain (D) appropriate; k. A first protective oxide layer is also applied over the entire pane contacts for the drain (D) and the control gate (G2 / Ga2 / LV), and the necessary connecting lines are made by means of metal vapor deposition; 1. A second protective oxide layer is made over the entire pane. 3. The method according to claim 2, g e k e n n z e i c h -n e t d u r c h following modification of process steps h and i: h. With the same mask Although the surface layers (G1 ') that extend over the surface are etched away, at least residues are etched away the first insulating layer (I1) are no longer etched away; i. through the remains of the The n-type doping is passed through the first insulating layer (I1) by means of ion implantation the source (S), the auxiliary region (Hs) and the drain (D) attached. 4. The method according to claim 2 or 3, g e k e n n -z e i c h n e t by inserting a further process step between the previous steps d and di. The remaining parts of the first polysilicon layer (G1, G1 ', L, VK) uncovered parts of the first insulating layer (I1) are etched away.