DE2748321A1 - TUNING DEVICE FOR HIGH FREQUENCY RECEIVER - Google Patents

Description

RCA 71007,

Brit.Ser.No. 44661-76 U patent «« «··

October 27. 1976 Dr. Dieter ν. Bezold

US Ser.No. 790,863 Dipl.-Ing.Pctcr Schütz

April 26, 1977 Dipl.-Ing. v / oif.jar ^ Hsusler

8 Munich Bo, P.O. Box 600668

RCA Corporation New York, N.T., V.St.v.A.

Tuning device for high frequency receivers

The invention relates to tuners using a phase locked loop.

It has recently been used for voting of radio and television receivers instead of conventional mechanical devices that work with passive tuning elements electronic tuning devices to use those with active tuning elements such as voltage-sensitive Capacitance diodes (varactors) work to find the appropriate superimposition frequency for matching to the individual to specify information-containing carriers. Such electronic devices are inherently more reliable and versatile.

However, unlike their mechanical counterparts, electronic voting devices require devices which the voting information (e.g. the respective tuning control voltage) is maintained during the absence of the supply power, so that the vote does not occur when the service reappears

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must be started again. Furthermore, among the many carriers covering a certain frequency range (e.g. the FM broadcast band), some compared to the others are preferred, e.g. because of their better signal strength or because of their program content. It is therefore desirable that an electronic voting system offers the possibility of preselecting a group of preferred voting positions. In addition, like their mechanical counterparts, electronic voting systems should contain devices to display the selected voting positions. This becomes a difficult task when the user preselects different preferred tuning positions depending on the receiving location. Unlike in the case where a recipient provides reconciliation settings for each information-containing carrier assigned, namely, neither the voting information for the preferred voting positions nor the corresponding one to be displayed Information known before the recipient has reached its destination.

Among the various types of electronic that have been proposed so far There are some tuning systems that contain what is known as a phase-locked loop, in order to produce through frequency synthesis Obtain beat signals of matching frequencies from a reference frequency signal generated by a crystal oscillator is derived. Such systems are particularly advantageous because their accuracy and stability are practically only dependent on the crystal oscillator depends, which can be designed very precisely and stably. In these working with phase-locked loop Tuning systems use a local voltage-controlled local oscillator, the control voltage of which is in such a Meaning is regulated that the phase and frequency differences between the reference frequency signal and the by a factor N frequency-divided signals of the local oscillator are kept to a minimum. A voting position is chosen in each case by setting the division factor N.

In order to be able to work in the phase-synchronized loop

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It is conventional to set the factor N in tuning systems programmable counters programmed using binary words, typically eight to ten binary digits (bits) contained. Devices such as thumbwheel operated switches, mechanically operating program cards, and non-permanent ones were used (power-dependent) magnetic and semiconductor memory in connection with reserve energy sources or permanent (power-independent) Semiconductor memory to store the content of the binary words for programming the 1: N frequency dividing counter and to control the preselection of preferred voting positions to allocate the binary words during the downtime of the network and have a source of binary information to visually display the selected tuning positions. Such Unfortunately, "storage" systems are relatively complicated and expensive.

Electronic tuning systems are also known in which a group of potentiometers are used to set DC tuning voltages corresponding to the different tuning positions for direct control of the frequency of a voltage controlled oscillator provide. Such a voting system is described in US Pat. No. 3,755,763. The potentiometers serve here to maintain the tuning information during the absence of the power supply and also the choice of certain to allow preferred voting positions. However, there are the usual programmable counters that are used in the phase-synchronized Loop voting systems are used via binary signals and not via DC voltages programmed, you have the potentiometer-controlled Tuning mechanisms not used in such systems. In US Pat. No. 3,983,497 there is a frequency divider for a phase-locked loop sequence identification system which is set by an analog control signal. This frequency divider is but not designed in such a way that voting positions are preselected and let it save while there is no power supply or that information, the selected voting positions

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show, could be displayed visibly.

With potentiometer-controlled voting systems, as they are in the U.S. Patent No. 3,755,763, referenced above, scales can be used in conjunction with the potentiometers to give an approximate indication of the tuning positions. Because of the relatively narrow frequency spacing between the Information-containing carriers, however, find it extremely difficult for a user to find voting positions that are close to one another to distinguish from each other.

Various more precisely working display devices for tuning positions are also known, their mode of operation basically relies on counting the periods of a signal that appear within a fixed period of time that is in gelation for the signal of a local oscillator, see e.g. US Patents 3,835,424-, 3,851,254 and 3,991,382. The voting systems in which these devices are used, however, do not have the desirable features a phase locked loop system which can be operated in a relatively simple and inexpensive manner, e.g. can be programmed or preset with the help of potentiometers.

A phase-locked loop tuning system according to the invention has a programmable frequency divider to divide the frequency of the signal generated by a local local oscillator. This frequency divider contains a first counter which, during the duration of a programming signal, has a programmed number N of input signal periods counts, as well as a second counter that counts a fixed number K of input signal periods to one To deliver an output signal whose frequency is a number N = K + M in inverse relation to the frequency of the local oscillator stands. The count M is stored by the first counter while the second counter counts so that it is decoded and can be displayed visibly to show a selected voting

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position. A voting position is selected in that a copy is made up of a large number of passive time-determining elements (e.g. from a large number of presettable Tuning potentiometer), which are assigned to the respective tuning positions, with a monostable multivibrator coupled to set the duration of the programming signal.

The invention is explained in more detail below using an exemplary embodiment with reference to drawings.

Fig. 1 shows partly in block form and partly with the aid of logic circuit symbols a preferred embodiment of the invention;

Figures 2 to 5

show in graphical representations relationships between individual signals in order to facilitate an understanding of the invention to facilitate.

The invention is explained below with reference to a tuning system for European FM broadcast carriers. However, it can also with a relatively simple modification of the system described for coordination with other information carriers, such as carriers for television reception.

In Europe, the FM broadcast carriers are spaced 100 kHz apart within a frequency band ranging from 87.3 to 104.5 MHz. So there are a total of 172 (ie) stations or channels available. 1 shows an FM radio receiver which picks up radio carriers with an antenna 12, then amplifies them in an RF input part 14 and processes them in some other way, in order then to pass them to a mixer 16. The receiver also includes a local oscillator 18 which can be controlled so that it selectively supplies one of a total of 172 superimposed frequencies which are spaced apart by 100 kHz within one

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Frequency range between 98 and 115 »2 MHz and in the mixer 16 can be combined with the respective broadcast carriers to generate a ZP signal with a carrier frequency of 10.7 MHz. The IF signal is amplified in an IF part 20 and treated otherwise, then demodulated in a demodulator 22 and then processed in the LF part 24 in order to have a Loudspeaker 26 to receive a sound reproduction.

The local oscillator (superimposer) 18 is located in a tuning device operating with a phase-locked loop 30, which supplies a control signal for influencing its oscillation frequency. The one generated by the local oscillator In addition to the mixer 16, the signal (superimposed signal) is also fed to a pre-divider 32 which, for example is a high speed counter in ECL technology ("Emitter Coupled Logic"). The pre-coater 32 serves to reduce the relative to divide the high frequency of the superimposed signal by a fixed number (e.g. by 8), so that the further division with the help of a relatively slow programmable 1: N frequency divider 34- performed which follows the presetter 32. The programmable 1: N frequency divider 34 divides the frequency of the output signal of the presetter 32 by an integer programmed according to the station selected.

A phase comparator 36 receives the output of the programmable 1: N divider 34- together with a reference frequency signal, which is provided by a reference pre-divider 38 which determines the frequency of the output signal of a crystal oscillator Divide 40 by a fixed number (e.g. by 8). The phase comparator 36 produces an error signal that is characteristic for the phase and frequency deviations between the output signals of the 1: N divider 34 and the reference pre-scaler 38. The error signal is filtered in a low-pass filter 42 in order to obtain the control signal for the local oscillator 18.

The frequency of the local oscillator 18 becomes under the influence of the control signal until the two input signals

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of the phase comparator 36 are substantially equal to each other in phase and frequency. The tuning device 30 is, so to speak, "synchronized" with this, and the frequency fy of the local oscillator is equal to Nf ", where fy is the frequency of the crystal oscillator. If f “is equal to 100 kHz, then the tuning device 30 can be used to selectively set the superimposed frequency fy between 98 and 115.2 MHz suitable for receiving a specific FM carrier by adjusting the division factor N to the relevant whole between 980 and 1152 Number that results from the quotient Ü. ΐΰόΉίζ

In the tuning device described here, the 1: N frequency divider is used 34 for voting on a specific station programmed by the user turning a selector switch 44- into the one Brings position in which this switch has a supply voltage + V via one assigned to the station in question Potentiometer coupled to a monostable multivibrator 48 · The potentiometer in question is one of a group of potentiometers 4-6 representing the different stations or voting positions assigned. If, as in the case shown, a station assigned to the potentiometer 46a has been selected then the monostable multivibrator generates 48 programming pulses, the duration of which is determined by a timer, which in this case also consists of the potentiometer 46a and one with the monostable multivibrator 48 coupled capacitor 50 consists. During each period of the output signal of the 1: N divider, im Course of the duration of a corresponding programming pulse, becomes a programmed number M of periods of the output signal of the prescaler 32 in an up / down counter 52 counted. In addition, during each period of the 1: N output signal a fixed number K of periods of the output signal of the prescaler 32 is counted in a fixed value counter 54. The up / down counter 52 and the fixed value counter 54 are applied in such a way that the 1: N output signal has a breakdown, which is equal to N = K + M periods of the output signal of the pre-scaler 32.

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In order to understand the mode of operation of the 1: N divider 34 in detail, reference is made to FIG. 2, which shows, in a graphical representation, various waveforms as they occur in the 1: N divider 34 of the present embodiment. At a point in time (the point in time 0 in Fig. 2) at which a period of the 1: N output signal has just ended, a negative-going pulse is applied to the output (O output) of the forward / backward signal indicating the count value O Counter 52 is generated and given to the reset input of the 1: K counter ^ A- and to the trigger input of the monostable multivibrator 48. The 1: K counter 54 is then reset to the count value 0, and the monostable multivibrator 48 is triggered. At this point in time (divided by N), an electronically controllable input switch 56 (shown only symbolically) couples the output of the superimposed signal pre-scaler 32 to the input of the 1: K counter 54-, and this begins to count up to the fixed number K. At the same time, a NAND gate 58 is activated in response to the programming pulse coming from the output of the monostable multivibrator 48 to couple the output of the superimposed signal prescaler 32 to the up-counting input of the up / down counter 52, so that this counter goes up counting begins. The output signal of the pre-scaler 32 is then fed to the forward input of the counter 52 via the NAND element 58 until the programming pulse from the output of the monostable multivibrator 48 comes to an end at time t ^. At this point in time the up / down counter 52 has counted a total of M periods of the output signal of the prescaler 32, this number being determined by the duration T _{Q of} the programming pulse. The programmed number M then remains stored in the counter 52 while the counter 54 continues to count. If at the time t ₂ the counter 54 has counted a total of K periods of the output signal of the prescaler 32, this counter generates an output signal “carry”. The "transmit" signal is coupled to the input switch 56, which then sends the output signal of the superimposed signal prescaler 32 to the reverse input of the up / down counter

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54- instead of at the input of the 1: K counter 5 ** ·. This counter now counts starting from the count M in the downward direction. When the counter 52 reaches the count value O (time t 1), again a negatively directed impulse becomes at its O-output is generated and a new 1: N division cycle begins.

So there is first a fixed number K of periods of the output signal of the pre-scaler 32 counted with the counter 5 ^, and then the counter 52 counts, depending on the duration of the programming pulse generated with the monostable multivibrator 4-8, a programmed number M of periods of the output signal of the Pre-scaler 32, so that during a 1: N division cycle a total of K + M periods of the output signal of the pre-scaler 32 are counted. If, for example, the fixed number K is chosen equal to 907 then all superimposed frequencies between 98 MHz can be set by setting M to integers between 73 and 24-5 and achieve 115.2 MHz in steps of 100 kHz with the tuner.

With the 1: N divider 3 ^ - it is also possible to display the selected tuning position practically continuously. During the I ⁿ tervalls in which the counter counts 54-, is the forward / backward counter 52 first in the forward counting operation (from time O until time t ,.), but stops with its count to before the counter 54- has reached the count value K. There is therefore a relatively long period of time (between t- and t ₂ ) during which it is possible to store the content of the up / down counter 52 and, after decryption, to display it in a corresponding decoder 60 by means of a seven- segment display device 62. During those intervals in which the content of the up / down counter 52 is changed by counting up and down (ie between 0 and t 1, and between t ₂ and t 1), a blanking signal (with "low" logic or Binary value) in order to prevent the display 62 from flickering. This blanking signal is generated by linking the programming pulse from the output

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of the monostable multivibrator 4-8 and the carry signal from the output of the 1: K divider 5 ^ · by means of an inverter 63 and an AND gate 64-. Using decoding arrangements of any type known per se, one can ensure that the display device displays the value of the frequency or else, in the case of a television receiver, the corresponding channel number reproduces.

Each of the potentiometers 4-6 is set to the preselection of a certain tuning position or station. While each of the potentiometers can be changed continuously, the frequencies of the superimposed signal can be programmed in steps of 100 kHz each. This is shown graphically in FIG. 3 with the stepped course of a characteristic curve reproducing the superimposed frequency f as a function of the resistance value R _x. As FIG. 3 shows, only one beat frequency can be obtained between the end points of a range of resistance values (not including the end points themselves). This corresponds to the situation where the end of the programming pulse lies between the leading edges of two adjacent output pulses or periods of the output signal from the superimposed signal prescaler 32. For example, _{only the frequency f Q is} obtained _{between the resistance values R 0} and Rq + AR (without including these values). However, at the endpoints of a range of resistance values, the tuning situation can become ambiguous. For example, at Rq the frequency can be equal to f _Q or equal to f _Q − 100 kHz, and at point Rq + AR the frequency can be at f _Q or at f _Q + 100 kHz. The ambiguity occurs when the end of the programming pulses practically falls within the leading edge of one of the output pulses of the superposition signal prescaler 32. This can be clarified with the aid of FIGS. 4 and 5. If the end of the programming pulse appears when the amplitude of the last pulse counted up from the pre-scaler 32 is still lower than the threshold of the up / down counter 52 (see waveforms A and B), then the forward / backward counter 52 turns on Accumulated count

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(e.g. 99), which is 1 lower than the count value (e.g. 100) which would then be accumulated when the end of the programming pulse would appear at a point in time where the amplitude of the last up-counted pulse was already is higher than the threshold of the up / down counter 32 (see waveforms D and E).

With the tuning device described here, there is a risk of ambiguity thanks to the phase-locked loop automatically reduced. If, for example, a potentiometer is initially set so that the end of the programming pulse closes appears at a point in time when the amplitude of the last pulse counted up just barely above the threshold of the up / down counter 52 (see waveforms D and E), the frequency of the superimposed signal is determined by the vom The control signal generated by the low-pass filter 4-2 is increased so that the last up-counted pulses are adequate in the subsequent case Have amplitudes (see waveforms D and F) to ensure stable operation. If, on the other hand, a potentiometer is initially set so that the end of the programming pulse appears at a point in time when the amplitude of the counting pulse is just below the threshold of the up / down counter 52 (see waveforms A and B), then the Frequency of the superimposed signal reduced, so that the last pulses counted up at the time in question are not close to the threshold and stable operation is guaranteed (see waveforms A and C).

Since changes can only lead to gradual changes in frequency in the duration of the programming pulses, the accuracy of the tuning means described herein, the working phase-locked loop is primarily dependent on the accuracy of the crystal oscillator 40. However, to ensure that the oscillator frequency is not from a tuning position to the other changes, the tolerance (expressed as time) in the duration of the programming pulses must be smaller than the shortest interval between the output pulses of the superimposed signal

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Prescaler 32. Assuming that the output signal of the prescaler 32 has a duty cycle of 50 #, then The following relationship applies with regard to the tolerance for the duration of a programming pulse:

(T) (M) (P) <0.5 P. (D

Here, T is the tolerance for the duration of the programming pulse from the output of the monostable multivibrator 4-8; M is the number the output periods of the upper bearing signal pre-scaler counted during the duration of a programming pulse, and P is the period of the output signal of the superposition signal prescaler 32.

The above relationship (1) can also be simplified in form

1 1
write t <iy yyy. In the preferred embodiment described above, M varies from 73 to 24-5. Therefore the smallest tolerance for the duration of the programming pulse is equal to ■ r * T— or about + 0.2 #. The following elements and factors influence the tolerance of the programming pulse duration: The monostable multivibrator 4θ, the potentiometers 4-6, the capacitor 50 »the supply voltage + V of the monostable multivibrator 4-8 and the operating temperature. The influence of supply voltage fluctuations can be made negligibly small if the integrated component SN74-121 TTL (transistor-transistor logic) from the manufacturer Texas Instruments is used for the monostable multivibrator. The integrated module SN74-121 has a temperature coefficient of +80 ppm (parts per million), which can be compensated by a capacitor with a negative temperature coefficient, such as the Erie type capacitor "Red Caps 8111", which has a temperature coefficient of -80 +30 ppm. For the potentiometer assigned to the multivibrator, elements such as the multi-turn potentiometer (Multitura potentiometer) of the Spectrol type No. 4-7 can be used, whose temperature coefficients are +50 ppm. With this proposed choice of the components, the tolerance of the programming pulse duration is over a temperature range between 0 ° and 4O ⁰ C is approximately between -0.16 and

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+ $ 0.16, so definitely within the desired limit of O, 2 #.

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Claims (10)

Claims Arrangement for tuning a receiver for reception any of several high frequency carriers characterized by: a plurality of passive timing elements (46) which are assigned to individual high-frequency carriers; a monostable multivibrator (48) for generating a programming signal; a program selector (44) via which one of the passive time-determining elements can be selectively coupled with the monostable multivibrator to the duration of the Set programming signal; a local oscillator (18) for generating a Superposition signal, the frequency of which can be set by a control signal; a first counter (5 ^ 0 ♦ the one when it is applied counts up to a fixed number K with a signal; a second counting device (52) which, when a signal is applied, individual signal periods up to one programmed number M, determined by the duration of the programming signal; an input switch (56) via which the superimposition signal is selectively transmitted to the first and second counting means can be coupled to generate an output signal whose period is directly related to a number N = K + M stands for the period of the superimposition signal and which contains an interval in which the programmed number M is stored in the second counter; a phase comparator (36), the one for the phase and Frequency deviations between a reference frequency signal and generating a characteristic error signal from said output signal and, therefrom, the control signal for the local oscillator dfeited. 809818/0910 - 15 - ORIGINAL INSPECTED 2. Arrangement according to claim 1, characterized in that the second counting device (52) has a display device (60, 62) is coupled to a programmed number in relation to the programmed number stored in this counter M to be displayed visibly, and that with the display device a blanking device (63, 64) is coupled to switch off the display device when the overlay signal is coupled to the second counter is. 3. Arrangement according to claim 1 or 2, characterized in that the second counting device (52) is an up / down counter with an up count input and a down count input is; that said fixed number K is greater than said programmed number M; that the input switch (56) the overlay signal simultaneously to the first counter (54) and to the up-counting input of the Up / down counter couples until the first counter has a number equal to said first count of signal periods has been counted, and that the input switch then sends the overlay signal to the downward counting input of the up / down counter couples until the up / down counter reaches the programmed number M has counted starting in the reverse direction to 0, and that the input switch then the overlay signal coupled again to the first counter and to the up counting input of the up / down counter 4. Arrangement according to claim 3 »characterized in that the Up / down counter 52 generates said output signal, when the count value 0 is reached. 5. Arrangement according to claim 1, 3 or 4, characterized in that in response to the generation of said output signal, the first counter (54) is reset and the programming signal is started and the forward / - 16 - # 809818/0910 Down counter 52 is switched to up counting. 6. Arrangement according to one of claims 1, 2 or 3 »thereby characterized in that the blanking of the display device (60, 62) between the time at which the programming signal comes to an end, and the point in time when the first counter (5 * 0 said fixed number K of signal periods counts, is canceled. 7. Arrangement according to claim 1, characterized in that the superimposition signal is sent to the input switch (56) via a Frequency divider (32) is supplied, which generates a pulse train with a frequency below the frequency of the heterodyne signal Repetition frequency generated, and that the duration of the programming signal has a tolerance that is less than the shortest Time interval between pulses of the said pulse train 8. Arrangement according to claim 1, characterized in that the passive time-determining elements (46) are ohmic elements. 9. Arrangement according to claim 1 or 8, characterized in that the passive time-determining elements (46) are changeable Resistance elements (46a) included. 10. Arrangement according to claim 1,8 or 9, characterized in that the number of time-determining passive elements (46) is smaller than the total number of high-frequency carriers allocated to the frequency reception range of the receiver are· 80981870910