DE2744245C2 - Circuit arrangement for fading in and out of pulses in a pulse train - Google Patents

Description

The invention relates to a circuit arrangement for fading in and out of pulses in a pulse train, J5 especially for the purpose of clock correction of the primary clock of a plesiochronous time division multiplex system according to the positive-negative stuffing technique.

DE-AS 21 17 344 discloses a method and a device for deriving a t-s clock pulse from one Pulse having pulse gaps while maintaining the mean number of pulses per unit of time known. This method can be applied at the receiving end to a pulse occurring at the output of a demultiplexer will. In contrast, the invention is a circuit arrangement that the Clock adaptation to the line clock is used

From DE-OS 25 57 609 a multi-bit phase shifter is also known starting point of this phase shifter is a circuit in which a given frequency and an oscillator-supplied frequency in divided in the same way, compared by a phase detector and its output signal as a control signal used for the oscillator. This circuit serves as a phase shifter to generate a phase difference between the given frequency and the frequency supplied by the oscillator, the phase difference being Changing an element of the timing element and / or the control voltage of the oscillator in the holding area of the Phase locked loop is adjustable

For the clock adjustment of plesiochronous multiplex systems there are two possibilities used in practice.

With the so-called positive stuffing technique, the sending side ensures that the Primary clocks are an amount above the frequency of the primary clock required on the receiving side. Receiving side is continuously compared to the required primary clock by fading out individual impulses faster clock according to the separately transmitted clock adjustment information to the correct one Value slows down circuit arrangements that do the job of fading out impulses when Solve positive stuffing technology are known. This also includes the use of an oscillator with a phase-locked loop (Phase Locked Loop) to recover the primary clocks from the multiplex clock at the status of the Technik (Fernmeldechnik, 15 [1975] H. 2, pp. 56-58. VEB-Verlag Technik).

The second correction method does not require a predefined increase in the clock rate on the transmission side. With her is also a with each clock increase of the transmitting-side clock generator over the target clock Transmit a special correction signal as in the case of a cycle lowering below the target cycle

This "positive-negative stuffing technique" has the advantage that on the one hand it can be used to write a bit, word or Frame-by-frame nesting is possible and, on the other hand, the channels when transitioning to a synchronous network for the timing adjustment information and marking the start of the superframe for other tasks can be used.

The "positive-negative stuffing technique" is more difficult than the positive stuffing technique accomplishing task of not only fading out individual impulses from a clock pulse sequence, but these also be: to fade in a negative clock deviation on the transmit side in the clock pulse sequence.

Two methods are known for solving this problem.

The first method is based on an oscillator for clock processing, which is a multiple the primary clock frequency must generate. The correction pulses are inserted and hidden at this high clock rate. For this purpose, very fast Schottky TLL circuits are used necessary that must be operated at their upper limit frequency. Despite this A relatively high proportion of jitter is present even with higher clock adjustment frequencies (DE-AS 20 23 656).

In another method, a very complex circuit is necessary in order to minimize jitter in the clock to regain. This circuit arrangement is, however, when several are connected in series Systems multiplexer-demultiplexer no longer usable (Bylstra, J. Α .: Α Technique for Smoothing Justification Jitter in Digital Systems with Low Justification Rates. Report No. 6982; Telecom Australia, Research Laboratories).

Based on the aforementioned prior art, the object of the invention is to provide a circuit specify, in particular the insertion of individual clock pulses in the clock to be corrected can be done almost as easily as the fading out of clock pulses in the positive stuffing technique. The clocks recovered in this way should have as little jitter as possible and the circuit should not require too much effort.

This object is achieved by the circuit arrangement specified in the claim Use of two identical pulse adapters with a downstream divider, one of which is in the clock feed and the other is switched into the feedback loop of a phase locked loop, one results very simple circuit that can also be used for purposes other than

operational to clock correction is connected to the circuit arrangement according to the invention, a clock pulse is determined by the Einblendbefehl first unterdrückt- in the feedback loop of the phase locked loop, the phase locked loop more than offset this reduction in frequency at its input, where it is, the output from the voltage controlled oscillator output frequency increases by exactly one clock pulse

The advantage of the circuit arrangement is that only pulses have to be suppressed and needle pulses no longer have to be inserted into a pulse series and that a frequency that is many times higher is no longer required. The circuit arrangement works independently of the frequency and the change of the positive and negative clock adjustment information; r> also works when several systems are connected in series, multiplexer-demultiplexer. The clock jitter is suppressed to a sufficient degree from a few Hertz (depending on the low-pass filter TP) so that no bit errors due to excessive jitter amplitudes are to be expected in the transmission devices. For the use of the circuit arrangement for clock recovery it is important that low-power Schottky TLL circuits can be used for multiplex systems of the 1st and 2nd order, which have a low power consumption and allow a high degree of integration.

In the following the invention is explained in more detail with the aid of a block diagram and two pulse diagrams explained so

B i 1 d 1 shows in the block diagram a circuit arrangement for recovering the plesiochronous clocks of the subsystems of a time division multiplex system of a higher order from the multiplex clock T _n and the clock adjustment information C + or C-.

The circuit arrangement according to the invention is the essential, but not the only component of the Block diagram.

From the received multiplex clock T _n , a clock frequency T _{x is} formed in the illustrated part of the demultiplexer with the aid of a first phase-locked loop PLL 1, which corresponds to the clock frequency of the multiplexer-demultiplexer system if no stuffing commands have been sent, d. h, if the clock frequency T _{x of} the subsystem of 2.048 Mbit / s can be derived directly from the multiplex _{frequency T n} of 8.448 Mbit / s. The first phase locked loop is not part of the invention and is therefore shown scheniatisch only in a common circuit block PLL I is composed in known manner of divider stages, the _n the multiplex clock frequency T, = 8.448 Mbit / s and the frequency of the associated quartz-stabilized voltage controlled oscillator to a divide common frequency. The voltage-controlled oscillator is then set to the synchronous frequency Zi = 2.048 Mbit / s of the subsystem via a phase comparator and a low-pass filter

The pulse adapter 1 connected to the output of the phase-locked loop allows the clock pulses T _x to pass unhindered until a fade-out command C indicates that the current frequency of the demultiplexer must be reduced. In the pulse adapter 1 a clock pulse is then deleted. This process is shown in the pulse diagram of Figure 2, lower line, using the divider 1, which divides the new clock frequency T ₁ ' by the factor m and a phase comparator PK with subsequent low-pass filter TP in very A second phase-locked loop PLL 2 is now controlled at a low cut-off frequency. In addition to the phase comparator PK and the low-pass filter TP with a very low cut-off frequency, it consists of a crystal-stabilized voltage-controlled oscillator VCO with a large capture range. The pulse adapter 2 with its divider 2 is now looped into the feedback loop of the phase locked loop PLL2 between the voltage-controlled oscillator VCO and the phase comparator PK . In the pulse adapter 2 something similar happens as in the pulse adapter 1. If the clock does not have to be corrected or only needs to be slowed down, the pulse adapter 2 lets the clock pulse h generated by the voltage-controlled oscillator ViCO through unhindered. If the cycle has to be increased (C +), a pulse is first deleted from cycle h , as with the fade-out command. This process is shown in B i 1 d 3, lower line The reduced by one pulse series of pulses / 2 'in the downstream divider 2 π divided by the factor at the phase comparator PK f \' ln and T {ln compared with each other and control the Phase-locked loop in such a way that the fading out of a pulse in the feedback loop of the phase-locked loop increases the output frequency / 2 of the voltage-controlled oscillator VCO by one pulse.

The following table shows the dependence of the output frequency f ₂ on the clock frequency T \ of the subsystems and the clock adjustment information C + and C-.

C-

C +

/ 2

O O 1 O O 1

-/1

By deleting individual pulses in the direct path of the frequency T _x to be corrected to the phase comparator PK , a lower frequency / 2 is set in the phase-locked loop PLL2, and by deleting individual pulses in the feedback branch of the phase-locked loop between the voltage-controlled oscillator VCO and the phase comparator PK , a higher frequency is set Frequency / i set The pull range of the phase locked loop PLL 2 must correspond to the maximum possible frequency change of the subsystem.

The circuit arrangement according to the invention can be used wherever single pulses to a Pulse train must be added or removed from it.

Hietzu 1 sheet of drawings

Claims (1)

Claim: Circuit arrangement for fading in and out of pulses in a pulse train, in particular for Purpose of clock correction of the primary clock of a plesiochronous time division multiplex system according to the positive-negative stuffing technique, characterized, that two identical pulse adapters, which are only suitable for masking out ι ο pulses, each with a divider in series, are connected to each input of a phase comparator (Ρφ,
that the first pulse adapter controlled by the fade-out command (C-) is switched on in the clock feed of the uncorrected clock (fi) and causes a clock decrease in a known manner,
that the second pulse adapter, controlled by the fade-in command (C +), in the feedback circuit is a phase-locked loop consisting of the phase comparator (PK), a low-pass filter (TP) with a very low cut-off frequency and a voltage-controlled oscillator (VCO) that oscillates at the corrected clock frequency (f ₂ ) ( PLL 2) is switched on, so that the fade-out of a pulse initially caused by the fade-in command in the feedback circuit causes the voltage-controlled oscillator to increase the clock frequency (h) by one pulse