DE2557609A1 - MORE BIT PHASE SHIFTER - Google Patents

Description

2b57609

Licentia Patent-Verwaltungs-GmbH PT-BK / Mon / jo

HK 75/31

Multi-bit phase shifter

The invention relates to a controllable electronic phase shifter with a wide displacement range.

In digital technology, there is often the task of creating a To shift clock sequence compared to a signal sequence steadily.

From DT-OS 21 55 489 a circuit is known which shift a clock sequence over several pulse periods can. This circuit works in such a way that a delay stage triggered by the pulses of the input pulse is provided, the delay time by a voltage applied to a control input it is controllable that a voltage generator generates a voltage that changes the delay time uniformly and the control input of the delay stage, and that

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ciiKi ro incidence level ascertains if the temporal «Tand dot. delayed output signal of the delay rate from an input impulse a given measure under & chroitet and then emits a signal at the output that converts the voltage generated by the voltage generator to a Returns the initial level.

This proposed solution has the stated problem the following disadvantages: only pulses with a large pulse duty factor can be processed; the circuit is not suitable for very high frequencies; while the clock sequence is shifted, its frequency changes temporarily versus the given input frequency, and also the circuit requires a considerable Expenditure.

The task leading to the invention was to provide an optimal phase shifter which enables a phase shift over more than + _ 1/2 period, while keeping the pulse duty factor constant and equal to 1: 1 when setting the phase shift, no frequency change during setting the phase shift results, can process very high frequencies, and finally the circuit should be able to be produced with little effort.

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The object is achieved as described in the claim.

Using a circuit example according to FIG. 1 and a pulse diagram according to Fig. 2, the mode of operation will be explained in the following.

Fig. 1 shows a phase-locked loop (phase-lockcdloop), which in addition to the basic components, such as phase detector 2, low-pass filter 3i voltage-controlled oscillator 5, additionally two identical frequency dividers 1 and 6, an analog adder 4 and / or an adjustable capacitance 7 contains.

Basic information on how the phase locked loop works:

The task of a phase locked loop is in general is to synchronize an oscillator in frequency and phase with an input signal. Im synchronized The state is the phase shift between the input signal and the oscillator signal zero or at least a minimum; as soon as a phase shift occurs between the two signals, the oscillator will continue to operate automatically readjusted until the phase shift is again zero or minimal.

A distinction is made between different types of

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2557603

Phase-locked loops, which are characterized by different phase motors or special low-pass filters, for example, according to the task in structure. There is s +. B. phase detectors which emit an average control voltage with a phase shift of 90 between the input signal and the oscillator signal, so that the oscillator oscillates at its center frequency ω.

Each phase-locked loop has a frequency range in which it applies to the. synchronized state and then remains locked in phase; this area is called the capture area. In addition, there is a hold area in which the synchronized state is maintained, although the input frequency changes compared to the oscillator frequency - in this case the phase position between the input signal and the oscillator signal is shifted, so that a control voltage is created for the oscillator that changes its frequency and thus minimizes the phase error φ again.

In the locked state there is always a constant phase error φ between the input signal and the oscillator signal, in addition to the 90 caused by the phase detector. Bs applies

- 90 ° <0 <+ 90 °,

so that the maximum range of the phase error 0 = * + _

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, .557609

is. If the phase error becomes larger, ilantt koniint dr. c- i'i.; i.st nr β ge J sch 1 ei Te out of step. In most cases, win! v.-seeks to keep the phase error φ as small as possible, I ₁ I ₁ It-Ui one makes the loop amplification of the ßegelbchleil'e possible.st ^: κ.ι.

In the proposed phase shifter, Ηκ .. ~, «· η-control circuit, on the other hand, has a small circular gain. . g, SO) that the largest possible phase angle 0 can result in n. A phase shift over the range 0) as * j ^ 90 addition is achieved by ,, dall the Ειι »£ .ί: ικ" - freejuenz: ^, and the Oszillatorfreqtxenz be> divided by equal frequency divider to dan factor N l; dat means an increase in the range of the phase shift θ between the input signal and the oscillator signal by N times.

Setting the desired phase shift 9 from outside can be done in two different ways, dit; even can be used side by side. For one, changes the frequency of the oscillator 5 by an additional control voltage, which is via the analog adder 4 of the Phase locked loop is fed, on the other hand you can change the center frequency of the oscillator with the help of an adjustable capacitance 7.

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ORIGINAL INSPECTED

.) ■

For the phase shift 9 between input signal a (t) and the output signal a (t), only the state of the phase-locked loop of Ut is in the locked state; ti iu t ti / it;, ie a phase shift is only possible within the range of the Hn! Preceded by ei non üuIKt »'!!
If, for example, the capacitance of the spanmingsjc-controlled oscillator and thus the center frequency of the oscillator intervenes, then the oscillator cannot oscillate at the new center frequency ω in the locked state (ω = ω always applies in the locked state), the phase locked loop then acts in such a way that it creates a
Control voltage is generated, which makes the oscillator oscillate at the original frequency ω. The control voltage required for this can only arise when a phase shift occurs between the input signal and the oscillator signal.

As the input frequency and the oscillator frequency, respectively are divided by the factor N, the compares

Phase detector 2 shows the phase position of the signals S and S.

-jr- and -

ω ω ^{x 2}
with the lower frequencies -jr— and —-, which can only be shifted by 0 = + _ 90, but for the input signal e (t) or! Output signal a (t) with the high frequencies ω = ω, this means a maximum phase shift of

θ = N - 0

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IMSFECTEO

As a pulse diagram, FIG. 2 shows an example with N = 10, in which a θ = 900 results for φ- 90 for the phase shift between the input signal e (t) and the output signal a (t).

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Claims (1)

Claim Application of to synchronize an oscillator a given frequency by a circuit known as a phase locked loop in which the given frequency and that supplied by the oscillator is compared in the same way divided by a phase detector and its output signal is used as a control signal for the oscillator, as a phase shifter for generating a phase difference between the given frequency and the frequency supplied by the oscillator, the phase difference being changed by changing one Element of the timing element and / or the control voltage of the oscillator adjustable in the holding area of the phase locked loop is. BK 75/31 709826/0509 ORIGINAL INSPECTED