DE2741683B2 - Planar diffusion process for making an NPN silicon planar - Google Patents
Planar diffusion process for making an NPN silicon planarInfo
- Publication number
- DE2741683B2 DE2741683B2 DE19772741683 DE2741683A DE2741683B2 DE 2741683 B2 DE2741683 B2 DE 2741683B2 DE 19772741683 DE19772741683 DE 19772741683 DE 2741683 A DE2741683 A DE 2741683A DE 2741683 B2 DE2741683 B2 DE 2741683B2
- Authority
- DE
- Germany
- Prior art keywords
- lattice
- emitter
- phosphorus
- diffusion
- planar
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000009792 diffusion process Methods 0.000 title claims description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims description 8
- 229910052710 silicon Inorganic materials 0.000 title claims description 6
- 239000010703 silicon Substances 0.000 title claims description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 12
- 229910052698 phosphorus Inorganic materials 0.000 claims description 12
- 239000011574 phosphorus Substances 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 10
- 239000013078 crystal Substances 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 5
- 230000035515 penetration Effects 0.000 claims description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims 3
- 229910052796 boron Inorganic materials 0.000 claims 3
- 238000004519 manufacturing process Methods 0.000 claims 2
- 238000005259 measurement Methods 0.000 claims 2
- 230000003647 oxidation Effects 0.000 claims 2
- 238000007254 oxidation reaction Methods 0.000 claims 2
- 125000004437 phosphorous atom Chemical group 0.000 claims 2
- 230000008602 contraction Effects 0.000 claims 1
- 230000007547 defect Effects 0.000 claims 1
- 230000003292 diminished effect Effects 0.000 claims 1
- 239000000463 material Substances 0.000 claims 1
- 230000007704 transition Effects 0.000 claims 1
- 230000000903 blocking effect Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 2
- 238000005496 tempering Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910001385 heavy metal Inorganic materials 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 238000005204 segregation Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0804—Emitter regions of bipolar transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Bipolar Transistors (AREA)
Description
,, = y .-\ d = R ■ 4,532 d, I In 2 ,, = y .- \ d = R ■ 4.532 d, I In 2
wobeiwhereby
R der in Ohm gemessene Wert der Vierspitzenmethode und d die Dicke des Objektes ist, wofür die Tiefe des Emitter-Basis-Übergangs im vorliegenden Falle zu setzen ist, da ein pn-übergang aufgrund seiner sperrenden Eigenschaften die Dicke des Objektes begrenzt. Demnach gilt R is the value of the four-point method measured in ohms and d is the thickness of the object, for which the depth of the emitter-base junction is to be set in the present case, since a pn junction limits the thickness of the object due to its blocking properties. Accordingly, the following applies
η = 4,532 · R ■ Xj [U ■ cm] η = 4.532 · R ■ Xj [U ■ cm]
so daßso that
ist.is.
R -= R - =
4.5324,532
wi Wendet man nun andererseits die allgemein bekannte Formel für einen Widerstand mit der Länge /und dem Querschnitt q If, on the other hand, one applies the well-known formula for a resistance with the length / and the cross-section q
auf ein Widerstanclselrment mit ileni rechteckigenon a resistance element with ileni rectangular
Querschnitt g= / · λγ, an, so ergibt sichCross-section g = / · λγ, an, then results
Dabei ist zur Unterscheidung der unterschiedlich definierten Widerstände der dimensionslose Ausdruck / α (per square) mit in die eckige Klammer genommen worden.The dimensionless term is used to differentiate between the differently defined resistances / α (per square) put in square brackets been.
Durch Vergleich von (1) und (2) ergibt sichComparing (1) and (2) gives
4,532 R [U] = Rs [U/ Π ] .4.532 R [U] = R s [U / Π].
Das Verfahren der Erfindung wird im folgenden anhand der Zeichnung erläutert, deren Figuren in üblicher Schrägschliffdarstellung zu den Hauptflächen einer Silicium-Platte Schliffe durch integrierte Planartransistoren zeigen, welche durch Versetzungen verursachte Schädigungen aufweisen, wie sie bei einer nicht durch die Bemessungsregel nach der Erfindung erfolgten Dotierung der Emittervordiffusionsschicht auftreten.The method of the invention is explained below with reference to the drawing, the figures of which in the usual beveled view of the main surfaces of a silicon plate. Grinds through integrated planar transistors show the damage caused by dislocations that one does not the emitter prediffusion layer is doped by the dimensioning rule according to the invention appear.
In Korrelationsuntersuchungen — meßtechnisch durch Sperrkennlinienanalyse, optisch durch Anätzen der Halbleiteroberflächen mit einer eigens entwickelten Strukturätzlösung — konnte nachgewiesen werden, daß über bei der Vordiffusion induzierten Versetzunglinien 1 die Störstellendiffusion rascher erfolgt als im ungestörten Kristallgebiet Dadurch entstehen Unregelmäßigkeiten über die Diffusionsfront an der Emitter-PN-Übergangsfläche, wie sie in F i g. 1 und 2 veranschaulichen. Lokal beschleunigte Phosphordiffusion entlang den Versetzungslinien 1 führen zu sperrspannungslimitierenden Ausbuchtungen (3 in Fig. 1) oder auch zu Kurzschlüssen (4 in F i g. 2) zwischen der Emitterzone 5 und der Kollektorzone 6.In correlation studies - metrologically through blocking characteristic analysis, optically through etching the semiconductor surfaces with a specially developed structure etching solution - it could be proven that over dislocation lines 1 induced during the prediffusion, the impurity diffusion takes place more rapidly than in the undisturbed Crystal region This creates irregularities over the diffusion front at the emitter-PN junction, as shown in FIG. 1 and 2 illustrate. Locally accelerated phosphorus diffusion along the dislocation lines 1 lead to bulges (3 in FIG. 1) that limit the blocking voltage or also to them Short circuits (4 in FIG. 2) between the emitter zone 5 and the collector zone 6.
Die F i g. 3 veranschaulicht einen weiteren Effekt, der beim Eintempern einer Aluminium-Kontaktierungsschicht 7 auftritt Beim Eintempern dieser Kontaktierungsschicht 7 entstehen nämlich Legierungskristalle 8, die innerhalb des Emitterkontaktierungsgebietes an Kristallversetzungslinien 1, 1' und 1" rascher in den Halbleiterkörper wachsen.The F i g. 3 illustrates another effect that occurs when tempering an aluminum contacting layer 7 when tempering this contacting layer 7 namely, alloy crystals 8 arise, which grow within the emitter contact area Crystal dislocation lines 1, 1 'and 1 "grow more rapidly in the semiconductor body.
to Folge solcher anhand der Fig. 1 und 3 veranschaulichten Störungen sind verringerte Abbruchspannungen der PN-Übergänge oder auch Kurzschlüsse, abgerundete Sperrkennlinien durch Schwermetallausseigerungen an Versetzungslinien und hohes Rauschen.to sequence of those illustrated with reference to FIGS. 1 and 3 Faults are reduced breakdown voltages of the PN junctions or short circuits, rounded off Blocking characteristics due to heavy metal segregation on dislocation lines and high noise.
Beim Planardiffusionsverfahren nach der Erfindung kann die Phosphordotierungskonzentration in der Vordiffusionsschicht mittels einer Teilmaskierungsschicht aus Siliciumoxid auf ausreichend geringe Werte abgesenkt werden. Zum gleichen Zweck kann der Partialdampfdruck der Dotierungsverbindung bei der Abscheidung aus der Dampfphase vermindert werden. Dies kann über die Zusammensetzung der Gasphase mittels eines Trägergases erfolgen oder durch Variation der Betriebstemperatur der Dotierquelle.In the planar diffusion method according to the invention, the phosphorus doping concentration in the Prediffusion layer to sufficiently low values by means of a partial masking layer made of silicon oxide be lowered. For the same purpose, the partial vapor pressure of the doping compound in the Deposition from the vapor phase can be reduced. This can be done through the composition of the gas phase take place by means of a carrier gas or by varying the operating temperature of the doping source.
Bei einem Ausführungsbeispiel des Planardiffusionsverfahrens nach der Erfindung wurde die Phosphordotierungskonzentration so weit reduziert, daß bei einer Eiiidringtiefe von ca. 1,5 μπι die Emitter-Vordiffusionsschicht einen /?-Wert. von 1,1 bis 1,7 Ω aufweist. DieserIn one embodiment of the planar diffusion method according to the invention, the phosphorus doping concentration was used reduced so far that at a penetration depth of approx. 1.5 μm the emitter prediffusion layer a /? value. from 1.1 to 1.7 Ω. This
jo Wert liegt also überraschenderweise nicht einmal eine Größenordnung unterhalb der bisher üblichen, so daß eine Verschlechterung der Stromverstärkungswerte kaum nachweisbar ist.jo We r t so is surprisingly not even an order of magnitude below the usual, so that a deterioration of the current gain values is barely detectable.
Hierzu 1 Blatt Zeichnungen1 sheet of drawings
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19772741683 DE2741683C3 (en) | 1977-09-16 | 1977-09-16 | Planar diffusion process for making an NPN silicon planar transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19772741683 DE2741683C3 (en) | 1977-09-16 | 1977-09-16 | Planar diffusion process for making an NPN silicon planar transistor |
Publications (3)
Publication Number | Publication Date |
---|---|
DE2741683A1 DE2741683A1 (en) | 1979-03-22 |
DE2741683B2 true DE2741683B2 (en) | 1979-09-20 |
DE2741683C3 DE2741683C3 (en) | 1980-07-10 |
Family
ID=6019082
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE19772741683 Expired DE2741683C3 (en) | 1977-09-16 | 1977-09-16 | Planar diffusion process for making an NPN silicon planar transistor |
Country Status (1)
Country | Link |
---|---|
DE (1) | DE2741683C3 (en) |
-
1977
- 1977-09-16 DE DE19772741683 patent/DE2741683C3/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
DE2741683C3 (en) | 1980-07-10 |
DE2741683A1 (en) | 1979-03-22 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
OAP | Request for examination filed | ||
OD | Request for examination | ||
C3 | Grant after two publication steps (3rd publication) | ||
8320 | Willingness to grant licences declared (paragraph 23) | ||
8339 | Ceased/non-payment of the annual fee |