DE2738713A1 - Analogue electronic timepiece display - uses concentric rings of display elements coupled to decoder and counter network - Google Patents

Abstract

The analogue display comprises two concentric rings, each with 60 radical display elements. EAch ring has a set of 12 spaced display elements, used for displaying the hours, coupled to one of the 12 outputs of a respective 1 out of 12 decoder (A, C). The binary outputs of the seconds counter (I) and the minutes counter (K) are coupled via a multiplier to the inputs of one decorder (A). The reset output of the seconds counter (I) is coupled to one of two further counters (L, M) each counting to 5 and coupled via a second multiplier (F) to a 1 out of 5 decoder (B). The latter together with a further 1 out of 5 decoder (D) is coupled via an inverter to one of the respective sets of display elements coupled in parallel.

Description

Electronic clock with analog display

Addition to the patent .. (Patent application P 26 41 779.8-31) In the main patent is an electronic clock with an analog display consisting of sixty on a circle arranged display elements for the hours / minutes and on another concentric circle arranged twelve or sixty display elements for the hour or hour / minute display, the display elements with one of counters, multiplexers and decoders existing control logic according to the hour, minute and and seconds and, if applicable, the date are controlled in such a way that the binary-coded outputs of the counters are fed to a multiplex arrangement will, their output signals to a decoder for decoding to control the display elements are supplied, described, which is characterized in that each sixty Display elements interconnected to form a matrix consisting of rows and columns are, the rows of display elements connected in parallel with the Outputs of a single 1-out-of-n decoder (n = number of elements in a row) and the other poles (anodes) of the display elements are connected together to form a column and that the ABDC inputs of the 1-out-of-n decoder with the binary-coded outputs a first multiplexer are connected, the inputs of which with the binary-coded Outputs of two counters for the seconds / minutes counting only up to the number n and / or minute-hour counting are connected and that the interconnected to one column each Poles (anodes) of the display elements, if necessary via drivers and inverters with the The inputs of a second multiplexer are connected to the outputs a counter counting up to the number of columns for the seconds / minutes and / or Minutes / hours are connected ..

The present invention has set itself the task of the circuit arrangement in such a watch, in which mechanical hands are used to simulate the course of the movement sixty display elements are provided on each of two concentric circles, The display elements on the inner circle show the hours in each case Show 12-minute intervals and the display elements on the outer circle each together with the corresponding inner Display elements show the minutes, with the outer display elements only showing the Perform seconds display, controlling the two rows of display elements takes place between seconds and minutes and minutes and hours in multiplex mode, to improve significantly.

To solve the problem set according to the invention, an electronic Clock proposed as described in claim 1.

With the clock according to the invention, the essential advantage is achieved, that with simple and relatively few components the above display the hours, minutes and seconds can be done by replicating the hands.

Furthermore, according to the present invention, a development of indicated in the main patent proposed electronic clock, which consists in that in addition to the electronic analog display by simulating the movement of the pointer in the or a digital display of the hours and / or minutes on the dial and / or seconds.

According to a preferred embodiment is located within the Dial a window in which the digital display, for example with 7-segment elements, takes place can.

To control the 7-segment elements, a known one is used suitable control logic proposed in cooperation with the aforementioned Control logic for the analog display can be integrated into the circuit arrangement.

According to a further development, it is also possible to use a control display the logic for a 7-SegcRent display, in which then the / time, in addition for example inside the dial; with the help of 7-segment display elements can be carried out. A suitable converter is then connected to the 7-segment outputs provided by 7-Segrent in the 1-out-of-10 code. The 1-out-of-10 code will then be used accordingly the measures of the main application or claim 1 of the present invention prepared for an analog display.

Based on the drawings, preferred embodiments are to be used as an example the subject matter of the invention will be explained in more detail.

In the drawing, FIG. 1 shows a schematic representation of the circuit arrangement an electronic clock with a simulated analog display.

Fig. 2 shows the plan view of a dial of a clock with electronic Analog display and additional digital display.

3 shows in principle a possible circuit for the display with the dial shown in FIG.

As can be seen from Fig. 1, twelve display elements are in each case present Case light-emitting diodes, on two concentric rings, as in Figs. 7 and 8 of the main patent shown connected in a matrix arrangement. Together the two series result in Display elements the seconds / minutes display or the minutes / hours display.

The cathodes of the light-emitting diodes or other display elements are used for this purpose connected to the outputs of a 1-of-12 decoder A for the seconds / minutes display. The cathodes of the minutes / hours display are summarized in the same way and connected to the outputs of a 1-out-of-12 decoder C. The grouped in columns The anodes of the display elements are connected to a 1-out-of-5 decoder B resp. D connected.

To carry out the display, a counter-to-twelve 1 for the seconds provided, the outputs of which are connected to a first multiplexer E. are. The reset output of counter I is connected to the input of a counter-bis-five L connected, whose -to twelve reset output with the input of the minute counter connected is.

The outputs of the counter K are connected to the multiplexer E.

The reset output of the counter K is connected to the input of another Counter -to-five and at the same time with the input of another -bi -two counter tied together. The outputs of the counter L and M are connected to the multiplexer F, whose outputs are connected to the decoder-1-Ausfünf B. At the same time they are Outputs K and M each connected to a further multiplexer G and if, the Outputs of the counter N to the multiplexer G and the outputs of the Counter -to-five O are connected to the multiplexer H.

The multiplexers G and H are the same as the multiplexers E and F are each connected to a 1-of-twelve decoder C and a 1-of-five decoder D. The multiplexers can be controlled, for example, by alternating 50 Hz pulses will.

When the input of the counter I receives 1-second pulses are then connected to the decoders A and B by the display elements the seconds and minutes are displayed at the same time.

By further counting up to twelve, the decoders C and D the display elements for the minutes and hours are controlled in such a way that that only one display element is activated for the hour display while one display element from the first group and one from the second to display the minute Group can be controlled to form a longer line.

In Fig. 2 is a modified version of the electronic clock shown according to the invention. Within a number blott 1 with the first Circle of display elements 2 for the seconds / minutes display and the second circle the display elements 3 for the minute / hour display is a digital display 4, consisting of two, four or six 7-segment elements.

This digital display can display the seconds and / or the minutes and / or make hour display in digital form while the Analog display of the time by the outer circles of the display elements mentioned above 2 and 3 is carried out.

In Fig. 3 is a circuit arrangement for implementation in principle the double display with the dial shown in FIG.

Here, a normal clock circuit 5 is operated by an oscillator 6, which with its 7-segment = outputs the individual 7-segment display elements 4 controls. The 7-segment outputs are simultaneous with a converter 7 for the conversion from the 7-segment code to the 1-out-of-ten code. The exits this converter 7 are via an adaptation logic 8, the decoders A and C. and correspond to the multiplexers E and G of Fig. 1, with the cathodes of the display elements in connection. The anodes are connected together and with the adaptation logic 9, which corresponds to the decoders B and D and the multiplexers F and H of Fig. 1, connected to the common control lines of the 7-segment display elements is switched. Of course, the converter 7 can also be a converter of the 7-segment code be in the BCD code.

With this circuit arrangement it is possible, in addition to the digital Display in the 7-segment display 4 is an analog display in the one shown above Way to perform.

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Claims (4)

P a t e n t a n s p r U c h e Electronic clock with analog display, consisting of sixty display elements arranged on a circle for the hours / Minute display and twelve or arranged on another concentric circle sixty display elements for the hour or Hour / minute display, with the Display elements with a control logic consisting of counters, multiplexers and decoders according to the hours, minutes and seconds to be displayed and, if applicable of the date can be controlled in such a way that the binary-coded outputs of the counters a multiplex arrangement, the output signals of which are fed to a decoder for the decoding for controlling the display elements are supplied, according to patent ... (patent application P 26 41 779.8-31), characterized in that with two concentric circles of sixty display elements each with two rows of twelve display elements one pole (cathode) of a row together to one of the twelve outputs of two 1-out-of-twelve decoders (A, B) and the others, each connected to a column Poles (anodes) each via an inverter to one of the five outputs of two 1-out-of-five decoders (B, D) are switched, and that the binary outputs of the seconds counter that counts up to twelve (I) and the minute counter (K) via the first multiplexer (E) to the inputs of the first I-out-of-12 decoder (A) are connected, and that the reset output of the counter (I) with the entrance a counter-to-five (L) is connected, whose Outputs with the outputs of a further counter-up to-five (M) via a second Multiplexer (F) are connected to the first 1-out-of-five decoder (B), the The reset output of the counter (L) is connected to the input of the counter (K), its reset output with the input of the counter (M) and an input of a another counter-to-twelve (N) is switched, its reset output with the input Another counter-to-five (o) is connected, the outputs of the counter (N) with the outputs of the counter (K) via a multiplexer (E) to the decoder (C) and the outputs of the counter (0) with the outputs (M) via the multiplexer (H) are connected to the decoder (D). 2. Electronic clock according to claim 1 or one or more Claims of the main patent, characterized in that in addition to the analog display an additional digital display, preferably with the help of 7-segment display elements or in the display panel or dial of the clock by a separate or combined Control logic is provided controlled. 3. Electronic clock according to claim 2, characterized in that the control of the additional digital display through a corresponding transformation and adaptation from the control logic according to claim 1 is carried out. 4. Electronic clock according to claim 2, characterized in that one 7-segment control logic (5) controlled by an oscillator (6) is used, whose 7-segment outputs are connected to the 7-segment display elements (4), with the 7-sepent outputs simultaneously via a 7-segment-in-1-out-of-ten codo converter (7) are connected, which via an adaptation logic (8) it the display elements for the analog display is connected.