DE2729309A1 - Measuring appts. data processing circuit - converts analogue to digital signal and performs convolution operation - Google Patents

Abstract

A signal processing circuit includes a microprocessor (1), a read only memory program store (2) and an RAM intermediate store (3) for the necessary data volume. An active or passive low-pass filter network (4) having a cut-off frequency of less than half the sampling frequency of the arrangement and an 8-bit analogue/digital converter (5) are connected to the input. A further low-pass filter (7) and a digital/analogue converter (6) are connected to the output. The setting of an evaluation function is made by means of a numerical keyboard (8). Instead of software controlled operation, a hard-wired circuit (9) may be employed to serve as a convolution calculation network.

Description

Arrangement for preprocessing

of electrical signals to be represented by measuring devices ========================================== The invention relates to an arrangement for preprocessing electrical Signals generated by recording measuring devices (chart recorder, x-y recorder, y-t recorder or the like) or by indicating measuring devices (oscilloscopes). Such arrangements are required to avoid noisy electrical signals in the frequency range from 0 Hz to approx. 1 kHz through matched filtering before being displayed on a To process a recorder or an oscillocope in such a way that an extensive elimination of noise, Averaging or adjusted Filtering takes place. Furthermore is a largely arbitrary filtering with one of the arrangement's own or from the outside adjustable lip pulse response possible.

This kind of signal processing is e.g. in biophysical experiments, biomedical examinations and generally useful wherever signals freed from noise or artifacts prior to their display or automatic evaluation, should be averaged or subjected to special filtering.

Known arrangements for achieving this goal are based on the following Principles: - on the use of process computers (relatively expensive) - on classic Signal processing with an adjustable filter, averaging or similar (the apparatus Effort is high and the setting awkward) - due to the inertia of the display device (e.g. recorder) that can be used for averaging (optimal signal processing is not possible with it).

The disadvantages of these methods are mainly that they either expensive equipment and software to be written specifically for preprocessing need or that when exploiting existing Device properties using electrical auxiliary circuits only an approximate, but in the sense the required operation to be performed on the signal by no means optimal signal processing can be achieved.

The invention is therefore based on the object of the aforementioned disadvantages to overcome known working methods and devices and to develop an arrangement, with which the desired signal processing is optimal at comparatively low costs, i.e. carried out with extensive adaptation to the properties of the signal can.

It has now been shown that this task can be achieved with an arrangement of the type mentioned above can be solved when the input signal of a microprocessor-controlled, a circuit arrangement containing a buffer can be fed between the source of the input signal and the connected measuring device and the real-time convolution, each with the help of a predeterminable, causal or non-causal impulse response - referred to below as the evaluation function - that the input signal of the desired operation (essentially noise reduction, moving averaging, adapted filtering).

According to a preferred embodiment of the invention, the respective Evaluation function adjustable with a numeric keyboard. On the other hand, can but also within the Invention of folding with the help of a Number of preprogrammed evaluation functions stored in an additionally inserted memory which can be called up via function keys. A combination of the the latter working method with the use of a numeric keypad setting certain evaluation functions are also possible.

Finally, according to a further embodiment, it is that of the invention Arrangement still provided, in addition a fast hardware arithmetic unit for convolution operations insert to the computation speed over the speed caused by solution the number of convolution operations in software can be further increased.

When using the arrangement according to the invention, the input signal first subjected to a low-pass filtering to remove signal components whose frequencies are above of the area still detectable by the arrangement of the order of magnitude of 1 kk lie, cut off. This avoids aliasing effects when digitizing. The signal filtered in this way is recorded in the subsequent analog-digitul converter 8 bit quantized. A higher resolution is not necessary because the Amplitude resolution of common recorders and oscilloscopes is no more accurate than 8 bit (corresponding to approx. 0.25%).

The signal processing, i.e. the convolution with a certain, from User prescribed evaluation function (, impulse response of the arrangement) is done at such a rate that there is no major data caching occurs in the arrangement according to the invention. Only the current signal parts are used cached in a memory for the time range over the the convolution becomes effective are required to calculate the output signal. The arrangement thus works in real time (so-called real-time operation), i.e.

that the user from the task of signal parts of interest to him to acquire and retrieve for display after calculation, is exempt. Its operating measures are limited to entering the evaluation function before starting the signal evaluation and the observation of the output devices (recorders, oscilloscopes).

Further features, advantages and possible uses of the invention are based on the following description of further details as well as the attached illustrations emerged.

FIG. 1 shows the block diagram of an embodiment of the invention Arrangement and FIG. 2 in a graphical representation a symmetrical evaluation function g (t).

The arrangement according to the invention consists in the embodiment according to FIG. 1 of a central microprocessor 1, a program memory (ROM) 2 and an intermediate memory (RAM) 3 for the instantaneous intermediate storage of the amount of information required for calculating the output signal (approx. 100 bytes at the electrical input the arrangement is a passive or active low-pass filter network 4, the cut-off frequency of which is less than half the sampling frequency of the arrangement, (e.g. a sampling frequency of 2.2 kiiz corresponds to a cut-off frequency of 1 kHz) together with an 8-bit analog Digital converter 5. On the output side there is a counterpart to this a digital-to-analog converter 6 and a further low-pass filter 7 for smoothing the steps in the output signal resulting from the 8-bit quantization is entered on a numeric keypad 8, which is part of the arrangement Program provided that a convolution of the shape k is an integer; e.g. -10 ~ + 10.

performs. Here Yi (ty) mean the vth quantized to 8 bits digital value of the input signal sampled at time intervals to, -k 1t0 to + k t ~ describes the time range over which the input signal is subjected to the evaluation function g (t) is weighted. The formula clearly shows that e.g. in case a symmetrical evaluation function, this weighting is symmetrical on both sides to a current value yfitv), i.e. signal parts yi (ty-ktO) which both removed by equal negative and positive time intervals kto from a value Yc (t,) are weighted with the same value g (kto).

An example of a symmetric weighting function g (t) is in Figure 2 shown. The convolution operation provides the output signal y8 (t). In the event of The convolution also follows a non-symmetrical evaluation function g (t) carried out this formula.

There is one more detrimental effect in this formula: because the Sampling frequency 1 / to is fixed, the time range is given by of the interval -k 1t0 ... + k 1t0 is also given, i.e., both for slow changing signals as well as faster changing signals (up to the maximum Cut-off frequency of the arrangement) can only occur within a fixed time limit Area to be folded.

That is very undesirable. One possibility to increase the time range expand consists in the variation of the sampling frequency.

This way is common, but requires a concurrent one Variation of the cut-off frequency of the input filter for aliasing effects even if the filter is changed To prevent sampling frequency. The change in sampling frequency is therefore only possible in stages for reasons of effort.

Another way to change the time range of the convolution is that the arrangement always with the maximum sampling frequency (approx. 2.2 pilz, corresponding to 1 kllz cut-off frequency) is operated and per program via a comparable selection of values of the input signal yi (tV) is averaged so that E.g. the number of further used averaged values is reduced accordingly and the time interval between two consecutive averaged Values yi (tV) so that it becomes a multiple of the sampling period t. You can do this do without switchable filters.

As an alternative to control with an input signal that is used as a time signal Yi (t) takes place (as in the formula shown above) in the case of coupling the proposed arrangement to a device that supplies an external clock, the Possibility provided instead of the temporal sampling of the process with the the arrangement's own sampling frequency, including the control of the arrangement through this external clock. To this end, the proposed arrangement has one Externally accessible interface for 8-bit digital signals (bit-parallel) directly behind the normally used A / D converter.

In a further preferred embodiment of the invention will a catalog of common evaluation functions is permanently stored in the program memory and accessed via function keys that are also part of the input keyboard. Based on experience with the evaluation of noisy spectra that are used in experiments were obtained for the evaluation of the serum electrophoresis, in particular one Weighting with weights corresponding to a Causs function has proven its worth / 1 /. A third The embodiment of the invention dispenses entirely with a numerical one for reasons of cost 10-key keypad: only function keys are stored permanently for calling up Evaluation functions and the program-controlled time adjustment provided.

All embodiments of the invention have in common that the signal processing Arrangement on a printed circuit board, approximately the format of a European map, accommodated can be.

Only the keyboard is expediently housed externally and connected to the circuit board via a separable plug connection. The power supply the arrangement is from a conventional, commercially available, to be connected via a plug connection Power supply module accepted.

On the particular advantage of this invention over the known Method of averaging using time constants (i.e. causal networks) is also pointed out: The convolution operation using Xausal networks can only weight the past of a signal, i.e. in principle all Signal parts yi (t) from t. - # oobis at the moment tv just reached with the evaluation function Link g (t). The arrangement according to the invention leads because it has a memory in which a certain time range of the signal to be filtered y1 (t) is temporarily cached, also a weighting of signal parts by, for t 7 ty applies. This non-causal behavior is only possible with a circuit arrangement possible, which contains a buffer. The advantages of non-causal convolution lie in the better averaging of signals ("sliding averaging") and the possibility of matched filtering for the optimal Adaptation of the evaluation function to the signal property is generally non-causal Impulse response required.

The solution of the folding operation can be done purely in software or by means of a special one to be connected to the microprocessor, shown in FIG. 2 Dotted lines indicated, folding arithmetic unit 9 can be made. This convolution calculator consists essentially of a fast hardware multiplier with a downstream Summing element for the convolution sum. This allows the computing speed and thus further increase the input frequency range / 2 /.

Claims (4)

Claims 1. Arrangement for preprocessing electrical Signals that are to be represented by recording or indicating measuring devices, characterized in that the input signal is one of a microprocessor (1) controlled circuit arrangement containing a buffer (3) can be supplied is that between the source of the input signal and the connected test tool is inserted and the convolution in real time with the help of a predefinable, causal or non-causal impulse response, here called evaluation function, such causes the input signal to be subjected to the desired operation. 2. Arrangement according to claim 1, characterized in that the respective Evaluation function can be set with a numeric keypad (8). 3. Arrangement according to claim 1 or 2, characterized in that the Folding with the help of a number preprogrammed, in one Additionally Inserted memory of stored evaluation functions, which can be called up via function keys are, is feasible. 4. Arrangement according to one of claims 1 to 3, characterized in that that in addition a fast llardware arithmetic unit for convolution operations was added is.