DE2717383A1 - CIRCUIT ARRANGEMENT FOR REGULATING THE BRAKING PRESSURE IN THE CONTROL PHASE IN BLOCKING PROTECTED VEHICLE BRAKING SYSTEMS - Google Patents

Description

27,7383

WABCO UESTINGHOUSE GMBH, Hanover Hanover, April 14, 1977

WP 19/77

Circuit arrangement for regulating the brake pressure in the control phase with anti-lock Vehicle braking systems

The invention relates to a circuit arrangement for regulating the brake pressure in the control phase in anti-lock vehicle brake systems with at least the rotational behavior a vehicle wheel scanning transducers, with the measured values evaluating threshold levels, with a control device for Control of inlet valves to control the brake pressure in the control phase, the control device timing elements and has a device for an initially rapid increase in brake pressure and subsequent slower pulsed or throttled brake pressure increase during the regulated rebuilding of the brake pressure.

It is already known that the characteristic curve is initially steep and then flatter in the pressure control phase to be provided. The time for the steep pressure control phase was determined using a pressure switch. An adaptation to the respective existing coefficient of friction was only partially possible.

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It is also already known to initially open the inlet valve for a predeterminable time in order to rapidly increase the brake pressure to be controlled and after this time has elapsed via a timer by means of a pulse generator to control the inlet valve for a further slow increase in brake pressure. This takes place continuously Adjustment of the respective time for the rapid increase in brake pressure. Because of the envisaged continuous adjustment is this procedure is relatively expensive.

The object of the present invention is therefore to provide a circuit arrangement of the type mentioned at the beginning, through which a sufficient adjustment of the time for the steep control phase to the respective existing coefficient of friction is achieved and the circuitry requires little effort.

According to the invention, this object is achieved in that the inlet valve is assigned to the predetermined friction coefficient ranges for predetermined times and is constant for these ranges are controlled for a rapid increase in brake pressure.

As a result of the solution according to the invention, the steep control phase is no longer adjusted steplessly, but rather in predetermined steps as a function of predetermined friction coefficient ranges (/ A value ranges). The hitherto relatively large circuit and control engineering effort can be reduced considerably as a result. The time levels are assigned to certain μ -value ranges and thus to certain control pressure ranges.

Since the frequency of the control signals and thus the control cycles is relatively high for smaller μ values, it is provided according to an advantageous further development of the invention that the inlet valve over a predetermined range of smaller μ values

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a timer and a pulse device for rapid brake pressure increase only for the pulse rise time (t.) of the pulses of the pulse device is controlled. Another embodiment of the invention for the range of smaller ytx values is characterized in claim 14.

In order to avoid excessive pulsed activation and thus underbraking in areas of middle fx values, a further development of the invention provides that for a given middle y value range, a timer for the steep activation phase of the activation time t for the Inlet valve is switched on for a time t _x . Another embodiment of the invention for the range of mean yu values is characterized in claim 15.

With larger M values, the risk of overbraking is lower, since in the upper brake pressure range the pressure gradient decreases with increasing control time and there is the risk of underbraking with pulsed or throttled pressure control. Therefore, according to another development of the invention, it is provided that the pulse device is switched off for a predetermined range of larger jj values and the inlet valve is actuated for rapid brake pressure increase until a delay signal occurs without any time restriction. A further embodiment of the invention for the range of greater u. -Values is characterized in claim 16.

Advantageous more detailed configurations of the circuit arrangement according to the invention are characterized in the further subclaims.

The invention will now be explained in more detail with reference to the accompanying drawing, in which exemplary embodiments are shown.

Show it

1 shows an example of a circuit arrangement according to the invention,

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Fig. 2 is a diagram in which it is shown

which pressure curves are used for the control phase in the various u. -value ranges, Fig. 3 is a diagram showing the pressure curve and

shows the control criteria in the various predetermined / Lt value ranges, and FIG. 4 shows a diagram in which an example of the rule for lanes with changing JU. Value ranges is shown.

The circuit arrangement according to FIG. 1 has two memories 2 and 4, which via fall delay timers 6, 8 and Io and logic modules 12, 14 and 16 with the outputs of acceleration and deceleration threshold levels, not shown are linked. All three drop-out delay timers are triggered by dropping the acceleration signals (+ b signals). The drop-out delay timer 6 controls the set input of the memory 2, its associated preparation input from Delay control signals (-b control signals) via the logical Block 12, which is an negator, is controlled. The timer 8 controls the logic module 14, which is an AND gate is, the reset input R of the memory 2 on. The -b signal is applied to the other input of AND gate 14.

The timer Io controls one preparation input of the Memory 4. The set input assigned to this preparation input is activated directly by the -b signal, which activates the second preparation input of memory 4 via logic module 16, which is an inverter, during which this preparation

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Set input assigned to the input with the output of the timer 8 connected is.

The circuit arrangement also has two further drop-out delay time elements 18 and 2o as well as a response delay time element 22. The timer 18 is an AND gate 24 with a inverting and a non-inverting input. The + b signal is at the non-inverting input placed and to the inverting input of the output of the memory 4, which is also to an input of a second AND gate 26 is placed / whose other input is controlled by the + b signal. The outputs of the timers 18 and 22 and of the AND gate 26 are combined in an OR gate 28, the output of which with the input of the timer 2o is connected. The output of the timer 2o is via a NOR gate 3o to the input of the Timing element 22 fed back, whereby a pulse switching is realized. The output signal of the timing element 6 is also fed to the NOR gate 3o via an inverter 32. The output of the memory 2 is connected to an inverting input of an AND gate 34 placed, whose other non-inverting input is connected to the output of the NOR gate 3o.

The output of the AND gate 34 is via an OR gate 36 connected to an inlet solenoid valve 38. The inlet solenoid valve is also controlled directly by the + b and -b signals (not shown). The -b control signal also controls the Timers 6 and 8 and resets them.

The function of the circuit is to be described below, reference being made to FIGS. 2 to 4 at the same time target.

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It is assumed that both memories 2 and 4 are initially at "low". This is not a limitation because also any other initial state is possible. Then the AND gates 24 and 34 are switched on and the AND gate 26 is blocked.

When the + b signal drops, the timing elements 6, and Io are activated, which then run, and on the other hand the AND gates 24 and 26 are activated. By the fall of the + b signal the inlet valve is de-energized, i.e. pressure is applied.

Since the AND gate 24 is switched through, the timer 18 is activated and expires. At the same time, the timer is activated and also expires. The high signal appearing at the output of the timing element 2o is negated by the inverter 3o so that the inlet valve 38 cannot be activated, ie remains de-energized until the timing element 18 and then the timing element have expired. It is thus in the control phase for the time t_ = t. + t. steeply controlled. Time t ₁ is the delay time of timing element 18 and time t_ is the delay time of timing element 2o. These relationships can be seen in FIGS. 2 to 4 in the diagrams or diagram sections for mean JLt values.

After the timer 2o has elapsed, a low signal appears at its output, which now negates and controls the inlet valve, which is thereby excited, whereby the pressure is maintained. The high signal at the output of the inverter 3o also controls the response delay timer 22 via the feedback line, the output of which only occurs after a time t has elapsed. goes to "high" so that the inlet valve remains _{energized for the time t 4 (pressure holding phase}

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when pulsing). The high signal controls the timer 2o again on, whose negated output signal de-energizes the inlet valve again / so that pressure is applied again until the timer has expired again. After the expiration, the timer 22 is activated again. And the whole process repeats itself. This pulsing process through the timers 22 and 2o and the inverter 3o is followed by the occurrence of the next -b control signal Expiry of the timer 6 ended, at the output of which a low signal then appears, which appears as a high signal at the NOR gate 3o and thus sets the output of the NOR gate to low, whereby the control of the timer 22 is interrupted. The memory 2 goes high, which also blocks AND gate 34.

If no -b signal occurs, then until it occurs Pressure applied steeply. This is shown in Fig. 3 in the lower diagram and in Fig. 4 in the part of the characteristic curve for gross yu.

If the total control time for the steep control phase t is less than the delay time t_ of the timer lo, occurs a -b signal on without a timer having expired. In the present case, the time t_ should be 90% of the time t_, i.e. 90% the sum of the delay times t and t-. The -b signal resets the timers 6 and 8 and the memory 1 via the AND gate 14. The timer Io is still running, so that the memory 4 goes high and the AND gate 24 blocks and the AND gate 26 switches through, so that in the next control cycle only the timing element 2o is controlled via the OR gate 28 when the + b signal falls is, so that steeply only for the time t, brake pressure is applied in the control phase. This is in Fig. 2 in the diagram section

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for small ytx values, in Fig. 3 in the upper diagram and in the 4 is shown in the middle section of the diagram for small M values.

If the total control time for the steep control phase t is less than t ~ and less than t _g , but greater than t _? is, then the timer Io has expired while the timers 6 and 8 are still running. t ₅ and t _g are the time delays of the timers 6 and 8. In this case, the memory 4 is low, whereby the AND gate 26 is blocked and the AND gate 24 is switched through, so that, as already explained at the beginning, a steep one Adjustment phase for mean yw values is achieved. This is shown in FIG. 2 in the middle diagram section, in FIG. 3 in the middle diagram and in FIG. 4 in the left diagram section.

If the total control time t is less than t, but greater than t ,. is, then the timers 8 and Io have expired; the Timer 6 is still running, however, so that a high signal is present at its output. Memory 2 stands as long as there is no -b signal occurs, to high, so that the AND gate 34 is blocked and the inlet valve 38 can not be activated, so still de-energized remain.

When the -b signal occurs, the timer 6 is reset, the preparation input of the memory 2 is no longer activated, and the memory 2 remains high because it cannot be reset because the AND gate 14 has already expired timer 8 is blocked. The memory 4 remains in its low state. The -b signal ends the control phase and initiates the curtailment phase. This is shown in Fig. 1 in the lower diagram.

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In addition to the pressure characteristics, the time course of the + b and -b control signals is also shown in the figures. In addition, FIG. 2 shows the timing of the wheel speed and the control signals for the inlet and exhaust valve shown.

Finally, some realistic numerical values for the time and fX values mentioned above are mentioned as examples:

te = 3oo ms

t _£ = loo ms ο

t_ = 9ο% of t ₂ (t ₂ =

t. = 2o ms

t = 2o - 25 ms

t, = 60 ms

small yut value range: <O.25 avg. / w. -Value range: ~ O.25 - o.5 large yw value range:> o.5

In addition, it should be noted that in connection with the description the invention explained pulse device for pulsed pressure increase in the control phase in principle also by a Throttle device is replaceable.

The circuit arrangement according to FIG. 1 shows an analog implementation of the invention, but this is not intended to be a limitation. A digital circuit implementation is also possible.

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Claims (16)

Claims Ι.ΐ Circuit arrangement for regulating the brake pressure in the control phase in anti-lock vehicle brake systems with the rotational behavior of at least one vehicle wheel scanning transducers, with threshold levels evaluating the measured values, with a control device for controlling inlet valves to control the brake pressure in the control phase, the control device timing elements and a Device for the initially rapid increase in brake pressure and subsequent slower pulsed or throttled brake pressure increase during the regulated rebuilding of the brake pressure, characterized in that the inlet valve or valves (38) are controlled for predetermined times, the predetermined friction coefficient ranges are assigned and are constant for these ranges, for rapid brake pressure increase will. 2. Arrangement according to claim 1, characterized in that the inlet valve (38) for a predetermined range of smaller values via a timing element (2o) and a pulse device (2o, 22, 3o) 809844/0097 .a. to increase the brake pressure quickly, only for the impulse rise time (t-) of the impulses of the impulse device. 3. Arrangement according to claim 1, characterized in that a time t is switched on for a predetermined mean yu value range via a timing element (18) for the steep control phase of the control time t for the inlet valve (38). 4. Arrangement according to claim 1, characterized in that the pulse device (2o, 22, 3o) is switched off for a predetermined range of greater u values and the inlet valve (38) is activated for rapid brake pressure increase until a delay signal occurs without a time limit. 5. Arrangement according to one of the preceding claims, characterized in that at least two memories (2, 4) are provided whose output signals by controlling or blocking the timing elements (18, 2o) and the pulse device (2o, 22o, 3o) the different, times assigned to the yes value ranges (t_; t. + t ,; no time) for the rapid pressure build-up in the control phase determine. 6. Arrangement according to claim 5, characterized in that the memory (2) two timing elements (6, 8) are connected upstream, which can be controlled by the + b control signal and of which the one timing element (6) the dynamic input of the memory ( 2) and the other timing element (8) controls the reset input (R) of the memory (2) via an AND gate (14). 809844/0097 .3 · 7. Arrangement according to claim 5, characterized in that the memory (4) is preceded by a timing element (lo) which can be controlled by + b control signals and controls a preparation input whose associated dynamic input can be controlled by the -b control signals. 8. Arrangement according to claim 5 or 6, characterized in that the timing element (6) is a fall delay timing element with a larger delay time (t) for determining the control time for larger yu values. 9. Arrangement according to claim 7, characterized in that the timing element (lo) is a fall delay timing element with a smaller delay time (t) for determining the control times for the areas of small and medium yu values. 10. Arrangement according to claim 5 or 7, characterized in that via the second memory (4) a fall delay timer (18) and a pulse device (2o, 22, 3o) or only the pulse device can be switched on for pressure control at mean fJL values or at small fj. Values. 11. The arrangement according to claim 5 or lo, characterized in that the pulse device consists of a fall delay timer (2o) and an upstream response delay timer (22), the input of which via a NOR gate (3o) to the output of the timer (2o) connected is. 809844/0097 12. Arrangement according to one of the preceding claims, characterized in that the inlet valve (38) is preceded by an AND gate (34) which can be blocked by the memory (2) in the case of large yu values for pulses from the pulse device. 13. Arrangement according to one of the preceding claims, characterized in that the output of the timing element (6) via an inverter (32) to the NOR gate (3o) is applied, so that the pulse device (2o, 22, 3o) after expiration of the timing element can be blocked. 14. Arrangement according to claim 1, characterized in that a throttle valve is provided via which the brake pressure increase is throttled for a predetermined range of smaller JLt values at the beginning of the control phase. 15. Arrangement according to claim 1 or 14, characterized in that a throttle valve (or the throttle valve according to claim 14) is provided over which for a predetermined range of mean jJL values after a certain time t_ (t_ corresponds to the sum t ₁ + t_ according to claim 3) after the start of control, the brake pressure increase takes place in a throttled manner. 16. The arrangement according to claim 1 or 14 or 15, characterized in that a throttle valve (or the throttle valve according to claim 14 or 15) is provided which is larger than jj for a predetermined range. Values will not be switched and that the inlet valve (38) until the occurrence of a delay signal driven without time limit for the rapid increase in brake pressure 8Q98U / 0097