DE2710270A1 - CIRCUIT ARRANGEMENT FOR GENERATING SYNCHRONIZATION PULSES - Google Patents

Description

PATENT LAWYERS

MANITZ. FINSTERWALD & GRÄMKOW

Munich, the P / Sv - M 3189

..3HU.

The Marconi Company Limited Marconi House, New Street, Chelmsford, Essex CMl IPL

Circuit arrangement for generating synchronization pulses

The invention relates to a circuit arrangement for generating pulses with incoming data pulses are synchronized.

Such a circuit arrangement is required, for example, on the receiving side of a telephone line which the incoming data does not have the clock pulses required for synchronization. In order to the received, incoming pulses by introduction into a clock register from the serial form to the parallel Form can be converted, clock pulses used for synchronization must be generated.

The present invention is intended to provide a circuit arrangement for performing the operation described above be created; according to the present invention

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DR. C. MANITZ ■ DIPU-INC. M. FINSTERWALD DIPL.-INO. W. CRAMKOW ZENTRALKASSE BAYER. FOLK BANKS

β MÖNCHEN SS. ROBERT-KOCH-STRASSf I 7 STUTTGART 00 (BAD CANNSTATTI MÖNCHEN. ACCOUNT NUMBER 72

TEL. <Οβ9> 22 42 II. TELEX 5-29672 PATMP SEELBERCSTR. 23/25. TEL. C07III56 72 61 POSTAL CHECK. MONKS 77062 -

holds a circuit arrangement for generating pulses, which are synchronized with incoming data pulses, a read-only memory to the phase difference between compare first and second counters; the read-only memory stores the count of the second counter such that a predetermined phase difference occurs between the counters; the first counter carries one Counting cycle during the period or duration of a bit cell of the incoming data pulses, while the The second counter's counting remains static or unchanged until it passes through the read-only memory once during every period of a bit cell is checked; after each incoming data pulse, the read-only memory generates a Synchronization pulse when the count of the first counter is equal to the count of the second counter plus a predetermined one Counting whole numbers from the first counter

As used herein, "bit cell" means the period of one bit of serial data, where it It does not matter whether serial data is present or not.

According to a preferred embodiment, a locally or locally generated sequence of pre-clock pulses is independent of the incoming pulse data is applied to the first counter; the output of a synchronizer is connected to the first input of a pair of AND gates, the second inputs of which are respectively are coupled to outputs of the read-only memory so that the first input of one of the elements is excited when the the first counter has a count greater than that of the second counter, and the second input of the other Member is energized when the first counter has a count that is smaller than that of the second counter

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is; the synchronizing element can receive the incoming data pulses receive and the first input of the members synchronously with pulses from the read memory on the desired excite the second entrance of the limbs.

In a preferred embodiment, the first counter generates a staircase waveform having sixteen pulse levels in circulation before repatriation; in such an embodiment, the synchronizing pulses can be generated if the count of the first counter is equal to the count of the second counter plus eight pulse stages of the first counter is.

The invention will be described in the following on the basis of exemplary embodiments with reference to the accompanying schematic Drawings explained in more detail.

Show it:

1 shows a block diagram of a circuit arrangement according to the present invention; and

2a, b, c, d and e are graphs of time-dependent and clock waveforms, respectively, occurring at various Places of the circuit arrangement according to FIG. 1 are generated.

The circuit arrangement shown in Fig. 1 has an input 1 to the locally or locally generated pre-clock Pulses at a frequency sixteen times the frequency of the incoming one are applied to a port 2 applied serial data. The pre-clock pulses shown in Fig. 2a are fed to a counter 3; for example, the type of counter manufactured and sold by Texas Instruments can be used as the counter

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No. 741 61 can be used; the counter 3 generates a return staircase waveform of sixteen incremental steps synchronous with the pre-clock pulses (Fig. 2b). The counter 3 is via a four-bit address multiple line connected to a read or read-only memory 4, which, for example, by the integrated circuit type no. 36ol-l of Monolithic Memories Inc. can be formed. Another counter 5, for example type no. 74193 from Texas Instruments, is also through a four-bit address line connected to read-only memory 4; the counters 3 and 5 as well as the read-only memory 4 are designed in such a way that that the read-only memory 4 is preprogrammed to to serve as a comparator for the counts registered by the counters 3, 5.

The read-only memory 4 has two outputs 6, 7; the terminal 6 receives a signal when the count of the counter 3 is greater than that of the counter 5, while the terminal 7 receives a signal when the count of the counter 3 is smaller than that of counter 5. The connections 6 and 7 are each with the respective input of AND gates 8, 9 connected, for example by the type no. 7400 from Texas Instruments. The pre-clock pulses are also sent to a synchronizing element 10 given that the incoming data pulses from the terminal 2 can receive. The synchronizing link 10 uses the pre-clock pulses to synchronize pulses at each transition or passage of the incoming data pulses to generate with pulses at each of the connections 6, 7 of the read-only memory 4, so that a further input of a each AND gate 8, 9 is excited. The output signal from the AND gate 8 is to an up-counting Input of the counter 5 applied, while the output signal from the AND gate 9 to a downward-counting input of the counter 5 is applied. The read-only memory 4

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has a further output 11, at which the desired pulses are generated that coincide with the incoming Data pulses are synchronized. The read memory 4 is preprogrammed so that the synchronized Pulses at terminal 11 occur when the count of counter 3 is eight pulse steps more than the count of the counter 5.

This circuit arrangement functions as follows: the first incoming data bit causes a first output pulse of the synchronizing element Io (shown in FIG. 2d); It should be assumed for the start of the first incoming data bit that the count of the counter 3 is five (see FIG. 2b) and the count of the counter 5 (shown in FIG. 2c) is seven. Because the count of the counter 3 is smaller than that of the counter 5, the read-only memory generates an output signal at the connection 7, so that the AND element 9 is activated, since a pulse from the synchronizing element 10 is also present. The counter 5 is thus held statically or permanently at a lower count of six. Because the read only memory 4 is programmed to produce an output on terminal 11 when the count of counter 3 equals the count of counter 5 plus eight, a clock sync pulse (shown in Fig. 2e) becomes synchronous with the fourteenth Stage of the staircase waveform of the counter 3 (see Fig. 2b) at the terminal 11 is generated. At the next transition of the incoming D _a TenBITS the Synchronisierglied 10 applies a pulse to again, to energize one of the terminals of the AND gates bathe 8.9, and the counter 3 has again a count of five on. The previously static count of the counter 5 is still greater than that of the counter 3, and so an output signal is derived again at the terminal 7 of the read-only memory, so that the AND gate 9 is controlled to incrementally increase the count of the counter 5 backwards five

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to count. The synchronization pulse appearing at terminal 11 is generated when the count of counter 3 is thirteen, i.e., the count of counter 5 is five is, plus aaht. At the next transition, i.e., the third pulse shown in Figure 2d, the counts are in the two counters 3 and 5 are the same, so that no realignment or readjustment of the counter 5 is necessary is.

It can therefore be seen that if the phase of the incoming data bits deviates by more than one sixteenth one cycle with respect to the count in the counter 3, the count in the counter 5 is increased by one or is decreased while the position of the synchronization pulse is reduced by one sixteenth of a cycle of counter 3 is reset. This feature has the additional advantage that if a noise spike occurs between the transition pulses according to FIG. 2d at the output of the synchronizing element 10 the count of the counter 5 depending on the counts of the counters 3 and 5 up or down, so that the Phase of the synchronizing pulse at terminal 11 (see Fig. 2e) by only one sixteenth of a cycle the count of counter 3 is set.

-Patent claims-

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Claims (3)

Claims 1.Circuit arrangement for generating pulses that are synchronized with incoming data pulses, characterized by a read-only memory (4) for comparing the phase difference between a first and a second counter (3,5) and for setting such a count of the second counter (5) that there is a predetermined phase difference between the counters, the first counter (3) a counting cycle during the period of a bit cell of the incoming data pulses while the counting of the second counter remains static until it is read by the read-only memory (4) is checked once during each bit cell period, and after each incoming data pulse the Read memory (4) generates a synchronization pulse when the count of the first counter (3) is equal to the Count of the second counter (5) plus a predetermined integer count of the first counter (3) is. 2. Circuit arrangement according to claim 1, characterized in that a locally generated sequence of pre-clock pulses (Fig.2a), which are independent of the incoming pulse data, applied to the first counter (3) is, and that the output of a synchronizing member (lo) each with a first input of a pair of 809819/0535 _ ₈ _ -Sr- AND gates (8,9) is connected, the second inputs each with outputs (6,7) of the read-only memory (4) are connected in such a way that the second input of an AND gate (8) is excited when the count of the first counter (3) is greater than that of the second counter (5), and the second input of the other AND gate (9) is excited when the count of the first counter (3) is less than that of the second counter (5) is, and that the synchronizer (lo) the incoming Receives data pulses and the first input of the AND gates (8,9) synchronously with pulses from the read memory (4) energized at the desired second input of the AND gates (8,9). 3. Circuit arrangement according to one of claims 1 or 2, characterized in that the first counter (3) is in front the feedback generates a staircase waveform (Fig. 2a) with sixteen pulse steps, and that the synchronizing pulses (Fig. 2e) are generated when the count of the first counter (3) is equal to the count of the second counter (5) plus eight pulse stages of the first counter (3). 809819/0535