DE2702964A1 - VIDEO TIME BASE CORRECTOR - Google Patents

Description

Patent attorneys

Dipl. Ing. H. Wni. knair. Dipl. Phy-. Dr. K. Fir.cke? 7 Γ)? 9 R Λ

Dipl. Ing. F. Λ. W .. knnrn. 0 * 1. Cl.cm. B. Huber Z / U ^ 3 O ^

8 Miiuctun SU, M-Jhlitraße 22

QUANTEL LIMITED
Maidenhead House,
Bartholomew Street,
Newbury, Berkshire, England

Video time base corrector

The invention relates to a video time base corrector with an analog-digital converter for converting an incoming analog video signal into digital form, a memory for recording successive ones Lines of video information in digital form from said converter, a digital-to-analog converter for converting a digital output signal from said memory in analog form, a control device for inputting the digital information into said memory and for outputting the same from the memory, a triggerable voltage-controlled Input oscillator for determining the speed at which the said analog signal is converted into digital form and the speed at which it is input into said memory and an output oscillator for controlling the output speed of the digital information the mentioned memory and the conversion speed in analog form.

Time base correctors are used, for example, in magnetic image recording systems (MAZ) for correcting errors in the timing of the signal generated at the output of the magnetic image recording system with respect to a constant one Synchronous signal used. These errors occur due to changes in the tape transport speed and the scanning device of the magnetic image on the drawing system.

Time base correctors can also use a compensator for reinstallation of information lost as a result of oxide tape imperfections (See e.g. British Patent No. 1,436,757 and U.S.A. Patent No. 3,949,416).

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In known time base correctors, this is done by the magnetic image recording system incoming video signal converted into digital format by an analog-to-digital converter (ADC). The digital output from the ADU is in a Stored memory, which will expediently have a capacity of one or more complete television lines. The output from the memory

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is converted into an analog video signal by a digital-to-analog converter (DAC) implemented.

The incoming video signal is determined by the input oscillator Clock frequency converted to digital format. The frequency of the input oscillator has the timing variations of the output signal from follow the magnetic image recording system.

The information entered from memory into the DAU is subject the control of an output oscillator, which is generally applied to a local synchronization signal and consequently a has a fixed frequency.

According to the working principle, the information is sent at a speed "* speed, which is dependent on the fluctuations occurring at the output of the magnetic image recording system, are entered into the memory, however issued from memory at a constant rate. The system therefore causes time fluctuations in the video signal switched off.

In a known arrangement, the input oscillator, which is designed to track the information coming from the magnetic image recording system, is in the form of a phase-locked loop. In such a ¹ ^ "system, a voltage controlled oscillator running at an appropriate switching frequency produces an output which is used to drive the ADC. The output is also applied to a system of multipliers and dividers which reduces the frequency to exactly the frequency of the television line frequency The output of the system is applied to one input of a phase discriminator, the other input of which comes from the synchronizing pulse for separate lines from the magnetic image recorder.

The phase discriminator generates a variable voltage at its output » which is designed to control the frequency of the voltage controlled oscillator in such a way that the phase error on the two Inputs of the discriminator is close to zero.

In such a system, however, the instantaneous frequency of the voltage controlled oscillator is a function of the output of the phase

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discriminator over several previous lines. Therefore if there is a phase error between the signal coming from the tape and the voltage controlled one Oscillator occurs, there is a limited response time before the error can be reduced to zero. For some types of dated Band coming time disturbances, it is not possible to be phase-locked Provide a loop that perfectly tracks the signal coming from the tape (i.e. with a time accuracy that is sharp enough).

The one in our concurrent UK patent applications Correctors disclosed in Nos. 11793/74 and 11794/74 (U.S.A. Patent Nos. 3,971,063 and 3,978,519) will provide more accurate compensation for timing errors achieved in that a triggerable oscillator is provided, which only on an incoming synchronization pulse or on a color sync signal and a sync pulse signal is triggered. However, since the frequency error occurs on the next incoming line is corrected, the error correction is always carried out with a delay of one line.

The invention is based on the object of a digital time base corrector that corrects frequency errors within the same television line.

According to the invention, this object is achieved in that a scanning device for sampling the voltage controlling the input oscillator during a line, a measuring device for determining a voltage difference in the control voltage during successive lines, holding means for holding the between successive lines detected voltage difference and a phase shift device for the phase shift of the output oscillator as a function of the voltage difference recorded by said holding device are provided.

Furthermore, according to the invention is a method for compensating for speed errors in a video time base corrector with an analog-digital

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Converter, a digital memory, a digital-to-analog converter, a triggerable voltage controlled input oscillator and an output oscillator provided, said method including determining the input oscillator control voltage during a line, measuring the voltage difference detected during successive lines,

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the recording of the voltage difference measured for at least one line and the phase shift of the output oscillator as a function of the voltage difference to compensate for speed errors at the output of the memory.

Exemplary embodiments of the invention are described below with reference to the drawings explained in more detail. Show it

Figure 1 is a block diagram of an embodiment of our pending British Patent Applications Nos. 11793/74 and 11794/74 (U.S.A. Patent Nos. 3,971,063 and 3,978,519) disclosed video time base corrector,

FIG. 2 shows waveforms for the operation of the corrector according to FIG. 1, FIG. 3 shows the triggered oscillator from FIG. 1 in detail,

FIG. 4 shows a block diagram of an embodiment of the corrector according to FIG of the invention and

Figure 5 Waveforms of the corrector of Figure 4.

The digital time base corrector 10 shown in FIG. 1 (which is disclosed in detail in the above-mentioned British and American patent applications ) comprises an input 11 which is connected to both an analog-to- digital converter 13 and a separator 14. The digital output from converter 13 (in parallel form) is applied to a memory 18, the output of which is applied to a digital-to-analog converter 20. The output from the separator 14 is fed to the input 15 of a triggered oscillator 16, the output 17 of which is used for clocking the input device of the memory controller 19 in connection with the clocking of the ADC 13 . The output device of the memory controller 19 is clocked by means of a clock generator 21, which also ensures the clocking of the DAC 20. The time base corrector is provided with an output terminal 22. The input terminal 11 is connected to a magnetic image recording system 12.

It can be seen from FIG. 2 that the incoming video signal (waveform (a)) contains a sync pulse 30 and color sync signal information 31. The separator 14 generates an output pulse (b). This output pulse from separator 14 is followed by the leading edge of the received

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Sync pulse is triggered and the start pulse triggers the oscillator to generate a pulse burst (c). The length of the series of pulses is sufficient to cause all of the video information to be in one effective format Line period converted and stored by the ADC before the oscillator output is omitted in anticipation of the arrival of the next start pulse from the separator 14.

Typical for the line length are about 64 ys and the frequency of the oscillators 16 and 21 is approximately three times the (burst) subcarrier frequency.

The input oscillator is shown in detail in FIG. The oscillator makes a change on a line by line basis its frequency.

With this arrangement, the length becomes each of the magnetic image recorder generated line is measured, and the result is used to regulate the oscillator frequency for the next line so that it comes closer to the desired frequency.

Although the beginning of the line is precisely timed and the color rendering is therefore accurate at the beginning of a line, the circuit shown in FIG Line is retained more precisely.

Although the start pulse of the oscillator in this case from the leading edge of the sync pulse is derived, the sync pulse information can mations also with those contained in the color subcarrier sync signal Information is combined as described in the aforementioned UK and US patent applications to provide timing stability the oscillator starting point to improve. The time between when the oscillator stopped and when the next start pulse is derived is compared. The resulting information is used to control the oscillator frequency, so that the time deviation is kept small. The oscillator stop point is determined by a counter that counts a predetermined number of Counts oscillator pulses and then shuts down the input oscillator.

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The triggered oscillator block 16 comprises a triggerable voltage-controlled Oscillator 40, which is a constant LC oscillator, but in which the frequency is changed by applying a variable voltage to a Voltage control input terminal 41 can be adjusted slightly. The triggerable oscillator 40 runs upon receipt of a logic low Level at its stop-start control terminal 42 and comes on receipt of a logic high level at its stop-start control terminal 42 to a standstill.

The received at input 15, derived from the sync pulse separator Pulses are used to control a bistable line length multivibrator 44 is used, which also generates the stop-start waveform for the triggered voltage controlled oscillator 40.

The output from the bistable line length multivibrator 44 produces an Ie pulse, which is also used to control a switch (FET) 45 for the period between stopping and restarting the oscillator to switch a current into a capacitor 46 for a new row. The current derived from a +5 volt rail and resistor 47 flows into the capacitor 46 and charges it to a voltage which is dependent on the pulse width driving the switch 45.

A resistor 48 is arranged to hold the capacitor 46 during the length of each line, said capacitor being charged from zero to a voltage that is the difference between the stop and represents start time during the interval between stopping and starting the oscillator.

An analog sampling circuit with an isolating amplifier connected to the capacitor 46 switch (FET) 50 and a monostable multivibrator 52 is designed so that it the peak of the voltage samples at the capacitor 46 and stores it in a capacitor 49, so that the resulting output from the isolation amplifier 53 is a uniform Voltage for the length of one line is and is used to drive the voltage control input terminal 41 of the triggered voltage controlled oscillator 40 is used. The sampling pulse driving the sampling switch becomes derived from the oscillator start pulse. In a typical practical circuit, the sample encoder monovibrator 52 becomes one pulse width about 1 microsecond after the oscillator start pulse. This

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1 microsecond pulse closes the sampling switch exactly at the moment in which the capacitor 46 reaches its peak voltage and charges the capacitor 49 to this peak voltage. At the end of the period from 1 microsecond the sampling switch opens and leaves the charge stored on the capacitor 49, which is available as a buffered signal for controlling the oscillator. Between the output of the voltage controlled Oscillator 40 and the set input of the bistable multivibrator 44, a counter 54 is connected to provide the stop pulse, after the correct count has been made. The time at which the stop pulse occurs depends on the number of counted Pulses, the period of this pulse block being variable depending on the oscillator frequency. While the oscillation frequency of Can vary line to line, the number of pulses of course remains constant for each line, as determined by the counter. So will the length of the sampling clock pulse series in accordance with the time duration of the lines varies from the tape by changing the frequency of the clock pulses from line to line. The oscillator pulses are provided at output 17. The voltage from amplifier 53 is provided at output 56.

The converter shown in FIG. 4 differs from that in FIG. 1 converter shown in that the output of the clock 21 via a voltage-controlled phase shifter 60 to the memory controller 19 and the DAU 20 and not directly to it.

The voltage for controlling the phase shifter 60 is one of the following Derived additional circuit arrangement described, which are generated under the influence of the output 56 of the voltage-controlled oscillator 16 There is tension.

This additional circuit arrangement includes sample and hold circuitry 62, which receives the frequency control voltage from the output 56 of the voltage controlled oscillator 16. The voltage from output 56 is also is applied to a subtracter 63 which is the difference between the voltage from the voltage controlled oscillator 16 (say at line n) and the Measures voltage at the sampling output of the holding circuit (line n-1). The from Subtracter 63 (at the beginning of line n_) measured voltage error applied to another sample and hold circuit 65, which this error voltage (while the line rO scans and holds. The output from the hold circuit 65 is placed on several storage paths (in this example

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there are four, and dir-s depends on the line memory capacity of the digital memory 18). Each path is provided with an input switch 67, 68, 69 or 70, a storage capacitor 72, 73, 74 or 75 and respectively an output switch 77, 78, 79 and 80, respectively. The input switches 67-70 are controlled by the input sequencer 90. The exit switches 77-80 are controlled by the output sequencer 91. The input sequence control system 90 ensures that that the voltage applied to a particular capacitor corresponds to the same line that is entered into the memory 18. Through the output sequencer 91 ensures that the correct capacitor is connected to the output, that of the one released from the memory Line corresponds. The voltage from the switched capacitor 72, 73, or 75 is applied to a sawtooth generator (integrator) 85, the a reset switch 86 to ensure that the ramp generated begins from a fixed reference point. With the exception of the reset switch 86, the sawtooth generator can be of a known design (i.e. a radio junction amplifier with an associated resistor and capacitor, as shown in Figure 4). The voltage generated by generator 85 is applied to the voltage controlled phase shifter 60 applied in order to make a phase shift of the signal from the clock generator 21 as a function of this voltage level. Voltage controlled Phase shifters are known in the art (e.g., a one-shot circuit which subjected the voltage to linear rise Receives voltage) and therefore this is not described in detail. Since each line of video is stored in memory for at least one line time is, it is possible by using the circuit arrangement according to Figure 4, not temporal errors of the magnetic image recording system compensate only at the input, but also at the output of the memory 18, namely in that the phase of the received from the output clock 21 Oscillations are changed to compensate for the errors measured by subtracter 63 for that line.

For the execution of the input and output sequencing systems 90, 91 can use the same technical means as in the known memory controller 19, which controls the sequence of the line memories (in memory 18) undertakes to be used. Accordingly, four step ring counters could be used to sequentially control switches 67-70 and 77-80 for capacitors 72-75 in turn. Although the switches as

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mechanical switches are shown, these would be off in practice proven solid-state components (e.g. field effect transistors).

In FIG. 5 are the waveforms for the arrangement according to FIG shown.

The output voltage from the voltage controlled oscillator is sampled and then given by the subtracter 63, in which the difference is in relation to the next voltage level from the voltage controlled oscillator is measured, and stored in capacitor 72 for further use (for example) after another sampling. Thus, each of the capacitors 72-75 will be used to store the output of the Interrogation switch 65 used and this level is fed to the sawtooth generator 85 at the appropriate time to enable error correction via the Make phase shifter 60 in the manner described above. The input sampling control waveform 62A may be obtained from counter 54, for example can be derived in the voltage-controlled oscillator 16. The input sample difference pulse 65A can also be derived from the counter is however, as shown in Figure 5, offset from 62A. The output reset pulses 86A can be derived from the output of the clock 21.

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Claims (10)

Claims fly video time base corrector with an analog-to-digital converter for converting an incoming analog video signal into digital form, a memory for receiving successive lines of video information in digital form from said converter, a digital-to-analog converter for converting a digital output signal from said memory in analog form, control devices for inputting and outputting the digital information in and from said memory, a triggerable voltage-controlled input oscillator for determining the conversion speed of the analog signal into digital form and the input speed in said memory, an output oscillator for regulating the output speed of the digital information from said memory and the conversion speed into analog form, characterized in that a scanning device (62) for scanning the input oscillator control voltage during a line, a measuring device (63) for Determining a voltage difference in the control voltage during successive lines, a holding device (65) for holding the determined voltage difference between successive lines and a phase shifting device (60) for shifting the phase of the output oscillator as a function of the voltage difference held by said holding device are provided. 2. Video time base corrector according to claim 1, characterized in that the sampling device includes sample and hold circuitry (62) for holding the sampled control voltage from said input oscillator during a line. 3. Video time base corrector according to claim 1, characterized in that the measuring means comprises a subtracter (63), de (a first Input for receiving the control voltage from said input oscillator and a second input for receiving the hold control voltage from said scanning device for the previous line to provide a voltage output corresponding to the difference in voltage between successive rows. 7098 31/0691 ORIGINAL INSPECTED ■ I " 4. Video time base corrector according to claim 1, characterized in that the holding device has a sample and hold circuit (65) for holding the detected voltage difference during a line, a plurality of analog storage elements (72, 73, 74, 75) on separate paths, - the number of elements of the number of lines being digital Storage of said memory corresponds to -, an input switching device (67, 68, 69, 70) for sequential switching of said memory elements for successive retention of the and hold circuit held voltage difference during a number of time periods corresponding to the number of lines of digital storage in said memory, and an output switching device (77, 78, 79, 80) for sequentially switching the voltage held at said analog storage elements to said phase shift device to control said output oscillator when the corresponding line is output from said memory, having. 5. Video time base corrector according to claim 4, characterized in that said input and output switching means comprises a plurality of switching elements, one on each storage element path, and sequential circuit means (90, 91) for sequentially switching the input and output switches for the purpose of applying the voltage for a line to a memory element corresponding to the same line entered into said memory and for switching it stored voltage to the phase shifter corresponding to the line that is output from said memory. 6. Video time base corrector according to claim 5, characterized in that said sequential control device from said regulating device for the memory is powered. 7. Video time base corrector according to claim 1, characterized in that the voltage from said holding means is applied to said phase shifting means via a sawtooth generator (85) will. 8. Method for compensating for speed errors in a video time base corrector with an analog-to-digital converter, a digital 709831/0691 memory, a digital-to-analog converter, a triggerable voltage-controlled input oscillator and an output oscillator, characterized in that said method consists in a) determine the input oscillator control voltage during a line, b) measure the difference in voltage detected during successive lines, c) the measured voltage difference at least for the duration of one line to hold on, and d) to shift the phase of the output oscillator as a function of the voltage difference in order to compensate for speed errors at the output from the memory. 9. The method according to claim 8, characterized in that the differential voltage is held for several lines in dependence on the number of storage lines in the memory. 10. The method according to claim 8, characterized in that the differential voltage for performing the phase shift of the output oscillator is integrated. 709831/0691