DE2655653C2 - Arrangement for determining the correct assignment of address and memory word in a word-organized data memory - Google Patents

Description

The invention relates to an arrangement according to the preamble of claim 1.

In connection with so-called linearly addressed memories, the address is known to be used for definition a specific location. Depending on the organization of the storage, the addressed storage location can be a whole memory cell for receiving one consisting of a plurality of bits, generally as Memory word denotes information, a memory element for receiving a single bit or a be memory section lying between these extreme values. The following are word-organized Memory required

■> The function of the address to define a Storage location has the consequence that each address at least temporarily has a specific one for input Information provided in this storage location or located in this storage location, a date, is assigned is. Usually only this assignment is of interest. In principle, nothing changes about that if the assignment from time to time intentionally, for example by deleting or overwriting the previous memory contents, changed or the originally specified address is modified (e.g. creation of real memory addresses). If the address is corrupted due to errors in the address paths including the address decoder the assignment is lost.

It is already known to protect memory contents against corruption (e.g. by faulty memory elements or data paths in the memory) by deriving check bits from both the data to be entered and from the read data according to certain constant rules and the ones formed during writing and also stored Check bits are compared with the check bits formed during reading. If differences are found when comparing corresponding check bits, this indicates data errors. For this purpose, a class of correction codes going back to Hamming (The Bell System Technical Journal, Vol. 26, April 1950, pages 147 to 160) is used, with the help of which it is possible within a data set treated in parallel and simultaneously (which is referred to below is referred to as a memory word and comprises, for example, 64 data bits and 8 correction bits) to correct single errors and to recognize double errors. Such codes are known as SEC-DED codes (Single Error Correcting-Double Error Detecting). Modifications of the Hamming codes which require less effort to handle them are known from the reference "IBM Journal of Research and Development", JuHl 970, pages 395-400.
Frequently, the memory addresses themselves are also protected against errors by a parity bit which is formed at the beginning of the address path, which is also transmitted and which is compared with a parity bit generated in the same way at the end of the address path.

Apart from the fundamentally limited performance of such error protection procedures in In general, this error protection of addresses has the serious disadvantage that the Address decoding is no longer included. Unrecognized falsifications of the address are annoying correct assignment of address and memory word. Errors on the address paths and in the decoder can be divided into some characteristic groups. The table below represents for different types of errors compared to the causes and their immediate effects.

Type

root cause

Result

A Interruption or short circuit of an address

management; certain errors in the decoder part

B Interruption or short circuit in the decoder

Entrance or exit

Choosing the wrong one
Memory word

Selection of 2 memory words at the same time

continuation root cause Result Type Interruption or short circuit in the decoder
Entrance or exit No memory woit will
selected C. Address error on a memory module Falsification of a part
of the memory word D. Address error in a (bit-gated)
Memory chip Falsification of a one
umpteen memory bits E.

The individual types of errors have different consequences.

Type A: The data is incorrect. However, since the check bits match, the error correction device notices none of it. Either there is a program glitch or it is wrong Data continued. The latter is particularly dangerous as none of the others are in the computer existing protective devices can detect such a fault.

Type B: Many bits of the memory word are incorrect, the data and the check bits do not match to each other. The error correction, which at most can reliably detect double errors, is overwhelmed. However, it reacts correctly in around 45% of all cases and then does not report you correctable memory error. In the remaining cases it reacts wrongly, it recognizes correctable individual errors. If the corrupted data are program instructions, will mostly a program fault is displayed. However, if the data to be processed is falsified, will initially continue to work with this incorrect data. But in general an address error spanning many memory words is the probability for the Eventual detection of a high error, because with each new access in the disturbed The error correction area has a 45% probability of being uncorrectable Reports error.

Type C: With a suitable design of the error correction, e.g. B. by inverting each one second check bits before storage, the error correction reacts correctly; she reports an uncorrectable memory error.

Type D: The error correction and the central unit of the data processing system react like for type B.

Type E: Since only one bit of the memory word is forged, the error correction can detect this and correct the fake bit.

Error type A is the most difficult to identify address error. Due to the number of components that can cause it, the probability of its occurrence, together with the error type D, is am biggest. DE-AS 12 50163 already provides a device for the detection or correction of Incorrect memory words known, which also have incorrect assignments of addresses and ID Can recognize memory words. This is done when writing to the memory and when reading from the Save the address and the password to one Superordinate information summarized, which are subject to the measures for error protection will. If an addressing error is detected, the memory is readdressed.

An identical one in terms of determining the correct assignment of address and memory word Device can be found in FR-PS 22 82 676.

The known device requires a very considerable amount of circuitry for the duplicate, especially in the case of longer data words and extensive addresses which are required in large data memories

Derivation of the check bit. The invention is therefore based on the object of providing a device for determining the specify correct assignment of address and memory word, which requires a significantly lower circuit complexity than the known device. These The object is achieved by the features in the characterizing part of claim 1. The invention has also has the advantage that in many cases, depending on the security code used and depending on the format of the addresses and memory words, the number of those required for error correction and detection Check bits can be reduced, which leads to further savings.

In the following, the invention will be described in greater detail using an exemplary embodiment shown in the drawing explained.

The drawing shows a data path on which the memory word 3 provided for input into the memory 2 is transmitted, analogous to this, an address path for transmitting the address 5 is provided. The memory word 3 is fed to a check bit generator 17 (CB generator). Here the memory word becomes check bits derived, the number of which depends on the width of the memory word. The individual check bits are generated by modulo-2 addition of certain data bits, whereby the rules according to which the individual Data bits are taken into account, differ from check bit to check bit. It should be mentioned that those of Hamming specified class of correction codes encompasses a multitude of possibilities regarding are equivalent to their performance in correcting or detecting errors. Special correction codes that make a allow simple construction of the circuit arrangements required for their formation and evaluation, are z. B. by the already mentioned reference "IBM Journal of Research and Development", Vol. 14, July 1970, pages 395 to 400 and become known from DE-OS 23 44 019.

The check bit generator 17 can technically be implemented in various ways. For example can do this using EXCLUSIVE-OR elements or logic elements of the type known from DE-PS 19 29 144 are used.

From the check bits generated in the check bit generator 17

CO to C1 , only the check bits C2-C7 are directly transferred to the memory 2 together with the memory word 3 during a write operation. It goes without saying that the address must also be involved in this process. In order to indicate that the address itself is not written into the memory 2, the corresponding operative connection 5 'is shown in the drawing with dashed lines.

The check bits CO and C t become one of the inputs of two EXCLUSIVE-OR gates 19 and 20 fed. At the other inputs of the EXCLUSIVE-OR gates 19 and 20 there is an address parity block 18, which is derived from the address 5 in the parity bit generator 16. It has already been pointed out that A parity bit is often added to the addresses to determine possible corruptions on the address path will.

The parity bit generator 16 shown in the drawing is generally located at the beginning of the address path. A second parity bit generator at the end of the address path and the associated comparison and evaluation device (as well as the address decoder) are not shown in the drawing because they are of no further interest for the present case. When the memory 2 is read, the memory word 3 is output together with the check bits CO *, Cl and C2. At the same time, in a second check bit generator 21, check bits CO 'to CT are again derived from the read memory word, which are identical to check bits CO to Cl if memory word 3 was not forged. From the bit-by-bit comparison of the check bits CO *, Cl * and C2 to Cl read from the memory 2 with the check bits CO 'to CT recently derived from the read memory word 3 in a comparator 8, the address parity bit 18 becomes analogous to the procedure for writing added modulo - 1 to the check bits CO 'and CY. The EXCLUSIVE-OR gates 22 and 23 are used for this purpose.

The result of the bit-by-bit comparison of the check bits in the comparator 8 forms what is known as a syndrome Error code with the syndrome bits 50 to 57, the back connections about the occurrence of an error of the Memory word 3 or the address parity bit 18 or the location of the error, if it is a Simply act wrong here. An error has not occurred if the syndrome has a binary value of zero, i.e. H. when all syndrome bits 50 to 57 are zero. If, on the other hand, at least one of the syndrome bits has the value 1, then it means that an error has occurred.

Syndrome bits 50 through 57 become a fault location decoder 9, which evaluates the information content of the syndrome. About the lines 10 and 11 there the fault location decoder emits 9 alarm signals when single or double faults are detected. Becomes a simple mistake detected, then the fault location decoder outputs simultaneously over one of the lines of the line bundle 12 from a signal to the correction circuit 13. Each of these lines is a bit of memory word 3 assigned. The correction circuit 13 consists, for example, of EXCLUSIVE-OR gates, on whose Inputs each have a bit of the memory word and a control signal supplied by the error location decoder 9. If one of the control signals emitted by the fault location decoder 9 has the binary value 1 and so that the assigned bit in the memory value is identified as falsified, the polarity of this bit is reversed. It however, it would not be advisable to add a forged bit in the area of the address of the stored data block correct, since in most cases it cannot be recognized whether an address error occurred during the Writing or while reading. If a single error occurs in the area of the Address, an error signal is therefore also triggered. This error signal can be output via the line 11 to display double errors or via a further line 14.

The modification of the check bits by the address parity bit is not limited to two check bits. In general, an even number of check bits must always be influenced by the address parity bit. In the present case, all check bits CO to C7 or CO 'to CT can therefore also be modified by the address parity bit 18.

In a further exemplary embodiment of a device for recognizing the correct assignment of address and memory word, the second EXCLUSIVE-OR operation of the address parity bit with check bits CO and C1 (or with an even number of check bits) takes place directly at the output of memory 2. The EXCLUSIVE-OR link at the output of the second check bit generator is then omitted. By modifying the check bits CO and Cl twice, they are given their original value again if no error has occurred. They are then also identical to the check bits CO 'and CY output by the second check bit generator 21.

1 sheet of drawings

Claims (3)

Claim: 1. Arrangement for determining the correct assignment of address and memory word in one word-organized data storage device with random access, with one to an error correction code for Correction of all single errors and error correction device adapted to detect at least all double errors, due to the joint consideration of the memory word and the address when deriving check bits according to the Rules of the correction code used for data backup with a first and second check bit generator for the formation of check bits according to a SEC-DED correction process, with one device for the formation of a binary coded error code (syndrome) by bit-by-bit comparison of the Check bits formed by the first and second check bit Geyerator, with an error location decoder for Generation of error signals and of correction signals, which a correction device for correction individual forged bits of the memory word read from the memory are supplied, characterized in that a parity bit generator (16) is provided for deriving an address parity bit (18) from the address is, as well as a first group with an even number of EXCLUSIVE-OR gates (19, 20) for Combination of the address parity bit with an even number of the first check bit generator (17) supplied check bits and a second group with an equal number of EXCLUSIVE-OR gates (22, 23) to link the address parity bit with the same number from on the Memory output side available check bits, and a possibly determined, the Address parity bit related error triggers an error signal, but is not corrected. 2. Arrangement according to claim 1, characterized in that at one of the inputs of the EXCLU-SIV-OR gates (22,23) of the second group are those supplied by the second check bit generator (21) corresponding check bits are present. 3. Arrangement according to claim 1, characterized in that at one of the inputs of the EXCLU-SIV-OR gates (22,23) of the second group the corresponding check bits read from the memory.