DE2655653A1 - Correct address and word assignment recognition in data memory - involves single error correcting and double error detecting facility - Google Patents

Abstract

The apparatus includes a device to form a binary coded error identifying character by comparing the test bits made by the first and second test-bit generators (6, 7). An error location decoder produces error signals and correction signals which are supplied to a correcting device (13) to correct erroneous bits of the word read from the memory. A data block is formed by linking up the address and the memory word. It is connected to each input of the two test-bit generators. An error is detected in the region of the address, the error location decoder transmits an error signal.

Description

Procedure and arrangement for recognizing the correct assignment

of address and storage location in a data store.

The invention relates to a method according to the preamble of claim 1. It also relates to an arrangement for carrying out the method.

It is used in connection with so-called linearly addressed memories as is well known, the address for defining a specific storage location. Depending on the Organization of the memory, the addressed memory location can be an entire memory cell for receiving one consisting of a large number of bits, generally as a memory extension designated information, a storage element for receiving a single bit or a memory section lying between these extreme values. Hereinafter word-organized memories are required.

The function of the address to define a storage location has to As a result, each address has, at least temporarily, a specific one to be entered in Information intended for this storage location or located in this storage location, a date is assigned. Usually only this assignment is of interest.

In principle, nothing changes in this when the assignment of time to Deliberately time, for example by deleting or overwriting the previous memory contents, changed or the originally Modified specified address (e.g. formation of real memory addresses). If the address is falsified the assignment goes through errors in the address paths including the address decoder lost.

It is already known to protect memory contents against corruption (e.g. B. by faulty memory elements or data paths in the memory) by both of the data to be entered and of the data read according to certain constant Regulations derived from check bits and the ones formed when writing and likewise stored check bits are compared with the check bits formed during reading. If differences are found when comparing corresponding check bits, then this indicates data errors. One on Hamming is commonly used for this purpose (The Bell System Technical Journal, Vol. 26, April 1950, pp. 147-160) Class of correction codes with the help of which it is possible within a parallel and the amount of data treated at the same time (hereinafter referred to as the memory word and comprises, for example, 64 data bits and 8 correction bits) resulting single errors correct and identify double errors. Such codes are under the designation SEC-DED codes (Single Error Correcting-Double Error Detecting) known.

The memory addresses themselves are often also represented by a parity bit, formed at the beginning of the address path, transferred and with a at the end of the Address path is compared in the same way generated parity bit against errors secured.

Apart from the fundamentally limited performance of such error protection methods in general, this error protection of addresses also has the serious disadvantage that address decoding is no longer included. Unrecognized falsifications of the address interfere with the correct assignment of address and memory word. Errors that can arise on the address paths and in the decoder can be divided into several characteristic groups. The following table compares the causes and their immediate effects for different types of errors. Tyn cause result A Interruption or short selection of the wrong memory end of an address word tung; certain errors in the decoder part B Interruption or short selection of 2 memory errors conclude in the decoder-one at the same time passage or exit C Interrupt or short- No memory word is deleted selected in the decoder input or exit D address error due to corruption of part of the Sea urchin green sseicherworts E address error in a corruption of a single (bit-organized) memory storage bits building block The individual types of errors have different consequences.

Type A: The data is incorrect. But notice that the test bits match the error correction facility does nothing of this. Either there is a program malfunction, or you will continue to work with the wrong data. The latter is particularly dangerous since none of the other protective devices in the computer have such an error can recognize.

Type B: Many bits of the memory word are incorrect, the data and the check bits do not match. The error correction, the maximum double error can still safely recognize is overwhelmed. But it reacts in about 45% of all Cases correct and then reports an uncorrectable memory error. In the remaining traps it reacts incorrectly, it recognizes correctable individual errors. If the corrupted data are program instructions, it will mostly be a program malfunction displayed. However, if the data to be processed is falsified, it will be used first wrong data continued. But there is generally an address error extends many memory locations, the probability is for the eventual Detection of an error is high, because with each new access in the disturbed area the error correction with a probability of 45 e0 an uncorrectable Reports error.

Type C: With a suitable design of the error correction, e.g. B. by inversion of every second check bit before storage, the error correction responds correct; it reports an uncorrectable memory error.

Type D: The error correction and the central unit of the data processing system react as with type B.

Type-E: Since only one bit of the memory word is corrupted, the Error Correction Detect this and correct the forged bit.

Error type A is the most difficult to detect address error.

Because of the number of components that can create it is the probability of its occurrence, together with the error type D, is greatest. The invention is therefore based on the object of presenting measures with which Help determine the correct or incorrect assignment of address and memory word is. In particular, the measures should be suitable for address errors of the previously described Detect type A and trigger an alarm when it occurs. According to the invention this object is achieved by a method with those listed in claim 1 Features solved. Embodiments of arrangements for carrying out the method can be found in claims 5 to 9. The invention is illustrated below with reference to the exemplary embodiments illustrated in FIGS. 1 and 2 are explained in more detail.

The embodiment of FIG. 1 is based on the idea of the address and the associated memory word to form a data block that is used for Formation of the check bits necessary for error correction or detection as a unit is treated.

If one assumes for the further that it is in the memory The memory word to be transferred primarily comprises 6! + bits, then 8 check bits are used for the Securing of the sneaker / site against falsification is required. On the other hand, could however, with the redundancy made available, a wider memory word can also be used secured will. By treating the address and memory word together with the measures for error protection according to the SEC-DED method, therefore, there is generally no larger Number of check bits are required.

The figure shows a data register 1 in which the input to the Memory word 3 provided for memory 2 is temporarily stored, analogously to this an address register 4 is provided for temporarily storing the address 5. Address 5 and memory word 3 are fed to a check bit generator 6 (CB generator). Here, the data block, which is created by the stringing together of address and Memory word has arisen, test bits are derived, the number of which depends on the width of the data block. The individual check bits are determined by modulo-2 addition Data bits generated, whereby the rules according to which the individual data bits are taken into account differ from check bit to check bit. It should be mentioned that those of Hamming specified class of correction codes encompasses a variety of ways which are equivalent in terms of their performance for error correction or detection are. Special correction codes that provide a simple structure to their formation and allow evaluation required circuit arrangements are, for. B. by the reference "IBM Journal of Research and Development", Vol. 14, July 1970, pages 395-400 and became known through DT-OS 2 344 019.

The test bit generator 6 can technically be implemented in various ways be. For example, EXCLUSIVE-OR elements or logic elements can be used for this purpose of the type known from DT-PS 1 929 144 can be used.

The check bits C ~ to C7 generated in the check bit generator 6 become transferred to memory 2 together with memory word 3 during a write operation. It goes without saying that the address must also be involved in this process. To suggest that the address itself is not written into the memory 2, is the corresponding Active connection 5 'in the drawing with dashed lines Lines shown.

When reading the memory 2, the memory word 3 together with the Check bits C ~ to C7 output. At the same time, a second check bit generator 7 from the read memory word and the address again test bits C ~ 'to C71 derived, Eie are identical to check bits C ~ to C7 if neither the address nor the memory word were counterfeited. If, on the other hand, an error has occurred or is in the memory word the correct assignment of address and memory word no longer before, then differentiate the check bits C ~ to C7 'differ from the check bits C ~ to C7. The bitwise comparison of the Check bits are carried out in a comparator 8. The result of this comparison forms a misidentification character called a syndrome with the syndrome bits S ~ to S7, which draws conclusions about the occurrence of an error or about the location of the Permits errors within the forged data block, provided it is a simple error acts. An error has not occurred if the syndrome has the binary value zero has, d. H. if all syndrome bits S ~ to S7 are equal to zero.

If, on the other hand, at least one of the syndrome bits has the value 1, then means that an error has occurred.

The syndrome bits S ~ to S7 are fed to an error location decoder 9, who evaluates the information content of the syndrome. Via lines 10 and 11, respectively the fault location decoder emits 9 alarm signals when a single or double fault is detected became. If a single error is detected, the error location decoder emits at the same time a signal to the correction circuit via one of the lines of the line bundle 12 15 from. Each of these lines is assigned to a bit of the memory word 3. the Correction circuit 13 consists, for example, of EXCLUSIVE-OR gates, on whose Inputs each one bit of the memory word and one supplied by the error location decoder 9 Control signal present.

If one of the control signals emitted by the fault location decoder 9 den has a binary value of 1 and thus the assigned bit in the memory word is falsified the polarity of this bit is reversed. However, it wouldn't be expediently, a forged bit in the area of the address of the secured data block to be corrected, since in most cases it cannot be recognized whether an address error is present occurred while writing or reading. When a A single error in the area of the address therefore also triggers an error signal.

The output of this error signal can be displayed via line 11 of double errors or via a further line 14.

It was already pointed out at the beginning that the addresses for determination A parity bit is often added to possible corruptions on the address path. By checking the parity bit at the input of the address decoder, up to Any single errors in the address that arise at this point can be recognized. Instead of the address and the assigned memory word according to the previously described embodiment to form a common data block and to assign this to the SEC-DED error correction subject, it is possible to use the check bits derived from the memory word alone to be logically linked with the parity bit of the address. A related embodiment shows the figure 2.

The parity bit generator 16 shown in FIG. 2 is located generally at the beginning of the address path. A second parity bit generator at the end of the address path and the associated comparison and evaluation device are (also like the address decoder) in Fig. 2 not shown because they are for the present Case are of no further interest. A check bit generator 17 (CB generator) forms the check bits C ~ to C7 from memory word 3. During a write process, with the test bits C2 to C7 entered directly into the memory 2 after the memory word 3. The address parity bit 18 is added modulo-2 beforehand to the check bits CX and C1. This is done with the help of the two EXCLUSIVE-OR elements 19 and 20. The modified ones Check bits C ~ * and Cl * are also assigned to memory word 3 in the memory 2 registered.

When reading a memory word 3, the check bits are simultaneously C ~ *, Ci * and C2 to C7 are output. The read memory word 3 becomes again as when writing into the memory by the check bit generator 21 check bits C0 ' to C7 'formed. Analogous to the procedure for writing, before the check bit comparison the address parity bit modulo-2 is added to the check bits C # 'and C1'. The modulo-2 addition is carried out by the two EXCLUSIVE-OR gates 22 and 23. The comparison the test bits, the evaluation of the test result (syndrome) and, if applicable the correction of the memory word 3 takes place as in the exemplary embodiment according to FIG. 1.

The modification of the check bits by the address parity bit is not limited to two check bits. In general, there must always be an even number of check bits can be influenced by the address parity bit. In the present case, therefore also all check bits C ~ to C7 or C # 'to C7' are modified by the address parity bit 18 will.

In a further exemplary embodiment of an arrangement for recognition the correct assignment of address and memory word is followed by the second EXCLUSIVE-OR link of the address parity bit with the check bits C ~ and C1 (or with an even number of check bits) directly at the output of memory 2. The * EXCLUSIV-0DER link then not applicable. Obtained by modifying the check bits C ~ and C1 twice this reverts to its original value if no error has occurred. they are then also identical to the check bits output by the second check bit generator 21 C # '. and C1 '.

Another advantageous embodiment is obtained when that through the parity bit generator 16 derived from the address address parity bit 18 instead the address itself is added to the memory word. The fail-safe measures according to the SEC-DED method, in particular the check bit formation when entering the memory and output, then refer to the one extended by the address parity bit Spoke front. It is in this * at the output of the second check bit generator case It is particularly noticeable that a single error correction in the area of the address is here so a correction of the address parity bit would be completely pointless. Only simple mistakes are allowed corrected in the memory word itself. When an address error occurs and an error in the memory word, the error protection device reacts correctly; it reports an uncorrectable double error.

2 Figures 9 claims L e r s e i t e

Claims (9)

Patent claims 1. Procedure for recognizing the correct assignment of address and memory word in a word-organized data memory with random Access to which an error correction device, in particular for correcting simple errors and is assigned to the detection of double errors, g e k e n n -z e i c h n e t through the joint inclusion of address and memory word in the measures for data security with the proviso that the determined in the area of the address Simple errors are not corrected, but just like all recognized non-correctable errors Double faults trigger an error signal. 2. The method according to claim 1, d a d u r c h g e k e n n -z e i c h n e t that from the address (5) and the memory word (3) by stringing together a data block is formed which, as a whole, is subject to the measures for data backup will. 3. The method according to claim 1, d a d u r c h g e k e n n -z e i c h n e t that from the address (5) in a known manner an address parity bit (18) even or odd parity is derived and that from the A # dress parity bit (18) and the memory word (3) a data block is formed by stringing them together, which as a whole is subjected to data backup measures. 4. The method according to claim 1, d a d u r c h g e k e n n -z e i c h n e t that from the address (5) in a known manner an address parity bit (18) even or odd parity is derived and that the address parity bit (18) to an even number of the check bits derived from the memory word (3) modulo-2 is added. 5. Arrangement for recognizing the correct assignment of address and Memory word in a word-organized data memory with random access, with a first and second check bit generator for the formation of check bits according to a SEC-DED correction process, with a device for forming a binary coded error identifier (syndrome) by bit-by-bit comparison of the first and second check bit generator formed check bits, with an error location decoder for Generation of error signals and of correction signals, which a correction device to correct individual, forged bits of the memory location read from the memory are supplied, that is, that at the inputs of the first and second check bit generator (6, 7) each one by stringing them together the address and the assigned memory word formed data block is present and that the error location decoder when an error is detected in the area of the address triggers an error signal. 6. Arrangement for recognizing the correct assignment of address and Continuation of storage in a word-organized data memory with random access, with a first and second check bit generator for the formation of check bits according to an SEC-DED correction process, with a device for the formation of a binary coded error indicator (syndrome) by comparing the bits formed by the first and second check bit generator Check bits, with an error location decoder for generating error signals and correction signals, that of a correction device for correcting individual forged bits of the the memory word read are fed to the memory, g e k e n n n z e i c h n e t by a parity bit generator (16) for deriving an address parity bit (18) from the address, through a first group with an even number of EXCLUSIVE-OR gates (19, 20) to combine the address parity bit with an even number of the the first check bit generator (17) supplied check bits and by a second group with an equal number of EXCLUSIVE-OR gates (22, 23) for linking the address parity bit with the same number of those available on the memory output side Check bits. 7. Arrangement for recognizing the correct assignment of address and Memory word in a word-organized data memory with random access, with a first and second check bit generator for the formation of check bits according to an SEC-DED correction process, with a device for the formation of a binary coded error indicator (syndrome) by comparing the bits formed by the first and second check bit generator Check bits, with an error location decoder for generating error signals and correction signals, that of a correction device for correcting individual forged bits of the the memory word read are fed to the memory, d u r c h e -k e n n z e i c h n e t that a parity generator (16) for deriving an address parity bit (18) from the address is provided that at the inputs of the first and second Check bit generator (6, 7) each one by stringing together the address parity bits (18) and the memory word (3) assigned to the relevant address (5) Data block is present and that the error location decoder when an error is detected triggers an error signal in the area of the address. 8. An arrangement according to claim 5, d a d u r c h g e k e n n -z e i c h n e t that at one of the inputs of the EXCLUSIVE-OR gates (22, 23) of the second Group of the corresponding check bits supplied by the second check bit generator (21) issue. 9. Arrangement according to claim 5, d a d u r c h g e k e n n -z e i c h n e t that at one of the inputs of the EXCLUSIVE-OR gates (22, 23) of the second Group the corresponding check bits read from the memory are present.