DE2650582A1 - LIMITING CIRCUIT - Google Patents

Description

PATENT LAWYERS

MANITZ, FINSTERWALD & GRÄMKOW

Munich, November 4, 1976 P / 2 / Sv-N 2098

NORTHERN TELEGOM LIMITED

1600 Dorchester Boulevard, West, Montreal, Quebec, Ganada

Limiter posture

The invention relates to an electrical signal limiting circuit and in particular a limiter circuit equipped with transistors, which is suitable for use in timing circuits or clock control circuits in high speed digital relay amplifiers suitable is.

In recent years, digital information transfer using extremely fast, high capacity Pulse transmission systems are gaining a foothold as a useful technique in wide area telephony applications. These systems are able to provide an information density of several hundred via coaxial cable lines equipped with amplifiers Transfer megabits per second. In order to ensure the integrity or the correct form of the digital impulses via the To maintain the entire system from one end to the other, digital amplifiers or relay amplifiers are used in

DR. C. MANITZ DIPL.-ING. M. FINSTERWALD DIP L. -IN G. W. G R A M K O W ZENTRALKASSE BAYER. FOLK BANKS MONKS 2S. ROBERT-KOCH-STRASSE I 7 STUTTGART 50 (DAD CANNSTATT) MONKS. ACCOUNT NUMBER 7270 TEL. (089) 22 42 It.TELEX 5-29672 PATMF SEELBERGSTR. 23/25. TEL. (0711) 50 72 ti POSTSCHECK MÜNCHEN 7 7062 - 80S

709819/0974

At intervals that depend on the type of coaxial cable, the bandwidth of the information transmitted and the error rate specified for the entire system. A digital relay amplifier takes the incoming pulse currents or pulse sequences and regenerates the scattered or widened in terms of shape and their temporal position Impulses in order to transfer them back to the following cable interval.

An essential function in a relay amplifier xv is made by exercised a threshold detector, which decides during an optimal time window whether a pulse is present or not by sampling a voltage above a predetermined threshold. The accuracy of this decision largely determines the error rate of the system. It is clear that this accuracy is a function of two Variables, namely first of all the integrity or the quality of the incoming impulses, which are ultimately sent to the Threshold detector are brought up, and secondly, the temporal position of the optimal time window. This situation will derived from the timing circuit, which generates a sinusoidal timing signal from the incoming pulse current extracted. The extracted sinusoidal signal has the correct phase position, which is necessary for precise timing is, however, it varies in its amplitude, which is mainly due to the quasi-random occurrence of the incoming Impulses. A dense sequence of pulses produces a greater amplitude than a less dense sequence. There are, however one determined by the coding scheme of the multiplex system lower limit, so that a relay amplifier only has to cope with a limited amplitude variation, the in most cases is between 10 and 20 dB.

To remove the change in amplitude from the timing signal, what is required for precise timing,

709819/0974

2850582

the raw timing signal must be amplified and limited to this. The phase response behavior is as expected of the limiter is essential. It must be within specified tolerances over the range of amplitude fluctuations be constant. So far, the limitation has been effected by diodes in two successive stages, one of which each was overdriven by sufficient amplification and was followed by a third amplifier stage. At a An alternative design was a series-parallel limiter used, preceded by reinforcement and followed by reinforcement. Such an arrangement is in the article of I. Dorros, entitled "An Experimental 224 Mb / s Digital Repeatered Line" in The Bell System Technical Journal, Volume 2XV, September 1966, No. 7, at page 1029. Under the heading "limiting" the shows Author in this article that a transistor limitation was avoided in order to achieve the amplitude-to-phase conversion to keep it to a minimum (i.e. keep the phase response constant). In this example, the application in question as in other state-of-the-art limiters a diode limitation is used ..

The main aim of the invention is to reduce the cost of digital relay amplifiers of the type described above to decrease. It was recognized that when the phase response problems can be solved by transistorized limiter stages could only require a simpler amplifier stage would be to drive the more sensitive limiter and that may not require any post boost would be. This would result in a not inconsiderable cost reduction.

It was found that a conventional, emitter-coupled A pair of existing amplifiers show a significantly improved phase response when a second one

709819/09 7 4

Phase compensation signal is applied to the base of the output transistor, this second signal having a certain phase position to the input signal. By a sensible or expedient choice of the amplitude of this second signal with respect to it

the
of the range of variation / amplitude of the input signal, the phase and amplitude response behavior of the limiter is optimized for the present case.

Thus, according to the invention, a limiter circuit for a periodic input signal with varying amplitude provided, comprising the following parts: first and second switching devices, which are connected and polarized in such a way that they work in current-wise switching mode, devices for applying of the input signal to a control electrode of the first switching device and devices for applying a second, periodic signal to a control electrode of the second switching device, this second signal at the control electrode having a predetermined amplitude and a predetermined phase difference with respect to the input signal.

In a preferred embodiment of the invention, the ' second signal is a delayed, attenuated version of that appearing at the output electrode of the first switching device AC voltage signal.

The invention is described below, for example, with reference to the drawing; in this shows:

1 is a general diagram of a conventional limiter with an emitter-coupled pair;

Fig. 2 the definition of the propagation delay of the emitter-coupled Pairs in Fig. 1,

Fig. P shows a typical phase and amplitude response the circuit in Fig. 1,

709819/0974

4 shows the diagram of a limiter circuit according to the invention,

Fig. 5 shows the manner in which the improved phase response behavior is achieved by the circuit in Fig. 4, and

FIG. 6 shows a typical phase and amplitude response of the circuit in FIG. 4.

A general circuit diagram of a conventional emitter-coupled limiter is shown in FIG. The input signal V. is applied to the base 12 of the transistor 10 GLn

and the output voltage V is at the collector of the transistor 11 received. Both base 12 and base 13 of the transistor 11 are intended, of course, to be essentially the same by any of the known biasing devices DC voltage must be biased. The supply voltage is applied between terminal 14 and ground. The current source 15 can be a simple resistor. Amendments These schematic circuit diagram from Fig. 1 are well known in the prior art, so that a further discussion unnecessary at this point.

Fig. 2 shows how the propagation delay t ^ between V ^ _n and V is defined. The DC levels have been neglected for the sake of clearer definition, which simply defines the propagation delay as the time difference or time delay tQ between the 50 / ^ points of V and V. specifies.

from em °

At a single frequency tj> can be converted into a phase angle, whose change in _a establishes as a function of the amplitude of V, which "response-phase", the amplitude-phase reaction is here referred to as the or the limiter. A typical phase response of such a conventional limiter at the frequency of interest, which in a preferred embodiment is 274.176 MHz,

709819/0974

is shown in the lower part of FIG. The ordinate indicates the phase angle in degrees, while the abscissa the relative Change in the amplitude of V. as the ratio of V. to reproduces. V. is the expected maximum value

ΘΙΏ Π13λ

θ 1X1 ^ ^ C ^

the amplitude at the limiter input (the terminal 12 in Fig. 1). As you can see, the phase response is far from it removed from being constant, making this type of limiter suitable for use in the present high-speed relay amplifier is unsuitable, although it is much more sensitive than / diode limiter.

However, it is not just the phase response that is too much depends on the amplitude, but also the amplitude of the limited output signal, albeit at a lower level Extent. The amplitude response behavior or the amplitude-amplitude conversion is shown in the upper part of FIG. The ordinate indicates the relative change in the output amplitude again. V__ is the maximum output amplitude that clUs uiax

V. is equivalent to. It should be noted that the actual Level of V. , over which the in Fig. 3 again-

ti -L. XX

given results were measured between 0.2 volts of Tip to tip and 2 volts tip to tip. A diode limitation can be used within a large part of this range Not used.

After this brief discussion of the conventional emitter-coupled limiter and its limits at the frequencies of interest, the circuit of a preferred embodiment in accordance with the invention will now be discussed. The circuit is shown in Fig. 4- and comprises two bipolar NPN transistors 10 and 11, the emitters of which are connected to one another and connected to ground via a resistor 12. The circuit shown in FIG. The transistors 10 and 11 are with their bases with a biasing DC supply voltage V _ß at the terminal 13 via the

709819/09 74

Resistors 14 and 15 connected. The base of the transistor

10 and the collector of transistor 11 are connected to input and output terminals 16 and 1? across the capacitors or 19 connected. The collectors of transistors 10 and ■

11 are connected via the resistors 21 and 22 to the main supply voltage applied between the terminal 20 and the ground or earth Vg laid. The collector of the transistor 10 is a series circuit of a resistor 23 j Capacitor 24 and a delay line 25 to the base of transistor 11 coupled. Additionally, if transistors 10 and 11 are not perfectly matched (i.e. have identical characteristics), as is usually the case, a potentiometer connected between Vg and ground 26 is provided, the wiper of which is connected to the base of the transistor 11 via the resistor 27. That Potentiometer 26 represents a device by which a difference in the emitter-base voltages of the transistors 10 and 11 can be compensated.

In the circuit of Pig. 4, the capacitor 23 is a DC blocking capacitor. The resistor 24 serves as an attenuator for the signal at the collector of the transistor 10; this attenuated signal is then fed to the base of transistor 11 via delay line 25. the upper representation in Pig. 5 shows the attenuated, trapezoidal signal V. as it is at the base of transistor 11 in FIG the correct phase position with respect to the input signal V.

C-X.XX

at the base of the transistor 10 for the two cases of a minimum and a maximum V, respectively. appears. The trapezoidal signal V ^ is phase shifted by an angle of approximately -5/2 TT (if integer multiples of 2 TT are neglected, then the relative phase of V, with respect to V., Is simply - ^ / 2). A phase inversion by TT is introduced by transistor 10 and the remainder of 3/2 TV is a delay caused by delay line 24

709819/0974

- ti -

Λ *

tion. The point of intersection L is the moment within one Cycle in which the base voltages of transistors 10 and 11 in the case of a maximum V. are equal to each other. In this At the moment of the cycle, the transistors 10 and 11 change their conduction state, the transistor 10 ceasing to be conduct and the transistor 11 begins to conduct. The corresponding transition of the output voltage V is immediately

3X1S

shown directly below in Fig. 5. The 5 ° ^ level (or the zero crossing if one neglects the DC level) of V becomes after a delay time t- ^ with respect to of point L reached. In the case of the minimum V · the point of intersection is S, which of course is earlier than L in the cycle occurs. The corresponding transition from V is in FIG. 5

3. U.S.

shown below, and here the 50 / ^ level becomes after a Delay time t- ^ g with respect to S reached. The behavior of the Circuit with regard to the positive transition of V

3 U. S

speaks exactly to the behavior just described. Hence it is clear that the correct choice of the amplitude of V, causes that the 5% level of V is independent of the amplitude

cLuS

from V . at a relatively constant phase angle inner

is reached halfway through the cycle, i.e. as long as V. within"

-. . _ ö -LXX.

The signal V _{: i} _compensates for the greater time delay in the case of a small V. in that it causes the switching transition of transistors ~ ΤΐΓ ~ and 11 to begin earlier in the cycle _{with decreasing V ^ 11} J ₁ ^11. Strictly speaking, Tt Ti does not have to be derived from the collector of transistor 10, but it is of course very convenient to do so.

The optimal amplitude for the signal V i is best determined experimentally. It would be presumptuous to give a fixed rule or formula for determining the amplitude of V ^, but it should preferably be smaller than the smallest operational "V · _η · The same is true for determining the optimal delay time or delay length, although certainly

70 9 819/0974

it can be said that the phase difference between V 1 and V. should be close to either - '■' / 2 or + 3/2 'if integer multiples of 2 * ~ are neglected. This condition can be expressed in the following way:

Phase difference = (~ i) ⁿ (2n - 1) - ^

where η = 1, 2, 3 ·> ··· etc .. However, it is important to emphasize that the experimentally determined optimal phase difference is ~ bi's ~ ZT3r-30-- ⁱ icÄd or more from that given by the above - F-ormel'-specific phase difference can deviate.

Before describing Fig. 6, which shows the improved performance of the circuit shown in FIG. 4, are the values and data of the components used in this circuit are listed: -__.

Operating frequency range from V.

Transistors 10 and 11

Delay line 25

resistance 24- 18th Resistances 12th 19th 14- 23 15th 21 22nd 27 Potentiometer 26 Direct current biowork capacitors

274.176 MHz 2O'dB- (O, 2 V

ss

2N5652 (for _r n = 4 GHz,

^ Nano seconds (causes approximately 280 degrees of phase delay at the operating frequency from "274.176 MHz)

27 ohms 220 ohms 82 ohms

220 0hm _ ^ -

24 ohms 82 ohms - "^ 1OK 0hm 1OK ohms 0.01 yuP 0.01 uF 0.01 uF

709819/09 7

- -e -

Supply voltages V 1 ^z ! -J5 volts

V _B 6.2 volts

In Fig. 6, the upper curve shows the amplitude response a typical circuit with the above values. As you can see, the amplitude of V changes a little more than

the end

1 dB over a corresponding change in V. from approx.

".1 .XJ.

20 dB, while the phase response behavior, which is reproduced in the lower curve, with a 20 dB variation from V . changes by about 10 degrees. A comparison of Fig. 6 with Fig. 3 shows how the superposition of V, at the base of transistor 11 is a significant improvement over the prior art limiter, as shown in FIG Fig. 1 is shown brings. If one compares the behavior shown in FIG. 6 with the prior art Diode limiters (not shown), there is a certain deterioration in the phase response, in particular in the direction of the minimum amplitude of V. . In most cases, however, there is such deterioration within acceptable limits (10 degrees).

Although the preferred circuit shown in Fig. 4- has one Resistor 15 as a current source, but a transistor or other suitable current source can also be used. this however, it is not essential and, if sufficient, a resistor has the advantage of lower cost.

The preferred embodiment described herein shows one Property that does not appear disruptive in the present application. If the circuit according to Fig. 4- is not of driven by an input signal, an unstable state results with an oscillation of approximately 1 MHz. Such a The astable state comes from the capacitor 23 'which causes the circuit as an astable rSultivibrator at lower frequencies acts, since the delay line 25 with such fre-

709819/0974

IS

sequences has a negligible delay. Of the
Capacitor 23 must therefore be chosen so that it has a
Oscillation frequency results that are sufficiently far below the
actual operating frequency of the circuit. In the present embodiment, 1 MHz is sufficiently far from 274 · »176 MHz. It is only necessary to ensure that the apparent astable state is actually suppressed when the minimum V- is applied to the input

ti JLXx

will. This condition is not the limiting factor for the minimum value of V * in the present application.

fciiiA

The invention thus provides a limiter circuit for the extracted timing signal in high speed digital relay amplifiers. The conventional, emitter-coupled limiter comprising a pair of transistors is modified in that the decoupled, attenuated and delayed signal am is applied to the base of the output transistor
Collector of the input transistor is applied. The delay is chosen so that the compensation signal is on
the base shows a phase shift of approximately -5/2 7Γ with respect to the input signal. An experimental determination of the delay and the attenuation results in optimal phase and amplitude response behavior, which shows a considerable improvement over the amplitude and phase response behavior of conventional limiters.

- patent claims -

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/ ff

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Claims (1)

Claims 1.! Limiter circuit for a periodic input signal with ■■ changing amplitude, with a first and a second switching device, which are connected and preloaded in such a way that they work in current-wise switching mode, and having means for applying the input signal to the control electrode of the first switching device, thereby characterized in that a second, periodic Signal is applied to a control electrode (base of 11) of the second switching device (11), this second periodic signal at the control electrode has a predetermined amplitude and a predetermined phase difference with respect to the Has input signal (Fig. 4). 2. Limiter circuit for a periodic input signal with varying amplitude, this input signal on from extracted from a high-speed pulse stream, sinusoidal. forms a shaped timing signal and is thus pre-amplified that it has a predetermined minimum operating level, and that circuit has a pair of high speed switching transistors same polarity with a common emitter resistor to a common circuit connection and comprises means for biasing the pair of transistors to operate in the unsaturated current mode, and furthermore, the sinusoidal timing signal is applied to the base of one of the two switching transistors, characterized in that the collector of one (1O) of the two switching transistors (1O, 11) to the Base of the other (11) of the two switching transistors by a series connection of a DC blocking device (23), a signal attenuator (24-) and a phase shifting device (25) is coupled. 709819/0974 original 2850582 3 · Limiter according to Claim 1 or 2, characterized in that the first and second switching devices is a first and second bipolar transistor. -. Limiter according to claim 3 1 characterized in that the first input signal is essentially sinusoidal (Fig. 5 »V.) And that the second, periodic signal (Fig. 5 ₅ V ^) is a delayed, attenuated version of the at the collector of the first switching device appearing V / alternating voltage signal. 5 Limiter according to Claim 4, characterized in that that the second periodic signal by the time equivalent of an optimal phase angle in the order of magnitude delayed by 3/2 / Γ plus an integer multiple of 2 / Γ is. 6. Limiter according to claim 4-, characterized by calibration e t that the second, periodic signal is essentially trapezoidal and has an optimal amplitude that smaller than the smallest expected amplitude of the input signal is. 7 Limiter according to Claim 6, characterized in that that-a limited output version (V) of the one-off output signal is obtained at the collector of the second switching device. 8. Apparatus according to claim 6, characterized marked eichn e t that the delayed, attenuated version at the base of the second, bipolar transistor is thereby obtained is that this base and the collector of the first bipolar 'transistor via a series connection of a capacitor (23), a V / iderstand (24) and a delay line (25) are connected to each other. 7 09819/0974 9 · Limiter after. Claim 8, characterized in that that the capacitor has a capacitance large enough to cause the limiter circuit in its astable state oscillates at a frequency that is far removed from the frequency of the input signal, when this input signal is below a predetermined minimum amplitude. 10. Limiter according to claim 9, characterized in that the predetermined phase difference is in the order of magnitude of (-i) ⁿ (2n - 1)%, where η is a positive integer. 11. Limiter according to claim 2, characterized in that that the biasing device has a resistor in the collector circuit of each of the two switching transistors between a first supply connection and the respective collector. · 12. Limiter according to claim 11, characterized in that that the biasing device continues to have a resistor in the base circuit of each of the two switching transistors between a second supply connection and the respective Base includes. 13 · Limiter according to claim 12, characterized in that that the first and the second supply connection have a common circuit connection as their common third connection on iron. 14-. Limiter according to claim 11, 12 or 13, characterized in that the pretensioning device further comprises a includes adjustable resistance device in the base circuit of one of the two switching transistors that are so connected ■ is that it biases this one of the two switching transistors to compensate for a mismatch in the base-emitter characteristics of the couple varies. 70 9 819/0974 15. Limiter according to claim 11, 12 or 13 _? characterized in that the device for coupling the sinusoidal timing signal is a DC blocking capacitor and that the collector of the other of the two switching transistors is coupled to an output terminal of the limiter circuit via a DC blocking capacitor. 709 819/0974