DE2636233A1 - Superconducting memory with optional modes - can be operated as free access or associative memory with cell matrix with Josephson junction - Google Patents

Abstract

A first coordination device has a first type of lead (S) which splits the bit column of the matrix in each cell (1) into the two branches of the loop of the line. One branch contains a Josephson junction as writing contact connects all lines of the first type. There are means at the boundary of the matrix for connection to drivers (5) for bit-writing pulses or data pulses as the index argument for associative interrogation or to reading circuits (6) for read-out of dat. A second coordination device has a line (W) coupled to the loop of each cell of the associated word line which can be connected to drivers (7) for word reading or reading pulses in free access or to provide reading pulses after successful association search procedures.

Description

Superconducting storage device

The invention relates to a superconducting memory device which can be used with random access or in associative mode of operation.

State of the art Superconducting memory devices for optional Access have become known, for example, from DBP 1 934278. The memory cells consist of conductor loops, each of which has a Josephson contact in both branches. The sense of circulation of the supercurrent defines the binary information.

Three types of drive lines are provided: a word line in the column direction divides into the two branches of the conductor loop at each cell; a bit write line and a read line with a run perpendicular to it Sensing contact in every cell. Writing is done by coincident word and bit pulses, the Reading through coincident impulses on word and reading line.

IBM Technical Disclosure Bulletin Volume 15 No. 2, July 1972 shows on pages 449-451 a usable memory cell with only one Josephson junction in the conductor loop as a write contact. The bit line acts as a control line for the Josephon contact; the non-destructive reading takes place by means of a Sensing contact in a special reading line.

A memory cell for associative operation is in IBM Technical Disclosure Bulletin Volume 16 No. 10 dated March 1974 to pp. 3321 and 3322 shown. The cell has two write contacts in the conductor loop; the associative query and the masking of certain bit positions is shown. However, it is not shown how a recognized, matching memory word can then be read out can; the memory organization shown is not suitable for this. Also the condition Information-independent concordance in which a match signal is independent of the query value is given, cannot be produced in this cell.

A memory cell suitable for use in a "linking matrix" is in IBM Technical Disclosure Bulletin Volume 17 No. 3 of August 1974 at p. 890 and 891. Here, too, a first control line splits at of the memory cell in two branches of a conductor loop, one branch of which is the Contains write contact. A second control line runs across (via the write contact) and a read line with a sense contact. In contrast to known memory cells the binary information becomes here due to the presence or absence of a ring current embodied. This is the mode of operation of the Boolean linking of the memory contents possible with query data.

The memory cells are personalized by registered mail via the two control lines. However, the reading is carried out by the query stream on the read line together with the input of data via the control lines of the first type. If the input values match the memory contents, their AND link output as read signal. However, the reading line only delivers the OR link of all cell signals.

Task The invention has the task of providing a memory device of the type mentioned at the beginning, either as word-organized Memory with random access or as associative memory is able to work. The associative mode of operation should not only be the associative Allow query with a search argument, but also to read out what you are looking for Allow memory words showing feature. None of those mentioned in the prior art Arrangements allow such a mode of operation. This task is achieved by the claim 1 defined storage device solved.

Preferred embodiments of the invention are set out in the subclaims contain.

The invention is based on exemplary embodiments with the aid of Drawings explained in more detail.

1 shows a schematic overview of a memory device with memory cells arranged in a matrix, which at will with optional Access or in associative mode of operation can be controlled.

Fig. 2 shows a first embodiment of a memory cell with a Josephson junction as a write contact in a conductor loop and three control lines, of which one with a sensing contact, which cell in the memory device of Fig. 1 can be used.

FIG. 3 shows the circuit diagram of the memory cell according to FIG. 2.

Fig. 4 serves to explain the use of the memory cell with random access.

Fig. 5 is used to explain the use of the memory cell for the associative mode of operation of the memory device.

Fig. 6 shows an embodiment of circuit devices for Provision of drive current pulses for reading out memory words after successful associative search.

Figs.

7 to 9 serve to explain the mode of operation of the memory cell with random access and show the writing of information, the non-destructive Reading out information in a first coordinate direction and the non-destructive part Read out in a second coordinate direction.

Figs.

10 to 12 serve to explain the associative mode of operation of the Memory cell and show the writing of information, the associative Abirage in a first coordinate direction and the readout in a second coordinate direction.

Figs.

13 to 15 schematically show a second embodiment of a Storage cell, with two conductor loops and one Josephson junction each as a write contact, a common sensing contact and four control lines, which are three different Can assume memory states, namely a first and a second binary value as well as a state of information-independent concordance.

16 shows a possible embodiment of the memory cell according to FIG the FIGS. 13 to 15.

Figs.

17 to 19 serve to explain the mode of operation of the memory cell and show the writing of information, the non-destructive reading or the associative search operation and the retrieval of information.

Fig. 1 shows schematically a memory device with a number of memory cells arranged in a matrix. Each memory cell 1 has at least three control lines such as lines 2, 3 and 4, which one too with the letters S, W and M are designated. In a first coordinate direction, e.g. the column direction, the S-line runs. The lines run in the direction of the lines W line and the M line.

The control lines with circuit devices are at the edge of the matrix connected, which are necessary for the operation of the storage device. The lines 2 are connected to bit driver circuits 5 at the lower end of the columns, which also contain corresponding decoding devices. At the top they lead to Reading circuits 6. Word driver circuits are located on the left side 7 with associated decoding devices. There are more on the right Circuit devices 8, which are required in particular in the associative mode of operation will.

The storage device can have both random access and word-organized Memory can be used as well as associative memory. The requirement is the ability of the storage elements, here called storage cells, to provide information to be able to save, write and read as well as compare and read. In addition, despite the versatility mentioned, the memory cells are still very simple in construction, so that one to improve the packing density the memory matrix also manages with a minimum of control lines. the Memory cells used for the dual purpose actually allow two various read-out methods that are used here according to the invention for a new type of memory organization be exploited.

A large matrix memory is usually word-organized and has driver circuits in both coordinate directions of the memory plane.

Word drivers call the memory cells combined in a memory word a row, whose information is in the other coordinate direction on the bit lines is written in or read out in parallel. Access is localized Memory locations, the address of which is decoded by the control circuits. In an associative memory, however, new information can be stored where there is currently space available.

It is not accessed by decoding a fixed address. That Reading the memory content, for example, takes place rather than content-related associative search operation, with features of the memory contents or significant Parts of the memory words themselves with a keyword entered for the query or bit patterns can be compared as search criteria. A first step in the selection is therefore a comparison operation. Thereby memory words recognized that match the search argument in the queried bit positions. Marking hold circuits must be set accordingly. In a second Step or in further steps, memory words are marked in this way read out.

The circuit devices 8 contain marking circuits for memory words recognized as matching as well as driver circuits for reading out highlighted memory words.

FIG. 2 shows a first exemplary embodiment of the one according to the invention Storage device usable memory cell in Josephson technology. In a superconducting loop is binary information as a permanent ring current stored, whereby the sense of direction embodies the binary value. In a branch of A first Josephson junction is arranged as a write contact 9 in a conductor loop. A second Josephson junction serves as a sensing contact 10 in the course of the M line. On a (not shown) superconducting base plate are in a first Metallization layer applied to the lower electrodes 11 and 12 in an insulated manner. she at the same time also form a section of the S line or the M line.

The hatched areas 9 and 10 steep the Josephson junctions of the write contact or the sensing contact, where a thin oxide layer themselves located between the superconducting electrodes. The upper electrodes or pieces of lead 13 and 14 of the S line and the M line are in a second metallization step upset. The M line consists alternately of such sections 12, 14 of the first and second metallization layers each with a sensing contact therebetween 10 at the location of a storage cell. In adjacent memory cells of the same row the arrangement is therefore made accordingly. The upper Eleletrodczn 13 of the write contacts 9 are built in mirror image in adjacent memory cells in the same column (see. Fig. 6), which is why an alternating sequence of sections of the first and the second metallization layer is present. Only owns the S line also sections 16 from a third metallization layer, which by contacting 17, 18 are galvanically connected to the associated line pieces. How to get there with a minimum of metallization layers and vias. Likewise in the third metallization layer is insulated over the lower branch of the conductor loop the W line 15 applied. The necessary insulating interlayers are not drawn for the sake of simplicity of illustration.

The information stored in a memory cell can be non-destructive by using the control line corresponding to the M line existing Sense contacts are read. Runs in a conventionally organized store hence usually the drive line used as the word line in that one Coordinate direction, which here would correspond to the S line. So is for example the storage device is organized according to the patent mentioned in the introduction. But you can also use the temporary switching of the write contact in the Conductor loop occurring magnetic flux changes induced by their Read voltage pulses as output signals. These voltage pulses run lengthways of the S line, so that in this case the word line is one in the other coordinate direction running control line would have to be used. This second reading process deletes the information, which is why an immediately following cycle for rewriting is required in the memory word just read. In the storage device according to the invention, both reading methods are used, but for different ones Purposes.

3 shows the circuit diagram of the memory cell and its implementation is shown as a first embodiment in FIG. The one in the column direction The S-line is divided into the conductor loop, one branch of which is the contains write contact shown as a symbol. The W line, which is inductive with that branch of the Conductor loop is coupled that does not contain the write contact. Likewise in line direction runs the M line, which is shown as a symbol at the location of the memory cell Contains Josephson junction as a sensing contact. Part of the one containing the write contact Branch of the conductor loop serves as the control line of the Josephson gate circuit of the Sensing contact. The arrows drawn define the respective positive current direction. The ring current IR should, for example, in the direction shown in the clockwise direction embody the binary value "1". The positive current directions are arbitrary in themselves chosen. They are appropriately retained in this way in the description. To note is also that e.g. a positive current pulse in the W-line has an opposite one Ring current induced in the conductor loop, which then corresponds to the binary value "0".

Such a memory cell has the advantage that in the Josephson Uebergat of the write contact, high current densities can be permitted without any resonance-like Phenomena occur which could have a disruptive effect on operation. In a The Josephson gate circuit acts on the magnetic field of the control current the Josephson junction and uses its maximum Josephson current for control purposes down. However, the memory cell's write contact does not have any in this way acting Control line. Rather, it is in an area where practically no magnetic fields originating from the control currents are effective.

This design helps to avoid resonances. Depending on his Sense of direction, the induced portion of the ring current adds to that already current present in the conductor loop or is subtracted from it. When crossing The Josephson contact switches certain current values: the currents can be chosen in this way that this switching process from the superconducting state to the energized State of the Josephson transition is only a temporary switching process and itself resets itself. A short voltage pulse is created which is sufficient about the current distribution in the conductor loop and thus the sense of direction of the resulting To change the ring current. The sensing contact in the M line is a Josephson gate circuit provided, the control line of which is part of the conductor loop.

Fig. 4 indicates how the memory cell is used when the Storage device as a word-organized memory with random access via address decoding devices is used. In this case, the reading method mentioned in the second place above is used the flow change needed, which is why the storage device differs from conventional facilities is now organized in such a way that the word line lies in the row direction because the as Output signals use voltage pulses in the column direction the # S line run through. For the control of the storage cell, therefore, the inductive with the W line coupled to the conductor loop as a word line and the galvanically coupled S line used as data line or bit line. In the drawing is symbolic the M line not used in this case only shown in dashed lines and the Designation (M) in brackets.

Now the reading method mentioned in the first place is in the other Coordinate direction free for other purposes and according to the invention is used for recognition of matching memory words in the associative mode of the memory device exploited. Fig. 5 indicates that in the associative query of the memory content the W line initially remains unused as a word line. It is shown in dashed lines, and the designation (W) is put in parentheses in the figure. The query takes place with the data pattern of the search argument on the 5 lines, with the sensing contacts sensitized or prepared with a bias current pulse on the M line.

However, an associative memory is incomplete if after associative Query recognized memory words cannot also be read out. In the case of the positive result of an associative query becomes the this Hold circuit associated with the memory word is set.

This holding circuit also belongs to the circuit devices which enable the reading out of recognized memory words.

Fig. 6 shows an embodiment for such shaft devices, which drive current pulses on the word line now used for reading out Provide memory words after a successful associative query. Appropriate the sense contacts of the memory cells work in such a way that they do not match switch to the energized state. They stay then and only then in the superconducting state when all queried bit positions of the memory word Show agreement. If even a single bit does not match, then lies Voltage on the M line, which is evaluated accordingly by switching devices will.

The word line W is for normal memory operation at word decoders 19 connected. At one end of the S lines running in the column direction there are sense amplifiers 20 that are used for the reading process of detecting flux changes are suitable. At the other end, the data inputs 21 are provided, which at (not shown) driver and Decoding circuits connected are. For normal operation, these supply the bit pulses for the data, which are in the memory location activated by the word pulse are to be stored. In the event of the associative query becomes the bit pattern for the search argument on such data entries entered. Of course, this pattern then contains fewer bits than the whole Memory word. The drawing serves to explain the principle. Therefore are also Selection circuits and masking circuits are not shown here. The associative In this example, the query results in a voltage on the M line if they do not match the queried bit positions of the memory word with the corresponding data of the Keyword is present. An inverter 22 is connected to the M line, its Output leads to a holding circuit 23.

This holding circuit 23 is therefore set in the event of a match and marks the associated memory word after a successful associative search.

The hold circuit now delivers for reading out a marked memory word 23 the drive current pulse on the word line W. The word decoder 19 is in this Trap shut off. The sense amplifiers 20 recognize the read out signals and pass them on to the data processing system for evaluation. In the drawing a further row of the memory matrix is indicated by three memory cells. To simplify the structure, these are from the in the description The reasons explained in FIG. 2 are constructed in mirror image. The next line of the Matrix then corresponds again to the line shown above and so on. For the first Loading of the associative memory with information can be done with the described memory device the word decoders 19 as well as existing ones are used.

Some possible modes of operation are given as examples in the following Described illustration of the operation of the memory cell in the memory device. In Fig. 7 it is indicated how ring currents IR for the first time in motion in the memory cell be set. For this purpose, a negative pulse is put on the S line and a positive pulse of a special shape is applied to the W line to create a ring current Induce IR for example clockwise in the conductor loop. The word stream pulse suitably has a short rise time and a relatively long fall time. Is once a ring current present in the cell, need to switch over and thus for storage operation the pulses no longer have the aforementioned special shape to have. The temporary switching of the write contact with a change in the power distribution in the conductor loop and thus the writing of information takes place with coincident Pulses on the W line and the S line. For example, a positive W pulse will result and a negative S-pulse a resulting ring current clockwise, which corresponds to the binary value "1", for example. To be written in a "0" the polarities of both impulses reversed. A negative W-impulse with a positive one After switching off, the S-pulse leads to a persistent counterclockwise ring current. This enrollment process can be used for everyone who is hitherto organized or word-organized Storage facilities are used.

8 serves to explain a first readout method. A Bias current on the M line still remains below the switching threshold Sense contacts connected in series in this line. Whether to switch the Josephson gate circuit takes place in the energized state or not depends on whether it is in the S line and thus in the control line at the same time The current pulse sent to the gate circuit is added to the existing ring current or subtracted from it. For example, a positive S-pulse is added to a clockwise flowing ring current, so that the switching of the Abfühjkon clock means a read binary "1" in this case. You can get the definition also choose differently that z. B. the non-switching means the criterion. That is useful in the case of the comparison operation of the memory cell with a ciative query, where a non-switching should indicate the agreement. In this case subtracted a negative S-impulse from the clockwise flowing Ring current of the binary value "1" and the non-switching of the discharge contact signals the Correspondence of the queried binary value with the storage value of the cell. This The readout process or comparison process does not erase those in the memory cell existing information.

Another readout method outlined in FIG. 9 is effected by a current pulse induced by the W line in the conductor loop switches over of the write contact when this induced current is added to the ring current.

The associated change in the magnetic flux linked to the conductor loop induces voltage pulses running in both directions along the S line. The magnetic flux n present in the inductance of the memory cell can be of the order of 100 flux quanta. Half of the converted energy contributes to a partial pulse at. The drive current pulse to be sent to the W line may have to be stronger than the word current pulse used for writing. This reading process erases the information in the memory cell, which is why it must be rewritten after reading out. Since only the addition of the currents in the conductor loop leads to a switchover and the subtraction does not, only reading out one binary value results in a voltage signal, so that the absence of an output signal when reading out indicates the other binary value.

To write a binary "1", use is made of Fig. 10, for example a positive W-pulse and a negative S-pulse. Since to store a l1 ~ 0 " the polarities of the control impulses have to be exchanged, the process of the Registration can be done in two steps.

For example, the first step is to write to all cells of the storage device a binary lllll. Then, in a second step, the relevant memory cells each have a binary l10 with the aid of a negative W-pulse and a positive S-pulse. This second step is necessary because the polarity of the word current pulse must also be reversed.

Fig. 11 is used to explain the associative query. The storage cell for example contain a clockwise ring current and thus a binary one "1". The comparison operation should be carried out in such a way that after the presence at one t is asked. The agreement is made by not switching the sensing contact signals. The positive bias current on the M line sensihilizes the sensing contact. A negative S-pulse-s is subtracted from the existing one in the conductor loop ring current of the stored binary value "1". ### As a result, the threshold not exceeded and the sensing contact does not switch.

However, by definition, this non-switching shows the agreement of queried with the stored binary value. When querying a saved "0" adds the positive S-pulse in the case of a stored "1", so that the increased ring current the sensing contact for switching into the energized State brings. But this is the signal of disagreement. in case of a stored ring current counterclockwise and thus a binary "0" the situation is reversed accordingly. Added to the value "1" when queried the negative S-pulse to the ring current of the stored "0" and brings the sensing contact to switch, which indicates the mismatch. The positive S-pulse one However, query for the binary value "0" is subtracted from the ring current of the stored ~ 0 ", which is why the threshold current is not exceeded. Not switching the Sense contact shows the agreement of the stored binary value with the requested binary value.

A stored binary “1” is read out according to FIG. 12 for example, so that a negative pulse is sent over the W line. Of the positive impulse induced in the conductor loop temporarily amplifies the ring current and therefore brings the write contact to switch. The change in the Magnetic flux-induced voltage pulses run over the S-line. One the voltage pulses is in the connected reading circuit evaluated.

The above exemplary explanations of possible operation states and operations show that the memory cell described is a memory device can be built according to the invention. Two independent reading methods are essential in different coordinate directions, one of which is for the associative comparison operation is used. The first embodiment relates to a storage cell with inductive coupled word line. This was chosen because of various additional advantages. But it is also possible to combine a memory device according to the invention with others Build types of memory cells. For example, the write contact can also built in the manner of a Josephson gate circuit with the word line as the control line be.

The use of memory cells with a write contact is also possible possible in each branch of the conductor loop in the storage device described .

The uses of associative memory are becoming significant expanded when its memory cells also have an information-independent state Are able to enter into concordance. Then these cells enter at associative Query always a match signal, regardless of it, on which of the two binary values this bit position is queried. Such Bit position is so to speak "insignificant" in special associative comparison operations, so that the memory "doesn't care" about it. This additional possibility the coding of memory cells is particularly valuable in associative memories, by taking advantage of this possibility, also calculations or logical links of data, for example for the modification of machine instructions can. Such memories are known as function memory or function memory known. This particular memory state of the memory cell is not synonymous with the masking of bit positions that are not queried at all. As is known, the number of bit positions is used for the associative query of the keyword compared to the full number of bit positions in the memory word limited by masking the excess areas.

A second embodiment of a for use in the inventive Storage cell suitable for the storage device also has the option of Coding in the X state, the state of information-independent concordance. These The memory cell has two conductor loops, each with a write contact into which the S line splits up. Two word lines WA and WB are also used as control lines for the two conductor loops in sub-cells A and B. The sensing contact is common and is part of the M line. His control line is the common part of the conductor loop of the S line that does not have any write contacts contains.

The circuit diagrams of FIGS. 13 to 15 show an example of coding or assignment of the memory states to the information values "1", "0" and "X". The binary values are embodied by ring currents in the conductor loops of this type, that in the common part of the control line of the sensing contact an unambiguous Current direction is present. For example, according to FIG. 13, the binary value "1" is through a clockwise ring current in sub-cell A and through a ring current in Defined counterclockwise in sub-cell B. The one flowing through the control line Current runs from top to bottom in the drawing. The binary value "0" is after of Fig. 14 by a ring flow counterclockwise in the sub-cell A and defines a clockwise ring current in sub-cell B. The control current of the Sensing contact sells from bottom to top in the drawing. The indefinite X state is characterized by opposing partial currents in the halves of the control line. According to FIG. 15, for example, the X state corresponds to being stored in the clockwise direction Ring currents in both sub-cells A and B.

One possible implementation of the second embodiment of a The memory cell is shown schematically in FIG. On the (not shown) superconducting base layer are insulated in a first metallization, the lower Electrodes applied to the Josephson junctions. These are the base electrodes 24 and 25 of the write contacts in sub-cells A and B, as well as the lower electrode 26 of the sensing contact with one of the sections of the line, which are in adjacent Memory cells of the same row of the matrix on the right or left side are located. Here, too, the sensing contacts in the line of the M line are alternating constructed in the order of the electrodes. Located in the hatched areas the thin oxide layers of the Josephson junctions of the write contact 27 of the Partial cell A, the write contact 28 of subcell B and the sensing contact 29. In a second metallization, the upper electrodes 30, 31 and 32 follow, respectively also a section of the S line leading out of the storage cell and the conductor loop or the M line. In a third metallization applied in an isolated manner the conductor loops are completed by a cross-shaped section 33 of the S-line. This is at the four ends by means of contacts 34 to 37 with the rest Lines connected.

Also in the third metallization are the inductive with the Conductor loops A and B of the memory cell coupled word lines 38 and 39 are applied.

The write contacts 27, 28 are Josephson Transitions without special control lines. The same apply mutatis mutandis to their dimensioning Conditions as explained above with reference to the first exemplary embodiment. Of the Sense contact 29 is a Josephson gate circuit with a transverse control line, which is formed by the part of the S-line running vertically in the figure. To reduce the self-field of the sensing contact, the M-line is on the side extended so that the Josephson gate circuit has a hammer-like floor plan. This advantageous design of a self-restoring Josephson gate circuit is for example by publication on pages 3031 and 3032 of IBM Technical Disclosure Bulletin in issue 9 of volume 16 of February 1974 became known.

Fig. 17 illustrates the writing of information in the Storage cell. For example, the coincident application of pulses to the Control lines WA, WB and S in the strongly drawn out form a resulting Distribution of the ring currents in a way that corresponds to a binary "1". One Reversal of all pulses according to the dashed representation results in a binary one "0".

With the associative query on a stored "1" according to the Fig. 18 becomes a pulse on the S line and a pulse on the M line created. The current fed in via the S line is added or subtracted of the portions of the persistent ones flowing in the control line of the sensing contact Ring currents. If the sensing contact is sensitized by an M-pulse, exceeds the sum of the partial currents is the threshold value for switching the Josephson gate circuit or the difference between the partial flows remains below this threshold value. Here too is it is expedient to design and operate the circuit in such a way that in the event of a match the queried with the stored information in the comparison operation of the Sense contact does not switch to the energized state, so that there is an absence the voltage signals the match. The bias current in the M line is set so that it is still below half the value of the maxima] en josephsonstromes of the sensing contact remains. In one half of the control line, the full current flow without the contact already switching. That way is it is possible that the contact, by not switching, will receive a signal of agreement when the memory cell is in the X state according to its current distribution.

Even in the case of a memory device with cells according to the second exemplary embodiment the readout takes place in the other coordinate direction via the S-lines the voltage pulses induced by the change in flux. As indicated in FIG. 19 cause pulses on both word lines WA and WB switching of the two write contacts in the sub-cells. The one in one of the two diverging The energy present in voltage pulses is now practically twice as large as with the first embodiment of the simple memory cell.

Claims (5)

PATENT CLAIMS Superconducting memory device for optional Access or for associative mode of operation with memory cells arranged in a matrix, which has a Josephson junction as a write contact in at least one conductor loop and those with at least three control lines for connection to drive power sources and provided on circuits for writing and reading binary information are, characterized in that in a first coordinate direction a first Kind of lines (S) is provided, which are located in each memory cell (1) of the bit columns of the matrix into the two branches of the conductor loop, one of which Branch contains a Josephson junction as a write contact, and which branches are reunite in the aforementioned lines of the first type, those at the edge of the matrix with drivers (5) for bit write pulses or for data pulses as search arguments for associative query of the memory content or with reading circuits (6) for reading out of information can be connected that in a second coordinate direction a coupled to the conductor loop of each memory cell of the associated word line Line (W) of the second type runs with drivers (7) for word write or read pulses with random access or with circuit devices (8) to provide can be connected by reading pulses after a successful associative search, and that also in the second coordinate direction lines (M) of the third type a row of Josephson junctions, one of which is used as a sensing contact for one of the memory cells of the associated word line of the matrix is used and in the case of the positive result of an associative query, the one belonging to this memory word Holding circuit (23) sets the reading of the found by associative query Enable information. 2. Storage device according to claim 1, characterized in that their memory cells in the case of associative interrogation except for the binary memory states can also assume a neutral state of information-independent concordance. 3. Sepicheinrichtung according to claim 2, characterized in that the storage cell in the course of the line of the first type (S) two conductor loops (A, B) each with a write contact (27, 28) contains two control lines per cell of the second type (WA, WB) are provided, and that the line of the third type (M) for both Conductor loops is common and a sensing contact (29) in the manner of a Josephson gate circuit with transversely running control line. 4. Storage device according to claim 3, characterized in that the sensing contact (29), as known per se, has a hammer-like layout where the control line is first through that part of the control line Type (S) or the conductor loops is formed, which does not contain a write contact. 5. Storage device according to claim 1, characterized in that said holding circuit (23) to the third line via an inverter (2-2) Type (M) is connected.