DE2560247C2 - Integrated semiconductor circuit arrangement - Google Patents

Description

The present invention relates to an integrated '5 Semiconductor circuit arrangement according to the preamble of claim 1.

Such a semiconductor circuit arrangement is known from DE-OS 20 36 686. With the well-known Arrangement, a low-frequency alternating voltage is fed in via ohmic contacts, i.e. via Electrodes that lie directly on the semiconductor body.

The object of the invention is to supply an integrated semiconductor circuit arrangement with alternating voltage to ensure high frequencies.

This object is achieved in the case of a semiconductor integrated circuit arrangement of the type mentioned in the introduction according to the invention by the features mentioned in the characterizing part of claim 1.

For optimal use of this type of voltage supply for the Fiinktionselemente, it is advantageous to use the To use transistor structures characterized in claim 2.

The invention is described below with reference to the exemplary embodiments shown in the figures of the drawing explained in more detail. It shows

Fig. 1 is a circuit diagram of a logic circuit with transistors / ur explanation of the principle of the voltage supply with a high frequency alternating voltage;

2 shows part of an integrated semiconductor circuit arrangement with a first embodiment of transistor structures;

J shows part of a semiconductor integrated circuit arrangement with a second embodiment of transistor structures; and

F i g. 4 a formation of strip-shaped base

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b5 and collector zones in transistor structures according to FIG. 3.

In the circuit according to FIG. 1, transistors T \ to Ts operated in emitter circuit are connected in cascade. In order to indicate that such a circuit can in principle be expanded as required, a transistor T> is added in dashed lines in the part of the circuit shown in solid lines.

The collectors of the transistors Γι and T ₂ , the base and the collector of the transistor T ₃ (and, if switched on, the collector of the transistor T ₄ ) and the base of the transistor Ts are connected to a terminal 5 via the capacitors G and C _{2, respectively} high-frequency alternating voltage supplied as supply voltage. Furthermore, a separate DC supply voltage from a terminal U is fed to the collector of the transistor Ti via a load resistor R. The transistors T ₁ and T ₂ (and if switched on also the transistor Ti) can be controlled at terminals I to I ₃ via their bases. A terminal O forms the output of the circuit.

A high-frequency alternating voltage, which has a sinusoidal or square-wave shape, for example, and a frequency of 15MHz at a voltage value of 5 volts, is applied to the ground as the supply voltage. Through the capacitance C and the base-emitter path of the transistor T ₃ and through the capacitance C ₂ and the base-emitter path of the transistor Ts , a current flows during the positive half-cycle of the high-frequency AC voltage at the terminal S , but the The voltage generated at the collectors of the transistors is smaller than the supply voltage due to the low resistance of the base-emitter path. The capacities form high-frequency current generators for the transistors.

If one of the transistors Γι or T ₂ at terminal I or I ₂ is switched to the conductive state by a positive control signal, the high-frequency current flowing through the capacitance C \ is short-circuited through the collector-emitter path of the conductive transistor, so that no more current can flow into the base of the transistor Tj, that is, the transistor T ₃ is blocked. If the terminals Λ and I _{2 are} at ground potential, the transistors Ti and T _{2 being} blocked, the positive half-cycle of the high-frequency current flows through the base of the transistor T ₃ . In this case, the transistor T _{3 is} conductive, so that it short-circuits the high-frequency current flowing through the capacitance C _2. Since the last stage forming transistor Ts with a separate DC supply voltage of z. B. 5 volts is operated, the supply voltage LJ is constantly at the output O when the transistor T _{3 is turned on.} If the transistor T ₃ is blocked, however, the voltage at the output O fluctuates in time with the high-frequency supply voltage between ground potential and the supply voltage LJ. This high-frequency output signal as well as a direct current signal obtained therefrom by screening are suitable for controlling further circuits.

The implementation of the circuit options described above in integrated technology is on the basis of the embodiments according to FIGS. 2 and 3 explained.

In the embodiment according to FIG. 2, a weakly doped or intrinsically conductive layer 2 is applied to a highly doped substrate body 1 of a conductivity type (for example p ^{+ type).} In this layer 2

are - for example produced by diffusion - zones 3 of the other conductivity type (for example η type). Metal coatings 4 are applied to the surface of this semiconductor structure. These metal assignments 4 form, on the one hand, Schottky contacts 5 in the large-area part and, on the other hand, Ohmic contacts 6 with η + -conducting zones in the η-conductive zones 3. The η + -conductive. Zones are in F i g. 2 indicated by double hatching

An insulation layer 8 is applied to the structure of semiconducting areas and metal coatings, on which in turn a metal electrode 9 is located. On the underside of the substrate body 1 is a further metal electrode 7 is provided.

Now the pn junction between the substrate body 1 and the zones 3 in the forward direction and the Schottky contacts between the zones 3 and the metal coverings 5 operated in the reverse direction, so the zone sequences work as transistors with emitter 1, base 3 and collector 4.

In the context of the explanations relating to the circuit according to FIG. 1, a high-frequency alternating voltage is now applied to the metal electrode 9 as a supply voltage. The integrated structure according to FIG. 2 offers the advantage that capacitors, such as capacitors C 1 and C ₂ according to FIG. 1, do not have to be additionally integrated. Rather, these capacitances are formed by the insulation layer 8.

Due to the ohmic contacts 6, an interconnection between the collector of a transistor Jo is at the same time and the base of another transistor possible. The weakly doped or intrinsically conductive layer 2 ensures an isolation between the transistors. An additional isolation diffusion or isolation through Oxide is not required because the s-> to be isolated Voltage is a maximum of 0.6 volts (threshold voltage of the base-emitter diode) and because it is important falling part of this voltage is absorbed by the potential barrier of layer 2. Still flowing Isolation currents are negligible.

F i g. 3, in the same parts as in F i g. 2 are provided with the same reference numerals, shows another Embodiment of the transistor structures. The emitter and base areas correspond to those according to FIG. 2. The collectors are not covered by metal but by semiconductor zones 13 (produced for example by diffusion), which with respect to the base zones 3 of opposite line type. Ohmic contacts 14, which are used for the electrical connection of the Individual transistors are used, result from heavy doping, which in turn is due to double hatching is indicated.

With an appropriate choice of conductivity types, for example, with an arrangement according to FIG. 2 pnp transistors and with an arrangement according to Fi g. J NPN transistors can be implemented.

The arrangement according to Figure 3 also has the The advantage that the semiconductor body is not interrupted by metal tracks, so that in the case of the described Structure, three-dimensional structures are also feasible. Such transistors and the Feeds for the supply voltage can also be arranged one above the other.

According to Figure 4, a transistor arrangement still simplify by the fact that the bases and the collectors are strip-shaped, with a Collector is created where a strip 13 crosses over a large area with a strip 3. The areas 14 in turn represent electrical connection points and base connections. If necessary, you can use a Base strip, several collector strips can also be guided. There are large geometric tolerances permissible because the different zones are not nested inside one another as is the case with conventional transistors are arranged. This results in smaller transistor structures, which further increases the packing density is increased.

Since only the positive half-wave of the high-frequency supply voltage is transmitted through the base of the transistors can flow, care must be taken that the same amount of charge is also in the negative half-wave can flow off so that the arrangement does not lock itself through the rectifier effect. With the arrangements according to Figure 4 this is possible through the parallel resistance to the base-emitter path, which is through lack of isolation results. With a few cascaded transistor stages, the charge in the negative half-wave also flow away via the collector-base sections prestressed in the flow direction. In principle, however, at least one of the transistors is parallel to the base-emitter path and one against it inversely connected diode is provided, which serves to discharge the charge. There is no such diode required for all transistor stages.

With a large number of stages it may be necessary because of the finite signal propagation time that Supply voltage at different stages with a different phase position or frequency to feed. A three-phase system with a phase difference of 120 ° is particularly important.

For this purpose 2 sheets of drawings

Claims (2)

Patent claims: 1. Integrated semiconductor circuit arrangement with active and passive functional elements in a semiconductor body and with an alternating supply voltage for at least some of the functional elements, characterized in that for supplying the high-frequency alternating voltage on an insulation ίο located on the surface of the semiconductor body (1, 2) (8) a low-resistance polycrystalline semiconductor layer is provided which, together with the insulation layer (8) and the semiconductor body (1, 2), has at least one capacitance (C, or C ₂ ) for coupling in the high-frequency alternating voltage is for transistors of cascaded transistor stages (T , to T ₄ ) forms, and that parallel to the base-emitter path -venigsteLs one of the transistors (Tu T ₂ , T ₃ ) is a diode which is polarized so that it is in the half-wave in which the base-emit !: he path of the transistors (T ₁ , T ₂ , T ₃ ) blocks, conducts. 2. Integrated semiconductor circuit arrangement according to claim 1, characterized in that a blocking layer operated in the reverse direction in the form of a pn junction or a Schottky contact is provided for supplying the high-frequency alternating voltage in the semiconductor body (1, 2), via which the high-frequency alternating voltage into the Transistor stages (T to Ta) can be coupled.