DE2560194C2 - Electronic clock - Google Patents

Description

The invention relates to an electronic watch according to the preamble of claim 1.

From DE-OS 23 02 978 an electronic clock with a frequency standard and a divider circuit is already and a timing circuit known. Find all signal transmissions within the known clock in continuous operation. The consequence of this mode of operation is a relatively rapid consumption of the small clock battery.

Compared to this prior art, the present invention is based on the object of an electronic Clock whose energy consumption is significantly reduced.

This task is achieved in a generic electronic watch by the features in the characterizing Part of claim 1 solved.

Due to the pulse mode, the individual circuit parts of the clock are periodically excited for a short time, which significantly reduces the energy consumption of the watch.

Preferred developments of the electronic clock according to the invention are specified in the subclaims.

The invention is described below, for example, with reference to the drawing; in this shows
1 is a schematic block diagram of a solid-state electronic watch according to the invention.
Fig. 2 is a schematic representation in which the general structure of the in F ig. 1 illustrated electronic watch is illustrated,

Fig. 3 is a simplified block diagram of an electrical circuit for the clock shown in Fig. 2, Figs. 4A, 4B and 4C are each an illustration showing a detailed block diagram of an electrical circuit reproduces for the clock shown in Fig. 3,

5 shows a preferred exemplary embodiment of a time normal signal oscillator as shown in FIGS. 4A, 4B and Figure 4C illustrates

FIG. 6 shows an example of waveforms generated by the circuit illustrated in FIG. 5 will,

7A and 7B each show a representation of a preferred exemplary embodiment of one in FIGS. 4A, 4B and 4C of the illustrated synthesizer,

Fig. 8 is a diagram showing the relationship between clock pulses and timing pulses; which are provided by the synthesizer illustrated in Figs. 7A and 7B,

Figs. 9 and 10 are each a diagram illustrating waveforms generated by the circuit shown in Figs. 7A and synthesizers shown in FIG. 7B are generated,

<ö F i g. 11A and 11B each show a diagram showing in detail a circuit for the timer register according to FIG Figures 4A, 4B and 4C illustrate

Fig. 12 is a diagram showing an electrical detailed circuit for the in Fi g. 4A, 4B and 4C Control unit illustrated.

Figure 13 is an example of a flexible circuit as shown in Figures 4A, 4B and 4C. 14 shows a schematic representation of a shift register according to FIGS. 11 and 12, 15 is a diagram showing an example of a logic level setting circuit according to FIG Fig. 12 illustrates

16 shows a detailed circuit arrangement of the timer used in the control unit according to FIG. 12, 17 shows a schematic representation of a wrist watch which is designed according to the invention, Fig. 18 is a section showing the relationship between the position of the crown and associated parts;

F i g. 19 is a diagram illustrating the operation of the crown and switches of FIG. 18 illustrates, FIGS. 20A and 20B each show a representation, showing a detailed circuit for the data modulation unit shown in FIGS. 4A, 4B and AC,

21 shows a representation which shows a preferred exemplary embodiment of the one shown in FIGS. 4A, 4B and 4C Alarm unit illustrates

22A, 22B and 22C are each a detailed block diagram of the display driver and associated parts. 23 is a schematic diagram illustrating an example of the display area, υ

24A shows an electrical detailed circuit for the level shifter shown in FIGS. 22A, 22B and 22C, FIG. 24B is a view similar to FIG. 24A, but showing a modified example of the level shifter illustrates

24C shows an example of a decoder as shown in FIGS. 22A, 22B and 22C; Fig. 24D is an illustration of the operation of the display driver shown in Figs. 22A-C;

25 is a diagram showing a general concept of the invention preferably in addition the intended system,

26 is a simplified block diagram showing a preferred embodiment of the preferably provided System illustrated according to the invention,

27A, 27B and 27C are each an illustration showing a detail block diagram for the according to the invention 26, FIGS. 28A and 28B each show a circuit diagram of a shift register ring circuit according to FIG. 26, 29 shows an exemplary embodiment of a clock pulse control gate according to FIGS. 27A, 27B and 27C, 30 shows a preferred exemplary embodiment of a data modulation circuit according to FIGS. 27A, 27B and 27C, Fig. 31 shows an example of a composite pulse generating circuit.

F i g. 32 shows an example of a timing pulse generation circuit according to FIG. 27 A, 27B and 27C, F i g. 33 is a diagram showing a sampling circuit for determining and displaying the current time;

34 is a diagram illustrating a synchronizing signal generating circuit; F i g. 35 is a diagram illustrating a sampling circuit for the status of an alarm time display; 36 is a diagram illustrating an example of a composite pulse generator; 37 is a diagram illustrating a combined signal generator; Fig. 38 is a diagram showing a manual shift control circuit, Fig. 39 is a diagram showing a circuit for setting a marker, 40 is a diagram illustrating an example of an input control circuit 41 is a diagram illustrating an output control circuit;

F i g. 42 is a diagram showing an example of a sampling circuit for coincidence of alarm time and FIG the current time illustrates

Fig. 43 is a diagram showing an example of a sampling circuit for the coincidence of a data alarm and corresponding data illustrated,

44 is a diagram showing an example of a shift register stop control circuit; 45 is an illustration of a circuit for counting a leap year; 46 is a diagram illustrating an example of a data gate control circuit; 47 is a diagram showing an example of a input analyzing circuit; 48 is a diagram illustrating an example of an arithmetic circuit; 49 is a diagram showing an example of a gain loss adjusting pulse generator;

F i g. 50 is a diagram illustrating waveforms of a flip-flop used in the preferred provided system according to the invention is used,

F i g. 51 is a diagram showing an operating mode of the FIG. 28A and 28B illustrated shift registers represents

Fig. 52 is a diagram showing waveforms generated in the manual shift control circuit can be used according to Fig. 38,

Fig. 53 is a diagram showing waveforms of the output signals generated by the synchronizing signal generating circuit to be delivered,

F i g. 54 is a diagram showing a further embodiment of the FIG. 46 data gate counter shown illustrated.

55 is a diagram showing the relationship between various timing signals; 56 is a schematic diagram illustrating the mode of transmission data in each case, and

F i g. Figure 57 is a diagram showing the relationship between those preferably provided in accordance with the invention System used pulses illustrated.

In FIG. 1 is a schematic block diagram of a standard timer system according to the invention or Timing system 10 illustrated. An optionally or preferably provided system 12 can if necessary can be connected to the standard timing system 10 to perform special functions, as follows is explained in more detail. The standard timing system 10 is constructed to have various Functions, for example a time measurement and a corresponding time display, with easy additional systems such as 12 can be connected, making the standard timing system additional Functions fulfilled.

According to FIG. 2, the standard time measurement system 10 has a time normal oscillator 14 which has a crystal contains and serves to deliver a very accurate frequency, the oscillator having a frequency of

oscillates in 32 768 Hz. This relatively high frequency is fed to a synthesizer 16, which with very exact frequency generates a time unit signal of 256 Hz and which continues to generate various timing signals which are used to control various components of the standard timing system 10. These Signals are fed to a timing register 18 which shows the number of pulses of the time unit signal counts, thereby measuring the current time and providing a time data signal. The time data signal is a display device 22 such as liquid crystal display elements via a display driver 20 fed. An electrical energy source such as a Siiberoxid-Batlerie is designated with 24, which serves to to supply various components of the standard timing system 10 with energy. If that is optional or preferably provided system 12 is connected to the standard timing system 10, the electrical energy source 24 also various components of the optionally or preferably provided Systems 12 supply. The standard timing system 10 also includes a control system 26 which is so arranged is that the synthesizer 16 is controlled, that furthermore the timing register 18 and the display driver 20 can be controlled for various purposes, as will be explained in more detail below.

The optionally or preferably provided system 12 is also referred to briefly below as an additional system 12 designated. The auxiliary system 12 is arranged so that it can store time data such as an alarm time, which are fed from the timing register 18 of the standard timing system 10, and it can continue to do so Store input data, for example data relating to a month or a date, with corresponding signals can be fed from external control elements. For generating alarm time data the external control elements of the standard timing system are used. The alarm time data are delivered to the auxiliary system that stores the data. Alarm time data is provided by both the standard timing system as well as saved by the auxiliary system. Several alarm time data stored in the additional system are sequentially given to the shift register of the standard time measuring system and there stored, whereupon the stored data is compared with the current time data. The additional system 12 is also used to generate new data, which are explained in more detail below. That on Additional system 12 constructed in this way serves to generate a gain loss adjustment signal (i.e. a signal “Faster / slower”) depending on the new data that is stored in the additional system 12 be generated. This signal can be fed to the time normal signal oscillator 14, as it is by a broken line in Fig. 2 is shown. However, the gain loss adjustment signal is sent to the synthesizer 16 supplied. Various data that are stored in the additional system 12 are also stored are fed to the timing register 18, from which various data are stored without the

4ii time measurement is disturbed, and these corresponding data are fed to the display device 22 via the display driver 20. While the data from the additional system 12 is not fed directly to the display driver 20 here, the various data from the additional system 12 can be fed directly to the display driver 20 for display.
3 is a simplified block diagram of the electrical circuit for the standard timing system 10 according to FIG. 1. The circuit generally comprises the following parts: a standard signal oscillator 14, a synthesizer 16, a control unit 30, a timing register 32, an alarm unit 34, a data modulation unit 36, external control elements 38, a level shifter 40, a bit-series-parallel converter 42, a decoder 44, a word-series-parallel converter 46, a display driver 20 and a display device 22.

The time normal signal oscillator 14 has a crystal! which oscillates at a frequency of 32 768 Hz. This frequency is fed to the synthesizer 16, which has a time unit signal of 256 Hz and various Zeitsieuersignälc for driver components of the standard Zeitmeßsystcms supplies. The time unit signa] is fed to the control unit 30, which generates an output signal based on the time unit signal based. This output signal is fed to the timing register 32, which determines the number of pulses of the

; s counts output signals and updates time data.

The timing register 32 has a storage register which can be incremented and in which an initial value can be easily set. It supplies output signals in bit-serial form. The control unit 30 is controlled by external controls 38 to set the initial value of the counter which the timing register 32 forms. The output data of the timing register 32 are sent to the data modulation unit 36

_6f) , which modulates the data which are to be displayed as a function of the stored data in the timing register 32 and as a function of the data 1 of the external control element 38.

The data modulation unit 36 is used to generate an intermittent output signal in order to thereby To save power consumption. This intermittent output is sent to the display driver circuits supplied, including the level shifter 40, the bit-serial-parallel converter 42. of the decoder 44, des

₆ .- V Vort serial parallel converter 46 and display driver 20. The level shifter 40 operates to vary the signal level in such a way that the logic amplitude is amplified. The bit-serial-parallel converter 42 has a 3-bit shift register which converts the output signal of the modulation unit from a bit-serial signal into a bit-parallel signal in order to generate word-serial signals. The output signal,

which has been converted in this way is fed to the decoder 44, the decoded word-serial Generates signals which are fed to the word-series-parallel converter 46. This generates digit-parallel Signals. The decoded partial code is amplified by the display driver 20 to thereby the display device 22 to drift.

According to the illustration, the electrical circuit for the standard time system is designed such that it supplies the output signal to the auxiliary system 12, as indicated by an arrow in FIG. 3 is illustrated. That Supplementary system 12 is constructed in such a way that it sends various signals to the synthesizer 16 and the timing register 32 of the standard timing system.

A detailed block diagram of the electrical circuit for the standard timing system is shown in FIGS. 4A, 4B and 4C illustrate in which the same or corresponding components are provided with the same reference numerals as in FIG. 3. As shown, the time normal signal oscillator 14 is connected to a crystal 43 and is controlled by this in order to generate an output signal Φ _ο , that is, a pulse train which has a pulse repetition frequency of 32,768 Hz and an extremely high frequency stability having. The output signal Φ _ο is fed to an input of a frequency summing gate 50 of the synthesizer 16. The frequency summing gate 50 has a further input which is connected in such a way that it receives a gain-loss setting signal Φ _Ν which is passed through a frequency summing gate 52. One input of this gate is usually grounded and another input of this gate is connected to the auxiliary system 12 to receive a low frequency signal, ie the signal Φ _Ν which is used to adjust the gain / loss as described above became. The output signal Φχ from the frequency gate 50 is fed to a first timing pulse generator 54 which forms part of the synthesizer 16.

The first time pulse generator 54 generates various timing signals, including the clock pulses Φ and Φ ₂ , the time pulses T ₁ to T ^ and the digit pulses D ₁ to D _x6 , and it also generates signals Φυοι ^and Φ _υη for up-converters that are in the Additional system 12 are installed. A second timing pulse generator 56, which also forms part of the synthesizer 16, receives the timing signals or timing control signals generated by the first timing pulse signal generator 54, and generates various combined timing control signals, for example a timing input signal T) ₁ Tl of 256 Hz, from which the Control unit 30 generates a signal X of 256 Hz, which is fed to the timing register 32. The timing register 32 has a shift register ring 58 for storing various data. The shift register ring 58 has a first shift register 60, an adder circuit 62, a second shift register 64, an AND gate 66 and an OR gate 68, which are connected in series in such a way that a loop circuit is formed. Shift registers 60 and 64 have shift registers of 60 and 4 bits, respectively, for storing time data and various other data. The adding circuit 62 has an adder 62β, a shift register 62b and an OR gate 62c. The adder circuit 62 serves as a write-in gate in order to be able to write other data in addition to the time data into the time measuring register.

The outputs Q ₆ -. Q ₆₃ , Q ₆₄ and Q _{65 of} the shift register ring 58 are connected in parallel to a data sampling unit 70 which has a carry request detector 72 and a data detector 74. The carry request detector 72 is used to determine the status in which a carry is to take place, and it generates carry request signals W _% , W ^ and W ₅ . These signals are fed to the control unit 30 and passed through a corresponding carry lock gate of the control unit 30 to a summing gate of the control unit 30, to which the timing control signal D _x T _{x is} also applied, in order to generate the output signal X which is sent to the OR gate 62c is fed to the adder circuit 62 for the carry.

The data detector 74 detects the contents of the data stored in the shift register ring 58 and generates output signals ATO, O-sup, CONTA and B. The output signal ATO indicates that the data of the alarm time is not stored in the shift register ring 58, and it does is fed to the alarm unit 34. The output signal O-sup indicates that the tens digits of the data stored in the shift register ring 58 are equal to "0", and it is fed to the data modulation unit 36. The output signal CONTA indicates that there has been an increase in the data stored in the shift register ring 58, and it is used to control the data modulation unit 36 so that it controls the pulsed indication of data and clock pulses. The output signal B is generated in response to the time data stored in the shift register ring 58, and it is supplied to the data modulation unit 36 so that the unit 36 causes selected data to flash or blink at 1 Hz.

The control unit 30 responds to the input signals SH, SM, SK, SD, SUO, SUT, SUl SUl, which are supplied by the external control elements 38, and generates output _{signals S 1} , S ₂ , U, UL, G, S ₀ and X. The output signals S ₁ and S ₂ are fed to the alarm unit 34, to which the inverted output signals UL are also fed from the control unit 30. The output signal X is applied to the timing register 58, as already described above. The output signals U, UL and G are fed to the data modulation unit 36. The signals SD, SK and SUZ, which have passed through the control unit 30, are fed to the data modulation unit 36. The output signal S ₀ is fed to the data sampling unit 70.

The data modulation unit 36 has various data switching functions. It modifies selected parts ω of data that are fed to the display, also the time pulses and the clock pulses that are also applied. According to the invention, the data modulation unit 36 has a circuit which serves to modulate the data, and the data chopper circuit 76 serves to achieve an intermittent modulation of the output data. More precisely, the data chopper circuit or intermittent output circuit 76 generates a serial pulse train DATA-OUT for the data to be displayed in a fixed period of 1/256 sec every 1/16 seconds, as well as intermittent modulated timing signals T _% A, Φ ₂ Α and Φ \ Α so that the energy consumed decreases According to the above embodiments is used, the data modulation unit 36 to modulate the contents of the data with respect to a display modulation. Continue to be

the display mode of the data modulates without changing the content of the data. Instead of, for example to illuminate a specific segment or part of an analog display and the To switch off the lighting of another part, the display occurs in such a way that the lighting of a certain part is interrupted and other frequencies of the output signals are significantly reduced, to keep the energy requirement to a minimum. Furthermore, the modulation takes place in such a way that such data indicating a mark or mark, the background and a unit of one to be displayed Present information. These modulations are particularly advantageous because the information is on are easily visible on the display area. The decoder is used to convert these various modulated data decode.

Intermittent or chopping modulation of the output data and the timing signals is reduced the energy consumption of the standard timing system is high. For example, it is possible to use energy display driver circuitry and adjunct system to less than 1/10 of existing standard timing systems by intermittently generating the output signals 16 times per second. In a known arrangement, it is necessary to use a large-scale integrated circuit, which consumes a considerable amount of energy, while according to the invention opens up the possibility is to produce wristwatches that fulfill multiple functions in a similar manner, but essential consume less energy. This also reduces the size and capacity of the battery. Be it notes that the output data can only be displayed if the content of the data is changed, and the output data can also be displayed at the request of the user. That way it is also possible to reduce the power consumption of the auxiliary system and the display driver circuit.

The output signals Q62, Q63 and Q65, which are supplied from the shift register 64, are supplied to the data modulation unit 36. When the output signals Q62 and Q63 are received, the data modulation unit 36 generates a blinking clock pulse of Φ, Hz. The output signal Q65 is used to supply a signal to display the daily alarm mark. The signals B and OSUP are also fed to the data modulation unit 36. The signal B is a synchronizing signal and is used to generate the 1 Hz flash signal. The OSUP signal is used to modulate the display of the time and date. The signal F supplied by the alarm unit 34 is used to generate a signal to flash the alarm coincidence signal. The data modulation unit 36 also responds to the SD, SK and tiLan signals and generates an output signal D ₀ to provide the alarm time, date and current time indications.

The input signals SUl and SU2 are used as input data for the standard timing system and are supplied to the components which have been selected by various combinations of input signals SH, SM, SK, SD and SUO or SUT which are supplied by the external control elements 38, such as it is explained below. The symbol SUO represents an input terminal for unlocking the input data, and SUT represents an input terminal in a timing device for unlocking the input data.

The signals SH, SM, SK, SD, SUO and SUT are fed to the control unit 30 and are used to perform the following functions:

a. Selection of the addresses which are to be unlocked by combined signals from the input signals SH, SM, SD and SK;

b. Unlocking of the selected addresses by the input signals SUO or SUT;

c. Supply of the input data SUl or SUl in the unlocked addresses, so that the change of the current time is made possible.

At this point it should be noted that the circuit is constructed in such a way that it is possible to automatically set the seconds display to zero, regardless of the unlocking signal. The circuit is also constructed in such a way that the previously set digit is prevented from being changed to a higher order digit by the signal X during the time setting.
The alarm unit 34 will be described below. The alarm time data, which is temporary

so required, i.e. intermediate data, or data required daily, are stored in the four digits of the shift register ring 58, which are generated by the digit pulses D ^ to D υ as a function of the signals SH, SM, SK ₁ SD, SUO ₁ SUT, SU> and SU _{1 are} set. The alarm unit 34 responds to the inverted signal UL at ur-d is held in an unlocked position so that the alarm time can be set. During the setting of the alarm time, the alarm unit 34 is prevented from supplying a clear signal to the timing register 32. If the alarm time coincides with the current time while setting the alarm time, the alarm will not sound. Further, the alarm unit 34 is arranged so that even if the current time coincides with the alarm time during setting of the current time, a clear signal for clearing the alarm time is not generated.
The coincidence of the time data stored in the shift register ring 58 and the alarm time data is determined by a comparison between a predetermined time interval between the times D _b and D ₉ T ^ an output signal, which is represented by DATA60 , which is the input signal to the 60th flip-flop of the Shift register ring 58, and an output signal Q29, which corresponds to the output of the 29th flip-flop, equal to the data represented by DATAIi. If such a coincidence is detected, the alarm unit 34 sends an alarm signal ALS to an alarm device 78, which via a predetermined

nes time interval is supplied with energy, ie over one minute. During this time interval, the alarm unit 34 sends a signal F to the data modulation unit 36, whereupon the unit 36 generates an output signal in order to cause all display elements to flash. If the user acknowledges the alarm and actuates a switch 80, a stop signal STP is generated and fed to the alarm unit 34 so that the up-

flashing or the flashing of the display and the alarm tone are switched off. Such a shutdown operation can also be carried out by one or the other of the input signals SUi or SUl , which are supplied by the control elements 38.

It should be noted that the shift register 58 is arranged to store temporary alarm data and daily alarm data. If the temporary alarm data are stored in the shift register ring 58, a display of the alarm time is triggered only once and is switched off by the stop signal STP , or the switching off is carried out by the signals S1 and 52, while the alarm unit 34 supplies a clear signal to the shift register ring 58 at the same time, so that the data stored therein will be deleted. If the daily alarm data is stored in the shift register ring 58, the clear signal is not generated by the alarm unit 34, the alarm time data stored in the shift register ring 58 can also be cleared by setting the alarm time to zero under the control of external control elements 38. The status "0" of the alarm time is determined by the data detector 74, which then generates a signal ATO , which indicates that the alarm time is in the status "0". This signal is fed to the alarm unit 34 so that a clear signal is generated. In this case the display device only shows the zero time of the hour digits. A flexible circuit is shown at 82, which serves to provide additional functions for the electronic watch than can be achieved by means of the external control elements. For example, the flexible circuit 82 has a flip-flop circuit which is designed in such a way that frequency division is carried out, and it generates a signal LY (ie “leap year”) which is fed to the data sampling unit 70.

FIG. 5 shows an exemplary embodiment of the time normal signal oscillator 14 and the switching elements connected therewith. According to the illustration, the time normal signal oscillator 14 has a quartz oscillator 48 which oscillates at a frequency of 32,768 Hz, furthermore has a CMOS inverter 90, a resistor 92 which has a resistance of approximately 30 mega-ohms , and a resistor 94 having a resistance of about 500 kilo-ohms and operated to maintain the output impedance at a substantially constant level so as not to impart a distorted waveform to the crystal oscillator 48. Furthermore, a capacitor 94 with a capacitance of approximately 25 pF and a trimming capacitor 96 with a capacitance of approximately 20 pF are provided. The quartz oscillator element 48 has a resonance frequency of approximately 32,768 Hz. Furthermore, two exclusive OR gates 50 and 52 are present. The exclusive OR gate 50 is used to generate a signal which has a frequency which is equal to the sum of the frequencies of the two signals Φ _Ν and Φ _ο which are fed to corresponding inputs. Since the output frequency is not changed by the logical negative of the OR gate 50, an anti-coincidence gate or an identity gate can also be used to serve the same purpose.

The F i g. 6 shows the waveforms of the input signals Φ _Ν and Φ _ο and the output signal Φ _ζ . From FIG. 6 it can be seen that the output signal Φ _{ζ is} achieved when the signals Φ _ο and Φ _{Ν are fed to the input terminals of} the exclusive OR gate 50, and it has a frequency which is equal to the sum of the frequencies of the signals Φ _ο and Φ _Ν is.

FIGS. 7A and 7B show an example! a detailed circuit of the synthesizer 16 according to FIG. 4A. According to the illustration, the output signal Φ _ζ from the frequency summing gate 50 is fed to a frequency divider 100 , which halves the frequency and forms part of the first time pulse generator 54, it also having a flip-flop circuit 102 and AND gates 104 and 106 . The frequency divider 100, which halves the frequency, thus generates clock pulses Φ and Φ ₂ which are fed to the timing register 32, a data modulation unit 36, a display driver 20, etc. also being present, which are used for the purposes described below. The clock pulse Φ ₂ is also fed to a frequency divider 108 which divides the frequency by four and has four cascaded shift registers 110, 112, 114 and 116 which are connected to the logic gate 118 to form a loop. The frequency divider 108, which divides the frequency by four, generates timing pulses 71, 7Λ, 7} and 7g, which in FIG. 8 are shown. Each of these timing pulses has a repetition frequency of four times the period of the clock pulse Φ ₂ and a pulse width equal to the period of the clock pulse Φ ₂ . These timing pulses are fed to the second timing pulse generator 56 which generates various combined timing signals. The timing pulse Ti is also fed to the data modulation unit 36 for purposes discussed below. The timing pulse T \ is fed to a frequency divider 120 which divides the frequency by 16 and has eight static locking circuits 122 to 136 and a flip-flop circuit 138 . The flip-flop circuit 138 is bistable, and its output signals Q13S are set up and released synchronously with the timing pulse 7Ί, and it has twice the period of the timing pulse T \. The output of the flip-flop circuit 138 has the same waveform as a clock pulse Φ ^ \ · The relationship between the signals Q138 and Φ _υη is from the waveforms of FIGS. 9 shows the waveforms of the various timing signals. AND gates 140 and 142 are connected to the flip-flop circuit 138 and generate a clock pulse Φ _α in response to the unlocking of the clock pulse Φ _υσι and a clock pulse Φι in response to the downward control of the clock pulse Φ _{υ €} \ according to FIG. 10 .

The signals Φ _α , Φ ₆ and T ₁ are linked by the following relationships:

Φα + Φ _ύ - T _x (corresponding ι to the low level »L«) Φα ■ Φο = O Φα ■ Ά = φ. Φο ■ Ά = φ *

The reason that the clock pulses Φ _α and Φ i are generated is to simplify the divider 120 to produce the 16 digit pulses D ₁ through D ₁₆ . 7A and 7B, the 74 divider 108, which generates the timing pulses T _x , T ₂ , T ₄ and 7 " ₈ in response to the clock pulse Φ ₂ , consists of the four data flip-flops 110, 112, 114 and 116, which triggered by the clock pulse Φ _2. If the divider 120 (1/10) - is constructed using similar components as are used for the divider 108 (1/4), it is necessary to have 16 main-minor Provide data flip-flop circuits to generate the 16 digit pulses, but in the example shown in Figures 7A and 7B, divider 120 (1/16) is made up of only eight latches which make up the four main-sub-flip -Flop circuits correspond.
The data input signal is entered into latch 122 in response to the up clock pulse Φ _α

^{n is} read in, so that an output signal Q122 is generated. The latch circuit 122 is latched when the clock pulse Φ _{α is} at a low level. Until the clock pulse Φ _α goes high, the latch circuit 124 responds to the clock pulse Φ ₄ and it is fed to the output 122 as a data input and it is latched. In this way, the data go through successive latch circuits to pass, and each time the data Hindu by a latch circuit rchge hen, will n to delay in phase by one period of the timing pulse T ₁ The outputs Q 124 and Q 132 are by a mode -Locking gate 14 4 hind , the output signal of which is fed to a NOR gate 146, which is also fed to the output Q128. In this way, the latch circuits 122 to 136 generate output signals Q122 to Q136 with a pulse repetition rate of 16 T) and a duty cycle of 50%. The digit pulses D _t to D ₁₆ are generated depending on the output signals of the respective latch circuits 122 to 13 6. For example, the digit pulse Z) is generated by a gate 148 in response to the inverted signals Q122 and Q136. Similarly Wei se the Zißernimpuls £> _is: generated in response to the inverted signal and the signal Q124 Q122 through a gate 150th The other digit pulses D ₃ to Dj ₆ are generated in a similar manner and are therefore not explained in detail.

Fig. 8 shows the relationship between the clock pulses Φ _ζ , Φ ₂ and P _x on the one hand and the timing _{pulses Π, T 2} , Tt and T ₈ on the other hand, which are generated by the divider 108 of FIG. 6A, which divides by four. 9 illustrates the explanation of the waveforms of the timing pulses Γι to 7 * ₈ , the digit pulses D ₁ to D ₁₆ , the data signal DATA and the clock pulses Φ _{υ € Χ} and Φυα- I ⁿ of FIG. 9, P shows the content of the data which are illustrated by the digit pulses D] to D i ₆ . The relationship between

3 "the digit pulses and the data results as follows:

D ₁ : 1/256 second word
D ₂ : 1/16 second word

D ₃ : 1 second word

D) ₆ : Alarm time marker number

According to the phases of these digits, the digits are divided into four groups. The high level of the pulse 7 "corresponds to" 1 "and the low level corresponds to" 0 ". The high levels of the pulses T ₂ , T ₄ and 7i correspond to the weights 2, 4 and 8, respectively. From this it can be seen that the The data T shown in Figure 9 indicates that the standard timing system provides a partial display showing the correct time of 2: 32 PM, 33 seconds with 1/16 second plus 8 / 256 seconds,

Sun July 24th delivers with the daily alarm time set at 11:59 AM. The designations AM and PM correspond to the usual information in the Anglo-Saxon time system "ante meridiem" and "post meridiem", ie "morning" and "afternoon". The clock pulses Φ _χ , Φ ₂ , the timing pulses 7Ί, T ₂ , T ₄ and T ₈ and the digit pulses Di are fed to the second time pulse generator 56, from which various combined time signals are generated. In order to simplify the drawing, a detailed circuit arrangement of the second time pulse generator 56 is not shown.

The F i g. 11A and 11B each show a circuit diagram showing an example of a timing register 32

As illustrated above, the timing register includes a shift register ring 58 and a data sampling unit 70 having a carry request detector 72 and a data detector 74.

The shift register ring 58 contains a 60-bit shift register 60, the output Q _{x of which is} connected to a four-bit shift register 64 via an adder circuit 62. The output Q61 from the shift register 58 is connected to one input of an AND gate 66, and the output of this gate is connected to an input of an OR gate circuit 68. The other input of AND gate 66 is connected to the output of an OR gate 162 through an inverter 160 so that when the output from OR gate 162 is "H", that output through the inverter 160 is inverted so that he

for the low income! "L" has. As a result, the output of AND gate 66 is "L". Of the The output of the OR gate 68 is fed back to the input of the shift register 60 with data D60, which are also fed to the modulation unit and the alarm unit, for different purposes to meet, as it is explained in more detail below.

The shift registers 60 and 64 are arranged and designed in such a way that they write input data into a stage when the clock pulse Φ, is at the "H" level, and that they read out data from the stage when Φ ₂ = "Η"

The shift register 64 includes flip-flops 64a, 646, 64c and 64d which store data when the clock pulse Φ is high, and their stored contents are read out in response to the build-up portion of the clock pulse Φ _2. The clock pulses Φι and Φ ₂ have a frequency of 2 ¹⁴ Hz, so that writing and reading processes are carried out 16,384 times per second. Accordingly, output signals from the flip-flops are sequentially shifted in a corresponding manner.

According to the above explanations, the shift register ring 58 has an adder circuit 62, so that the arrangement consequently serves as a counter. The adding circuit 62 has an adding stage 62α, a shift register and a gate 62c. The adder 62α has an input a, to which the data from the shift register 60 are fed, and also an input./? Which receives an output signal from the gate 62c. The adder stage 62α has an output S which is connected to an input D of the flip-flop 64a ″, and an output C which is connected to the input of the shift register 626.

The gate 62c of the adding circuit 62 is supplied with a signal X including a carry signal, a timing setting signal and a time unit signal D \ T _V. The 64-bit shift register ring 58 sequentially transfers the data in response to the clock pulse at a frequency of 256 x 16 x 4 = 384 Hz, and the initially applied signal "1" appears at the input α of the adder 62α with a time control DT every 1/256 seconds. The carry signal C passes through the shift register 626, which delays it by one bit, so that a delayed signal D ₂ T _{2 is} generated which is fed to the input ^ of the adder 62a. Output signals appearing at the outputs S and C are expressed by the following equations:

25th

5 = a-ß, C = aß + aß

In order to avoid confusion and to provide a better understanding of the invention, the following are provided Definition and description of the terms given:

i. Registration and readout:

According to the description above, the latching of data is carried out in the master stage of a master-slave flip-flop referred to as registered, and referred to as readout of this data if the data is on Output of the slave stage appear.

35

ii. Shift register:

A shift register made up of a plurality of master-slave flip-flops also becomes simple referred to as a "shift register". The mere term "register" is not referring to a shift register limited, but also includes a system which is able to provide information or a part to register information.

iii. Time control:

Signals appearing at different output terminals of the respective shift registers are different from each other, and such output signals are generated in response to the clock pulses. Since the clock pulses have a constant frequency, it is possible to view the output signals of the shift registers as a function of time. The output of shift register 60 is represented by a symbol "DATA" {x, t) which is a function of position x and time t . The time / is also referred to as "time control". The output data of the shift register ring 58 are output periodically in pulsed form and then fed to the display driver or the additional system. At this point it is incorrect to say that the signal is a function of time, but rather it should be denoted by the number of clock pulses. In the present specification, however, the term "timing" is used in the usual manner. The time control signals D iT _t and D \ 7g Φ \ should also be able to be designated by the expression “time control”.

iv. Data:

Where information or data stored in the shift register ring 58 is read out in response to the clock pulses from any output terminal of the shift register, the read out information is referred to herein as "data". The number 60 in the designation of the output Z) / (7M60 indicates the number of outputs of the flip-flops that form the shift register ring. Sometimes DATAix ■ :) is abbreviated as "DATA x" or as "t DATA", with that on the designation DATA following * means that the data are to be fed to the x-th data input of the shift register. The symbol D ₁₆ DATA also means the content of the data in the number Z) ₁₆ . Hence, it is convenient to express this as D _i6 DATA 60. The xth output of the shift register is referred to as Qx . DATA60 thus corresponds to Q59. In other words, the 59th output of the shift register is connected to the bareest data input terminal of the shift register.

The counting mode is explained below using a word 1 / 256th of a second as an example.

If the output signal &, which is fed to the input α of the adder 62α, is a binary "1" and the binary signal "1" is fed to the input /, the 5-output Q6S is a binary "0" and the C output generates a binary "1" as an output signal. The shift register 62b writes in the binary "1" and reads out the signal "1" when the clock pulses are at the high level "H", and it supplies an output signal which is delayed by one bit via the gate 62c the input of the adder 62α. At this time, addition and carry are carried out according to the following relationships:

oj5 + qß = S, a-ß = C

For example, if 4 bits of the Di data, which are designated by the timing of D _t and are sensed through the shift register ring 58, are binary output signals "0" and if the output signals are the binary digits "0", "0", "0""," 0 "along the time axis, the information is added by the adding circuit 62 at the time of D \ T \ . As a result, the Dj data becomes the binary digits "1", "0", "0", "0". After 1/256 seconds, when the next piece of information is added to the time of Di T ₁ , the relationships a " 1 and / = 1 are retained, so that a: binary digit" 0 "is supplied as output signal at output S. To During this time a relationship a · / - 1 also applies. A binary signal "1" is delayed by one bit by the shift register 626 and fed to the input / of the adder 62α at the time of Dr. At this time, the relationships a - apply. "0" and / = "1" in such a way that the output signal 5 generates a binary output signal "1." At the same time, the relationship a · = 0 applies in such a way that the output C becomes the binary digit "0" the D, data, which was passed through the adder circuit 62, to the binary digits "0", "1", "0", "0". In this way, the content of the Dp data changes from "1" to "1"" 0 «» 0 «,» 0 «» 0 «» 1 «» 0 «,» 1 «» 0 «» 1 «» 0 «,» 0 «» 1 «» 1 «» 0 «... in chronological order every 1/256 of a second In other words, the four bits of the D 1 data change their binary states between "0" and "1" every 1/256 see, 2/256 see, 4/256 see and 8/256 see, each in such a way that 1/256 second digits are displayed.

When the DpData has reached the binary state "1", "1", "1", "1", if the information was added to the time of D \ T \ , the binary state is changed to "0", "0" , "0", "0". The D data, which are designated by the time of Di , are converted from the binary states "0",>"0","0","0" to the binary states "1", "0", "0" , "0" is transferred at the time of D ₂ 71. The four bits of D ₂ data are changed at 1/16 see, 2/16 see, 4/16 see and 8/16 see, respectively, so that they are 1 / Represent 16-second digits.

In this manner, the shift register ring 58 is enabled to serve as a 4-bit, 16-digit counter in addition to its function of storing data. For example, the data of the _{D 3 data denoted by the time of D 3} Ti changes every second and represents a one-second signal.

As is known per se, a clock is counted as follows: The digit units of a second, one minute and one day are based on the maximum values for the "ones" and "tens" digits. Seconds and minutes require a range from 0 to 9 in the "ones" place and from 0 to 6 in the "tens" place, Hours and months a range from 0 to 9 in the "ones" place and from 0 to 2 in the "tens" - Digit, and days of the week require the range from 1 to 7. Thus, the shift register the function a clock, it must be arranged in> 3 way that the digits of the corresponding counts be brought to the corresponding counting units.

Whether or not a transfer should be carried out depends on the nature of the information content. A transfer takes place in the following way:
For example, the four-bit information of D ₃ data represents the weight of 1/1 second, 2/1 second, 4/1 second and 8/1 second of the second unit, respectively, so that when the D ₃ data are in the binary state »0« »1« »0« »1«, 10 seconds are displayed. In this case it is necessary to set the four bits of Dj data to "0" and use the carry for the 10-second digit. For example, if the four bits of D ₄ data are "0""0""1""0", it is necessary to increase by carrying to "1""0""1""0". In other words, the process of carrying over is carried out in the following way:

(a) simultaneous determination of the information of four bits of the same digit,

(b) sensing whether the information is a prescribed one or not,

(c) Conversion of all four bits of the data into the binary state "0" and

(d) Add a "1" to the following digit, which is delayed by one bit.

In the embodiment according to the invention, as shown in FIGS. 11A and HB, the Output data Q62, Q63, Q64 and Q65 are sampled by a data sampling unit 70 and a carry operation is performed executed depending on the scanned contents.

According to the above embodiments, the data sampling unit 70 has a carry request detector 72 and has a data detector 74, which generates various output signals necessary for this are to operate the control unit according to the invention, wherein it also scans the internal states of the system.

The carry request detector 72 has matrix gate circuits 166, 168, 170, 172 and 174 which are connected to the inputs of the flip-flops 64a, 64b, 64c and 64d of the shift register 64, respectively. The matrix gate circuit 166 responds to the digit pulse D, s and determines the content of the data which is stored in the shift register 64 so that it serves as a decoder to effect a carryover of the hour, month, etc. of 12 digits. More specifically, the gate circuit 166 detects the high level of the input D ₁₅ , ie,

Dis ■ ((Q65 · QfA · Q62) + {ß65 · Q64 ■ ß63)) = »Η«,

which is read out by the shift register 64 at the time of the timing _{pulse Γ 8} Φι and is delayed by one bit. The delayed signal is derived as an output signal W ₁ which has a width which corresponds to a bit between the beginning of the next digital pulse D ₁₆ , which occurs synchronously with the clock pulse Φ ₂ , and the falling part of the digit pulse D ₁₆ . The output signal W ₁ represents the counts 13, 14 and 15 of the hour digits of the alarm time, and it is fed via the OR gate 162 and the inverter 160 to the input of the AND gate 66, through which the hour digit of the alarm time is in the state » 0 «is brought. The alarm time is represented by the 12 digits, which run from (0 to 12). In this way, the output signal W ₁ is used to bring the second digit of the alarm time to the "0" state.

The Matnx gate circuit 168 is used to determine the count "0" of the 10-day digit in response to the digit in the PuIsZ) _n , and it also determines a month digit as well as the counts 13, 14 and 15 of the hour digit of the alarm time, in response to the digit pulses Z) _n and D ₇ . The gate circuit 168 also determines the count "7" of the day of the week (1-7) of the day of the week digits when timing the pulse Τ% Φ \ in response to the digit pulse D ₉ . The count "0" for the one-day digit is determined by the timing of the pulse Γ ₈ Φι in response to the digit pulse D _n. In other words, such a determination is made by the timing pulse T _g <Pi if the following relationship is applicable:

D ₁₁ · Q65 · Q64 · 063 · Q62 = »H«

and an output signal W ₂ is generated. This output signal W ₂ is generated when the counts "0", "13", "14" or "15" one of the hour digits of the current time, a month digit, a weekday digit are determined. The output signal W ₂ causes its own digit to be deleted and a "1" to be added to its own digit, and it does not contribute to the carryover for the next digit.

The output signal W ₂ is fed to the AND gate 66 via an OR gate 162 and the inverter 160, so that its own digit is thereby deleted. At the same time, the output signal W _{2 is} fed via an OR gate 182 to an input of an AND gate 184, the output of which is fed via an OR gate 186 of the circuit 890 to the OR gate 68 as output Z. The output signal Z is fed to the OR gate 68, which adds a 1 to its own digit. Such an addition also causes the day digit to start counting from "1". Since the transfer of the manat digits is not carried out by the shift register ring 158, the output signal W _{2 is} fed to an AND gate 188, which generates a logical product of W ₂ · D _n · Φ _χ as output signal NY , which is sent to a flexible circuit 82 for control of a leap year is supplied.

The matrix gate circuit 170 is used to determine the count "4" of the 10-day digits, and it also determines the count "6" of the 10-minute digit, the 10-second digit, and the 10-minute digit the alarm time, in response to the digit pulses D ₁₁ , D ₄ , D ₆ and D ₁₄ . The gate circuit 170 also determines the count "10" of the one-second digit, the one-minute digit, the one-day digit and the one-minute digit of the alarm time, in each case in response to the digit pulses D3, D5, D ₁₀ and D ^, and it determines the count "2" of the PM marker digit in response to the digit pulse D ₅ . An output signal W ₃ is thus generated which is used to delete its own digits and carry over to the next

ι Ut

To deliver digit. The output signal W ₃ is fed through the OR gate 162 to the inverter 160 to cause its own digits to be erased. At the same time, the output signal W _{3 is} fed to the control unit, which generates an output signal X which is fed to the adder circuit 62 of the shift register ring 58, so that a carry to the next digit is brought about. ■

The output signal W ₃ from the matrix circuit 170 is fed to an input of an AND gate 190, which supplies _{an output signal in synchronism with the digit pulse D 9.} This output signal is fed to an OR gate 192. The output of this OR gate 192 is delayed by one digit by a shift register 180, and an output signal W _{4 is} generated, so that this output signal W ₄ is used to serve as a carry for the next digit. In addition to the PM marking number as a carry-over to the one-day number, the weekday number is also treated accordingly.

The matrix gate circuit 172 stores the count "11" of the hour digit of the alarm time in one storage cycle in response to the digit pulse Di ₅ . The matrix gate circuit 172 detects the change between the count "11" and the count "12" and generates an output signal which is fed to the OR gate 192 to produce the output signal Jf ₄ which is used as a carry for the next PM- Digit is used.

When a second zero control signal S _{0 is} supplied to the matrix gate circuit 174, namely when the second digit is on the order of 30 sec, 40 sec and 50 sec, a carry signal for carrying out a carry to the minute digit of the current time and a Carry signal for carrying out a carry to the PM digit of the current time delayed by one digit in each case by the shift register 180 in order _{to form the output signal W 4} and in this way activate a carry to the next digit.

The matrix gate circuit 176 determines long and short months in order to generate an output signal W ₅ for controlling the one-day digit, the ten-day digit and the month digit. Furthermore, the matrix gate circuit 176 is connected to latching circuits 194, 196, 198 and 204, which determine and store the data relating to February, 20 days, 30 days and short months (February, April, June, September and November). The conditions that are detected in order to generate a word carryover and to change the display for the first day of the following month are:

(i) February 29th in a normal year;

(ii) February 30th, or counts higher than 30;

(iii) 31st day of the short months;

(iv) 32nd day and above for the long and short months.

The results of items i, ii, iii and iv above are summed to produce an output signal W ₅ . The signal W _s is used as a carry signal to form a carry to the next digit after the own digit has been deleted (one-day digit). In the case of the month of February, the signal W _s is used to form a carryover to the 10-day digit, so that the 31st February turns into the 41st February

is changing. In this case, the 10-day digit is immediately reset to zero and a carry signal is given the month digit, thus indicating the first of March. In the case of a short and of a long month, the result is the 41st day, so that "1" becomes the month digit by carrying over the 10-day digit is added and in this way the 10-day digit is reset to zero. In February a carryover is carried out on the 28th day. No time adjustment is required under normal conditions and the display is such that March 1st is displayed after February 28th. However, if a If the switch is operated to indicate February 29th after February 28th, a Überirag blocking signal will be activated which causes the carryover to March 1st. Accordingly, February 29th is indicated, and when it reaches February 30th, the display will be changed to March 1st, after Scan mode of (ii). This precaution is used to avoid the manual setting of February 29th in a leap year without the need for an additional counter for a leap year.

A data detector 74 is formed by a matrix gate circuit 202 which determines the count "0" in each case in a digit for 1/16 see, "ones" and "tens" of a second, and "ones" of a minute, in response on the digit pulses D \, D ₂ , Z) ₃ and Z) ₄ to generate an output signal. This output signal is delayed by one bit by the shift register 180, so that a signal [B] is generated which is used as a time synchronizing signal. The signal [B] also serves as a reset signal of a timer circuit and a logic level setting circuit of the control unit, whereby the logic level of the input terminals connected to the switches is controlled. Furthermore, the signal [B] is used to generate intermittently modulated output signals in the modulation unit. The logical product AZ) ₅ of the output signal [B] and the digit pulse D ₅ delivers a one-minute signal, and the logical product BZ) _{4 of} the output signal [B] and the digit pulse Z) ₄ delivers a 10-second signal .

In response to the digit pulse Z) _n, the matrix gate circuit 202 determines the count “0” of the 10-day digit and generates an output signal (OSUP) to suppress the count “0” of the 10-day digit. The display of the “0” count of the 10-second digit and the 10-minute digit is not critical, but the display of the “0” count of the 10-day digit makes a strange impression on the user. It is therefore desirable to suppress "0" when the 10-day digit is displayed. Of course, »0« is not suppressed when the 10-second digits are displayed. Incorrect identification can also be prevented by suppressing "0" in the 10-minute digit. For this reason the circuit is arranged in such a way that the count "0" is only suppressed for the 10-day digit as an example. It should be noted, however, that various modifications in the circuit arrangement are possible in order to achieve the

■ Suppress »ο counting» 0 «in any desired digit. The signal (OSUP) is fed to the data modulation unit in order to modulate the data in such a way that the count "0" of the 10-day digit is not displayed.

The matrix gate circuit 202 determines the "0" count of the 1/256 second digit in response to the output Q62 of the flip-flop 646 of the shift register 64 and generates an output signal. This output signal is delayed by one bit by the shift register 205, which generates an output signal (CONTA).

Furthermore, the matrix Gattcrschaltuns 292 connected to a latch circuit 204 that the count "0" of the hour digit of an alarm time in response to the timing pulse D _iS Tg0i determined, and generates an output signal (ATO), which indicates that the alarm time is not set. The matrix gate circuit 206 detects a signal which has a weight of 2 ^{2 of} the 1/256 second digit, ie the output signal (764 of the flip-flop Md. The output signal QM is activated by a latch circuit 207 at a timing of the timing pulse Ώ _Χ Τ% Φ ι read out, and a 32 Hz signal is generated for the driver display elements.

In the F i g. 11A and 11B show an input signal LY which indicates a leap year and which is supplied from the external control element of a switch. By operating the switch, a carry-over blocking signal U is generated by the control unit and used to control the signal for the 28th February. An AT-ERASE signal is fed to the OR gate 162 from the alarm unit if the current time and the alarm time coincide with one another while the alarm time is temporarily set. The ERASE signal is used to clear the alarm time data through gate 66. During this deletion process, only the hour digit is deleted and all minute digits, hour digits and PM digits are deleted. In this embodiment, the circuit is so constructed that the alarm time data is cleared in the normally displayed state.

Table 1 shows the relationship between the digit pulses D ₁ to Z), ₅ and the output _{signals W 1} bi; W ₅ from the data sampling unit 72. In Table I, the symbol ⁺ means that when a carry is made to the next digit, a carry is made from the day digit to the 10 day digit and the carry is made from the day Digits for the month digits at the end of the month. In this case, the own digit is set to "1" after the carryover to the next digit has been carried out. The ⁺⁺ symbol means that a day-of-the-week digit was exceeded to a one-day digit. The ⁺⁺⁺ symbol means that the transfer between the counts "11" and "12" of the hour digit has been determined and a transfer to the next

60 194 count
Min. Max. + W ₅ + S ₀ + Digit, to
which one
transfer
made
became Output Y
own
Digit 0 Exit Z
own
Digit +1 Output X
Carry over to
next
Digit DATA-CL + [SUi) exit 5 ■;.; 0 15 2. Put "1" in your own number: D ₂ - not
necessary not
necessary - 10 25th 0 15 Z = (W ₂ + W ₅ ) T ₁ + Tuesday not
necessary the same the same - 0 9 ■ DATA-IN Z) ₄ necessary the same necessary W ₃ 15th Digit or to the next PM marker digit. The symbol "-" means that the output
signals W are not generated. 0 5 3. Carry over to the next digit: D ₅ the same the same the same D ₁ + SUD T ₁ W ₃ Table I. 0 9 X - [(UT ₅ W ₃ + W ₄ D ₆ the same the same the same W ₃ Data Detected
Digit 0 5 D ₁ the same the same the same W ₃ 20 I. 1/256 sec D _x 1 12 Tuesday the same necessary necessary ⁺⁺⁺ W ₂ , W ₄ ⁺⁺⁺ 1/16 sec D ₁ 0 1 D ₉ , Z) ₁₀ the same not
necessary necessary ⁺⁺ W ₃ 1 sec D ₁ 1 7 no
Digit the same necessary not
necessary W ₂ 10 sec Z) ₄ 0 9 D _n the same necessary* necessary ⁺ W ₃ 1 min D _s 0 3 D ₁₂ the same not
necessary necessary W ₃ 30th 10 min D ₆ 1 12 (NY) the same necessary not
necessary W ₂ Hour D ₁ 0 9 D ₁₄ the same not
necessary necessary W ₃ 35 PM Z) ₈ 0 5 no necessary not
necessary not
necessary W ₃ Week- D ₉
Day 0 12 Z), 6 the same the same necessary W ₁ 40 1 day D _t0 0 1 no the same the same not
necessary - 10 days D _after 1 28-31 Dn the same the same necessary W ₅ Month D _after Generate the Signals Y ,, Z and X can be summarized as follows will: 45 AT-I min D _n 1. Deletion of previous data: AT-IO min Z) ₁₄ γ = W ₃ + W ₁ + W D ₁ (T ₂ + T ₄ ) + ERASE + 50 AT hour Z) ₁₅ AT-PM Z) ₁₆ 55 I. _Date- D i0, D _n ,
number Z) ₁₂ The conditions for + W ₅ ) - (carry lock) + (HOLD) ■ The F i g. 13 shows an example of the flexible circuit 82 which is formed by a flip-flop counter,
which serves to provide a more flexible or versatile standard timepiece according to the invention
fen. An output of a gate 206 is normally held high "H", but will
momentarily brought to a low level "L", namely 8 times per second. During these intervals with
If the level is low, flip-flops 208 and 210 are preferably set in such a way that FB = "L" and FC =
"0". When the signal F _R is brought to the high level "H", by grounding, the gate 206 is
13th 60 fe 65 \\

"L" Fc ⁼ "L" »Η« F _c - "L" "L" Fc = "H" »Η« Fc- "H"

short-circuited during a short time interval in which the signal T _R goes to a low level "L", ie when the switch is released. However, since the short-circuit period is short, it is possible to limit the average current to be less than 100 nA. Under the short-circuit conditions, ie Fr = "H", the flip-flops 208 and 210 carry out counting operations. Assuming that F _A = "L" and F _B =

⁵ »L« the following relationships apply when counting »0«:

: '; ■ when counting 0 F ₈ =

> when counting 1 F _e =
when counting 2 F ₈ =

^ln at count 3 F _B =

i ν ^The terminal F _R is used as a signal source for a signal of 8 Hz. When the terminal F _{R is} on the high

] | Level "H" is grounded and the output signal NY is fed to terminal F _A , it is possible to have a leap year

| i to be taken into account by a 4-digit counter, which is formed by the flip-flops 208 and 210. Even though

§ ^l5 the consideration or setting of the leap year is somewhat complex, it is possible to make a setting

a by simply confirming the carryover on February 29th and continuing to effect that

i | December 31st is scanned to generate a New Year signal NY.

4, FIG. 12 shows a preferred embodiment of an electrical circuit for the control unit 30. The

; Control unit 30 is provided with a plurality of switch input terminals SH, SM, SK, SD, SUO. SUT. 5i /, and SU ₂

J ²⁰ , and corresponding input signals are fed to these terminals in order to

; fe ^ne to generate control signals to control the timing register 32 and the data modulation unit 36 to

% taxes. SUO and SUT are input connections for electrical “unlocking” that control unit 30

ι * j make ready for operation, so that switches SH, SK, SM and SD allow the setting of new time data to the

, | set the correct time, SU ₁ and SU ₂ supply the data inputs 5 and S ₂ , respectively. The input terminals SH, SM.

% ²⁵ SK and SD are used to control the storage locations for the data to be transferred. This one

U output terminals are connected to output terminals of a circuit for setting a logic level,

";;, which is designated by 214 and is designed in such a way that the input terminals are at a logic level

I "L" must be brought. The input terminals SH directs the data input signal 51 to the digit 12 or 13,

-if ^wen " SH = " H ". If SM = " H ", the data input signal 51 becomes the 60 digit or 28-, 29-, 30- respectively

% 30 and 31-digit led. If SV = "H", the data input signal 51 of the data, month and day of the week

I number added. If Sp = "H", the data input signal 51 will display the second, minute and hour digits.

, $. remotely supplied, and the PM flag number of the current time is supplied. SUO and SUT provide

»Input terminals of an unlocking switch device, which set the time on the clock

ΐ? enables, and SUl and SU2 represent data input terminals, which are used to control the data input

fg 35 gnale S, and S ₂ each to be delivered.

Ii Table II shows an example of the relationship between the modes of operation of switches SM, SH, SK and SD,

i | and it illustrates the data setting modes of the watch as well as the display modes. For example, it recognizes

In the "Time setting" section, you can tell that a combination of SH and SK, if they have "H" levels, is a

| {causes the current hour display to flash and this data to be updated. (The table

I 40 is followed by an explanation of symbols).

Table II

Setting mode

counter

Locked mode

TIME ADJUSTMENT

DAY
DATE
DISPLAY
GE

SM

SH

SK

SD

UL

0I0I0I0I0I0I0I0I 00II00II00II00II OOOOIIIIOOOOIIII IIIIOOOOOOOOIIII

oooooooooooooooo

0I0IOI0I0IOIO101 OOIIOOIIOOIIOOII OOOOOOOOIIIIIIII IIIIOOOOOOOOIIII I I I I I I I I I I I I I I I I I

SU,

SU ₂

I I

I I

I I

2.2SEC SEC

MIN

DAY

DATE MONTH MIN / AT H / AT MPM MDD

MALS MDLY

(MULTI-ALARM)

Cl

Cl

Explanation: Normal time display DATE Date of month STANDARD either 1 or 0 MONTH Month of year + second zero setting M / AT Minute of the alarm time So counter HAS Hour of the alarm time Sw Transfer locked MK / AT Marking the alarm time Cl renovation INH Input blocked U Rlitrpn Ό * snhalH Her 73h1 «r οι, ΓΝιιΙΙ"., noil · iol η second the counting is done from zero SEC minute I. high level MIN hour 0 low level H Day of the week DAY

According to the above, each of the input terminals SH, SM, SK, SD, SUO, SUl and SUl is connected to the circuit 214 for setting the logic level, which sets the input terminal of the switch to a low level "L" when the switch is open is. According to FIG. 15, the circuit 214 for setting a logic level has an inverter 214a and a NOR gate 2146, which are connected in the form of a ring. The input of inverter 214α is connected to the output of NOR gate 2146 and the input terminal, while the input of NOR gate 2146 is connected to receive the output of inverter 214α and a timing pulse β · Di · 7g · Q62. In other words, this circuit has a memory circuit which has a positive DC voltage feedback circuit and a terminal for input

15th

setting of a predetermined logical level. This terminal is connected in such a way that it receives an intermittent pulse which has a small width in order to set the memory circuit to the particular logic state. In this example, the special logic state corresponds to the low level and a pulse BD ₂ T ₁ , which has a width of 64 osec, is applied to the terminal every 1/16 seconds, so that the low level "L" is supplied. The low output impedance at the low level is about 100 kilo-ohms in the C / MOS circuit shown. It is possible to easily set the input terminal to the high level "H". When the terminal is high, the output of the memory circuit is short-circuited each time the pulse BD ₂ T% is brought to its high level. However, a corresponding current flow is extremely small and does not cause any serious trouble. Thus, an input terminal for the clock is designed in such a way that it has an average power consumption which corresponds to 100 kilo-ohms x (1/16 msec / 64 u.sec) and a low impedance of 100 kilo-ohms. This circuit proves advantageous in suppressing noise which has frequencies greater than 16 Hz. The switch input terminals SK, SD, SUO, SUT and Si /, are connected to a timer or timing control device 216. When a signal which controls an unlocking is fed to the timer device 216 via the input terminals, the timer 216 generates an unlocking signal UL which unlocks the locked state. The input terminals SUi and SiZ ₂ are connected to differentiating circuits 218 and 220, respectively, which differentiate the data input signals which _{are fed to the switch input terminals Si / 1} and SU 2 and which, depending on the number of operations of the switches, differentiate signals S ₁ and Generate S ₂ . The signals S ₁ and S ₂ correspond to the differentiated signals of the signals SU ₍ resp.

^{2 (1} SU ₂ , and their corresponding rising parts are arranged in synchronism with the rising part of the digit pulse D _1. These differentiated signals each have a width which is equal to the repetition frequency of the digit pulse D ₁ .

The input signals from the input terminals SH, SM, SK and SD and the unlocking signal UL from the timer 216 are fed to the input terminals of the matrix gate circuit η 222,224,226 and 228. The matrix gate circuit 222 is used to select the digits that are to be used in response to the digit pulses and correcting the input signals supplied by the input terminals. The digit pulses D ₄ , D ₆ , Z) ₉ , Di ₁ , Z) ₁₂ and D ₁₄ correspond to the minute digit and the hour digit of the current time, the date digit and the month digit as well as the minute digit and the hour digit of the alarm time.
The minute digit of the current time is selected when the input applied to the gate circuit 222 is in a state in which the relationship applies:

W-SM SK -S3 UL = »1«,

and the gate circuit 222 generates an output signal U. This output signal is delayed by one digit by a shift register 180 which is supplied by a data flip-flop register, after which this signal is supplied to an input of an AND gate 230. At this time, the differentiated signal S \ is also applied to the AND gate 230 which provides a minute digit correction signal in response to the timing pulse Ti . The minute digit correction signal is fed to an OR gate 232, which supplies a corresponding output signal. The output signal χ is fed to the adding circuit 62 of the timing register 32 in order to add a "1" to the minute digit.

Similarly, the hour digit of the current time is selected when

SH SJi SK SÜ · UL = "1".
The date digit is chosen when
W SM SK SK SD · UL = "1".
The month number is chosen if

SH SM SK SD ■ UL = "1".
The minute digit of the alarm time is selected when
SH SM -ST? SD ~ ■ UL = "1".

The hour digit of the alarm time is selected when

SH -SM SK ■ 325 · UL = "1".

The gate circuit 224 generates a carry disable signal when the minutes or hours, etc. are to be set or corrected. For this purpose, various input signals from the input terminals unlock the signal UL, and digit pulses D ₉ , D, o, D ₇ , D ₁₂ and D, ₅ are fed to the gate circuit 224. The digit pulses D ₉ and D ₁₀ correspond to the weekday digits and the Date sjffer. In response to this digit pulse, the gate circuit 224 generates output signals to inhibit the carryover of the weekday digits and the date digit to the next digits when the PM mark as indicated is changed to the AM mark as indicated. This digit pulse D ₇ corresponds to the hour digit of the current time. The gate circuit 224 responds to this digit pulse and generates an output signal for locking de

Carry over to the hour digit when the minute digit of the current time is corrected. The digit pulse Z) ₁₂ corresponds to the month digit. The gate circuit 224 responds to the digit pulse Z) ₁₂ and generates an output signal to block the carryover to the month digit when the date is corrected. The digit pulse Z) ₁₅ corresponds to the hour digit of the alarm time. The gate circuit 224 responds to the digit pulse Z) ₁₅ and generates a /. asgangssigna! for disabling the carryover to the hour digit, thereby avoiding the hour being corrected when the minute digit of the alarm time is corrected. The carry inhibit signals generated in this way are fed to an inverter 234 which inverts the output signal of the gate circuit 224. The gate circuit 236 generates an output signal for setting a daily or a temporary alarm time and an output signal for setting the days of the week. The timing pulse D _t Ti is used to set the days of the week and the timing pulse Z) i ₅ 7i is used to set the daily alarm time.
When the input terminal SUZ is brought to a high level "H", namely when

37? · 3Ä? SK SD ■ UL = »H«

37? · SÄ? ■ SJ ■ SD ■ UL = »H«

and the differentiated signal S _{2 is} generated, the gate circuit 226 generates output signals for setting the days of the week and for setting the daily alarm time. When the input terminal SUl is set to a high level "H", namely when

37? · SJ? · W ■ SD ■ VL = »H«

S ~ RS ~ M ■ SK SH = "H",

an output signal S _{0 is} generated to set the seconds to zero. This output signal S ₀ is fed to the input of the gate 66 of the timing register 32, so that the second digit is set to zero.

The F i g. 16 shows an example of a detailed electrical circuit of the timer 216 which is used in the circuit shown in FIG. Control unit 30 shown in FIG. 12 is used. The timer unit is arranged in such a way that when the input terminal SUT is brought to a high level "H", a start occurs. When the input terminal SUT is brought to a high level "H", an output signal of an OR gate 242 is applied to an input for setting a flip-flop 244 of the first stage, which is indicated by a one-minute signal BD ₅ T _s Φ or a timing pulse SDSK is reset . A flip-flop 256 is set to a high level "H" after a time interval of less than a minute when the output Q of the flip-flop of the first stage 248 has reached a high level "H". The output Q of the flip-flop 248 of the first stage, the output Q of the flip-flop 256 of the second stage and the signal SUO are fed to an OR gate 260 which generates an unlock signal UL. To activate the setting of a time, a corresponding switch SUT is actuated. The output Q of the flip-flop 256 of the second stage and the signal SU ₁ are fed to an AND gate 258 which generates an output signal by which the flip-flop 248 of the first stage is set. If the input terminal Si /, is brought to a high level "H" when the timer is set, the output signal UL is continuously generated for another minute. The timer 260 is forcibly reset when 5Z) * 37? = "H". This timer 216 is particularly advantageous when the date is entered by using a pushbutton. If the level of the terminal SU \ is changed alternately between "L" and "H" after the input terminal SUT has been brought to a high level "H" and then brought to a low level "L", it is possible to determine the time easily set by pressing an appropriate combination of keys. The F i g. Figure 17 shows an example of a perspective view of an electronic watch made according to the invention. FIG. 18 shows a switching device which is used in the electronic watch shown in FIG. The F i g. 19 is a circuit diagram showing the operation of the FIG. 17 illustrated clock illustrated. In Fig. 17, a crown 262 is provided on one side of the electronic watch. This crown is mounted so that it is movable in two stages, namely a rear and a front stage, and the crown 262 can also be rotated in each stage. The electronic watch also has a marker setting switch for setting a corresponding display 264 and a manual slide switch 266 for setting multiple alarm times. The switch 266 can also be used as a push button to turn on a lamp. At 268 a display area is shown in which the time information is shown. The hours and minutes, e.g. B. 12:38, are displayed on the display surface 268 together with the PM mark. When switch 262 is depressed, the date and day of the week are displayed. This occurs when either of the switches 262, 264 and 266 is not printed. When switches 264 and 266 are depressed, the display is not changed and the current time is not affected. However, when switches 264 and 266 are depressed together, the seconds digit is set to zero. In Fig. 18, when the crown 262 is in either the forward position or the second rearward position, the SD door input terminal is grounded and opened for the date, day and month

brought to a high "H" level. At this time, a lever 268 is operated by a shaft 269 connected to a contact 270. When the crown 262 is in one of the first and second rearward positions, a lever 270 comes into contact 272 for engagement, which is consequently grounded. In this situation, the input terminals SK and SUT are placed tial for the current time information on Erdpoten- ⁵ and brought to a high level "H". When the crown 262 is rotated clockwise, a toothed segment 274 is also rotated, also in a clockwise direction, the rotation taking place by means of a toothed wheel 276 over a predetermined angle.Then the toothed segment 274 rotates freely and presses a spring 278 against a contact 280. At this time, the spring 278 comes into engagement with the contact 280, and the input terminal SH is brought to a high level. On the other hand, if the crown 262 is rotated counterclockwise Ό, the sector gear 274 is rotated clockwise so that the spring 278 with the contact 282 comes into action so that SH is brought to a high "H" level. When the crown 262 is rotated, the shaft 279 is rotatably connected thereto. Gear 276 is fixed in place and rotatable with shaft 269. A cam 284 is attached to the gear 276. A lever 286 is normally pressed against the cam 284. When the cam 284 is rotated, the lever 286 is moved toward a contact 288 ¹⁵ so that the input terminal SU1 is grounded and brought to a high "H" level. Since the lever 286 is urged against the cam 284 by its spring force, the lever 286 is held in a stable position at a distance from the axis of the cam 284, namely at a minimum distance when the crown 262 remains in its normal position. The spring 278 is coupled directly to the toothed segment 274, and it is ι? not engaged with any of the contacts 280 and 282 when the crown 262 remains in its normal position.

> i 20 When the spring 278 is engaged with one of the contacts 280 or 282, the crown 262 is rotated slightly.

ζ '; Even if the crown 262 is rotated beyond an extent at which a predetermined angle exceeds

£ is stepped, and when the part 274 is released from the gear 276, the spring 278 is still with the

I j kept both contacts in contact. One end of a lever 290 is connected to the shaft 269, and it

\ t pushes shaft 269 in the axial direction. The lever 290 is provided with grooves 292 at its upper end,

f | ²⁵ which are designed such that they come with a stationary pin 294 for engagement. If the user

^ zer lifts his finger off the crown 262, in a position held forward, the crown

|; 262 returned to its normal position by the action of lever 290. When the crown 262 is off

When its normal position is pulled to the rearward position, the crown 262 remains in this extended position

| f position. A lever 296 is assigned to the switch 264. When switch 264 is depressed, it comes

fi 30 with a contact 298 to engage, so that the input terminal SUl is brought to a high level. In

In the same way, the input terminal MSIN comes to a high level when a lever 300 makes contact

ξ 302 is brought into action.

jl The F i g. 19 shows an example of the modes of operation of the crown and switches shown in FIG. 18. According to the above

For versions, when the crown 262 is moved forward, a date is displayed. If, on the other hand, the

l & 35 crown 262 is brought to its first rearward position, the input terminal SK goes high

β and the input terminal SD is brought to a low level »L«. Since the input terminal SUT

'•' t is connected to the SK input terminal, it is possible to set the current time by turning the crown in

λγ is pulled to its first rearward position. When the crown 262 is rotated counterclockwise, i. H.

ί according to Fig. 19 upwards, the display of the hour digit is made to flash or light up.

| i; 40 If the crown is turned further, the hour digit will be corrected. If, on the other hand, the crown 262 is clockwise

v is rotated in the opposite direction, d. H. according to FIG. 19 down, the display element for the minute digit begins to

'. ^: . zen or light up. If crown 262 is rotated further in the same position, the minute digit becomes

corrected. Since the digits to be corrected are shown on the display, there is no risk of erroneous correction. If switch 267 is depressed without rotating crown 262, 45 the seconds digit will be set to zero. If the seconds display shows 0 to 29 seconds, and V ₁ is while the seconds are being zeroed, the second digit is set to zero. However, if during

U of the zero setting 30 to 59 seconds are displayed if the second second digit is set to zero,

; a carry signal is generated for the minute digit. In Fig. 19, there are essentially two modes of operation As shown, the first mode of operation is to depress crown 262 and switch 262 equal to -50 early to operate in the normal display position, and the second mode of operation is to switch the switch 264 depress while the crown 262 is held in its first rearward position. Accordingly it is possible to adjust the watch according to the user's wishes and the environmental conditions . use. When, after setting the time, the crown is fully pushed in to the forward position in which

; the date is displayed, a compulsory electrical lock is created so that an accidental contact

55 tion with the fingers does not affect the current time. If, after setting the time, the user presses the ; ■ 'If the trigger switch is not fully depressed, a timer works in such a way that after a predetermined interval the electrical interlock is automatically applied. When the crown is in its second posterior Position is pulled, and when it is turned counterclockwise, the adjustment is in the same way the month digit, while if the crown is turned clockwise, the setting can be made 60 of the date is possible. Under these conditions, if switch 264 is depressed without the When the crown is turned 262, the days of the week can be set. When the crown 262 is in its second rearward Position is pulled, the month digit can be set, and the date digit can be set the display elements for the days of the week are made to light up or flash. If the crown 262 is turned at the same time, the flashing of the display elements for the day of the week number is displayed hold, and only the display elements of the other digits start to light up, which depends on the direction of rotation depends on the crown. This indicates that the digit can be corrected.

When the crown 262 is pulled to its first rearward position, the adjustment mechanism for the momentary time unlocked in such a way that when the crown is returned to its normal position,

18th

Immediately after unlocking the current time setting device, the input terminal Sl / Γ reaches a low potential "L", so that the unlocked position is maintained. Accordingly, an alarm time is displayed and it is possible to set the alarm time. Under these circumstances, if crown 262 is rotated counterclockwise, d :? The hour digits of the alarm time can be set, while rotation of the crown 262 clockwise allows the minute digits of the alarm time to be set. s

If only the switch 264 is depressed without turning the Krona, it is possible that the alarm time in is discontinued on a daily or temporary basis. A second switch 266 is used to set the alarm times while moving this switch manually. Thus it is possible to do a review whether the alarm times are set or not. Every time the switch 266 is depressed, the registered alarm data is read out and displayed. If among these If the crown 262 is rotated, the displayed alarm time can be corrected or set be made possible. If switch 266 continues to be depressed for a period of more than 1.5 seconds instead of depressing switch 266 every time the displayed alarm time changes becomes, a plurality of stored or registered alarm time data at a speed shifted by 1 Hz and displayed continuously. The shift stops when switch 266 is released will.

Furthermore, the circuit is constructed in such a way that, when it is desired to set an alarm time, immediately after the display has been switched from the display mode to the current time the Alarm time of a free address of the register is displayed, which is automatically searched for again display free register. When the register is filled with the alarm data, the finally set Data displayed to end the automatic search. The automatic search requires a maximum Time of 0.5 sec.

In the clock according to the invention or the time measurement system according to the invention, the state of the display surface the clock switched between three possible positions, d. H. either the current time is displayed or the alarm time is displayed or a date is displayed. In addition, the display mode changed to make it easier to identify the time information. The decoder for the display driver circuit is constructed to identify a variety of conditions and to display reversed, deleted or modified by modulating the displayed data. Farther the arrangement is chosen so that the user can easily judge which digit is corrected or corrected as the indicator of the corrected or updated digit flashes or flashes. This can be done with the aid of the FIGS. 2OA and 2i) B shown data modulation unit can be achieved. First, the display system itself is discussed. There are many methods of getting time information on one Display face or a display surface of a clock. The time display is as essential as the timekeeping. Since there are many types of display devices, the display driving circuit is interchangeable depending on the display system used.

Furthermore, it is necessary that the main circuit provides certain information to the display circuit transmits, taking into account the type of display system. According to the invention, a selected one Data information which is to be displayed is transmitted to the display unit, and In addition, the display data is chopped up into pulsed data streams before transmission.

More precisely, according to FIG. 20A and 20B, a signal DA TA 60 is modulated by a data modulator 350 and then passed through a chopper circuit 352 as a data output signal. The data modulator 350 includes an AND / OR gate circuit 354 and a matrix gate circuit 356 as shown. Both gate circuits can, however, also be designed as customary gate circuits or can be combined to form a single matrix circuit. However, the use of a matrix circuit is advantageous because it is easy to see the matrix structure and because an inexpensive and compact read-only memory matrix can be achieved by using C / MOS integrated circuits. It is also possible to build different gate circuits into the matrix, which are labeled 356, 358, 360 and 362. As an example, an i / ⁺ signal for controlling the flashing or lighting up of the entire correction digit is used to control by increasing the pulse width of an input signal for correcting a digit (signal U) , which is indicated by the functions shown in FIG. 2OB shown circuit happens. The gate circuit 362 is controlled by switches SK, SD, UL and SUi to switch the data to be displayed. Corresponding display digit pulses Z)) 3, D \ o ^{un £} i Ds are selected to display the alarm time or to display the data and the current time, and the circuit is constructed in such a way that the data to be displayed depends on be switched by the phase of the display digit pulse D ₀ . The selected digit signal is passed through one stage of shift register 366 to delay it by one digit and to shape the waveform of the digit signal accordingly. In this way, after a peak of the waveform and a slight delay have been removed, the digit signal is then sent out. In the digit signal selection circuit 368 , a signal is selected which has a phase which is advanced by an angle corresponding to a delay of one digit. A gate circuit 370 is used to generate an intermittent chopping signal, which has a frequency of 16 Hz, from a COAT ^ signal. By means of the chopping signal, the data stream leaving the shift register 388 is chopped into periodic pulse sequences by means of the AND gate 389. The 16 Hz chopper signal is used to recover the timing data from the chopped data in response to a signal that is synchronous with the chopper signal. The retrieved time data is displayed as explained below. If the CONZ ^ input terminal (a continuous input terminal) receives an "L" signal, an intermittent signal is generated; if the signal is "H", data and clock pulses are transmitted continuously. Gate circuits 372, 374 and 376 control the generation of the intermittent signal. A signal synchronous with the signal Φ2 is multiplied with a signal on the line 378 synchronous with a signal Φί

and a signal synchronous with the signal Φ \ is multiplied by a signal Φ1. The zi your signal Φ 1 synchronous signal is generated by the latch circuit 380. By transmitting de data in pulsed form, considerable energy savings are achieved for the driver and additional circuitry. The following Table III shows a truth table of the display decoder which corresponds to the display modulation.

Tabel III 0 »4» "δ" output
away' 1 (digital block)
c 'd' e ' 1 1 1 G' A ' output
50 'Sl' 0 (analog block)
sr sy si 0 0 SS ' S6 ' 10 No 0 0 0 1 1 1 0 0 0 0 0 ! 1 0 0 0 0 0 0 input
"1""2" 1 0 0 0 1 1 1 I. 0 0 0 0 0 0 0 0 0 0 15th 1 0 1 0 0 1 1 0 1 0 0 1 0 0 0 1 1 0 0 0 2 1 0 0 0 1 1 1 0 0 1 1 0 0 0 0 0 1 0 0 3 0 0 1 0 0 0 1 1 0 1 1 0 0 0 0 0 α 0 0 4th 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 1 0 20th 5 0 1 1 0 1 1 1 0 0 0 1 0 0 0 0 0 0 0 1 6th 1 0 1 0 1 1 1 1 1 1 0 0 1 1 0 1 1 0 0 7th 0 0 0 1 1 1 1 1 0 1 1 0 0 0 1 1 1 1 0 25th 8th 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 9 0 1 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 10 1 0 0 1 0 1 1 1 1 0 0 1 1 1 1 1 0 1 0 30th 11th 0 0 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 0 12th 1 1
1 1 1 0 0
0 0 0
0 0
0 0
0 0 0 1 1
0 1 1
0 1
0 0 0 13th 0 1
1 1
1 0
0 0
0 0
0 0
0 1
0 1
0 1
0 0
0 35 14th
15th 1 0
1

Explanation:

Output "1" means lighting up,

"0" means deletion for the display segment outputs,

"0" corresponds to low level and

"1" the high level at the series-parallel converter outputs.

The data modulation can be carried out according to the following methods and analog methods:

(1) a method in which the content of the data to be changed is not changed, but the display mode is changed (the display of the second digit is changed from white to black or vice versa);

(2) Without changing the content of the data to be displayed, the display lights up or the display becomes deleted (e.g. the day of the week display lights up);

(3) the content of the data to be displayed is changed (e.g., a date alarm display);

"(4) the display is made by using markings (for example, a black mark for displaying an alarm time).

These methods are carried out in the following way:

(1) Information regardless of the content of the data to be displayed is displayed (for example becomes an alarm coincidence by flashing the display area and a mismatch of an alarm is displayed in the same way).

(2) The appearance of the display is changed by changing the background of the display area so that it is possible to see at a glance the type of data presented (to

For example, to show a time, a marker that contains the time is shown brightly, while the date is displayed by lighting a marker indicating the Date included).

(3) A display scale is displayed (for example, a weekday scale is displayed).

(4) The display unit is displayed (for example, a character indicating a month or includes a date).

(5) The display of the content of the displayed data is supplemented (for example a Λ / ^ signal is displayed and a Λ / 55 signal is displayed to illustrate PM and AM).

These ads are controlled as follows:

(1) By a switching operation (switching the display area),

(2) by the content of the digit to be displayed (for example, deleting a minute digit in a Alarm time 0),

(3) by the information entered from the outside (for example a control which is carried out by data, entered from the DIN input).

Although according to this description the data modulation unit in connection with a time-series shift register is used, it should be understood that the invention applies to any system other than is a time-series shift register can be used, for example in connection with a parallel system, which uses a static flip-flop circuit.

According to FIGS. 20A, B, on the right-hand side of the rows of the matrix 356, the reasons for the selection of the crossing points on the rows of the matrix and its object are explained. The output DATA 60 from the shift register ring is delayed by 4 bits more than the output Q ₁ from the shift register ring, which serves as a reference for the clock system according to the invention, so that the indices appended to the digit signals of the matrix 356 are one greater than those Indices attached to digit signals, which are used for a carry or the like, so that they represent signals delayed by one digit. The output from gate circuit 354 is combined to the output of matrix circuit 356 so that the display signals are modulated. A signal of Φ1 Hz is generated by a latch circuit shown in Fig. 20A, and it is converted by the gate circuits 352 into signals Φ 1 and Φ1 G, ^ causes the entire display to flash in the event of an alarm and G represents a flash - Or flash block signal, which is sent out by the control unit shown in FIG. 8A. The signals D 14 and 015 are logically added so that the minute display of alarm data is deleted when the alarm hour data is set to zero. If the PM marking is to be suppressed during the display, timing pulses £> ₉ 7] are sent to the matrix.

Where the display of the second is inverted by a timing pulse D ₅ T _B , although a day of the week and a 10-second signal are alternately displayed on the same area of the display area, as can be seen from the codes shown in Table III, the codes are so constructed that in the case of a linear display of numbers of 6 or 8 digits with the signal 7g at the "H" level, the states of the illuminated parts and the non-illuminated parts are reversed. In this system, only a predetermined portion is illuminated in the 10-second display, and only a predetermined portion is illuminated to indicate the days of the week, so that by marking it in this way, it is possible to quickly and easily determine that the contents the indications are different.

If a 10-day digit is to be _{suppressed by a digit pulse Ζ), 2} , the digit signal Dp is added to the data in order to suppress the 10-day digit of the data if this digit is equal to zero. Ordinarily a user is familiar with the calendar so it is advantageous not to suppress the 10 second digit in the same digital display, rather it is not desirable to suppress the data. Since timepieces are not only measuring instruments but are also worn by users, it is necessary to take such circumstances into account.

In order to be able to clearly distinguish the hour-minute display on the one hand and the month-date display on the other hand, if the month display is suppressed but the date display is delivered, namely when the date is set, the month is also displayed. However, in view of the need for constant display of the date, only the date and day of the week are displayed. If the switches S _D , SK are at a low level "L", a date and a week are displayed alone, while if the switches S ₀ and you are at a high level, the month, the date and the day of the week are displayed will. For this reason, the Mcnatsziffer is suppressed when the switches S _b and Sk are at the high level "H" by adding the signal D π to the data.

In order to make the display of the weekdays flash or flash, the signals Z), ₀ and Φ \ G are added to the data in the state in which the digit is not selected.

{SR -SM + SH-SM = "L"),

so that the weekday number flashes or flashes under normal conditions. Such blinking or flashing can lower operating costs and add commercial value. Following the principle of flashing the digit to be updated, the flashing stops when a certain digit is dialed. The flashing of the 10-second digit, which is caused by signals D ₅ TgK ₁ Φ 1 G , does not select any digit in the same way as the flashing process for the days of the week and requires a single flash. Since the T% signal is "H" to reverse the display, it is added to the product of the TJ and D ₅ signals.

To make the display of the one-second digit flash, marked in the embodiment shown the display driver circuit only the PM digit mark such as 10 minutes, one minute and 10 seconds are displayed. However, to provide a digital indication of the second by using the auxiliary unit

one-second data is modulated in a manner similar to that used for the one-second digit.

In order to cause the correction digit to light up or flash, a signal for selecting the correction digit data input signal from the shift register is delayed by one digit, which is used to determine a correction block (e.g. a one-minute correction is made to one minute -Digit selected as correction data input signal. However, the 10-minute digit and the one-minute digit that are affected by the correction should be lit or flashed. A logical product of Φ \ Ηζ is added to the specified block (which is two digits wide).

In order to light up or flash the daily alarm mark, the date mark and the PM mark, the signal for actuating these markings is modulated by a reproduced signal of Φ 1 Hz.

A continuous activation terminal 384 is normally brought to the "I" level by the output signal Q from a reset flip-flop 386, which is continuously held in the reset mode by a narrow 1 Hz signal BDi T _s. In the circuit shown in FIGS. 20A and 20B, the output signal CONTA can be maintained by determining a moment at which the shift register of the timing register assumes a comparable status at which its 1/16 second digit becomes "0" . This initial signa! is used by the latch circuit 386 to generate an output activation signal which is one memory cycle wide, or about 4 milliseconds wide, which is delayed 1/2 bit more than the instant at which the predetermined 1/16 second Digit becomes "0".

This release signal is stored or locked with the clock T ₁ Φ 1 in 388 'and is used periodically

generate chopped data pulses as well as chopped clock signals which do not contain any pulses with false transitions. For this purpose, the signal is passed through the OR gate 370, and a continuous enable signal is obtained by setting CONTA to the "H" level. By means of the AND gate 376, pulsed clock pulses Φ1 are obtained. The delay circuit 370 also achieves this in the following cycle (see FIG. 8) after Φ2 for ΦIx and for Φ8.

The pulsed output of data can reduce the energy consumption of the subsystems that contain this data received, can be greatly reduced by adding to the subsystems, which the entire system arrangement for Form transmission of the intermittent signal, which can also be transmitted spontaneously, a frequency converter device is added to produce a low frequency output signal, or by adding a device which serves to send out only the changeable part when

3u an information changes, so that thereby a signal with a high speed to the whole system is applied by a system that operates at a higher speed, the Display system or the auxiliary system is not required to run continuously at high speed work.

In FIGS. 20A and 20B, the signals which are marked with a symbol "J", for example the signals TSA, ΦΙΑ, Φ2Α and DATA, represent intermittent signals which have a frequency of 1/16.

Sole intermittent data signals are advantageous because wherever a multitude of platelets are integrated with Circuits are electrically connected to each other, the loss of energy due to charging and discharging a stray capacitance of the terminals is increased.

The F i g. 21 shows an example of a circuit arrangement of the alarm unit 34 in which the data flip-flop circuits which form the shift register ring of the timing register are numbered as described above, the 60th data input being identified by the designation "DATA 60". Similarly, the data input to the 28th flip-flop circuit of the shift register ring (which is the same as the output from the 29th flip-flop) is labeled DATA 28. The non-coincidence of the logical values of DATA 60 and DATA 28 is determined by an exclusive OR gate 404, so that a current time tKT and an alarm time tÄT are compared with one another. The phase of the DATA 60 signal is delayed by one digit by the DATA 64 signal. Because the DATA 28 signal has been delayed by 32 bits or 8 digits more than the DATA 60 signal, each time Z) ₆ , D ₁ , Z) ₈ and D ₉ are timed, the DATA 60 signal represents the minute, 10th Minutes, hours and PM markers of the current time, while the DATA 28 signal illustrates the minutes, 10 minutes, hours and PM symbols and other symbols of a corresponding alarm time.

The time coincidence is determined by setting a flip-flop with preparation reset terminal 400 at Ζ) ₅ 7 " ₈ Φ to" Η "and by setting the flip-flop 400 to the output signal from the exclusive OR gate indicating the non-coincidence If tKT = tAT, the flip-flop 400 is held in the set state during the timing of the signals D ₆ -D ₉ , more precisely, until the timing of the signals D ₉ , T ₄ and Φ 1 is completed the instantaneous time signal tKT and the alarm time signal tAT are compared with one another. The content of the output signal from the flip-flop 400 is read out by the data flip-flop circuit 402 when the signals D ₉ , T ₁ and Φ \ are timed, however, since there is a time difference or delay between the comparison between the current time tKT and the alarm time tAT supplied by the gate circuit 404 and the reading out of the flip-flop circuit 402, di e signals DATA 60 and DATA 28 compared with one another during an interval of Ζ> ₆ Γ ₂ Φ1 to ΰ ₉ Τ ₄ Φ 1. Although the value of the timing of the signal DATA 26 by Ω ₉ Τ ₂ Φ 1 and the value of the timing signal of the signal DATA 28 by D ₉ T ₁ IpX are normally held at the low level "L" when the contents of the shift register forcibly from the outside is set via the DATA-IN terminal, which is shown in FIGS. 11A and 1IB, it is possible to establish a relationship which is: DATA 60 Φ DATA 28 by ΰ ₉ Τ ₂ ΦΙ ·

An alarm coincidence can be indicated by the fact that the logical output signal from the flip-flop 402 is at the "H" level. Oz minutes units are compared with each other during an interval in which TKT = fact, the logical output value increases continuously for one minute to

Level "Η", and in the remaining interval it assumes the level "L" at the moment when the flip-flop 402 changes from "L" to "H", so that the flip-flop 406 is triggered in such a way that it is set. The output signal from this flip-flop controls the activation of an audible alarm. According to the invention, the alarm signal is modulated in two ways, namely by a signal which has a frequency of 2045 Hz and a duty cycle of 25%, this signal having a frequency of 1 Hz. If the double-modulated alarm signal is further modulated by a signal of a few Hz, then an audible alarm occurs which resembles the chirping of a cricket, and this is an alarm which, although not irritating, does attract the attention of the watch user directs. The rising portion of the output signal from flip-flop 406 triggers flip-flop 408 in such a way that it is set. The output signal F from flip-flop 408 controls the lighting or flashing of the display surface of the clock. Both the flip-flop 406 and the flip-flop 408 are preferably set by the input data signals S ₁ and S ₂ and the STOP input signal for the clock. Thus, the user can transmit a signal to the clock indicating that he has acknowledged the alarm, whereby the watch responds to this signal by turning off the alarm. Even if such an alarm acknowledgment signal is not given, the circuit is so constructed that the alarm is automatically turned off after one minute This is done with a view to keeping the energy consumption of the battery to a minimum and avoiding unnecessary noise. In this case, however, the flashing will continue until the alarm is confirmed by the user. The flip-flop circuit 406 is connected in this way that it receives a signal from the gate circuit 410 one minute after the alarm coincidence, whereby the flip-flop circuit 406 is reset is generated that a boost signal of 2048 Hz is modulated with a signal with a duty cycle of 25% and a frequency of 1 Hz, it has a frequency in the range of 1 kHz to 2 kHz, which is audible to the human ear. Furthermore, due to the 25% modulation by a signal of 1 Hz, the energy required to activate the acoustic alarm can be greatly reduced, so that the service life of the battery is extended. An output signal ALS is applied to the base of an NPN transistor with a grounded emitter through a resistor of 100 kilo-ohms, and the working coil of a piezoelectric buzzer is connected in series with the collector of the transistor. Instead of using a piezoelectric buzzer, a dynamic buzzer can also be used. In any case, the increase in current required to activate the acoustic alarm is only about 10%.

The output of flip-flop 402 is delayed by data flip-flop 406. Gate circuit 410 is used to sample the non-coincidence of the logic values in the output signal from flip-flop 402 and flip-flop 412 as well as the rising portion of the coincidence signal (which is one minute wide) for tKT = tAT by the output signal from the flip-flop 402 is used at that time. The signal DATA 28 is used to determine the setting of the daily alarm time with the timing of D ₉ T _% 0 1, so that in this way an erasure inhibit signal ERASE is formed, which is supplied by the alarm coincidence signal ALDET of the flip-flop 406 and of a logical negative output signal QER of the delete-lock signal, of a correction unlocking signal (76, of a digit time control signal and a signal 5ATO, which represents an alarm time 0 according to the following equation:

ERASE = (Z) ₁₄ + D _{: 5} + Di ₆ + Z) ₁ F ₈ ) · VL ■ (ATO + QER ■ ALDET)

Even if the alarm time coincides with the current time, the cancellation will only occur under a normal condition (ie UL = "H"). Unless a UL logical product is used, setting a temporary alarm becomes extremely difficult. If, when setting an alarm time, such a setting is made after the current time, the alarm data would be deleted by the setting.

Usually, the information concerning the alarm flag is included in the flag digit of the alarm data, but according to the invention, special flags of the alarm flag digits are used, that is, the daily flag and the alarm setting flag, which are expressed by the instant time display mode. This enables the user to continuously check the status of the alarm setting. The daily marking is determined and stored by a locking circuit, and it is fed to the output DATA as a timing signal for the current time Z) ₈ 7 " _4. The sampling of the signal QDLY and the modulation of the display of DLY are shown in FIG. 10A The alarm setting flag is a signal which is achieved by inverting a signal generated when an "hour 0" of the alarm time digit is sampled, and this signal is derived as signal ALO (alarm not set), and it is then used by the The alarm not set signal is sampled by the circuit shown in Figures 11A and 11B and supplied to the circuit shown in Figure 21 to serve as a display modulation signal.

The F i g. 22A to 22C show details of the FIG. 4 shown display driver 20. In the circuit according to FIG. 22A to 22C show liquid crystal display elements which are driven by a source AL , and a level shifter 40 is also provided. Examples of the level shifter are illustrated in Figs. 24A and 24B. The level of the data is changed by the level shifter 40, and the data is then passed through a bit serial to parallel converter 42 formed by the shift registers 502, 504 and 506 to generate output signals P ₁ , P ₂ , P ₄ and generate P _5. Combinations of these output signals are read out by a digit-serial-parallel converter 46 _{during the time control of T 8.}

Decoders 508 and 510 serve to decode the 4-bit parallel signals, each of which contains four bits, the decoder 508 serving to provide a 7-digit digital display while the decoder 510 is used to provide a 7 part analog linear display. A transfer switch arrangement 592 is used to switch decoders 510 and 508 so that the

analog display _{output signals S 0} to S ₆ serve as a 7-digit digital display. The truth value of the decoder is shown in Table III.

The digit-serial-parallel converter 46 is formed by a plurality of latch circuits 514-526, of which the latch circuits 514-524 are used to convert digital serial decode output signals into perfectly parallel signals. These latch circuits continuously supply a signal having a constant level as long as the time information does not change. The latch circuit 526 functions as a delay circuit to provide an output signal obtained by slightly delaying the input signal OLC.

As shown in FIG. 24D, the Anzeigetreiber20 a plurality of AND-NOR Gattem which those in number corresponding to the latch circuits, and which operate in such a way that they generate a signal that dentisch with the signal 0COM i is when the interlock outputs are at the low level, while a signal slightly delayed with respect to the signal 0COM is supplied when the interlock outputs are at the high level. In FIG. 24D, the display element, which is arranged between an output 0COM and the output 0dg of the driver circuits, is applied with a voltage of zero volts when the latch output is at a low level, and with a voltage which has a frequency which is equal to that of the output 0 _C om ^ t when the latch output is high.

A time pulse reproduction circuit 530 has shift registers 532,534,536 and 538 in order to reproduce time pulses D \ 1g 0 \, D ₂ Ti0], Dill 0 \, Z) ₄ Tg 0 \ and D ₅ Ii 0 _X as well as gate circuits 540. The timing pulse Z) ₅ + T ₁ 0 1 is applied to latches 514 and 516 to serve as a clock signal. Similarly, the timing pulses Z) ₄ + T _s ,, Z) ₃ + T% 0 _U D ₂ + T% Φι and D _] + T _s 0 _i are fed to the latch circuits 518, 520, 522 and 524, respectively.

The signal from the output terminal Λ / 55 is used in the Fi g. 23 to light up the colon markings shown, for example marking 561, which provides a time display. The signal from the output terminal Λ / β », /, is used to illuminate a flag indicating that a daily flag has been set, for example a flag 562 shown in Fig. 23, while the output signal is being output is used by the output terminal M _a l to light up an alarm setting mark, for example a marking 564. When the output signals appear at the output terminals 562 and 564, the daily marking and the alarm setting mark are

y> is displayed even while an alarm time is being set or while the watch is showing a current time under normal conditions. The output from the output terminal M _DD is used to light up letters such as a mark 566 indicating a date, or a day of the week mark 568, or a period. The output signal at the output terminal Mjü is used to bring a part 570 to light up, which, when it is combined with a part 572, is dei brought by an output signal from the output terminal Mob ^to light, a distinction between the states of P _{Indicates M} and Am . 574 illustrates a second scale represents, which is brought by the output to the lamps, which occurs at the output terminal Mob The output terminal Mου "ζ ^w i ^f d switched such that a part is 578 (dz) to glow, which in the Figure 22C illustrates when a 7 digit digital display is specified. If the driver circuit according to the invention is added to a normal clock, because the second display digit contains the parts a ₂ to g ₂ , it shows IC minutes or the 10th day, the state of the lighting of the parts a ₂ and d ₂ always being the same is. Ow! For this reason, an output for part d _{2 can be} omitted. When the drive circuit is used in a timekeeper or an electronic desktop calculator, it is necessary to drive the parts a ₂ and d ₂ independently zi. The leftmost digit or the O-th digit of the display device shows a marking, the first digit 580 provides a digital display through the parts α, to g, and Ai, the second digit 582 provides a «digital display through the parts a ₂ to g ₂ , the third digit 584 provides a digital display through the parts a ₃ b \:

g _h the fourth digit provides an analog display through parts S ₀ to S ₆ or a 7-digit digital display 586 when the signal S _{DE is designed} so that it has a high level.

According to the above, the potential of the signal fed to the driver circuit is changed between K ₀₀ (0 volts) and K ₅ J ₁ (-1.5 volts), but according to the invention a level shifter 40 is used to set the potential V ₃₅₁ to Bring K ₃₅₂ (~ 5 volts), so that this creates a logical amplitude. As in the Fig. 24 A, the level converter 40 is formed by a C / MOS flip-flop for setting and resetting with a negative logic, which has two NAND gates with the transistors 601-609, the output of one gate with an input of the other Gatters is connected, and the other input is driven by the complementary input. The MOS-FET transistors 602 and 604 are designed in such a way that they are not brought into a pinch-off state due to their gate potentials. If the input logic level is switched from "H" (K ₀₀ ) to "L" (Vss \) , the output level changes from V ₀₀ to K ₅₅₂ due to the power paths through the transistor pair 601, 607, with the transistor 606 being switched over of the flip-flop is opened or switched off. Fig. 24B shows another embodiment of the level converter. Somi two or an even number of inverters, which are driven by a voltage source which has a logical amplitude, are connected to one another in the form of a ring via resistors, and the gate potentials of the inverters are made the same by independent field effect transistors, which are used for the purpose Set and cause reset, with an odd number of inverters placed between two points used for set and reset. Since a logic level converter takes up a large space in an integrated circuit arrangement, it is necessary to reduce the number of converters. On the other hand, in order to reduce energy consumption, the number of integration operations per unit of time for the number of logical changes in the logic level converter must be kept to a minimum. A reduction in the number of logic circuits can

be done by placing them immediately after the input terminal.

The signals SET for setting and RES for resetting is not always necessary that the inversion relationship SET = R ~ ES is satisfied in a perfect manner, this relationship can rather also terms have the first logical products from the common clock pulse signal <P _t ι contain . In the exemplary embodiment shown in FIG. 22A, the level shifter 40 is connected directly to the input terminal. The rectangular blocks, which are constructed similarly to the logic level converter 40, represent similar logic level converters.

In FIG. 22 A, the data input signal DATA-IN is converted from time-series signals by a shift register into parallel signals, which contains flip-flops 502, 504 and 506, and the parallel signals are supplied to the decoder 508. The output codes of decoders 508 and 510 are shown in Table HI. Each of the decoders 508 and 510 contains an arrangement of AND gates and OR gates and forms signals for 8 sections or segments or digits α to g for the digital display and for 7 parts of an analog display of 2 ^U combinations of four bits ( P ₁ , P ₂ , Ή and P ₄ ).

If the decoder is constructed as a dynamic decoder from C / MOS integrated circuits, with a matrix of field effect transistors only of the P or N type being constructed, a capacitor of extremely small capacity is first discharged, then charged by the matrix circuit containing AND-OR field effect transistors, and the result is immediately read by the latch circuit, so that it is possible to make the decoder as a compact unit. Fig. 24C shows an example of such a decoder. In the circuit of FIGS. 22A to 22C, the transfer circuit 512 is controlled by a digital, analog transfer control signal S _DE so that the signal is thereby freely transferred to the latch circuit 524 between digital and analog signals. This is because it can be advantageous to replace the decoder 510 with a 5-bit decoder which contains a combination of the transmission circuit 512 and the decoders 510 and 508. The digital display has been made determinable or determinable because it is desirable to use the same digital display driver circuit as the integrated circuit even in the event that it is desired ^{to display the data with digital 2S} digits so that the cost of the integrated circuit can be mass-produced can be reduced and also the number of integrated circuits can be reduced, which are required for a specific case when a lot of digital display data are required, as in the case of the time recording which is preferably to be provided. Latch 526 is used to provide an appropriate delay to an AC drive pulse <P _LC. When the delayed signal <t> _LC is denoted <f> _L c , an AND-OR gate 580 sends the signal 0lc to the terminal of a part to be lit and further sends the signal <P _LC to the terminal of a part to be erased . If the signal 0 _{LC is} fed to a common electrode signal Φ _€ ομ, an equal potential is fed to the segment to be deleted or the part to be deleted, with the result that this display element is short-circuited with its associated element. A potential (0lc ~ Φζτ) is applied to a segment or section which is to be made to light up, so that during almost all times an alternating voltage having an amplitude equal to half the source voltage is applied during to the time of switching, the applied voltage to a short circuit which does not include the source of the driver circuit is formed for a short time, so that the capacitive display elements are discharged. For this reason, it is possible to reduce the display power by 50% as compared with a case where the charging current flows through the source as in a conventional arrangement.

An example of the auxiliary system 12 according to the invention is illustrated in a block diagram in FIG. 25, wherein the additional unit is combined with a standard unit 10 of the clock system. Different Control signals are transmitted between the standard unit and the additional unit via terminals 13 011, 13 012,13 021 and 13 022 as well as via the conductors 13 041 and 13 042, the direction of the signals is determined by arrows relating to the conductors 13 041 and 13 042.

Each of the conductors 13 041 and 13 042 can be omitted. If these conductors are absent, it means however, that the two units are opposed to each other without connection, and it becomes such a case not included in the invention. At least the standard unit should be a continuously operating one Have subsystem (including the clock system). An input terminal 13 061 is only for the additional system provided, but in some cases this terminal can be omitted.

A main operating system 13 031 has a memory register if a multiple alarm is preferably intended is. Alternatively, an operation unit, a storage register and a pulse generator can be provided if an automatic lead / lag correction is intended. Alternatively, an operating unit and a storage register if the addition is intended to be a computer. Alternatively can a detector, a data converter and a memory register can be provided if a blood pressure measurement is used as an addition is intended. A control unit 13 032 is available. If a multiple alarm addition is intended, the control unit 13 032 generates a signal for a progressive comparison of a plurality of signals with the current time and a control signal for a continuous display of the alarm time information, which in are stored in the memory register on the display area. When a lead / lag correction is intended is, the control unit 13 032 generates a signal designating the start of an error measurement or a Operation control signal which serves to cause a pulse generator circuit in the additional unit to generate a fast-slow correction pulse which is necessary for correcting an error.

If a computer addition is intended, the control unit 13032 generates a signal indicating the exchange of signals between the computer and various registers controls, depending on of various operational control signals such as x, + +, =, etc. In addition, the control unit 13032 can also be so constructed that it stores the operation of all or part of the unit, or that part of the standard unit is controlled by the additional unit via the signal conductor 13 041. For example

in the case of a multiple alarm add-on system, if the time of the alarm data and the the data stored in the additional unit is automatically deleted at the moment, then the circuit is switched off for the transmission of the signal from the additional unit 12 to the standard unit is closed, and a signal generated by the control unit, which serves to send a clock pulse to the shift register of the additional unit 5 deliver. At this time, alarm time data that just coincides with the current time is sent to there Register supplied to the standard unit, which contains an alarm time from the additional unit, so that thereby the Alarm time data can be set in the default unit. One minute later, the Clock pulse from the additional unit to the standard unit resumed, so that sequentially others Alarm data are transmitted from the additional unit to the standard unit. When the normal time display is in ic an alarm time setting status is changed by operating an external actuator, so the control unit generates a signal indicating the start of scanning or finding an empty register controls When an empty register is found or a prescribed time, for example 0.5 seconds, has elapsed a signal is generated which terminates the search for an empty register. If an empty register is found, a signal is generated to ensure that the clock pulse is fed to the shift register of the main op-15 interrupt or terminate ration unit, whereby the empty register of the register contents of the additional unit which stores the last data that was collected at the time of terminating the search for a certain time are shown. Furthermore, the transmission of the alarm data to the main operating unit is also carried out of the auxiliary unit is ended, and a transmission circuit from the standard unit to the auxiliary unit becomes and the operations of the register of the main operating unit of the auxiliary unit and the Regi-20 sters of the standard unit are synchronized in such a way that the data of the empty address or of the register, which contains the data last displayed at the time when searching for a given interval has been completed, can be the same as the alarm data transmitted from the standard unit to the additional unit were sent. This generates a control signal that can be used to set or correct the alarm data if in the standard unit designed in such a way that it allows the setting or correction of the in the corresponding

Yes; 25 registers of the additional unit corresponds to the data contained. In the case of a computer as an addition, it is immediate

| f after data input or an operation control signal, a clock pulse with a high frequency (e.g.

l | i 1 Mega-Hz) sent to the computer for a short time longer than a certain time, for example

|| wise one second, so that this enables the computer to run at a high speed

|| to work. Thereafter, the frequency of the clock pulse is in the range of a limit of, for example, 8 kHz

p 30 decreased. The clock pulse can also be terminated so that the data to be displayed from the standard

Ii standard unit are supplied. When an operation command is given or data input is made, after-

| § that the additional unit was controlled by the high-frequency clock pulse signal, operation data,

|| which were included in the standard unit are transferred to the additional unit. After that again

ρ The result of the operation has been transferred or data has been input to the standard unit, the

jU 35 clock frequency of the computer add-on can be reduced to a low value or to zero. With the one above

Il construction described it is possible to use the operating power of a conventional small computer from

|| j should be reduced by a few milliwatts to 1 μW, which corresponds to a reduction of 10 ³ .

ψ More precisely, the combination of the standard unit and the additional unit including the cable

If ter 13 012 for the transmission of signals from the standard unit to the additional unit, the conductor 13 011 to the

($? 40 Transmission of signals from the additional unit to the standard unit, the control unit 13 032 and the Il main operating unit 13 031, so that signals can be exchanged automatically or manually, in the same way

p like the clock pulses, are controlled by the control unit, which is extremely advantageous because it allows

jH the energy consumption can be reduced and at the same time the number of components can be reduced,

li | because the signal for the timer or for the clock pulses can be supplied by the standard unit. It is

|| 45 a status sensing block is provided, of which a status indicating the relationship between the additional unit and Iff of the standard unit indicates the status of the additional unit itself, the status of the standard unit (e.g. the status

Il a battery) as well as the status of the external environment can be scanned. Especially where

| g it is desirable to know the number of external operation elements or the number of operation states

$. It is necessary to reduce certain operational elements through the standard unit and the additional unit

H so to use together. By determining these states, it is possible to achieve a satisfactory arrangement ? '! the standard unit and the additional unit.

j | For example, the input terminal SU ₂

* ■ '? the standard unit and the input terminal Ui of the additional unit together with the operational switching element

;: | i ment of the standard unit, and the normal input signal for correcting the seconds and the input

gi 55 output signal for controlling the automatic fast-slow operation is provided by a signal for setting ;, development of the marker display of the multiple alarms. For a multiple alarm addition, the status

f; | tus of the control of the standard unit is scanned by its external control in that the information

% tion is determined, which determines the display data, and the sampled signal is used to data

fj ¹ .; to be exchanged between the additional unit and the additional multiple alarm system, which

;,. 60 stars are required. In such a case, a multiple alarm add-on is required to only detect the 'i to record data of the alarm time, which are formed by the standard unit. It is also possible that

rι control unit 13 032 so that it has the display and the time unit signal in the standard unit

can control. For example, where the data relating to the month and date to be set, using a control signal at a multiple alarm accessory to bring ten to one "point" to Aufieuch- ₆ 5, which indicates that the number displayed represents a date and a letter DATE is used to delete a colon which is used to indicate an hour. In the case of a fast-slow automatic accessory, a fast-slow correction signal is supplied to a timing pulse generator which constitutes a standard unit of time so that the timing operation of the clock can be performed

. '■■ 26th

is controlled. The signal conductor 13 042 is used not only to transmit the data, but it is also used to transmit various clock pulses and timing pulses as well as to transmit an electrical current. For example, while in this example the standard unit works with clock pulses Φ, and Φ ₂ , which have a frequency of 16 384 kHz, intermittent clock pulses Φ? and Φ $, which have an average frequency of 1024 Hz and are generated by intermittent interruption of the clock pulses Φ, and Φ ₂ with an interval of 1/16 second, are supplied to the additional unit. In this way, although the standard unit and the auxiliary unit operate at different clock frequencies, they exchange synchronous signals. This arrangement eliminates the need to provide an independent clock pulse generator for the auxiliary unit, thereby reducing power consumption because it is not necessary to use an oscillator. Furthermore, the signals Φ UCl and Φ UCl for supplying boost energy and for transmitting ekies signals for reproducing a ZüTernimpulses are transmitted from the standard unit to the additional unit. In the additional unit, the signal is rectified and amplified by a diode rectifier circuit, and the amplified output signal is fed to the display driver. It is also possible to operate the additional unit by using the boosted or raised voltage or a DC voltage which is derived from an intermediate point of the diode rectifier circuit.

In accordance with the above, a system which comprises the combination of the one shown in FIG. 4A Additional unit and the standard unit includes a number of features which are not in each of the units May be present because such a combination is a unique combination of the characteristics of both Units guaranteed.

Fig. 26 shows a basic block diagram of an example of an auxiliary unit which performs multiple alarm and fast-slow functions. For the sake of simplicity, the wiring for the digit pulses, the timing pulses, the clock pulses, the φ pulses and the timing signals, which include the combinations of two or more thereof, is not shown. Table IV shows the classified functions of the respective blocks shown in Figs. 27A, 27B and 27C. In Table IV, the main pulse feeds, labeled α , show a group of devices for reproducing or synthesizing basic pulse signals required to operate the auxiliary unit. The status scans labeled b show a group of devices for scanning different states, which offer the possibility of indirectly controlling the additional unit through the standard unit and bringing about changes in the states. The control signal generation designated by c shows a group of devices for generating a signal which determines the control of the additional unit. In some cases, not only the auxiliary unit but also the standard unit and such control signal generation play an essential role in the operation of the auxiliary unit. The gate systems or the logical combination systems, which are denoted by d , are logical combination systems which are provided in connection with main operating elements and are controlled by signals which are supplied by the main operating unit or by the control signals of the status detector, or they are main supply sources or other gate systems. The main operating systems denoted by e correspond to the device for measuring the mean frequency deviation of the time unit signal in the case of the automatic fast-slow control, while they correspond to the register circuits in the case of the multiple alarm system. By comparing Fig. 26 and Fig. 25, it can be seen that Fig. 26 shows an example of a system which is controlled by the clock pulses sent by the standard unit because the main pulse supply device 13069 is controlled by the Signals is controlled, which are supplied by the standard unit 13 010 , and because the main pulse supply device 13 069 delivers a signal 13 065, which is composed of an input signal 13 050 to the status detector device, the control signal generating device 13 063 and the main operating unit 13 064 . FIG. 26 corresponds directly to that in FIGS. 27A, 27B and 27C, so that according to Table IV, groups a, b, c, d and e, which include the blocks shown in FIGS. 27A, 27B and 27C, also include blocks 13 069, 13 062 , 13 063 and 13 064 shown in FIG.

Table IV

KJassification group No. symbol contents Outputs
(in Figs. 27A-27C) a 1430 Qi-RR-a composite digital
Playback signal Q.-Q.6 Main group 1431 Tj-RP-a Timed Pulse Playback 7ϊ "7ϋ>7Ϊ2> Tin Supply group 1451 Φ-GEN-a
WlDTH-a Φ signal form, synthesis off
Signal transmission and
Receive pulse width Φ1-Φ4
WKT. WDT. WATI,
WATO 1454 TPG-a Synthesis from timing signals
different combinations ex. Φ ^ ϋ _Η Τ _% Φ

continuation

KJassification Group No.

symbol

contents

Outputs

(in Figs. 27A-27C)

b 1410 QHAT Alarm 0 time sampling OHAT status 1411 QOH Alarm-O-time status scanning QOHER Scanning 1424 DET-DT Sampling the coincidence of EKDT Date alarm and date 1425 DET-AT Sampling the coincidence of the DETAT, QERAT Alarm time and the current Time 1427 AT-DISP-DET Alarm time display QA, 0Φ3ΑΤΙι Status scanning Q03AT1 1429 KT-DISP-DET Current time display QKT Status scanning 1482 DT-GATE Fast-slow operation, DGOK which the date sampling certainly C. 1402 SB-c Output control SB · ,, SB ₂ , C «3 1403 SA-c Input control SA steering 1420 MAN-SHIFT-C manual shift Mc + I Ms + 2 signal Count Φ generation 1426 SRG-STOP-C Register stop Tax? 1452 MARK-SET-C Setting the marker ALIu ALI ₂ , ALDu ALD ₁ 1483 ANALYSIS-C Fast-slow adjustment pi to determine the operation d 1401 OUT-CONT-a Data output gate DOUT, there. Gate system 1408 CLOCK-CONT-d Clock gate Φ, #, Φ ₂ # Combined with 1409 DATA-DOMOD-d Input detnodulation gate DIN 1, DIN 2, DIN 3 Main component 1407 DIU-GATE-d Data entry gate uon-ouT 1406 AL _r d Mark input gate, SRG-44S-IN 1405 AL ₇ -d Marking input gate ₂ SRG-43S-IN Gate system 1404 DT-ER-d Date data clear gate ΑΧΟ Combined with 1480 ADT-PE-d Gate for fast-slow- FSO Main component Adjustment pulse generation gate e 1490 SRG-RING-e Data storage register SRG-OUT (IIl, 121, 311, 441) Main operating system 1480 COMP-e Surgical facility Ö3.-Ö36

In describing the construction and the mode of operation of the exemplary embodiment of the additional unit according to FIG 27A, 27B and 27C, the overall function of the unit will first be explained. The additional unit has a Shift register ring 1490 with 64 bits, which is designed so that it can receive alarm time data, a group of gate blocks 1401 to 1454 including various gate circuits for control the shift register ring and a device for generating various signals for actuating the gate circuits, an automatic fast-slow adjustment block 1480 and an additional gate block 1470. The 64 bits of the shift register ring 149t can hold four alarm time data for hour and minute. It is possible to increase the number of data by adding more shift registers. It is also possible to set an alarm for a month, a date, an hour and a minute. the Alarm time data can distinguish AM and PM, and you can select either daily alarm mode, which gives an alarm at a certain time every day or you can choose the temporary one Select the alarm mode in which the iCoincidence of the set time and the current Time is sampled only once, and to activate an alarm device, while thereafter the set Alarm is automatically cleared. The setting of the multiple alarm data of the additional unit takes place in this way.

28

that the standard unit is used, so that it is not necessary for the additional unit to have an external operating element to add.

In the fast-slow system, it is possible to adjust the oscillation frequency of a manufactured as a mass product quartz oscillator element with an error of 7 x 10 ~ ⁷ without a trim capacitor or correction capacitor is used. Such a matching accuracy leads to an error of 2 seconds per month, which is smaller than the error of the oscillator which uses a quartz crystal adapted by the manufacturer. In this embodiment, it is possible to immediately set the fast and slow operations with high accuracy by taking the result of measurement of an average frequency error caused by effects of the ambient temperature, the result of the behavior of the user and the aging of the quartz -Oscillators over a week in relation to a standard clock are taken into account in the required manner.

In fact, with the clock according to the invention, a frequency adjustment can be so extraordinarily high Accuracy can be achieved by the user (to the extent that it cannot be achieved by a professional can be), which the "secondary nerve" zero reverse button in an A. interval of one week twice presses, e.g. B. in accordance with an exact time signal, as it is transmitted on the radio. Through such a measure is a compensation for the running speed depending on the week Made mistakes. It has been shown that a precise fast-slow setting made which quartz watches other than the clock according to the invention can not be achieved.

The gate circuits 1404, 1405 and 1406 are provided for the shift register ring 1490 and serve the purpose of supplying the required data in a semi-parallel arrangement in a short time, and these gate circuits are used to set an alarm flag and clear the data, as will be explained below . The output signal SRG-IU is sent from the additional unit to the standard unit under the timing of the pulses D ₁ to Z) ₁₄ during normal use of the watch. The output signal SRG-121 is used to change the number of shift pulses per time unit of the shift register 1490 under normal conditions and a status in which an alarm time has been sent when alarm time data has been sent from the additional unit to the standard unit in order to set the alarm time . For this reason, the position of the derivation of the data is shifted by one bit. The output signal SRG-441 is used to compare the month and date information, which is provided by the standard unit |

with the date alarm data stored in the shift register 1490 30 j $, while the output signal SRG-311 is used to compare the real-time information stored in the standard unit with the alarm time, which is stored in the alarm unit of the additional unit. fjj

In principle, the time system according to the invention is of a time-series type, so that it is possible to add all data to | i

process by deriving a signal from a point on the shift register ring. However, since according to the &

In the invention the clock pulse is given intermittently, it is impossible to process the information if it is not processed in parallel. Accordingly, the flow of the main alarm system signals will be discussed in connection with the main operating unit. More precisely, the data which are supplied to the input terminal DIN are supplied to the shift register ring 1490 with 64 bits via a gate circuit 1407, which controls the writing of the information into the shift register and the memories therein, and via a data demodulation block 1409. The gate circuit 1407 writes information into the shift register ring 1490 in response to an input designation signal SA supplied from an input data control block. Signals that were taken from the output terminals SRG-IU and SRG-121 of the shift register ring are used as the.DOt/r signal with the aid of a gate circuit 1401 which controls the information output, the signals being connected to the DATA-IN input of the standard unit are fed by clock pulses Φ * and Φ ₂ ⁺ shifted, which were generated by clock pulses Φ, and Φ ₂ , from the standard unit by the clock pulse control circuit 1408. It is possible to increase the capacity of the shift gate ring 1490 by adding a shift register 1494 with 64 (n-1) bits between its output terminal AXO and the input terminal AXI , where it represents a natural number.

According to FIG. 27A, 27B and 27C, the auxiliary unit receives signals from the standard unit at its clock pulse input terminals Φ, and Φ ₂ , at the data input terminal DIN, at the reference numeral signal input terminal Dn, on the display reference numeral terminal D _D. at the input terminals Φ ^ ι ^and Φυα * " ^{Γ eme} composite time control signal input, at the input terminal MSIN for a manual shift signal and at the marker setting signal input terminal UDII. An output terminal DOUT of the additional unit is connected to an input terminal DIN of the standard unit, and an output terminal D. _CL is connected to an input terminal D _CL , in this way information is exchanged between the standard unit and the additional unit via the corresponding input and output terminals.

The additional unit also has an output terminal FSO for pulse signals which set the speed of the clock, this terminal being connected to an input terminal FIN of the standard unit which uses the pulse signals to correct the frequency of their time measurement unit signals. Furthermore, the additional unit has an output terminal AXO and an input terminal AXI , which allow the installation of additional shift registers in order to increase the capacity of the multiple alarm memory in the additional unit. While a direct short circuit of these terminals AXI and AXO allows four different alarm times to be set, eight data are added by providing an additional 64 bits and 16 data are added by providing an additional 256 bits. It should be noted that for data above 16, the CONT terminal of the standard unit must be held high in order to use the clock pulses in a continuous mode.

Input and output terminals of the gates and flip-flops are also provided for the purpose of the

'; To equip the clock with the necessary flexibility. In the F i g. 27A, 27B and 27C a booster circuit 1470 is shown with a dashed line, which uses logical combination circuits with regard to flexibility. The inverters have N-channel transistors, the substrates of which are electrically isolated from the substrates of other Ksjl operational transistors. The source of a P-channel transistor is connected to V ₃₃ I. ⁵ The pulses 0UC _x uns 0UC ₂ , which are made complementary to one another by a gate 14 703

⁽ Clamped by the combination of a capacitor Cl and a diode Dl, or by a combination of a capacitor Cl and a diode DI. This is done in such a way that their high levels become equal to the level V ₃₃ I. The in this way clamped output pulses are supplied to the output terminals of the inverter, which are connected in a positive feedback in a crosswise connection such that ¹⁰ a negative potential is developed equal to the width of the pulse voltage on the negative power source side of the corresponding inverter, the source potential V ₃₃ I of the field effect Transistor at his

; Basis is so that a negative potential V ^ l is supplied, which corresponds to 2 K ^ l. The output is ^ 2

\ | able to provide a boosted or boosted voltage to the display driver circuit, and

H with an efficiency of more than 95%.

I ^L5 Ysw denotes a clamp which is used to control a part of the function of the auxiliary unit,

γ and Ysw denotes a terminal which is used to set the initial conditions of a part of the

j $ to set the counter in the additional unit. While the Ysw terminal, when turned to a high level,

fi , creates the possibility that the alarm time of the month, day, hour and minute and the

i-i those of the usual hour and minute can be set to the same time, then enables them when they are on

t ^{20 is set to} a low level, the setting of the hour and minute alone. The terminal Xsw is used

; ■ to determine the starting position of a static electric servo system, which determines the speed

H controls the clock. If the terminal Xsw is held high for a short period of time,

'|; the counts in the counters that make up the servo system quickly reach zero, and the positive ones

5 and negative control areas become substantially equal to each other in width with respect to this point. I ²⁵ The signals fed to terminals Φ _χ and Φ ₂ as well as DIN occur in a pulsed manner, ie intermittently when the CONT terminal of the standard unit is at a low level, and they occur continuously when this!? ■!; · Not the Case is. The signals fed to terminals Du, 0UC _x and 0UCi are always continuous. the

_j? Additional unit is designed so that it can be operated properly, regardless of the mode

£, in which the signals 0 _X , Φ ₂ ^and DIN occur.

U 30 Such data, which are fed from the standard unit to the DIN terminal of the additional unit, are

j- fed to a shift register ring circuit 1490 via a data demodulator block 1409. The data

■ 'demodulator block is used to reduce the influence of the display modulation from the supplied by the standard unit

• i'i; to delete the th signal.

■ ij The data are fed to the shift register ring 1490 via a gate 1407, which is controlled by a

I 35 control signal S / l is controlled, which is generated by a data input control block 1403. The output

f ge SRG-Ul OUT and SRC7-121 OUT of the shift register ring circuit are in the form of an output

| s DOUT recorded via an output gate 1401. The output gate 1401 is activated by control signal SB 1

6 and SBl controlled, which are fed from a data output control block 1402, while an output signal SB 3 of the control block 1402 in the form of an output signal DCL is applied to the deletion Ji; 40 of the data in the standard unit to control.

I The shift register ring has shift registers with a total of 64 bits and is able to store four different

to save the alarm time data.

I The clock pulses Φ, and Φ ₂ with different phases are converted to the by a clock control circuit 1408

fe pulses Φ * and Φ ₂ ⁺ diluted, which are then fed to the shift register ring 1490 to reduce its

% 45 operation to control. The clock control circuit 1408 is controlled by a signal CONT Φ , which the through

The output of the clock pulses is monitored. The control signal CONT Φ is generated by a manual shift block 1420

S generated.

¹ I; The input signal D _n controls the display of the month and the day of the month and the week. That

nt date can be displayed constantly by connecting the signal D _{n to} an input terminal DD of a display driver

V 50 circuit is supplied, which is provided separately.

? · :. ' A Qi reproducing circuit 1430 is adapted to receive composite digit signals from the

: £ signals 0UC _x and 0UC ₂ , while the signal D _{n is used} as a reference for the digit pulse.

j? composite signals, are represented by Q ₁ = D ₁ + D _{1 + x} , where / = 1,2, ..., 16 and Qij = Qi- Es is closed

ψ note that the 0UC ₁ and 0UC ₁ signals were originally used for boosting or amplifying purposes

If ': 55 were generated.

i "i A reproducing circuit 1431 for Tij reproduces a signal which, with the increasing part of the time

n control signal 7J is synchronized by the signals 0UC ₁ and 0UC ₂ and synthesizes timing signals T ₂ , TJ,

'i; Tg and T _{x of} different phases in response to clock pulses Φ _χ and Φ ₂ , on the basis of a

■ 5f application of the shift register reproduced signal. The timing pulses T _x to 7g generated in this way

■ ■ { 60 were reproduced using the clock pulses Φ _x and 0 ₂ , occur intermittently, which is

; J sen circumstances, the clock pulses 0 _X and Φ ₂ do. Circuit 1431 also outputs composite time

; ■; Control pulses 7J ₂ and Tu again. Here the relationships Tx ₂ = T _x + T ₂ and T _u = T ₂ + ζ apply, and since the time

(I control pulses 7J to ξ from the composite timing pulses 7J ₂ and T ₂ * are reproducible, can

■ the interconnection within the integrated circuit can be significantly simplified. A timing signal generation

' ¹ ^ 65 rator TPG-a 1454 is designed in such a way that it outputs any signals from reproduced digit signals Qi.

^: ■; selects as well as from the timing signals 7j and the timing signals φ _χ to j> ₄ , which will be discussed below,

, '; and also from the clock pulses Φ, and Φ ₂ , so that a logical product signal such as φ-J) _n T% 0 _X synthesized

; ■; is assembled or assembled.

i1 30

The timing of the signal exchange between the standard unit and the additional unit under different conditions is controlled by control signals W _KT , W _DT , W _AT \ and W _AT0 , which are generated by block 1451.

1428 denotes a circuit for generating timing signals φ for synchronization. The output data of the standard unit are subjected to the display modulation in order to extend the blinking or flashing at IHz if there is a coincidence of the correction numerals or the alarm, so that a disturbance is caused when the information is read out on the basis of the blinking phase. Since this can be prevented by only providing the standard unit with an additional data output terminal DATA OUT , which is free from modulation, this terminal can be provided in addition to the data output for display purposes. In the illustrated embodiment, the data output terminal, which is used exclusively for the additional unit, can be omitted because this saves output terminals in the integrated circuit, and instead a signal φ ₂ , which is synchronized with the falling part of 1 Hz, and a signal q> _t2 , which is a product of φ ₂ and g> _} , synthesized or combined in that the signal g> _{3 is formed} from a memory cycle width and synchronized with the falling part of a 2 Hz signal of the timing data by selecting a phase which is free from the influence of blinking or flashing. If the signal ψ} as the term of the logical product is multiplied by the sampling pulse, which is used to determine the content of the data signal, the information can only be read out at a high level of q> s , so that interference in this way are avoided. The signal p ₄ is delayed by one storage cycle with respect to the signal φ _3.

A circuit 1429 of a circuit KT-DISP-DET-b for sampling the state of the current time display is designed in such a way that the data which coincide with the month and the day of a month-day alarm are deleted, and only if the current time is displayed on the face of the watch to find the relationship DD = D ₆ .

A circuit 1427 of a circuit AT-DISP-DETECT-b for sensing the state of an alarm time display is responsive to the alarm setting mode of the watch, and when this mode is detected, empty data and controls of the direction of signal transmission between the standard unit and the auxiliary unit are given. The circuit 1427 supplies two signals, namely QSATX and QSATl, which have a phase shift of a memory cycle with respect to one another in order to sample the memory cycle immediately after the display mode has been switched to the alarm time, and it also forms a signal QA for the display AT from the logic Product of the two signals. The circuit 1427 indicates empty data when the signal QpSATX, QpSATl is high. The signals QSATX and ASATl are fed to a circuit for manual shifting, which is labeled MAN-SHIFT , to shift the clock control signal, and also to the block for generating the signals SA and SB to switch the input and output data .

An alarm time coincidence detector circuit AT-AET-bX41S is used to determine the coincidence of an alarm time, which is stored in the additional unit, with the current time, which is supplied by the standard part. The circuit AT-AET-b compares an output signal from SRGSXX with the current time, and in the event of a coincidence the alarm time, which is stored in the corresponding shift register, is cleared immediately using a signal QERAT within the same storage cycle. The coincidence signal labeled DET is also fed to a block SRG-STOP in order to thereby stop the operation of the shift register.

In the same way, a month-day alarm coincidence detector circuit compares month-day information with corresponding alarm data in normal time display mode. A coincidence signal from this one Circuit deletes the marking that connects the alarm time data with the above alarm data, by using gate 1402.

The circuit SRG-STOPX416 is related to an output of the circuit 1425 and an automatic specification of an empty address. The stop control signals contain an alarm time coincidence signal DETAT and an automatic index control signal Qq> 3ATX ■ QpSAT1, while the stop trigger control signals consist of a signal 6051 and a sampling signal OHAT for an empty address. With regard to the coincidence in the alarm time, this means that the transmission of the alarm time signal to the standard unit is interrupted by 1 minute on the side of the additional unit. The standard unit functions in a corresponding manner for this one minute, namely in the case of a clock which triggers a single alarm.

A gate 1410 of OHÄT-b is designed so that it detects sin output signals of an empty address of the circuit SRG-STOP . If an empty address is found in the alarm setting mode, the standard unit modifies the corresponding alarm data output signal to the cleared state. When the auxiliary unit receives the corresponding erased data and transmits it to the standard unit, an error may occur in the upper digits of the standard unit because the four bits of the minute digits are all high. To avoid this, a gate 1411 is used, for example a gate like gate 1405 in the additional unit, which clears the 10-minute digit of the corresponding data to zero.

A manual shifit circuit MAN-SHIFT-c 1420 feeds a clock pulse control signal to the clock control block _ω 1408 in order to change the relative synchronization of the shift register ring circuit 1490 and the shift register circuit of the standard unit. The manual shift circuit 1420 feeds a control signal MS 12 to an output control circuit 1402 in order to create the possibility that new data can be transferred manually from the additional unit to the standard unit. A SIM terminal is connected to an alarm monitoring switch.

A marker setting block 1452 is designed so that the daily, temporary, monthly and time of day as well as an alarm of the additional alarm data can be set, and it sets these markers depending on the number of changes in the level of the input signal UDII.

speaking a. The marker set block 1452 is also operable to set the extra alarm time clears

A signal MS © Hrd from the manual shift block 1420 is supplied to the marker setting block 1452 to thereby zero the count in a counter for the above marker setting, whereby the marker setting operation can be easily carried out with accuracy.

An example of an additional multiple alarm circuit is shown in FIGS. FIGS. 28A and 28B illustrate a sliding register, which is shown in the middle part of the drawing, has 64 data hip-hops, which are labeled 111 to 448. The shift register ring is shown interrupted by two terminals Ax ₀ and Ax \ to provide the ability to add additional shift registers 1494 as needed. The terminals Ax ₀ and Ax \ are connected directly if the 1494 shift registers are not available. An output DOUT is connected to the DATA-IN terminal of the standard unit, while an output DCL is connected to the DATA CL terminal (see FIG. 8). The DATAOUT terminal of the standard system is connected to a DIN input terminal of the additional unit. Reserve signals, which are available in connection with another additional system, are designated by Φ ₂ ⁺ and CONT <P. There

the signals DIN, Φ ₂ and Φ ₂ occur intermittently, appropriate precautions must be taken to distinguish when the additional unit is addressed in combination with the standard unit. The additional unit is designed in such a way that it can normally be actuated, regardless of the signal mode, ie regardless of whether there is an intermittent or a continuous signal mode. The input data from the outside are converted into a signal DINl by a corresponding waveform shaping.

forms by two inverters which are present in a data processing block 1409, and they are fed to the shift registers via the input gate 1407. The gate 1407 is controlled by a control signal SA which is generated by the data input control block 1403. The input data is written with the high level of the signal SA and circulates in the ring of shift registers with a low level. An output signal of the shift register ring is taken from the output of the shift register SRG-111 or SRG- U1 and applied to the output terminal DOUT via the output control block 1401, from where the signal is applied to the DATA-IN terminal of the basic timing block 203. The output gate block 1401 is controlled by output control signals SS1 and SB 2 , which are generated by the output control block 1402, respectively. Data for the display of the markings are generated by the output control block 1401 and also transmitted from it. The data for the marker display is information prepared in a special way, which is continuously fed to the data elements only during the alarm setting, whereby it remains permanently at the low level of the marker _{digits , or it is the data D 8} and D i6 in the basic timing system, ie Data elements D _i6 T ₂ and 0 ₁₆ 2J, so that a practical setting of the alarm data is thereby facilitated.
While the month-day data of a month-day alarm is set as explained below, a data signal D ₁₆ T ₂ for displaying the data mark is supplied to the input terminal DIN of the standard unit 10 to indicate that the data is present is monthly-daily data.

The data component Z), ₆ 7J is structured in such a way that when a monthly / daily alarm is set, it can be confirmed whether the shift register of the additional unit can accept two alarm data. When setting a monthly / daily alarm, an alarm time is set first and then the

• Set to monthly-daily data, which are linked to the alarm data. In this context it is essential to know whether any addresses are open for setting the month-day data. In view of the fact that in the system according to the invention the alarm setting flag is turned on when an alarm time is set, an alarm setting flag is supplied to the terminal DIN of the standard unit 203 by means of the timing signal from Di ₆ T ₄ , even in the Status in which no alarm times have been set, the alarm setting flags thus remaining off, indicating that no month-day data can be entered in the following addresses because they already contain other alarm times.

The shift register ring 1490 is driven by clock pulses Φ, ⁺ and Φ ₂ which are supplied by the controlled clock pulse generator block 1408. The clock pulses Φ, ⁺ and Φ ₂ are supplied by the clock pulses Φ | and Φ ₂ , which are supplied by the standard unit in order to control the relative phase between the shift register ring 321 and the shift register ring (64 bits) of the standard unit 203. The thinning or narrowing of the clock pulses occurs when the signal CONTΦ is low . the output control signal SBl, which is generated by the output control block 1402 is formed se that it controls the transmission of a signal SRG-lll-OUT by the gate is opened 1,401th

if, in the normal mode, data are transmitted from the additional unit 12 to the standard unit 10 according to the embodiment according to the invention. On the other hand, the signal 552 is designed so that it transmits the data displayed in the event of monitoring or setting of an alarm from the additional unit to the standard unit. The control signals SB 1 and 552 are derived in phase by 4 bits with respect to each other. The signal 55 3 represents the logical sum of the signals SB 1 and 552, and it is used to delete the data which are supplied by the additional unit and are stored in the shift registers of the standard unit 10. In the shift register ring 1490, there are gates 1405 and 1406 by which identification tag data are set using the setting element: the standard unit, these data being input into parts corresponding to D ₁₆ T ₂ and Di ₆ T _{4, the} remain unused while setting alarm data. Since, in the illustrated embodiment, processing on a time-series basis does not find sufficient capacity due to the thinned or narrowed pulses, time-parallel processing is partially carried out by the gates 1405 and 1406 with a view to setting the identification mark data. With 1404 a husband is: denotes, which is used to delete the month-day data at 12 noon of the day on wel

chem the month and the day have coincided with the corresponding alarm data.

It is useful at this point in the description of a preferred embodiment to describe the relationship in explain the synchronization between the standard unit and the additional unit.

The shift register ring 1490 of the additional unit and the shift register ring of the standard unit do not always work in full synchronization with one another. The shift registers of the standard unit require 1/256 see for a single cycle, and thus they cycle 256 times per second. The auxiliary unit's shift registers 1490, on the other hand, rotate ten times per second. Thus, the standard unit and the additional unit are synchronized in their cycle only once every 16 cycles of the standard unit. If you look at the standard unit from the side of the additional unit, the operation of the standard unit for the 15/16 second, in which the shift registers of the additional unit are not in circulation, takes place in a short time interval, which is between two clock pulses Φ, and Φ ₁ lies in the addition unit, as can be seen on a "sequential axis of the coordinate" of the auxiliary unit for this reason, and because Φ + φ ₁ are at a low level, in the above-mentioned interval are determined by the auxiliary unit no Difficulties caused The "sequential axis of the coordinates" refers here to the axis of the coordinates, which results when the relationship in the course of logical processes of a sequential logical system is plotted according to the sequence on the basis of a measure which here is not the absolute » Second «, but the number of clock pulses that drive the serial system. If the additional unit is viewed from the side of the standard unit, the data transmission from the additional unit to the standard unit can be carried out synchronously, although the former unit works in an intermittent manner because both units work with synchronized clock pulses at least during the operation of the additional unit. In the example shown, new alarm data, which are stored in the additional unit, are transmitted in the normal state only once in each storage cycle of the additional unit to the standard unit, ie in 16 storage cycles of the standard unit. The alarm data continues to circulate in the standard unit and is fed in this way until the subsequent data reaches it, ie for 15 storage cycles. When the COAT terminal of the standard unit 10 is grounded to attain a high level, the clock pulses from the standard unit are continuously supplied so that the standard unit and the auxiliary unit enter into fully synchronous operation. However, this is not disadvantageous for the functioning of the system. In other words, the relationship between the standard unit and the additional unit can be viewed under the scale of the clock pulses, except for the marker formation in the output control block 1401. In this exceptional part, marker signals in the alarm setting mode are transmitted from the additional unit to the standard unit, namely under the timings of Z) ₁₆ ξ and Z) ₁₆ ZJ, without a differentiation of the mode of occurrence of the clock pulses is present, the relationship in the signal transmission between the additional unit and the standard unit, when viewed from the first side, variable is what depends on the mode of occurrence of the clock pulses on the sequential axis. However, the above relationship remains unchanged when this part is viewed on the timeline.

In the standard unit, as shown in Fig. 1IA, the output signal Q _{1 of} the shift register, which is fed to the adder, is used as a reference signal, and this time-series signal Qi has its timing which is determined from Z) ₁ to Z) ₁₆ , the digit for 1/256 see is assigned to the time control signal Z) ₁ . The signal Q ₁ has a delay of 4 bits in the detector device of the upper digit, which is passed through gates for deletion or for the input of an external data signal, wherein it is generated in the form of an output signal DATA-OUT after it is in a Data modulator was delayed by another 4 bits. As a result, the data output signal DOUT of the standard unit is delayed by two digits with respect to the digit pulses of the standard unit, and the data input signal DATA-IN and the data erase input signal DATA-CI of the standard unit are each delayed by one digit. In the illustrated embodiment, the digit signal and the timing signal in the additional unit are denoted by the same indices as in the standard unit, and the digit signal Z) _{16 of} the additional unit is synchronous with the digit signal D _{16 of} the standard unit in terms of absolute time. The standard unit transmits 16 digits of data from the 1/256 sec digit to the alarm mark, which corresponds to the 16 digits of the additional unit from the digit signal D] to the digit signal Di to Z) ₁₆ . Attention should therefore be paid to the fact that the indices of the digit pulses in the additional unit differ by two digits from those of the standard unit when processing common data. The delay is one digit when data is transferred from the optional unit to the standard unit. This means the timing

WATI = Du + D ₁₆ + D ₁ + D ₂ ,

55 whereby an alarm data signal is fed from the standard unit to the additional unit, and the time control

WATO = Z) ₁₄ + Z) ₁₃ + D _n + D _n ,

whereby data is transmitted from the additional unit to the standard unit, both of which are from the timing controller

D _n + Z) ₁₄ + Z) ₁₅ + D ₁₆

the alarm data of the output signal Q ₁ differ in the standard unit.

Below are various ways of transferring information between the standard unit and the additional unit.

(1) In the normal state, alarm data is transmitted from the auxiliary unit to the standard unit. the Alarm data is replaced with other alarm data in each memory cycle of the auxiliary unit.

(2) In the alarm setting mode (in which the alarm time data is displayed), the shift registers of the standard and auxiliary units run synchronously. The same set of alarm data is then repeatedly transmitted and displayed by the standard unit. Since the same data stream is transmitted to the additional unit and the display unit and the data is normally modulated at a low frequency in order to display some of the data in a flashing manner, these transfers only take place when the synchronization pulse q> _{} is} high. φ ₃ has a frequency of 2 Hz and - as shown in FIG. 53 - only has a high level when there is no blink modulation.

ίο (3) In the alarm data setting mode (with multiple alarm options) it is possible to change the alarm data displayed in order to display all the alarm times stored in the additional unit. This is done by pressing the manual slide switch, whereby the alarm time stored in the standard system is transferred to the additional unit, to its shift register synchronously with Ji ₃ . Then the data in the shift register ring of the additional unit are increased by four words with respect to the time sequence of the standard system.

stems and transferred once to the standard system at MS®. The two shift register rings

are then set synchronously again in the following storage cycle. So it just becomes a new set of Alarm data displayed continuously If the slide switch is pressed continuously, it repeats itself the above procedure so that a new alarm time is displayed every half second.

(4) When the alarm time coincides with the current time in the normal state (current time display mode), the data transmission from the additional unit to the standard unit is interrupted for one minute.

chen, and after this one minute has passed, the data transfer will be in the same direction resumed.

(5) When the system changes its state from the normal state to the alarm setting state, an empty address of the optional unit data (data at zero o'clock) is first indexed. If there is an empty address in the auxiliary unit data, the shift registers of the auxiliary unit are turned off so that the empty address data is synchronized with the standard system, whereupon the empty address data is transferred from the auxiliary unit to the standard unit. As a result, alarm indication data is transmitted from the standard unit to the auxiliary unit in synchronism with the timing pulse φ ₃ . This is a function built into the system to give an alarm signal quickly and

easy to adjust. If no empty addresses are found, the automatic indexing operation will run stopped in 0.5 seconds, whereupon the synchronized data from the additional unit to the Standard unit are transmitted. In this state, the system is in an alarm data waiting mode. Thus, a manual shift or an automatic shift is used. For an automatic shift, the manual shift input terminal 266 (Fig. 18) is open put a high level, continuously for more than a second, from where the Alarm data from the auxiliary unit one at a time at a rate of one data record per second are displayed, shifting being stopped when the input terminal goes low Level is brought back.

(6) When the system is in its operation mode, which is changed to the normal state by an alarm indication, the signal transmission from the auxiliary unit to the standard unit is carried out after alarm data is transmitted from the standard unit to the auxiliary unit in synchronism with the timing pulse φ ₂ .

While in the above description the signal transmission has been carried out in such a way that it takes place in synchronism with the timing pulse φ _ζ for the purpose of avoiding the influence of the blinking or flashing of the data, such synchronization with the timing pulse φ _{3 can} except Care should be taken if a DATA-OUT terminal is available which is free from the influence of the blinking or flash modulation , so that it is independent of the DATA ^{A -OUT terminal.} In the illustrated embodiment, the blinking data is used solely for processing because it is desirable to have the number

so to diminish the output signals of the standard unit. Furthermore, additional shift registers can also be incorporated in the illustrated embodiment. In the event that a significant number of shift registers are to be added, the CONT terminal of the standard unit is connected to the unlocking terminal ULO or ULT of the switch in such a way that a number of data can be set by using continuous clock pulses only during an alarm setting and, in the normal state, the time error (on the order of one second) required for sampling an alarm time coincidence can be used to serve as intermittent clock pulses. This results in a saving in the electrical energy used. Alternatively, continuous clock pulses can only be used for one second on each revolution in one minute in order to save electrical energy. In addition, the use of a computer, if it is desired as an add-on and is operated with intermittently occurring clock pulses, will only permit a low computing speed and thus be unsustainable in practice. A mode of operation at high speed and a lower energy consumption can, however, be achieved when using a computer in that continuous clock pulses are only supplied when the computer is in operation or only during the calculation. The fact that the clock pulses can be controlled to occur either intermittently or continuously makes the basic timing system of the present invention extremely advantageous.

The following is a circuit block for providing a signal to operate the shift register ring described.

According to FIGS. 28A, 28B and 28C, a signal ϋΟΝΤΦ, which is fed to the clock control block 1408, is locked by a clock pulse £ Φ _ι so that it has a delay which is slightly shorter than 1 digit. The logical product of the delayed signal CONT0 and the signal Φ is generated as a signal Φ ⁺ without peak noise occurring. In a similar way, a signal Φ {is generated which has a slight delay in relation to the signal Φ ₂ ^+. The signal CONT Φ must therefore be a signal which leads a digit in relation to the timing at which a clock pulse is to occur. This signal ΟΟΝΤΦ is generated by the manual shift circuit K20.

The input terminal MSIN of the manual shift circuit 1420 is connected to the terminal SU ₂ or SUT of the standard system or to an alarm monitoring switch for exclusive use at the terminal MSIN , so that the circuit 1420 operates in connection with the switching operation in the standard unit Every time the input terminal MSIN is brought to a high level in the alarm data display mode, a manual shift signal MSl t having a width corresponding to about one memory cycle is generated in synchronism with the timing pulse q> ₃ , whereupon the signals MSI t and MS3 1 are generated in succession at intervals of one memory cycle each These signals are generated in the manner illustrated in Figure 38. Since the terminal MSIN is continuously held low for more than one second , the shift signals MSl t to MS3 1 occur one after the other once per second. The generation of these signals is immediately interrupted. after the level of the terminal MSIN is changed from a high level to a low level. The clock pulses that have passed through the gate circuit 1408, which is controlled by the signal ΟΟΝΤΦ , appear with a timing which in the normal state is 12 bits away from Οη to D ₂ via Z) ₁₆ , which in the alarm display mode is 4 bits from D ₁₅ until D ₂ is removed via Z) ₁₆ , which is 4 bits _{removed from Z) 14} to Z)] in the following one memory cycle, 8 bits are removed from D _n D ₁ in a subsequent one memory cycle and which is then 4 bits from D _i5 to D _{2 is} removed. Because the signal ΟΟΝΤΦάό. must be one digit ahead of the occurrence of the above-mentioned clock pulse, it is generated by a synthesis or combination of the digit pulses, the indices of which in the number were reduced by one. In the normal state, the clock pulses, which occur in the shift register ring in the additional unit, are missing 4 digits out of a total of 16 digits, so that the data between the standard unit and the additional unit differ by 4 digits or according to an alarm data record with regard to a storage cycle of the clock pulses, which are created by the standard unit. As a result, new alarm data are progressively transmitted from the auxiliary unit to the standard unit. Assuming that the status of the system is changed from normal display to alarm display, the auxiliary unit's shift registers can be viewed as rotating in the normal current time mode at a rate three times that the one in the alarm display mode. Thus, the data of the auxiliary unit which is synchronized with the timing pulse q> _} in the alarm display mode is also synchronized with the timing mode q> i in the normal mode. It follows that when the normal state is switched to the alarm display in synchronism with the timing pulse p ₃ , the alarm display data in the standard unit are synchronized with the corresponding alarm data in the additional unit. If these data are transmitted to the additional unit synchronously with the timing pulse <p _} , namely after a correction or setting, the corresponding data are also corrected or set in the additional unit. If an empty address is detected in the additional unit by the gate 1410, whereupon the data circulation in the shift registers is interrupted, and after the data representing the empty address has been written into the standard unit, the data of the empty address from the standard unit has been transferred to the timing of φ _{3 is} transmitted to the additional unit. In short, the correspondence between the alarm data in the standard unit and that in the auxiliary unit is established within 0.5 seconds, which is the frequency of the timing pulses φ _} when the normal state is switched to the alarm display. The switching of the data transmission paths between the standard unit and the additional unit, which result from a change in the operating mode, can therefore take place without destroying the alarm data that were previously set in the additional unit. When the alarm time data displayed on the standard unit is corrected, the data which is stored in the auxiliary unit and which corresponds to the alarm time is also corrected through data transmission from the standard unit to the auxiliary unit. If the manual shift is made for the purpose of setting another alarm time after an alarm time is set, the alarm data set in advance in the standard unit is transmitted to the additional unit under the timing from D _is to D ₂ , in synchronism with the timing pulse p ₃ , and then the data corresponding to an address following the one in which the previously set data is stored is transferred from the auxiliary unit to the standard unit under the timing from D _H to D _x in the immediately following storage cycle of the additional unit. In a further memory cycle of the additional unit, which follows the above cycle, clock pulses corresponding to a data record or 4 digits are added in such a way that the data in an address following the previously set alarm data are matched with the alarm data in the Standard unit are brought into agreement, in response to the following timing pulse p ₃ and synchronously with it. Since ω the alarm in the standard unit has already been delivered with the data from the additional unit in response to the manual shift signal MSl t, the same data are stored in the standard unit and in the additional unit, which correspond to one another. The indexing of the empty address, which was shown and described in this embodiment, proves to be particularly advantageous when the number of alarm data is increased. In particular, when additional shift registers are installed and the status of the system is changed from the normal state to the alarm setting state, a status of an empty register is immediately displayed to prepare for the alarm timing, thereby enabling a new alarm timing to be set quickly. If the shift registers with alarm data

If the data are filled in, unnecessary data is also selected and processed manually or automatically Shift reset. This process of indexing an empty address is limited to the Deletion of initial values in various additional units possible, including a hemadynamometer and a calculator, and it can be easily carried out by a switching signal from a normal State is determined on an additional unit.

Fig. 55 shows relationships among output clock pulses (Φ ,, Φ ₂ ), clock pulses (Φ *, Φ ₂ ) occurring in the normal alarm mode and the manual shift mode, output data of the standard unit, and input and output data of the auxiliary unit.

A marker setting block 1452 is adapted to generate control signals for processing alarm time data and includes a control input terminal YSW. If this has an "H" level, date alarm times can be entered, otherwise hour or minute alarm times can be set. A counter provided in the block is operated by a signal (/! »//, which here comes from the SUl terminal of the standard system. With each transition from L to Η level of the UDII signal, the bit sequence of the outputs ALIl changes over time, alil and Aldi, as can be seen in Table V. These signals are used to lock or data for the gates 1405 and 1406 of the shift register ring 1490 set to. the bit input at the time D ₁₅ T ₄ means by Aldi that previous alarm time data, directly after the following date data: The bit D ₂ T ₂ set by ALD 1 means that a symbol indicating date digits is to be displayed when this data is displayed.

Table V

0 T ₂ Ά T _t Ά D ₂ T ₂ I. 0 S. ALD count 0 ALDI ALD Ö: Data entry 0 0 0 0 0 0 0: 0 0 1 0 0 0 0 ! Ö Oj 0 1 0 0 0 0 ok 0 2 0 r
1 : --- τ
1 : 1 1 j 1 0 0 ALI 3 0 ALIl ALIl 1 data 0 0 0 0 0 0 1 0 activation 0 0 0 0 0 0 1 1 0 input 1 0 0 0 0 1 data 0 2 0 1 0 0 1 0 3 enterable data set

Explanation 1: H level
0: L level

clock pulses, which only correspond to 4 digits, are fed to the shift registers of the additional unit while an alarm time is being set. In order to set a marker that extends from a first data set to a second data set, the clock pulses are fed to the shift registers at various points under the control of the timing signal from D ₂ with respect to the currently displayed alarm time _{data, the timing of Z) 15} with respect to the data is located in the following address. The signal QERAT, which is fed to the marker setting block 1452 , is designed in such a way that it cancels the alarm time in the additional unit which has coincided with the current time in the standard unit. When the alarm data address is Jeer and when it is zero o'clock, data is transferred from the auxiliary unit to the standard unit, with the 1-minute and 10-minute digits being undesirably modulated to erase the minute digits. The signal QOHER prevents this by deleting the minute-digit section where the data are suppressed if they are transferred from the standard unit to the additional unit by manual shifting.

In FIGS. 36 and 27B, 1451 denotes a gate or a logic combination circuit which is used to determine the widths of the timing pulses which are used for data transmission between the additional unit and the standard unit. As can be seen from the circuit arrangement in FIG. 27B can be seen, the signals WATO and WATI with the timing from Z> _M to D ₁ and from D ₁₅ to D ₆ are only generated when clock pulses are supplied by the standard unit. On the other hand, the signals WKT and WDT determine the timings at which data is transmitted from the standard unit to the auxiliary unit, and they are derived from a composite digit remote pulse

derived, which in turn is composed of continuous boost pulses Φ ZZC ₁ and Φ [/ C ₂ . Thus \

the signals WKT and WDT are free from the influence of the intermittent clock pulses. These signals WKT and WDT are each used in continuous form, since no problems arise from the point of view of the circuit arrangement.

Denoted at 1427 is a circuit which is used to scan the alarm display mode. The status of the alarm display can be determined by comparing the signals DD (which numerical signals are and for which D ₁₄ = DD and Df, = DD applies in the alarm state or in the normal state). However, because the changes in the signal transmission between the additional and the standard unit when switching from the normal display to the alarm display must be timed by the pulse p ₃ , as already discussed above, the operating mode is initially activated by a signal p ₃ D _X iT% Φ \ sampled and then read out after locking by a signal in a signal Qf ₁ ATl, so that interruptions in the switching timing of the signals between the additional unit and the standard unit are free from the influence of the display switching sampling outputs. The signal Qp ₃ ATl is in turn locked and read out by a signal p ₃ D ₃ ZJ Φ \ in order to deliver a signal Qp ₃ ATl , so that a signal is formed which is synchronous with the pulse p ₃ , but with respect to the signal Qp ₃ ATl lags behind by 0.5 seconds. The signals Qp ₃ ATl and Qp ₃ ATl are combined to form a logical product QA , so that the signal changeover from the combined additional and standard system in 0.5 seconds after the actual changeover from the normal current time display to the alarm time display is completed. The signals QA, Qp ₃ ATl and Qp ₃ ATl are used in the corresponding blocks 1420 (manual shift), 1402 (output control), 1403 (input control) and 1426 (shift register stop) which participate in the signal switching operation.

With 1429 a circuit is referred to, which is used to sample that the display of the normal instantaneous Time, this circuit is constructed in the same way as the alarm display sampling circuit except for timing.

Furthermore, 1425 denotes a circuit which compares an alarm time setting in the additional unit with the current time which is supplied by the standard unit, and which deletes the corresponding data in the additional unit in the event of a coincidence. In order to erase the corresponding data in the same memory cycle as when the coincidence was sampled, the comparison should be made under the timing from D ₁ to Z)] O in the normal status while current timing information is being transmitted from the standard unit, assuming that the deletion takes place at the timing from D ₁₅ to D ₂ in the normal status. For this purpose, the flip-flop, which was set by the signal QA · Q ₄ according to FIG. 14B, when determining a difference between the data input signal from the standard unit and the signal SRG-3U OUT via an exclusive OR gate in the Time control from WKT or Z) ₇ to D _w reset. However, since the flip-flop is not reset if the two data sets or the times are the same, a logical product is formed from the flip-flop output signal and the signal, which has a width of Z) _{] 5} to D ₂ , or WATI is applied to gate 1452 as an alarm data clear signal.

A month-day coincidence sampling gate labeled 1424 is similar to the alarm coincidence detector Built in 1425. However, since the time control ξ the marking number of the month-day data on a If the level is high, the conditions necessary for the coincidence between the data from the standard unit must be met and the data stored in the auxiliary unit are required, including the conditions that

SRG-Ul OUT- Z) ₁₄ ? Φι

is at a low level. When deleting the month-day data in the additional unit by the coincidence signal, the data in the following address have their sections, which correspond to ZJ (which indicates the connection with the month-day data) and % of the marking number, deleted in this way that the alarm time associated with the month and day becomes temporary alarm time data which can be compared with the current time. When comparing the time stored in the additional unit with the current time, the marking of the month-day data (a high level at T ₂ ) and the month-day connection data (a high level at ZJ) will never coincide with the current time since all values T to $ in the marking part of the alarm time data in the additional unit are compared with the low levels at Tj "and % of the data supplied from the standard unit and with those at ξ and Zi which are set in the additional unit _f

At 1426 a shift register stop block is referred to, which is designed such that it stops the operation of the ψ

Holds shift register in the auxiliary unit for one minute, during which the standard unit stores the alarm data in the event that an empty address is indexed in the auxiliary unit and a coincidence occurs in the alarm time in the normal status. As for the indexing of an empty address, the flip-flop is set when the time from zero o'clock is within 0.5 sec, which is an interruption between the normal display and the alarm display, and it is reset when the signal Qp ₃ ATIaUf goes high. The flip-flop for stopping the shift registers is also controlled under the timing D] ₀ Tg Φ _{2 of} the «> signal DETA T (supplied by the circuit 1425) in the normal state. An output signal from the flip-flop is latched by a signal D ₃ % Φ \ in the following memory cycle of the additional unit, and it is transferred to the manual shift block. When determining the coincidence between the alarm time data and the current time data, the clock pulse clears the alarm data which are stored in the additional unit, whereupon the shift registers in the additional unit are stopped. One minute after this point in time, a signal Q ₉ 6o5T (which represents an interruption in the minute digits) is received via a circuit 1483, whereupon the flip-flop 1426 is reset in order to be able to resume a circulation of the data in the shift registers . if

The data processing block 1409 forms a data input signal from the standard unit to the additional unit and forms signals DIN1 and DIN1 by the circuit which is illustrated in FIG. 14B. The signal DINl is equal to the input data. A modified data signal is fed from the input data to the marking part of the current time for display purposes, so that the data which is the actual

^s indicate time, are only effective when 7j "(a timing which indicates PM), and the other signals T ₂ to 5 must be at a low level. For this purpose, the signal DIN3 is supplied, in which ξ to 2J of the marking number (which corresponds to a time control ZJ ₁₀ ) can be set to a lower level in the additional unit. The signal DIN1 is formed by the circuit illustrated in FIG. 14D. The circuit illustrated in FIG. 30 is constructed and designed in this way that the output signal DINl only then on one

■ ο remains high if an uncorrected state of the clock is determined, so that the date gate pulses can be counted in the fast-slow automatic control section by determining that PM the current time data is available in the normal state of the watch.

A signal DINl ■ Dn 3g Φι reaches a high level when the time control % of the weekday digit is at a high level. A blinking or blinking of the weekday number occurs in the uncorrected state as well as in the totally blinking state (which is caused by a coincidence in the alarm), the blinking is sensed and a signal QFL is generated. The signal DIN1 is thus formed on the assumption that the blinking of the weekday digits in the current time display is normal. The phase relationship between the timing pulses ₁ , φ ₇ and> ₃ and the blinking is illustrated in FIG. 53. If it appears appropriate, a circuit according to FIG. 54 can be used, in which a gate is designated by 1463 'which is the gate 1463 of FIG. 46 replaced, while in combination the circuit which leads from DIN1 to 1463 can be replaced by the circuit illustrated in FIG.

The block 1430, which reproduces Qi , is adapted to reproduce digit pulses from the continuous signals Φί / Cl and 0UCl. The signal ΦUQ is the sum of Z) ₁ , Z) ₃ , ... and Z) ₁₅ . The signal 0UC ₂ on the other hand delayed from the signal 0UC _x a shorter period of time which is equal to the Diffe Renz zw i rule the signals Φ and Φ _2. Thus, if two clock pulses Φα = 0UCi '0UC ₂ and 0ß = 0UC \ ■ 0UC ₂ are present, 16 latch circuits generate a composite signal Qi (Qi = Di + Di + 1, / and ß ₁₇ = Q).

The 1494 shift registers are used in addition to the existing shift registers when there is it is desirable to increase the number of alarm data.

With 1480 a block for automatic lead-lag setting is referred to, which is made up of the elements 1481, 1482, 1483 and 1484 is formed, of which 1482 is a date gate block. The counter has an octal Counter which detects changes in the date in response to the time information, which of the Standard unit, which continues to open the automatic setting gate on the eighth day and which inverts another flip-flop Q43 on the ninth day to establish a waiting status. That On the first day, data gate returns to counting in response to an unamplified input signal which was administered before or after the eighth day. A slow-fast control input signal can go through the gate on the eighth day, and after the control is complete, a Signal delivered to the data counter, which then returns to the first day. These measures are in the F i g. 56 illustrates. In FIG. 56, the broad arrows show advancing one step per day in response on the current time data, while the narrow arrows indicate the incremental advance which caused by the control input signals.

The identification gate 1483 is adapted to detect the case where the second remote reset switch is brought to a high level for more than 4 seconds and less than 20 seconds in the normal state, whereby an identification signal P ₁ after one minute the determination is generated. The F i g.

57 shows the relationship between the signal P ₁ and the input signal UDII.

The circuit 1481 (FIG. 48) includes a divisor 60 counter 1465, the count of which is over a week is kept constant while the lead / lag correction takes place. Another counter 1466 of this type counts the units of the seconds data of the starting time. Counter 1465 and the seconds count of the current time (in register 58, FIG. 4) are set to zero at the beginning of the lead / lag calculation

so posed. So at the end of a week, when the running seconds count is zero, one may become zero deviating counter reading in counter 1466 show the time leading or lagging in seconds, namely based on the period of one week. The result is the reading of counter 146S on counter 1466 added, which is subtracted from the initial counter reading stored within a week. The exits of the counter 1466, Q31 to Q36 are used to control the generation of an error correction return pulse

ses FSO, which are given to the timing pulse generators of the standard system. An increase of +1 in counter 1466 has the consequence that the standard timing system counts an additional second in a week. In order to subtract the count of 1465 from that of 1466, _{a gate is opened by a pulse P 1} at the end of the calculation time, whereby a high-frequency pulse train of ξ Φ is applied to the inputs of both counters at the same time. The control signal P ₁ drives the counter 1465 forward rapidly, with it

a high frequency until the count in counter 1465 reaches zero. This is detected, and the high frequency The pulse train is switched off, which means that the counter 1466 has its initial value minus the initial counter reading from 1465 remains.

Circuit 1484 generates feedback pulses that correspond to the count in counter 1466. That Feedback signal is generated in that existing time pulses are combined with one another without a frequency divider is used. It is assumed that the following relationships hold:

"S _2. · J2n " S ₂₃ -U- (Q ₂₅ + Q ₂₆ ) = λ, Έ Hz t = A

Φ2 ■ Tu T ₁₄ Q ₁₆ Qi Φ, = F, = Bq> ₂ D \ T ₄ <P,

> Pi ■ T ₂₄ ■ Q ₁₀ · Q ₁₁ · Φ, = F ₂ = B ₉₂ D _n Oi + £) <*>,

(P ₂ · Ώιι · Qio · Φι = F ₄ = B ₉₂ DM + T ₂ + T ₄ +

TI ₂ ■ ^ ₂₄ · Q ₁₆ · Qi ■ Φι = F ₈ = B

ίο 7 ^ 4 ■ Qi6 · (3ι ■ Φι = F ₁₆ = ZfZ) ₁₆ (T ₂ ¹ + TJ) (P ₁ ,

P ₂ Qi ₆ Qi Φι = F ₃₂ = Ζ> ₂ (7Ϊ + 3J + TJ + Τ _% ) Φ \ -Ip ₂ -B,

it is further assumed that the frequency of the signal FSO is equal to fso and that the frequency of the is signal FSI is 0 Hz; then applies:

F ₁ 1 Hz

F ₂ 2Hz

F ₄ 4 Hz

F ₈ 8 Hz

F ₁₆ 16 Hz

F ₃₆ 28 Hz

Since the logical product of any two signals from the signals Fi to F _{32 is} at a low level, frequency addition is possible if they are added by the OR gate. The average frequency of fso of the signals Fso can be expressed as follows:

fso = 1/20 (2 ° ■ Q ₃₁ + 2 ¹ · Q ₃₂ + 2 ² · Q ₃₃ + 2 ³ ■ Q ₃₄ + 2 ⁴ · Q ₃₅ + 28 ■ ^ ₃ T) (Hz)

where Q ₃₁ to (Jj _{6 are} either 0 or 1.

Adding 1/20 Hz to the 32,168 Hz timing frequency makes it possible to change the clock in a week about 1 second, which means that the system according to the invention automatically corrects the weekly error presses to less than 1 see after the pre-run / run-on setting process has ended.

Counts 33 to 59 in counter 1466 can be matched with -27 to -1 when, in use, the weight of signal Q _{26 is} not 32 but is -28. Assuming that the high level of the signal indicates "-28" and the low level indicates "0", then the counts 0 through 59 in counter 1465 can be used as 0 through 31 and -28 through -1. This enables the weight of signal Q36 to be considered "-28" so that 56 Hz _{corresponds only to the frequency of signal F 32} at a high level of signal TJ ₃ ^. The signals 8 Hz t and q> ₂ have a common storage cycle and build up simultaneously, although the frequency of the first signal is 8 Hz and that of the last signal is 1 Hz. If the signal q> _{2 is added} as a term of a logical product to an input part of the gate which _{corresponds to the signal F 32} , only this part which _{corresponds to the signal F 32} is supplied with a frequency of 7/8 Hz.

FIGS. 28A and 28B show a preferred embodiment of an electrical detailed circuit for the shift register ring 1490, which is illustrated in FIGS. 27A, 27B and 27C. 28A and 28B, the shift register ring 1490 includes 64-bit shift registers labeled 111, 112, 114, 118, 121, 122, ..., 448 . These shift registers are driven by intermittently modulated clock pulses. The intermittent modulation of the clock pulses takes place during a time interval between the clock pulse Φ \ and the clock pulse Φ ₂ , ie when Φ \ ■ Φ ₂ = "L". More specifically, each of the shift registers is composed of a main-sub-data flip-flop which has a main stage latch circuit of a dynamic memory and a sub-stage latch circuit of a static memory. The shift register ring 1490 has a plurality of input terminals and a plurality of output terminals which are designed so that data can be input and read out in parallel from the shift register ring 1490 for corresponding processing, within a time unit which is determined by the intermittently modulated clock pulses is. While the alarm time data are being read out from the shift register ring of the above-mentioned electronic watch in response to the digit pulses Z) ₁₅ to D ₂ , those data which correspond to the alarm time are output from an output SRG-WX-OUT of the shift register ring 1490 in response to the same digit pulses D ₁₅ to D _{2 are} read out.

The signals from the electronic clock are supplied to the additional system in response to a synchronization signal q> i, which has a pulse repetition frequency of 2 Hz, with a pulse duration of one memory cycle. At this point it should be noted that the alarm time which is read out from the output SR G-Hl -out of the shift register during the timing of the digit pulses Di ₅ to D ₂ is also referred to below as the first data record.

While the alarm time is being set, only 16-bit shift registers are driven by the clock pulses. The digit pulses Z) ₁₅ to D ₂ are supplied to the shift register ring 1490 when it receives the data from the electronic watch, while when the shift register ring 1490 supplies the data to the electronic watch, the clock pulse Φ? and Φ ₂ ⁺ , which correspond to the four digit pulses Z) ₁₄ to Z) 1, are supplied to the shift register ring 1490. The shift register ring 1490 receives data from the electronic watch in

Response to the Ziffemimpuise D ₁₅ to D _2, that is S _A = H. On the other hand 1490 supplies the shift register ring the data to the electronic clock of the timing of the digits pulses D ₁₄ to D ₁ in response to a signal SS 2, which by oen signal generator 552 is generated in response to an input signal MS1 which is supplied by the manual shift part.

In a normal state, the shift register ring 1490 is driven by the clock pulses for 48 bits during the period of the digit pulses D ₁ to D ₂ . The alarm time data are supplied to the input terminal DIN of the electronic clock under the timing of the digit pulses D ₁₄ to D _x , namely by one digit before the output signal of the standard time measuring system. For this purpose, the alarm time data are derived from the output SRG-III-out

ίο Under normal conditions, the data of the outputs SÄG-211 and SRG-311-out of the shift register ring 1490 at the time controls of the digit pulses D ₁₅ to D ₂ are still stored therein, and they are hereinafter referred to as first and second alarm time data. With the time controls of the digit pulses D ₁ to O ₁₁ , which are faster than the time controls Z) ₁₅ to D ₂ , namely around the eight digits, the current time data, which are stored in the minute digit, and the marking digit from the electronic clock delivered. It is thus possible to determine the coincidence in the logic level between the data of the output SRG-311-out and the _{data fed to the input terminal} D 1n, so that the first alarm time data with the current time data for the time controls from D ₁ to Z ) ₁₀ can be compared. If at this moment the first alarm time data coincide with the current time data, the first alarm time data for the time controls from Z) ₁₅ to D ₂ are deleted by a gate 1406, which is connected between the input SÄG-448 and the output SÄG-lll-out of the shift register ring 1490 is arranged. An input signal ALI _{x is} fed to gate 1406 for this purpose.

The month and date data are supplied by the electronic clock to the time controls from D ₁₂ to Z) ₁₄ . If the data _n from the output ARG-Hl to the timings of D are read by Z) _14, beze first preliminary data with respect to the first alarm ^data: ~ be .hnet which can be taken from the output SOEC-221 , the advance data and the month and date data in the phase differ by one digit. Namely, the digit pulse Z) ₁₂ corresponds to the ten digits of the minute in the preliminary data, while the digit pulse D \ ₂ corresponds to the one-day digit in the month and date data. It is therefore necessary to compare the data from output SÄG-441, which are delayed by one digit more than the data from output SÄG-111, with the month and date data.

3D The compared result is sampled in response to the downward control of the digit pulse Du , and then the month and date alarm data which were stored in the auxiliary system are released in response to the digit pulses D ₁₅ to D ₂ . It should be noted that if the clearing gate is arranged between the output SÄG-411 and the input SÄG-348, the data stored in the four digits, ie the one-day digit up to the marking digit of the alarm month and the date data can be completely deleted. This is because the advance data are stored in the shift registers SÄG-411 to SRG-AAt under the timing of the downward control of the digit pulses Du. In the embodiment shown, however, the delete gate 1405 is arranged between the output SÄG-441 and the input SÄG-431 in order to delete the data which are stored in the 16 bits contained in the 2 ² bits for the connection marker and the 2 '-Bits for the daily marking are contained in a second preliminary data record, which is stored in the shift registers SäG-348 to SÄG-311, and in a one-minute digit (one day), furthermore in a 10-minute Digit (10 days), furthermore in an hour digit (months), furthermore in a 2 ° bit for the PM marking and in a 2 'bit for the date marking in the first preliminary data, which are in the shift registers SÄG-411 to SÄG-448 are stored. If the 2 ² bits for the connection marking of the alarm time data in the second advance data set store a "1", the month and date data in the first advance data set are linked to the alarm data in the second advance data set. With the alarm time connection mark thus supplied, the coincidence between the alarm time data and the current time data is not sampled. However, if the alarm time connection mark is deleted in the second advance record, then the alarm time in the second advance record is changed to a normal temporary alarm which is automatically cleared after the audible alarm signal

so temporarily generated.

The gates 1405 and 1406 are used to enable the marker display digit to be set. Upon receipt of the output signals from the tag setting circuit 1452, the tag data ii is stored in the shift register ring 1490 in the manner shown in Table IV. In the table Y \ the symbol ALIl indicates that the "1" in the first data represents the input signal for the data marking. In a similar way, the symbol ALD 1 indicates that "1" and "0" of the input data represent the data which are supplied as the input signal. "1" of ALII represents the input signal for the first previous data and the symbol ALDI represents the data in this input signal. The symbol "N" indicates the number of cases in which UDII is changed between a low and a high level . Table IV shows that the display of the data marking is not changed when N = O, the data setting de

go first alarm and the setting of the continuous alarm are unlocked if N = 1 un < N = 2. and the month and dates of the first alarm are set and the first advance alarm is linked to the month and dates of the first alarm.

The shift register ring 1490 also has a gate 1410 which is designed such that it determines the digit zero of the alarm data in the additional system. This gate 1410 thus generates an output signal OHAT, which indicates that the hour digit of the alarm data is equal to zero, that is, a free address. If the output signal OHAT of the gate 1410 is read out at the timing of p ₄ Di T _% Φ _χ , it is possible that it is determined that the shift register for the second alarm data is unoccupied. The gate circuit 1401 has a marker display gate which outputs a marker signal upon timing of Di 5 Q

lets through. When the second alarm time is set and stored in the shift register, an alarm flag setting signal is supplied to the display device to display the alarm setting flag. The gate circuit 1401 also has a gate to which the timing signal D \ T _V Q _{A is} applied to sample the date setting flag. An output signal is generated at the timing of Z) ₁ ^ ₄ Q _A and supplied to the display device of the electronic watch so that the date mark is thereby displayed, thereby indicating that the date setting alarm is set. While the data which are fed to the input DIN of the time measurement register 32 of the electronic watch under the time increments of Z>, T ₁ and Z) ₁ ZJ, are cleared by the gate 66 of the time measurement register 32 (see FIGS. HA and 11B), it is possible to control the functions and the display mode of the electronic watch by continuously supplying the timing signals Z) j TJ or D ₁ T ₂ in order to scan the coincidence between the current time and the alarm time and the time signal Z)] TJ for to block the special display such as a month and a date marking etc. in the DATA-IN input of the timing register 32 of the electronic watch.

The gate 1411 is used to determine the status "15", ie (1,1,1,1), namely in the digit for the ten minutes of the alarm time, and it generates an output signal QOHER to clear the status "15" in the data stored in the auxiliary system. In the event that the alarm time is displayed in the electronic clock, the shift register for the alarm time is free, ie the hour digit is "0". In this case the displays of the one-minute digit and the ten-minute digit are deleted by a signal which corresponds to the binary code "1,1,1,1", this signal being fed back to the shift register of the additional system. Then this special signal is fed to the timing register of the electronic watch, and therefore the ten-minute digit is transferred to the hour digit through the gate 68 of the timing register 32 of the electronic watch in such a way that the hour digit of the alarm time differs from "0" changes to "1". The QOHER output from gate 1411 is used to clear the special codes in the ten-minute digit of the "vacant" data in the adjunct system. This is done by gate 1404 in response to the inverted signal ERDT provided by marker setting circuit 1452 in response to the output signal QOHER.

In Fi g. FIG. 29 illustrates an exemplary embodiment of a detailed circuit of the clock pulse generator 1408. As shown, the signal CONT0, which is provided by the manual shift circuit 1420, is fed to the input of the clock pulse generator 1408. This signal is fed to a locking circuit and locked at the time of T ^ Φ so that an output signal CONTΦ ' which is ^{delayed by 3 1} Z ₂ bits and is synchronized with the clock pulse Φ _χ is generated. The signal ϋΟΝΤΦ ' is fed to an AND gate, which is also fed with the clock pulse Φ ₂ , so that a clock pulse Φι is generated. The signal ϋΟΝΤΦ ' is also fed to a latch circuit and is latched therein by the clock pulse Φ ₂ in order to be delayed in half a time. Thus, a clock pulse CONTΦ "is generated, which is synchronized with the clock pulse Φ ₂ , and it is fed to an AND gate, which generates a clock pulse Φ * in response to the clock pulse Φι . The clock pulses Φ? And Φ ₂ are the shift register ring 1490 fed to drive this.

The F i g. 30 illustrates an embodiment of a detailed electrical circuit for the data demodulation circuit 1409. The data demodulation circuit 1409 has an even number of inverters which serve to shape the waveform of the input data accordingly, so that a signal D _{! N} , is thereby provided which is transmitted to the various components of the auxiliary system is supplied, for example, the gate 1407, the timing pulse generator 1454 and the frequency setting circuit 1484. The demodulation circuit 1409 is so constructed that it detects a state in which the weekday digit flashes and a signal Q _FL generates which an AND -Gate is fed. This AND gate generates data D, _N2 in the normal state only when the current time and the weekday digit are flashing. This output signal Difii is applied to the date gate 1482 so that the automatic setting date gate cannot be adversely affected while the time is being set. The data demodulation circuit 1409 also generates an output signal D _mi by clearing Dx ₀ T ₁ through D _w T _{t of} the output D _lfn . Since the signals or data corresponding to the timing signals DiOi ₂ to Di ₀ ^ are the data of the alarm time which is not related to the current time, the above-mentioned data are deleted when the stored alarm time data are compared with the current time data, and it correct instantaneous time information is reproduced. For this purpose, the output D _{/ N} y is connected to the comparison circuits 1425 and 1426.

FIG. 31 shows an example of a detailed electrical circuit for the composite digit pulse regeneration circuit 1430. This circuit 1430 has input _{terminals i / C} i and U _c2 to which the clock pulses Φ υα and Φ _{υ € 2} are applied in each case. According to FIG. 9 the clock pulse Φ _{υη is synchronized} with the clock pulse T \ . The clock pulse Φ ^^ is delayed compared to the clock pulse Φ ^ ι , and it has an inverted waveform. Thus, the clock pulses Φ _α and _Φ β are generated which _α the clock pulses Φ and Φ ₄ correspond, by the l ogisc he P roduc t from the clock pulses Φ ^ \ ^un d Φυα ^un d, the logical product of the inverted clock pulses _Φ υ _{€ 1} and Φυα- to this end, the composite numbers pulse regenerating circuit 1430 sixteen cascaded latches. The digit pulse D \\ is written into a first latch in response to the clock pulse Φ _β and an output of the first latch is written into a second latch as a data input in response to the clock pulse Φ _α . Thus, an output pulse Q i is generated which has a pulse width which corresponds to the two digits. The signal Q _b, which is regenerated from the continuous digit pulse D _n and the continuous clock pulses Φ _{υ €} \ and Φ _{ϋ (Γ2} , is a continuous signal which is not adversely affected by the intermittent modulation of the output signals from the electric clock.

The F i g. 32 shows an example of a detailed circuit for the timing pulse regeneration circuit 1431. This circuit is supplied with the output signal Φ which is the logical sum of the clock pulses Φ _χ and

Φ2 'S's and is used to regenerate the timing pulses T _n and TJ _4. If the clock pulses Φ, and (P _{2 are} generated intermittently, the output signals of the interlocks are influenced by the intermittently modulated clock pulses, and therefore the timing pulses 7 [, T ₁ and Z »are converted into intermittent signals which are synchronous with the clock pulses Φ ₂ The timing pulse T ₁₂ is the logical sum of the timing pulses T \ + T ₁ , and the timing pulse T _2A is the logical sum of the timing pulses T ₂ + T _t . If there is a gap between the downward control of the timing pulse 7J and the upward control of the timing pulse T ₁ is present, timing pulse 7J ₂ is a noise signal, which the adjunct adversely affected to overcome this problem, the OR-gate is additionally supplied with a pulse which occurs in response to the clock pulse Φ \ when the timing pulse 7J is at level "H", and which is reduced when the timing pulse When T _{2 is} "H", a noise-free signal T _{n is} regenerated. The timing pulse T ₂ 4 is regenerated in the same way. The composite timing pulses T _n and T] ₄ are advantageous because the number of circuit connections is reduced. The F i g. 33 teigt an embodiment of an electrical detailed circuit for the current time display

'5 sampling circuit 1429. The clock signal D _0, which is the display data specifies the display of the current time, if D ₀ = _{Z)] 6,} there is, however, the display of the date on when D _{n 0} = D and indicates the alarm time display when D ₀ = D ₁₄ . Thus, the current time display sampling circuit 1429 is provided with the signal D ₀ as a latch input which is latched under the timing of D ₆ , thereby sampling the status of the display of the current time.

The F i g. 35 shows an example of a detailed electrical circuit for the alarm time sampling circuit 1427. According to the above, the display status of the alarm time in the electronic watch under the timing of Z) ₁₄ is sampled by the interlock circuit which takes D ₀ as an input. When the alarm time is displayed, it means that the alarm time has been set. Since it is necessary under these conditions to maintain the synchronous relationship between the electronic watch and the auxiliary system, the signals are thereby transmitted in a highly reliable manner in one direction and in the other. To this end, the status of the display is sampled by the timing of PiDi _A T _t Φχ and an output signal is generated by a first latch circuit. This output signal is fed to a second interlocking circuit and sampled under the timing control fjDjTi Φι , so that an output signal Q ₉ 3 _A t \ is thereby supplied. This output becomes a third

Latching circuit supplied and read out under the timing of _{φφ ί} Τ ₄ Φ _ι , so that an output signal Q _{9iAT2 is} generated. The output signals Q _{9 3ATl} and Q _{9 3AT} j are fed to an AND gate, through which an output signal Q _{A is} generated in order to sample the status of the alarm time. The output signals Q and ₉ UTi QfiATi be the shift register-stop circuit fed 1426 is to the unoccupied shift register during the setting of the alarm time in a way to be indexed, which is subsequently explained in inzelne e n. The logical product of the output signal Q ₉ j _a ti ^un & the inverted output signal ~ Q ~ for ~ i are synchronized with the pulse j> j and kept at level "H" for half a second, which is displayed that the alarm time is set.

36 shows an example of a detailed electrical circuit for the pulse generator circuit 1451, which is designed such that the pulse signals W _KT , W _0T , W _AT0 and W _{AT are} generated. The pulse signals W _KT and W _AT indicate portions of the current time data and the date data in the output data of the electronic watch.
The signals W _KT and W _0T are generated by a logic summing gate according to the following equations:

Qr + Q ₉ = Di + D _s x + D ₉ + D ₁₀ = W _KT

Qn + On = D _n + D _n + D _IA = W _DT

The pulse generator circuit 1451 also generates timing signals W _{AT 0} and W _AT \. The timing _signal W AT0 is used to open a gate to receive signals from the auxiliary system to the electronic watch

so to be supplied, and the time control signal W _{AT χ} is used to open a gate in order to feed the output data from the electronic watch to the auxiliary system. These timing signals are required to be intermittently modulated when the clock pulses Φ ₁ and Φ ₂ and the timing pulses 7J to 7J are intermittently modulated. Similarly, the timing _signals W AT0 and W _{ATl are} required to be continuously present when the clock pulses Φ and Φ _{2 are} continuous. For this purpose, the pulse generator 1451 has a flip-flop which generates an intermittent signal which is built up under the time control of Qi ₂ TI ₂ and is released under the time control of Q ₃ . This intermittent signal is supplied to gates by which two intermittent signals W _AT0 and W _ATX are generated in response to signals Q ₂ and Q, j, respectively, which have reduced pulse widths, respectively. The timing signal W _AT q builds up in response to the upward control of the digit pulse D \ and is released in response to the downward control of the digit pulse Z) ₁ . The time control signal W _AT ι builds up in response to the upward control of the digit pulse Z) ₁₅ and is built up in response to the downward control of the digit pulse D ₂ .

41 shows a preferred exemplary embodiment of an electronic detailed circuit for the output data control circuit 1402, which generates a signal SB which enables the data to be transmitted from the additional system to the input terminal D _{M of} the electronic clock, synchronously with the pulse p ₃ . The data output control circuit 1402 has a gate which abtaZ lh d Shibi ih hl id ie Q 0

pp ₃ g

steady, ie Q ₉ } _A T2 ⁼ "L" and the state in which the shift register is not stopped, ie Qs ₇ -P - 0, and it generates a signal SB 1, which is directed so that the data from the Output SRG-121-out of the sliding H

42 I.

beregisterringes 1490 with a delay of one digit compared to the data of the output SRG-I U-out of the input terminals D _{tf / of} the standard timing system at the times from Z) ₁₄ to Z> j are supplied one digit faster than the output data of the alarm time in the Standard timing system. The Dalen output control circuit 1402 also has a gate which generates a signal SB1 in response to a signal MS1 , which is directed so that the new data from the output SÄ G-H1 are supplied to the standard timing system at the times from Dt to D ₁ when the manual slide switch is operated and the new data, which are stored in the auxiliary system, are fed to the standard timing system. The data output control circuit also has a gate which generates a signal SB3 if SB1 - "H" or if 552 = "H". The signal SB3 is applied to the DCL terminal of the standard timing system in order to delete the alarm time data stored therein.

40 shows a preferred embodiment of a detailed electrical circuit for a data input control circuit 1403, which is constructed in such a way that it generates a signal SA. The data from the standard timing system is passed to the adjunct system via gates 1407 when SA = "H" (see Figure 14B). The signal SA is generated by a gate in response to the signal W _ATi , that is, at the times from Z) ₁₅ to D _{1 of} the alarm time data supplied by the standard timing system when half a second has passed after the alarm time is set, ie

QA = Q _fiAT \ ■ Q, 3AT2 = "H",

in response to the pulse signal &. This signal SA is applied to 1407, which lets the data through, except for the data represented by D ₂ (? + T ₄ ) , i.e. the data containing the date marking bit for the alarm, the PM marking Bit and the digits of the hours, tens-minutes and one-minutes. However, when SA = "L", the shift register ring 1490 is closed to form a ring circuit in which the stored data is shifted.

34 shows a preferred exemplary embodiment of a detailed electrical circuit for the pulse generator 1428, which is constructed in such a way that it generates a signal.

The standard timing system and the auxiliary system are synchronized with each other by the signal φι, which has a pulse width equal to that of a memory cycle, and which is synchronized with the downward control of the 2 Hz signal of the timing register of the standard timing device. The signal Dini is supplied as an input signal to a first latch circuit which is _{read out at the time of Z) 4} Z) Φ \ so that a 2 Hz signal is derived in response to the signal D ₄ T ₄ <P \ . This 2 Hz signal is fed to a second latch circuit and read out at the time D ₄ "ξ Φ \ . The inverted output signal ~ Q from the second latch circuit and its input signal are fed to a gate which generates a signal q ^ which corresponds to the In this embodiment, the digit pulse Z) _{4 is applied to} the gate as a disable signal, and thus the signal #, is established in response to the upward control of the digit pulse D ₅ and in response to the downward control of the digit pulse D) removed. Similarly, the signal Z> _W1 is fed to a third latch circuit as the input signal and read out _4% Φι at the time D, so that an I-Hz signal is derived. This I-Hz signal is a second gate which generates a signal q> ₂ of 1 Hz when the I Hz signal is at level "L", ie within 0 to 0.5 seconds at the current time. The signal is also fed to a fourth gate which generates a signal $> i when the I Hz signal is "H", ie within 0.5 to 1 second. The signal φ _} is fed to the fourth interlocking circuit and read out at the time D _} % Φι , so that a signal q> ₄ is delayed by one storage cycle compared to the signal q> _}. This signal φ ₄ is used to scan the unoccupied state of the next shift register. Referring to Fig. 15C, the signal ^ j is a 2 Hz signal which takes a position in phase, the signal q> ₃ not being affected by the modulated data output signal which is indicated by the standard timing system and which is a position after the change It is therefore advisable to read out the output data from the standard timing system in synchronism with the signal φ _{} in order to} read out the corrected data which have not suffered from the display modulation. It is to be noted that if a common time multiple for a data cycle in the shift register ring of the standard timing system must be chosen to be 0.5 seconds, the relationship between relative phases of the shift registers of the standard timing system and the additional system with respect to the pulse q> _{} is} kept constant.

In FIG. 44, there is shown a preferred embodiment of an electrical detail maintenance for the shift register stop circuit 1426 which is _{configured to} generate a signal Q srP which is used to stop the shifting operation of the shift register ring 1490. The shift operation of the shift register ring 1490 is halted under the following conditions:

a. When the hour digit of the alarm time data is zero, i.e. H. if

OHAT · D ₁ ξ Φι = »Η«,

during the time period of 0.5 sec when

d. H. during that time period in which the unoccupied shift register automatically indexes just after the alarm time is displayed and

b. when the alarm time data coincides with the current time, d. H. if

D _W T _S 4> 2 ■ Detat = "H",
in the normal state

(Q _v iAT2 = "L"),

d. i.e. when the current time is displayed.

The shift operation of the shift register ring 1490 is started by the signal Q _{f 3/4} n when 0.5 seconds has elapsed after the alarm time was displayed, ie when Q _r } _A Ti ~ "H". When the alarm time data coincides with the current time, the shift operation of the shift register ring 1490 is stopped in the following manner. If the alarm time coincides with the current time under the condition!? If the normal current time is displayed, this coincidence in between is determined at the time of Dio ξ 02 and the alarm time data which coincide with the current time are fed from the additional system to the standard timekeeping system in the time from D ₁₄ to D ₁ . At the same time, the alarm time data is passed through the four-bit shift register and cleared by the additional system at times from £> i5 to D ₂ , and then the clock pulses Φ? and Φ ₂ prevented from being supplied to the shift register ring 2i circuit 1490, so that the shift operation thereof is stopped. The shift operation of the shift register ring circuit 1490 is restarted when 60 seconds have passed after the alarm time coincides with the current time by the signal Q ₉ 60S . The supply of the clock pulses Φ * and Φι is stopped at the times from D ₃ to D ₆ under normal conditions and at the times Dj to Z) ₁₄ provided that the alarm time is displayed. The signal Oj ₇₇ . is generated by the interlock circuit in response to the signal D ₃ Jg Φι.

The F i g. 43 illustrates a preferred exemplary embodiment of a detailed electrical circuit for the date alarm data coincidence sampling circuit 1424, which is constructed in such a way that it generates a signal ERDT. The data output SRG-441 and the signal D, _Ni are compared by three digits, i.e. by D _n to Z) ₁₄ , and at the same time the month and date data of the alarm time and the connection marking of the advance alarm time are deleted by the four digits, ie through Z) ₁₅ to D ₂ . The deviation between the month and date data of the alarm time and the month and date data of the current time is sampled at the times from D _n to Z> _i4 , that is, when W _DT = T, and at the same time the level becomes "H" of the data on the data bit, ie bit 2 ^{1 of} the marking digit of the month and date bits of the alarm time, scanned by using the data from the SRG-III-out output. When closing lent passes one of the signals to the level "H", dasjen strength Fli p-flop is reset, which has been set at the time of Dt of the instantaneous time display. The signal ERDT is the logical product of the output of the flip-flop and the signal fV _ATl , ie the timing _{signals Z) 1} ; to D ₂ , and it is used to clear the month and date data of the alarm time, and the data of the connection mark of the alarm time are cleared through the gate 1404.

H) The Fi g. Fig. 42 shows a preferred embodiment of an electrical detail circuit for the alarm time coincidence sampling circuit which is so constructed that it generates a signal with which the alarm time data is cleared when the alarm time data coincides with the current time data. The current time data which _{are fed to the input Z) // v3} and the data from the output SRG-3U-out of the shift register ring circuit 1490 are fed to a comparison device such as an exclusive OR gate and are fed through this at times D ₆ to Z ) ₉ compared with each other, ie W _KT = "H". If at this time the alarm time is not set, that is, if Q _A = "L", a flip-flop is reset by the output of the exclusive OR gate which serves as a sampling device for the non-coincidence between the alarm time data and the current time data. On the other hand, if the alarm time data coincides with the current time data, the output of the flip-flop will be "H" level for a period of time represented by D ₁₀ Ti through D ₄ . The corresponding output signal is fed to an AND gate, which is also fed as an input signal W _ATI , so that an output signal Ογβ _λ τ is generated. This output signal is fed to the marker setting circuit 1452, which consequently produces an output signal ALI ₁ which is fed to the gate 1406 of the shift register ring circuit 1490, thereby clearing the alarm time data. The output signal DETAT of the flip-flop is fed to the shift register stop circuit 1426.

38 shows a preferred embodiment of an electrical detailed circuit for the manual shift circuit 1420. The manual shift circuit 1420 operates in such a way that it generates an output signal CONT Φ which is used to control the supply of the next clock pulses Φ * and Φ ₂ to the shift register ring circuit 1490, whereby when the normal current time is displayed, the alarm 6i, time data to be fed to the standard timing system in each memory cycle is corrected or updated, while then, when the alarm time is displayed, the alarm time data that has been displayed is renewed in response to alarm time data that controls a signal brought about by the operation of the manual slide switch. In the normal display state, the relationship Q ₄ = "L" is used. When Q _x = "L", the signal Q _A - Q ₄ - Q ₂ -, which is established in response to the upward control of the digit pulse D ₆ and is decreased in response to the downward control of the digit pulse Z) ₁ , is passed through a gate passed in the form of the output signals ΟΟΝΤΦ , which are fed to the clock control circuit 1408, whereby the clock pulses Φ ^ and Φ ₂ , which correspond to the four digits from D ₃ to D-, are not generated. Provided that the alarm time is displayed

is, that is, when Q _A = "H", the signals D ₂ to Df, are blocked because MS12 = "L" in the normal display state, and the signal W _AT0 , which in response to the upward control of the digit pulse D _H built up and broken down in response to the downward control of the digit pulse D ι, is passed through a gate of the manual shift circuit 1420 in the form of an output signal CONT0 . The shift register ring circuit 1490 is supplied with the clock pulses Φ * and Φ ₂ ^at the times Z) ₁₅ to D ₂ , in response to the signal CONT <P, which is established in response to the upward control of the digit pulse Z) _H and is released in response to the downward control of the digit pulse O ₁ , so that when the alarm time is displayed, the data is shifted for four digits, ie one data set in one storage cycle. The manual shift circuit 1420 has an input MSIN, which is used to shift or sample the alarm time data or the alarm time date, which is fed to the external control element such as a manual slide switch 266, which is shown in FIG. 18 and which is normally resolved. In the normal display state, the input terminal MSIN is held at level »L« by the reset signal ΰ ₂ Τ ^ Φ \. When the manual slide switch 265 is pressed, the input terminal MSIN is at a level "K". If the logic level at the input terminal MSIN is held at the level "H", namely over a time interval of more than one second, if 0, _φ3λ τι ~ "H", provided that the alarm time is displayed, the level “H” at the input terminal MSIN is read out in a first latching circuit under the timing of q> ₃ D ₃ 23 Φ [, whereby a gate 1422 generates a signal MSIN. The output of the first latch circuit is read out by a second latch circuit at the time of P ₃ Z) ₃ TJ (P ₁ , so that an output signal delayed by about one second is generated. The output signals from the first and second latch circuits are fed to an AND gate 1421, which is also fed with the input signal to the first latch circuit and the signal φ ₂ , so that one of the output signals MS 'ti is generated.

The input terminal MSIN is brought to a low level in order to manually sample the alarm time data. The flip-flop for storing the manually set input is normally reset in response to the signal which is the logical product of the signal q> ₃ and the signal Z) ₃ TJj Φ \ . If the input terminal MSIN is set to a high level, if q> ₃ = "L", the flip-flop is set and reset by the signal P ₃ Z) ₃ Tu ^ ₁ . The logical product of the output signal of the flip-flop in its set state and a signal p ₃ is a signal which is obtained by sampling the high level of the input terminal MSIN in synchronism with the signal φ ₃ . Under a condition in which the outputs of the first and second latch circuits are high, the MSIN input is provided at a high level to gate 1422 as a manual scan input.

The output signal MS1 1 is delayed by a third latch circuit at the time of D ₃ T ₂ Φι by one memory cycle, and a signal MSM is generated. The MSM signal is used to feed new data from the auxiliary system to the standard timing system in the next memory cycle after the manual shift operation has just been performed. Since in this case there is a need to use clock pulses Φ | ⁺ and Φ _{2 to} the shift register ring circuit 1490 for 16 bits between Du to Z) ₁ , enables the signal ΟΟΝΤΦ to deliver the pulses, which have a width corresponding to 16 bits, and only if MSM = »H «. The signal MSM is fed to a fourth interlocking circuit, by means of which the signal MSM is delayed by one storage cycle at the time of D ₃ T ₁ Φ _ι , so that a signal MSt 3 is generated. If MSi 3 = "H", the signal W _AT0 , which is built up in response to the upward control of the digit pulse Z) ₁₄ and is released in response to the upward control of the digit pulse Z) ₁ , and the signal which is generated in response to the Upward control of the digit pulse Z) _{] 0 is} established and decreased in response to the downward control of the digit pulse D ₁₃ , added to each other, and in this way the signal Ο0ΝΤΦ is generated. The signal ΟΟΝΤΦ is used as a control signal to apply the clock pulses to the shift register ring circuit 1490, thereby causing the data therein to be shifted. As a result of the supply of these clock pulses, the data in the shift register ring circuit in the additional system are advanced by one data record, which corresponds to 16 bits, further than the data in the standard timing system with regard to the pulse <p ₃ . The signal MS ti is applied to the file marker setting circuit 1452, in which a marker setting counter is reset to zero so that the data newly stored in the shift register ring circuit by the manual shift operation is not adversely affected. The manual shift circuit 1420 is supplied with the signal Q ₅₇₀ P , which is synchronized with the signal D ₃ J ₃ " Φ \ from the shift register stop circuit 1426, which makes the Takiimpuis control signal synchronous with the signal Z> ₃ 7jj Φ \ controls When constructed in this way manual shift circuit 1420, the shift register ring circuit 1490 is not supplied with the clock pulses which correspond to the numbers pulses D ₃ to Z) _6, ie, 16 bits in the normal state in which the current time is displayed so that the shift mode of the data in the auxiliary system is shifted by 16 bits, which corresponds to one data record in each storage cycle, and other alarm data are transmitted from the auxiliary system to the standard timing system in each storage cycle at the timing of Z) _{! 4} to Z) 1 supplied Under the condition that the alarm time is displayed, however, the data in the additional system are advanced by 16 bits, which corresponds to the one data record, and indeed far it as the data in the standard timing system in each memory cycle. At this time, the data entered into the standard timing system is fed back to the auxiliary system, twice per second in synchronism with the signal <p ₃ (= "H"). Because the signal φ ₃ is determined to have a period of 1/2 second which is a common multiple of the time, ie 1/256 second, which is required for one cycle of the data in the shift register ring circuit of the standard timing system as well as the time required for one cycle of the data in the shift register ring circuit in the auxiliary system so that the relative relationship between the data in the standard timing system and the data in the auxiliary system is established. Consequently, if the level of the input terminal MSIN is changed from "L" to "H" or if the input terminal MSIN continues

the data in the shift register ring circuit is held at level "H" for more than a second of the additional system shifted by 16 bits, which means one more data record in the shift register ring circuit of the standard timing system, so that a particular record is updated and displayed will.

39 shows a preferred exemplary embodiment of an electrical detailed circuit for the marker setting circuit 1452. According to the illustration, the marker setting circuit 1452 has two flip-flops, by means of which a marker setting counter is formed. As mentioned above, the alarm time data is renewed and displayed by the manual shift operation. At this time, when the input terminal UDII is depressed three times, the marker setting circuit 1452 generates the signals

id ALI _x , ALD _x , ALI ₂ and ALD ₂ in a manner as shown in Table IV to represent the month and date alarm mark and the connection mark which inhibits the sampling of the coincidence of the alarm time data and the current time data . The marker setting counter is reset in response to at least one of the signals MSt 1 corresponding to the state in which the alarm time is not set and the level "L" of the terminal Y. When Y = "L", the marker becomes on -

15 Position counter forcibly reset to zero, making it impossible to set the month and the data alarm. _{Assume that counts 0} , _{1, 2} and 3 of the marker setting counter N 0, N _x , N 1 and N ₃

are, and then the following equations hold: I.

I ALI, = N ₃ - <p ₃ D ₁₅ %

£ ALI ₂ = (N _x + N ₂ + N ₃ ) ■ PjZ) | 55 + Q, ₆ · QOHER

% ALD _x = N ₃ ■ IPiD ₂ Ii

I 25 ALD ₂ = (N _x + N ₁ + N ₃ ) ■ ί> ₃ Ζ> ₂ 5 ₄ + QERAT.

46 shows a preferred embodiment of an electrical detailed circuit of the date gate

ß. Shown in 1482. The date gate 1482 has a counter 1467 which is used to count to 8 (0 to

C 7). When the count 7 is determined by counter 1467, a trigger input pulse is sent to a second

I w counter led. When the count 8 is obtained by the first counter 1467, the first counter 1467 turns up

p, "0" is set, and the second counter is set to "1". The setting input becomes the first counter

fi 1467 blocked. If DGO = "H" (ie ~ BU0 = "L"), the first counter 1467 counts the number 8, and in this one

l ·; State the date gate is opened. The first counter 1467 is activated by one of the following inputs

.7 deferred, namely

Ii, which will be explained in detail below, and a calculation start signal from a gate 1462 (FIG. 48), where

^ the second counter is reset by the input signal P _x . According to the illustration, the date gate

I 4u circuit 1467 also has a gate 1463 which determines the downward control of the signal which the PM

I indicates marker data, and the sampled down control signal is input to the first counter

'ifl fed.

|| 48 illustrates a preferred embodiment of an electrical detailed circuit for the

Calculation circuit 1481. The calculation circuit 1481 has a first counter 1465 and a second counter 1466 45, both of which count up to 60 (0 to 59). Computation circuit 1481 also has first and second flip-flops 1471 and 1472 which are connected to the first counter 1465 and the second counter 1466, respectively.

β; The count above 60 is stored in flip-flops 1471 and 1472, and the outputs of the

■] i flip-flops 1471 and 1472 are fed to the reset inputs of counters 1465 and 1466, respectively, which

I must be reset to "0". The computing circuit 1481 has an input terminal X, which is normally

il is brought to a level "L" in this way. When X = "H", the outputs of flip-flops 1471 and 1472 become dem

P is supplied to the first counter 1465 and the second counter 1466, which are consequently reset to "0".

ψ The arithmetic circuit I48I also has a third flip-flop 1473, which is soft due to the inverted signal! DGO

ψ by the date gate circuit 1482 and the arithmetic control signal P _{is set, which is from the input

$ Analyzer circuit 1483 is supplied so that counting begins. The computing circuit also has a gate

| S 55 1461 to which signals φ ₃ ΰ ₃ 'ξΦ _ι and p, are supplied, in such a way that a 1 Hz signal

| i is generated, which is synchronized with the timing ξ Φ _χ. A gate 1462 is with the signals 3g Φ _χ

% and Qc supplied and generated a 64 Hz signal which the first counter 1465 and the second counter 1466

• jft is fed. This signal is also fed to a gate which generates a reset signal which

| l is to be fed to the reset input of the counter 1467 of the date gate circuit 1482.

I ₆ o If the switch is depressed to start the arithmetic circuit 1481, if DGO = "H" then

f. an input signal Ρ _{λ is} generated when one minute has passed after the switch was depressed. There

't, actuation of the switch automatically brings the seconds display in the standard timing system to zero,

;; the first counter 1465 of the arithmetic circuit 1481 is reset, and the count in the second counter of the

The standard timing system coincides with the count in the counter 1465 of the computing circuit 1481. Included

i; ₆₅ , the count in each of the counters is "0" and thus the date gate circuit 1467 is reset.

Egg; If the next input signal P _{1 is} generated a week later, when DGO = "H", it becomes the third flip-flop

£ 1473 of the arithmetic circuit 1481 is set and generates a signal Q _c , ie Q _c = "H" and consequently the number

¹ lings or contents in the first counter 1465 and the second counter 1466 at a higher speed

ΐ: 46

in response to the signal Tjj Φ , shifted so that the count or the content in the first counter 1465 goes to "0". At this time, the third flip-flop 1473 is reset to "0" and the second counter 1466 stores the calculated count therein at Q _c = "L". The reset signal is the Date-gate circuit also supplied to the gate r-date counter 1467 1482, so that the inverted output signal DGO reaches a higher level. Assume that the count of the second counter 1466 calculated in response to the first timing input signal P ₁ is ATi and that the count C _{t of} the first counter 1465 is zero after the first timing input signal P _{1 is} applied . It is further assumed that the count of the first counter 1465, which was calculated in response to the second time input signal P ₁ , is equal to C ₂ , so that the situation then exists that the electronic watch in the illustrated embodiment is C ₂ seconds within one Week is advanced. Now, when the second timing input signal P _{1 is} supplied to the third flip-flop 1473, the output signal Q _c becomes high and therefore a number of (60-C ₂ ) pulses becomes the second. Counter 1466 supplied, which consequently counts on the number (K ₁ + 60-C ₂ ). Since the second counter 1466 is constructed so that an overflow occurs when the calculated result exceeds the count of 60, the resulting count in the second counter is equal to (K ₁ -C ₂ ). If the circuitry is so constructed that it generates a correction signal to advance the time in a week by one second when the count of the second counter 1466 is increased by one, the count stored in the second counter 1466 becomes C ₂ seconds reduced, whereby a gain loss is precisely adjusted.

47, a preferred embodiment of the electrical circuit for the input analyzer circuit 1483 is shown. The input analyzer circuit 1483 includes a gate which generates an output signal in response to the signals UDII and QKT. This output signal is fed to an inverter 1464 which generates an output signal UDII ^+. This output signal is fed as an input signal for automatically resetting the seconds display to zero in the current time display to a first locking circuit and is locked _{by a composite digit signal Q 6.} The inverted output signal of the first latching circuit ^{and the output signal UDII +} are fed to a gate through which a differential pulse UDII is synchronized with the upward control of the output signal UDII ⁺ . The signal UDII is fed to a reset input of a flip-flop. The output of the first latch circuit is also fed to a second latch circuit by which the signal of the four second bits in the standard _{timing system is sampled in response to the signal Ji 3} Z) ₅ ^ Φ, · D IN2 and for reading out the output signal from the first locking circuit is locked. It is assumed that the state UDII = "H" is retained for a time interval beyond 4 seconds. The second interlocking circuit scans the state that the 4-second bits are at a high level, while the input signal UDII ⁺ , which is fed to the first interlocking circuit, is held at a high level. As a result, the inverted output signal "Q goes from a high level to a low level, so that the flip-flop is set and consequently generates an output signal of a high level. In other words, when the status UDII" = "H" is continued beyond a time interval of 4 seconds, the gain loss setting signal is stored as an input signal in the flip-flop. If the signal UDII ⁺ goes to a low level after the time interval has exceeded 4 see, the signal DINl is locked as a data signal in a third latch circuit in response to the signal q> zD <, Ti, Φ _{ and an output signal, which corresponds to the bits of 40 see in the current time. Thereafter, the change in minutes of the current time, which is represented by the downward control of the signal of the 40 see, is sampled by a fourth interlocking circuit. A signal that shows the change in minutes is referred to as signal 605t. 605t · UDII ⁺ denotes a signal which indicates that one minute has just passed after the signal UDII was held at a high level for the time interval of more than 4 seconds in the second mode of resetting to zero. The control signal P ₁ is the logical product of the signal 605 t · UDII ⁺ and the output signal QsD ₆ T _{24 of} the flip-flop, and it is used as a control signal to start the calculation of the adjustment loss. The output signal, which is the logical product of the signals 605 t · ^{UDII +} and Q ₉ , is fed to the reset input of the trigger-set flip-flop. The output of the trigger-set flip-flop and the output signal 605t · UDII ⁺ are fed to a gate which generates an output signal which is fed to a further gate to which a signal Q _{8 is also} fed. This gate generates an output signal DGR, which is fed to the reset input of the flip-flop of the date control circuit 14S2, so that the control circuit is reset to its initial state, ie is brought back to the status of the first day.

If the switch to reset the seconds display to zero over 4 seconds is not pressed, the trigger set flip-flop of the input analyzer circuit 1483 will not be triggered and therefore a signal which controls the setting of the gain loss will not be generated. As stated above, the output signal P _{1 is} not generated within one minute after the switch is pressed, and accordingly it is possible to cancel the application of the gain loss adjustment signal by setting the signal UDir high within one minute.

Fig. 49 shows a preferred embodiment of a frequency adjusting pulse generating circuit. This circuit has already been discussed above and therefore does not need to be explained in detail.

For this purpose 49 sheets of drawings

Claims (10)

Patent claims: 1.Electronic clock with a normal frequency signal source that applies a relatively high-frequency signal for counting the current time to a time measuring device, which emits time information signals that can be fed to a display for the current time, and with a frequency converter connected between the normal frequency signal source and the time measuring device, the clock signals, emits a time unit signal and time control signals which are low-frequency with respect to the high-frequency signal, characterized in that a device (36, 76; 386, 380) is provided which converts the time information signals, the clock signals and / or the control signals into periodic pulses (DATA A, Ts 3, Φ _λ Α, Φ ₂ Α ) chopped up, and that this ίο Signals are transmitted in chopped up form between the units of the electronic watch. 2. Electronic clock according to claim 1, characterized in that the chopping device (36,76; 386, 380) reduces an equivalent frequency of the chopped signals. 3. Electronic clock according to claim 2, characterized in that the chopping device (36,76; 386,380) chopped the signals in synchronism with the change in state of the time information signal. is 4. Electronic clock according to one of the preceding claims, characterized in that the chopping device (36,76; 386,380) the clock signals and the time information signals different from each other Duty cycle chopped up. 5. Electronic clock according to one of claims 2 to 4, characterized in that the equivalent frequency is less than 257 Hz. 6. Electronic clock according to one of claims 2 to 5, characterized in that the chopping device (36, 76; 386, 380) is responsive to the relatively low-frequency signal of the frequency converter (16). 7. Electronic clock according to one of the preceding claims, characterized by the device (40) for recovering the time information signals from the periodic bursts depending on i'S the periodic impulses of the clock signals. s | 25th 8. Electronic clock according to claim 7, characterized by a driver circuit (502 to 526) which on • f responds to the restored time information signals and generates a driver signal with which the display ■: ■ '■' geeinheit (22) can be operated in such a way that the time is displayed continuously. ^! s; 9. Electronic clock according to claim 4, characterized in that the duty cycle of the chopper ff direction (36, 76; 386, 380) can be set by an external control element. ; I 30 10. Electronic clock according to one of claims 1 to 9, characterized by a device (388), | i with which the time information signals can be brought into a serial form before they are egg (36, 76; 386, 380) must be chopped up.