DE2560193C2 - Electronic clock - Google Patents

Description

The invention relates to an electronic watch according to the preamble of claim I.

DE-OS 23 02 978 describes an electronic clock with a frequency converter that receives from a source divides emitted high-frequency signals and emits, for example, signals with a frequency of 1 Hz. the Timing device consists of several divider stages connected in series, which correspond to the seconds, Make a division of the impulses in minutes and hours. The well-known watch also has one Alarm function. The hour display and the minute display can be corrected by means of a push button switch each will. These push button switches are also used to enter a single alarm time into one specially provided alarm time memory. A coincidence circuit is used to check whether the saved Alarm time coincides with the current time. If there is agreement v, i. so becomes an alarm triggered. The function of the known clock is therefore limited to the time display and the Detection of a single alarm time.

The invention is based on the object of specifying an electronic watch of the generic type in which additional data groups can be stored, selected and displayed with the simplest means.
According to the invention, this object is achieved by an electronic watch having the features of the characterizing part of claim 1.

The additional register arrangement that can be attached to the electronic clock enables the storage of further ones Data groups that can be easily accessed via an external control element a trigger signal is applied to the additional register arrangement, so that these additional data groups in the main register of the electronic clock is transferred, where an update and / or a display is initiated can be.

Preferred developments of the electronic clock according to the invention are characterized in the subclaims.

An embodiment of the electronic watch according to the invention is shown below with reference to the drawing explained in more detail. It shows

F i g. 1 is a schematic block diagram of a solid-state electronic watch according to the invention;

FIG. 2 is a schematic representation in which the general structure of the shown in FIG electronic watch is illustrated.

K i g. 3 a simplified block diagram of an electrical circuit for the in the I-i g. 2 shown IIhr. F i g. 4Λ. 4B and 4C each show a representation, which is a detailed block diagram of an electrical panel door the in the F i g. 3 reproduces clock shown.

F i g. 5 shows a preferred exemplary embodiment of a time normal signal oscillator, as shown in FIGS. 4A, 4B and Figure 4C illustrates

FIG. 6 shows an example of waveforms generated by the circuit illustrated in FIG. 5 will.

F i g. 7A and 7B each show a representation of a preferred exemplary embodiment of the one shown in FIGS. 4A. 4B and 4C of the synthesizer illustrated,

F i g. 8 is a diagram illustrating the relationship between clock pulses and timing pulses deviate from the one shown in FIGS. 7A and 7B are provided to the synthesizer illustrated.

F i g. 9 and 10 are each a diagram illustrating waveforms generated by the circuit shown in FIGS. 7A and synthesizers shown in FIG. 7B are generated,

F i g. 11A and 11B each show a diagram showing in detail a circuit for the timer register according to FIG F i g. 4A, 4B and 4C illustrate,

F i g. 12 is a diagram showing a detailed electrical circuit for the FIG. 4A, 4B and 4C Control unit illustrates

F i g. ! 3 shows an example of a flexible circuit as shown in FIGS. 4A, 4B and 4C is shown.

F i g. 14 is a schematic representation of a shift register according to FIG. 11 and 12,

15 is a diagram showing an example of a circuit for setting a logic ·. Level according to Fig. 12 veraiisehauiiciii,

F i g. 16 shows a detailed circuit arrangement of the circuit arrangement in the control unit according to FIG. 12 timer used,

F i g. 17 is a schematic representation of a wrist watch formed in accordance with the invention;

Fig. 18 is a section showing the relationship between the position of the crown and associated parts;

F i g. 19 is a diagram illustrating the operation of the crown and switches of FIG. 18 illustrates

F i g. 20A and 20B each show a representation which shows a detailed circuit for the in FIGS. 4A, 4B and 4C illustrated data modulation unit illustrates,

F i g. 21 is an illustration which shows a preferred embodiment of the embodiment shown in FIGS. 4A, 4B and 4C Alarm unit illustrates

F i g. 22A, 22B and 22C each show a detailed block diagram of the display driver and associated parts.

F i g. 23 is a schematic diagram illustrating an example of the display area;

F i g. 24A shows a detailed electrical circuit for the circuit shown in FIGS. 22A, 22B and 22C shown level shifter,

F i g. 24B shows a representation similar to FIG. 24A, which, however, is a modified example of the level shifter illustrates

F i g. 24C is an example of a decoder such as that shown in FIGS. 22A, 22B and 22C is shown,

F i g. 24D is an illustration of the operation of the FIG. 22A-C of the display driver shown,

F i g. 25 is an illustration showing a general concept of the invention preferably in addition intended system.

F i g. Figure 26 is a simplified block diagram illustrating a preferred embodiment of the preferred embodiment provided System according to the invention illustrates

F i g. 27A, 27B and 27C are each an illustration showing a detailed block diagram for the according to the invention preferably provided system according to FIG. 26 illustrates.

F i g. 28A and 28B each show a circuit diagram of a shift register ring circuit according to FIG. 26th

F i g. 29 an exemplary embodiment of a clock pulse control gate according to FIGS. 27A. 27B and 27C,

30 shows a preferred exemplary embodiment of a data modulation circuit according to FIGS. 27A, 27B and

F i g. 31 shows an example of a composite pulse generation circuit;

F i g. 32 shows an example of a time pulse or clock pulse generation circuit according to FIG. 27A. 27B and 27C,

Fig. 33 is a diagram showing a sampling circuit for detecting and displaying the current time

illustrates

F i g. 34 is a diagram illustrating a synchronizing signal generating circuit;

F 1 g. 35 is a diagram illustrating a sampling circuit for the . Tus of an alarm time display;

V i g. 36 is a diagram illustrating an example of a composite pulse generator;

I i g. 37 is an illustration showing a combined signal generator.

I i g. 38 is an illustration of a manual shift control circuit;

F i g. 39 is a diagram illustrating a circuit for setting a marker.

F 1 g. 40 is a diagram illustrating an example of an input control circuit.

F i g. 41 is a diagram illustrating an output control circuit;

F i g. 42 is a diagram showing an example of a sampling circuit for a coincidence of an alarm time and oo

the current time illustrates

F i g. 43 is a diagram showing an example of a sampling circuit for the coincidence of a data alarm and FIG

corresponding data illustrated,

F i g. 44 is a diagram illustrating an example of a shift register stop control circuit; F i g. 45 is an illustration of a circuit for counting a leap year;

F i g. 46 is a diagram illustrating an example of a data gate control circuit; F i g. 47 is a diagram showing an example of an input analyzing circuit; F i g. 48 is a diagram illustrating an example of an arithmetic circuit;

Fig. 49 is a diagram showing an example of a gain loss adjusting pulse generator

clearly, |

F i g. 50 is a representation which illustrates waveforms of a flip-flop, which in the preferred

se provided system according to the invention is used, <

Fig. 51 is a diagram showing an operation mode of the illustrated in Figs. 28A and 28B]

Shift register represents ji

F i g. 52 is a diagram illustrating waveforms generated in the manual shift control circuit |

according to FIG. 38 are used, I.

F i g. 53 is a diagram showing waveforms of the output signals generated by the synchro · s

ίο nisiersignal generating circuit are supplied, ti

F i g. 54 a position. which is a further embodiment of the in FIG. 46 illustrated data gate- I

Counter illustrated. |

F i g. 55 is a diagram showing the relationship between various timing signals, ij

56 is a scrematic diagram each illustrating the mode of transmission data, |

and I.

Fig. 57 is an illustration showing the relationship between the in the according to the invention preferably jj

provided system illustrated pulses used. p

In the F ι κ. I is a schematic block diagram of a standard timing system according to the invention? I.

or timing system 12 illustrated. An optionally or preferably provided system 12 can be used in I.

Need to be connected to the standard timing system 10 in order to fulfill special functions, such as %

is explained in more detail below. The standard time measuring system 10 is constructed in such a way that it ', -> fulfills various functions, for example a time measurement and a corresponding time display, with
slightly additional Sy ^c systems such as 12 can be connected, so that the standard time measurement system fulfills additional functions.

According to FIG. 2, the standard time measurement system 10 has a time normal signal oscillator 14 which has a *,>

Crystal and serves to provide a very accurate frequency, with the oscillator operating at a frequency \

oscillates from 32 768 Hz. This relatively high frequency is fed to a r * synthesizer 16, which with very |

more precise frequency generates a time unit signal of 256 Hz and which continues to have various time control I

Signals generated around the EU are used to control various components of the standard timing system 10. These signals j

are fed to a measurement register 18 which counts the number of pulses of the time unit signal so that \

thereby the current time is measured and a time data signal is provided. The time data signal becomes I.

fed via a display driver 20 to a display device 22 such as liquid crystal display elements. With ji

24 is an electrical energy source such as a silver oxide battery, which is used to power various,

To supply components of the S andard timing system 10 with energy. If this is optional or preferably 5

se provided system 12 is connected to the standard timing system 10, the electrical energy f

source 24 also supply various components of the optionally or preferably provided system 12. %

The standard timing system 10 also includes a control system 26 which is arranged such that the |

Synthesizer 16 is controlled, that the timing register 18 and the display driver 20 for different \.

ne purposes are controlled, as will be explained in more detail below. S.

The optionally or preferably provided system 12 is also referred to briefly below as an additional system 12 |

designated. The auxiliary system! 2 is arranged so that it can store time data such as an alarm time, |

which are fed from the time register 18 of the standard time measurement system 10, and it can still be |

Store input data. for example, data relating to a month or a date, where |

jj corresponding symbols can be supplied by external control elements. To generate alarm time |

data, the learned control elements of the standard timing system are used. The alarm time data is i

which is delivered to the adjunct that stores the data. Alarm time data is taken from both the standard |

Timing system as well as saved by the additional system. Several alarm time |

data are sequentially given to the shift register of the standard timing system and stored there, |

whereupon the stored data is compared with the current time data. The additional system 12 serves |

also to generate new data, which are explained in more detail below. That on this V.; ise |

The additional system 12 formed is used to generate a gain-loss adjustment signal (i.e. a signal »Faster / |

Slower «) depending on the new data generated in the additional system 12 *

will. This signal can be supplied to the time normal signal oscillator 14 as shown by a broken line in Fig. 2. However, the gain loss adjustment signal is supplied to the synthesizer
16 supplied. Furthermore, various data, which are stored in the additional system 12, the
Timing register 18 is supplied from which various data are stored without the timing
is disturbed, and these corresponding data are transmitted to the display device 22 via the display driver 20
While the data from the additional system 12 is not fed directly to the display driver 20 here
the various data from the auxiliary system 12 can be sent directly to the display driver 20 for display
are fed.

The F i g. 3 is a simplified block diagram of the electrical circuit for the standard timing system 10 according to FIG. 1. The circuit generally has the following parts: a standard signal oscillator 14, a

Synthesizer 16. a control unit 30. a timing register 32, an alarm unit 34, a data modulation input?

heu 36. external control elements 38, a level shifter 40. a bit-series-parallel converter 42, a Dckof The latter 44, a word-to-series-to-par converter 46, a display driver 20, and a display device 22.

The time normal-fit signal oscillator 14 has a crystal which oscillates at a frequency of 32,768 Hz. J

This frequency is fed to the synthesizer 16, which generates a time unit signal of 256 Hz and various I

provides the timing signals for driver components of the standard timing system. The time unit signal |

is fed to the control unit 30, which generates an output signal based on the time unit signal. This output signal is fed to the timing register 32, which shows the number of pulses of the output signals counts and updates time data.

The timing register 32 has a storage register. which can be increased and in which an initial value can be easily set. It supplies output signals in bit-written form. The control unit 30 is controlled by external control elements 38 in order to set the initial value of the counter which forms the timing register 32. The output data of the timing register 32 are fed to the data modulation clock 36, which modulates the data which are dependent on the stored data in the Zeilmeßregister 32 and depending on the data of the external control element 38 are to be displayed.

The data modulation unit 36 is used to generate an intermittent output signal in order to thereby Power consumption / u save. This intermittent output signal is used by the display driver circuits supplied, including the level shifter 40. of the bit-serial-parallel converter 42. of the decoder 44. des Word to serial to parallel converter 46 and the display driver 20. The level shifter 40 operates so that the Signal level is changed in such a way that the logic amplitude is amplified. The bit-series-parallel converter 42 has a 3-bit shift register, which the output signal of the modulation unit from a Converts bit serial signal to bit parallel signal to generate word serial signals. The output signal, which has been converted in this way is fed to the decoder 44 which generates decoded word-serial signals which are fed to the word-serial-parallel converter 46. This generates digit-parallel Signals. The decoded partial code is amplified by the display driver 20 to thereby the display device 22 to drift.

According to the illustration, the electrical circuit for the standard time system is designed such that it supplies the output signal to the auxiliary system 12, as indicated by an arrow in FIG. 3 is illustrated. That Supplementary system 12 is constructed in such a way that it sends various signals to the synthesizer 16 and the timing register 32 of the standard timing system.

A detailed block diagram of the electrical circuit for the standard timing system is shown in FIGS. 4A, 4B and 4C illustrate in which the same or corresponding components are provided with the same reference numerals as in FIG. 3. As shown, the time normal signal oscillator 14 is connected to a crystal 48 and is controlled by this in order to generate an output signal Φο, ie a pulse train which has a pulse repetition frequency of 32,768 Hz and has an extremely high frequency stability . The output signal Φο is fed to an input of a frequency summing gate 50 of the synthesizer 16. The frequency summing gate 50 has a further input which is connected in such a way that it receives a gain loss setting signal Φη which is passed through a frequency summing gate 52. One input of this gate is usually grounded and another input of this gate is connected to the auxiliary system 12 to receive a low frequency signal, ie the signal Φ _Ν . which is used to adjust the gain / loss as described above. The output signal Φζ from the frequency gate 50 is fed to a first timing pulse generator 54 which forms part of the synthesizer 16.

The first time pulse generator 54 generates various timing signals, including the clock pulses Φ \ and Φ ₂ , the time pulses Γ, to T ₈ and the digit pulses D ₂ to Di ₆ , and it also generates signals Φικ ι and Φι 11 ₂ for up-converters that are in the additional system 12 are installed. A second time pulse generator 56, 4C,

which also forms part of the synthesizer 16, receives the time signals or timing signals, which are from «

the first timing pulse signal generator 54, and generates various combined timing control *

signals, for example a time input signal D \ T ₁ of 256 Hz. From which the control unit 30 generates a signal X of. |

256 Hz, which is fed to the timing register 32. The timing register 32 has a shift register ring 58 for storing various data. The shift register ring 58 has a first shift register 60, an adder circuit 62, a second shift register 64, an AND gate 66 and an OR gate 68, which are connected in series so that a loop circuit is formed. The shift registers 60 and 64 have shift registers of 60 or 4 bits to store the time data or various other data. the Adding circuit 62 has an adder 62a. a shift register 626 and an OR gate 62c. the Adding circuit 62 serves as a write-in gate to add data other than time data to the timing register to be able to enroll.

The outputs Q ₆₂ . Qu, Qm and Q _{65 of} the shift register ring 58 are connected in parallel to a data sampling unit 70 which has a carry request detector 72 and a data detector 74. The carry request detector 72 is used to determine the status in which a carry is occurring should, and it generates carry request signals Wz, W ₄ and VV ₅ . These signals are fed to the control unit 30 and passed through the corresponding carry lock gate of the control unit 30 to a summing gate of the control unit 30, to which the timing signal Di T _{1 is} also applied, in order to generate the output signal X , which is sent to the OR gate 62c the adder circuit 62 for the carry is supplied.

The data detector 74 determines the contents of the data which are stored in the shift register ring 58 and generates output signals A TO, O-sup, CONTA and B. The output signal A TO indicates that the data of the alarm time are not stored in the shift register ring 58, and it is supplied to the alarm unit 34. The output signal O-sup indicates that the tens digits of the data stored in the shift register ring 58 are equal to "0", and it is fed to the data modulation unit 36. The output signal CONTA indicates that an increase in the data stored in the shift register ring 58 data has taken place, and it is used for controlling the data modulation unit 36 so that it controls the pulsed specifying Daien and clock pulses, the output signal B is determined depending on the time data, which are stored in the shift register ring 58 is generated, and it is supplied to the data modulation unit 36 so that the unit 36 causes selected data to flash or blink at 1 Hz.

The control unit 30 is responsive to the input signals SH. SM, SK. SD, SLJO, SLJT, SLJ 1 and SLJ2. which are supplied by the external control elements 38, and generates output signals S \, S2, LJ, LJL. G, So and X. The output signals S 1 and 52 are fed to the alarm unit 34, to which the inverted output signals UL from the control unit 30 are also fed. The output signal X is applied to the timing register 58, as already described above. The output signals U, LJL and G are fed to the data modulation unit 36. The signals SD, SK and SLJZ, which have passed through the control unit 30, are fed to the data modulation unit 36. The output signal So is fed to the data sampling unit 70.

The data modulation unit 36 has various data switching functions. It modifies selected parts of data that are fed to the display, as well as the time pulses and the clock pulses that are also applied. According to the invention, the data modulation unit 36 has a circuit which serves to modulate the data, and the data chopper circuit 76 serves to achieve an intermittent modulation of the output data. More precisely, the data chopper circuit or intermittent output circuit 76 generates a serial pulse train DATA-OUT for the data to be displayed in a fixed period of 1/256 sec every 1 / lb seconds, as well as intermittent modulated line control signals Tu / 1. ΦιΔ and Φ \ Δ, so that the energy consumed decreases. According to the above, the data modulation unit 36 serves to modulate the contents of the data with a view to display modulation. However, the display mode of the data is modulated without changing the content of the data. For example , instead of the CiIiCi iiiiaiugcn display a ucbiiiuniics segment uuci illuminate a ucätiillinicFi part lü and switch off the lighting of another part, the display is done in such a way that the lighting of a certain part is interrupted and other frequencies of the output signals are significantly reduced to the Limit energy requirements to a minimum. Furthermore, the modulation takes place in such a way that data which indicate a marking or mark represent the background and a unit of information to be displayed. These modulations are particularly advantageous because the information is easily visible on the display area. The decoder is used to decode these various modulated data.

Intermittent or chopping modulation of the output data and the timing signals is reduced the energy consumption of the standard timing system is high. For example, it is possible to use energy display driver circuitry and adjunct system to less than 1/10 of existing standard timing systems by intermittently generating the output signals 16 times per second. At a known arrangement, it is necessary to use a large-scale integrated circuit, which consumes a considerable amount of energy, while according to the invention the possibility is opened up Manufacture wristwatches that fulfill multiple functions in a similar way, but much less Consume energy. This also reduces the size and capacity of the battery. Be it notes that the output data can only be displayed if the content of the data is changed, and the output data can also be displayed at the request of the user. That way it is also possible to reduce the power consumption of the auxiliary system and the display driver circuit.

The output signals Q 62, Q 63 and Q 65, which are supplied by the shift register 64, are supplied to the data modulation unit 36. When the output signals Q 62 and Q 63 are received, the data modulation unit 36 generates a blinking pulse of Φ \ Hz. The output signal (65 is used to provide a signal to display the daily alarm mark. The signals B and O-SUP are also the Data modulation unit 36. The signal B is a synchronizing signal and is used to generate the lightning signal ν η 1 Hz. The signal O-SUP is used to modulate the display of the time and date

Signal F supplied to alarm unit 34 is used to generate a signal to flash the alarm coincidence signal j

allow. The data modulation unit 36 is also responsive to the SD, SK and UL signals and generates an output signal D _n to provide the alarm time, date and current time indications.

The input signals SU 1 and SU 2 are used as input data for the standard timing system and are fed to the components, which are determined by various combinations of input signals SH. SM. SK, SD and SUO or St / Taus have been selected, which are provided by the external controls 38, as will be explained below. The symbol SUO represents an input terminal for unlocking the input data, and SLTT represents an input terminal in a timing device for unlocking the input data.

The signals SH, SM. SK. SD. SUO and SUT are fed to control unit 30 and are used to perform the following functions:

a. Selection of the addresses, which by combined signals from the input signals SH. SM, SD and SK are to be unlocked;

b. Unlocking of the selected addresses by the input signals SUO or SUT;

c. Supply of the input data SU 1 or SU 2 to the unlocked addresses, so that this enables the current time to be changed.

At this point it should be noted that the circuit is constructed in such a way that it is possible to automatically set the seconds display to zero, regardless of the unlocking signal. The circuit is also constructed in such a way that the previously set digit is prevented from being changed to a higher order digit during the time setting by the signal X.

The alarm unit 34 will be described below. The alarm time data, which can be temporarily required, i.e. intermediate data, or data required daily, are stored in the four digits of the shift register ring 58, which are indicated by the digit pulses A3 to D \ & as a function of the Sigrmlen SH. SM. SK. SD. SUO. SUT. SU ₂ and SUi are set. The alarm unit 34 responds to that

inverted signal TJL and is held in an unlocked position so that the alarm time can be set. While the alarm time is being set, the alarm unit 34 is prevented from supplying a clear signal to the time-off register 32. If the alarm time coincides with the current time during the alarm time setting, no alarm ion will be generated. Further, the alarm unit 34 is arranged so that even if the current time coincides with the alarm time during setting of the current time, a clear signal for clearing the alarm time is not generated.

The coincidence of the time data stored in the shift register ring 58 and the alarm time data is determined by a comparison between a predetermined time interval between the times D ₆ and Ο3Γ4, an output signal which is represented by DATA 60, which is the input signal to the 60th flip-flop of the shift register ring 58, and an output signal ζ) 29, which corresponds to the output of the 29th flip-flop, equal to the data represented by DATA 28. If such a coincidence is established, the alarm unit 34 sends an alarm signal ALS to an alarm device 78, which is supplied with energy over a predetermined time interval, ie over one minute. During this time interval the alarm unit 34 sends a signal F to the data modulation unit 36, whereupon the unit 36 generates an output signal in order to make all the display elements flash. When the user acknowledges the alarm and operates a switch 80, a stop signal STP is generated and fed to the alarm unit 34 so that the flashing or blinking of the display and the alarm sound are switched off. Such a shutdown operation can also be carried out by one or the other of the input signals SU 1 or SU 2 , which are supplied by the control elements 38.

It should be noted that the shift register 58 is arranged to temporarily store alarm data and daily alarm data. If the temporary alarm data are stored in the shift register ring 58, a display of the alarm time is triggered only once and switched off by the stop signal STP , or the signals S 1 and 52 are switched off, while the alarm unit 34 supplies a clear signal to the shift register ring 58 at the same time , so that the data stored in it will be deleted. If the daily alarm data is stored in the shift register ring 58, the clear signal is not generated by the alarm unit 34, the alarm time data stored in the shift register ring 58 can also be cleared by setting the alarm time to zero under the control of external control elements 38. The status "0" of the alarm time is determined by the data detector 74, which then generates a signal ATO , which indicates that ( ⁴ per alarm time is in the status "0". This signal is fed to the alarm unit 34 so that a clear signal is generated In this case, the display device only shows the zero time of the hour digits. A flexible circuit is shown at 82, which serves to provide further functions for the electronic watch than can be achieved by means of the external control elements the flexible circuit 82 has a flip-flop circuit which is designed in such a way that frequency division is carried out, and it generates a signal LY (ie "leap year") which is fed to the data sampling unit 70.

FIG. 5 shows an exemplary embodiment of the time normal signal oscillator 14 and the switching elements connected therewith. According to the illustration, the time normal signal oscillator 14 has a quartz oscillator 48. which oscillates at a frequency of 32 768 Hz, furthermore has a CMOS inverter 90, a resistor 92, which has a resistance of about 30 mega-ohms, and a resistor 94, ^ it has a resistance of about 500 kilo-ohms and is operated in such a way that the output impedance is maintained at a substantially constant level so as not to impart a distorted waveform to the crystal oscillator 48. Furthermore, a capacitor 94 with a capacitance of approximately 25 pF and a trimming capacitor% with a capacitance of approximately 20 pF are provided. The quartz oscillator element 48 has a resonance frequency of approximately 32,768 Hz. Furthermore, two exclusive OR gates 50 and 52 are present. The exclusive OR gate 50 serves to generate a signal which has a frequency which is equal to the sum of the frequencies of the two signals Φν and Φο which are fed to respective inputs. Since the output frequency is not changed by the logical inclination of the OR gate 50, an anti-coincidence gate or an identity gate can also be used to serve the same purpose.

The F i g. 6 shows the waveforms of the input signals Φν and Φο and the output signal Φ /. From FIG. 6 it can be seen that the output signal Φ / is achieved when the signals Φο and Φν are applied to the input terminals of the exclusive OR gate 50, and it has a frequency which is equal to the sum of the frequencies of the signals Φο and Φν .

The F i g. 7A and 7B show an example of a detailed circuit of the synthesizer 16 shown in FIG. 4A. According to the illustration, the output signal Φζ from the frequency summing gate 50 is fed to a frequency divider 100 which halves the frequency and forms part of the first time pulse generator 54, it also having a flip-flop circuit 102 and AND gates 104 and 106. The frequency divider 100, which halved the frequency, thus generating clock pulses Φ \ and Φι, which are fed to the timing register 32, a data modulation unit 36, a display driver 20, etc. are also present, which are used for the purposes described below. The clock pulse Φ2 is also fed to a frequency divider 108 which divides the frequency by four and has four cascaded shift registers 110, 112, 114 and 116 ec which are connected to the logic gate 118 to form a loop. The frequency divider 108, which divides the frequency by four, generates timing pulses Tu T2, Ts, and Ts, which are shown in FIG. 8 are shown. Each of these Zeits * euerimpulse has a repetition frequency of four times the period of the clock pulse Φ2 and a pulse width equal to the period of the clock pulse Φ2. These timing pulses are fed to the second timing pulse generator 56 which generates various combined timing signals. The timing pulse 7s is also fed to the data modulation unit 36 for the purposes explained below. The timing pulse Ti is fed to a frequency divider 120 which divides the frequency by 16 and has eight static locking circuits 122 to 136 and a flip-flop circuit 138. the

Flip-FlDp circuit 138 is bistable, and its output signals Q 138 are set up and removed synchronously with the timing pulse Γι, and it has twice the period of the timing pulse 75. The output of the flip-flop circuit 138 has the same waveform as a Clock pulse Φυ € \ · The relationship between the signals Q 13tr and Φυη is taken from the waveforms in FIG. 9, which illustrates the waveforms of the various timing signals, AND gates 140 and 142 are connected to flip-flop 138 and generate a clock pulse Φ _α in response to the unlocking of the clock pulse Φυη and a clock pulse φ in response to the down control of the Taktünpulses Φυη according to FIG. 10.
The signals Φ * Φο and Γι are linked by the following relationships:

ίο <Pj + Φη = Γ,

& _d & b = 0 (corresponding to the low level »L«)
0, -T ₁ = Φ,

Φί, - Tt = Φο

The reason why the clock pulses Φ ₃ and # £ are generated is that the divider 120 simplifies t vv so !! to generate the! 6 digit pulses D- to D; z . According to F: g . 7A and 7B see the j'4 part 103.

which generates the timing pulses 75, T ₂ , T ₄ and Tg in response to the clock pulse Φ2 , from the four data flip-flops 110, 112, 114 and 116, which are triggered by the clock pulse Φ ₂ . When the divider 120 (■ i0) is constructed using components similar to those used for the divider 108 (1/4). It is necessary to provide 16 main-sub-data flip-flops to generate the 16 digit pulses. In the example according to FIG. 7A and 7B, however, the divider 120 (1/16) is made up of only eight interlocking switches

2 ") rings, which correspond to the four main-sub-flip-open circuits.

The data input signal is read into latch circuit 122 in response to the warm-up clock pulse Φ to produce an output signal Q 122. The latch circuit 122 is latched when the clock pulse Φα is at a low level. Until the clock pulse Φ _α goes high, the latch circuit 124 responds to the clock pulse Φο and it is fed to the output Q 122 as a data input and it is latched. In this way the data goes through successive latches every time the file! through a locking circuit , they will be delayed in their phase by one period of the timing pulse Γι. The output signals Q 124 and Q 132 are passed through a mode locking gate 144, the output signal of which is fed to a NOR gate 146, which is also fed to the output <? 128. In this way, the locking circuits 122 to 136 generate output signals Q 122 to Q 136 with a pulse repetition frequency of 16 T \ and a duty cycle of 50%. The digit pulses A to D \ 6 are generated depending on the output signals of the respective latch circuits 122 to 136. For example , the digit pulse D \ is generated by a gate 148 in response to the inverted signals ζ) 122 and ζ? 136 produces. Similarly, the digits pulse Di by a gate 150 in response to the inverted signal Q 124 and the signal is generated) 122 ζ. The other digit pulses Eh to Di6 are generated in a similar manner and are therefore not explained in detail.

The F1 g 8 shows the relationship between the clock pulses Φ /, Φι and Φ \ on the one hand and the timing pulse T-. T ₁ . Ti and Tg, on the other hand, which are produced by the divider 108 of FIG. 6A which divides by four. FIG. 9 illustrates waveforms of the timing pulses T to Ts of the digit pulses

4 ^ I) to D _1b . of the data signal DATA and the timing pulses Φιχ \ and Φη ι- In the Fig. 9 is shown with the content of the data, which are illustrated by the digit pulses D \ to D \ _b . The relationship between the remote pulses and the data is as follows:

D 1-256 second word

/> - M6 second word
/ YI second word

Diβ: alarm time marker digit

According to the phases of these digits, the digits are divided into four groups. The high level of the pulse Γι corresponds to "1" and the low level corresponds to "0". The high levels of the pulses T ₂ , T ₄ and Tg οι correspond to the weights 2, 4 and 8. It can be seen from this that the waveform of the data signal represents its content. The data shown in Fig. 9 indicate that the standard Zeitmeßsystcm cino part provides the correct time information 2: 32 PM, 33 seconds with 1/16 seconds plus 8/256 seconds. 24.) supplies u! I, whereby the daily alarm time is set to] I: 59 AM. The names AM

as well as PM correspond to the usual information in the Anglo-Saxon time system »ante meridiem« and »post meridiem«, & h. »In the morning« or »in the afternoon«. The clock pulses Φ \ ; 02. the timing pulses Ti, Ti, Ti and Tg and the digit pulses D \ are fed to the second timing pulse generator 56, from which various combined timing signals are generated. In order to simplify the drawing, a detailed circuit arrangement of the second time pulse generator 56 is not shown.

The F i g. 11A and 11B each show a circuit diagram showing an example of a timing register 32 In accordance with the above, the time register includes a shift register ring 58 and 58 a data sampling unit 70 having a carry request detector 72 and a data detector 74.

The shift register ring 58 contains a 60-bit shift register i50, the output Q \ of which is connected to a four-bit shift register 64 via an adder circuit 62. The output Q 61 from the shift register 58 is connected to an input of an AND gate 66, and the output of this gate is connected to an input of an OR gate circuit 68. The other entrance to the. AND gate 66 is connected to the output of an OR gate 162 via an inverter 160, so that when the output signal from the OR gate 162 is at an "H" level, this output is inverted by the inverter 160, so that it has the low level "L". As a result, the output of AND gate 66 is "L". The output of the OR gate 68 is fed back to the input of the shift register 60, and for the moment with data D 60, which are also fed to the modulation unit and the alarm unit, in order to fulfill various purposes, as will be explained in more detail below.

The shift registers 60 and 64 are arranged and designed in such a way that they write input data into a slufe when the clock pulse Φ \ is at level "H", and that they read out data from the stage when Φι = "H".

The shift register 64 has flip-flops 64a, 646, 64c and Md which store data when the clock pulse Φ \ is high, and their stored contents are read out in response to the build-up part of the clock pulse Φι. The clock pulses Φ \ and Φι have a frequency of 2 ¹⁴ Hz, so that writing and reading processes are carried out 16,384 times per second. Accordingly, output signals from the flip-flops are sequentially - shifted in a corresponding manner.

According to the above explanations, the shift register circuit 58 has an adder circuit 62, so that the arrangement consequently serves as a counter. The adder circuit 62 has an adder 62a, a shift register 626 and a gate 62c. The adder 62a has an input a, to which the data from the shift register 60 are fed, and also an input / which receives an output signal from the gate 62c. The adder 62a has an output S. which is connected to an input £ 7 of the flip-flop 64c /, and an output C. which is connected to the input of the shift register 62 £>.

The gate 62c of the adder circuit 62 is supplied with a signal X including a carry signal, a time setting signal and a time unit signal D \ T \. The 64-bit shift register ring 58 sequentially transfers the data in response to the clock pulse at a frequency of

256 χ 15 χ 4 = 16 384Hz.

and the initially applied signal »1« appears on input a. the adder 62a with a timing DTaIIe 1/256 seconds. The carry signal C passes through the shift register 62b , which delays it by one bit, so that a delayed signal D2T2 is thereby generated, which is fed to the input β of the adder 62a. Output signals appearing at the outputs S and C are expressed by the following equations:

S = t ß.C = Λβ + ~ xß

In order to avoid confusion and to provide a better understanding of the invention, the the following definition and description of the terms are given:

1. Registration and readout:

According to the above description, the latching of data in the master stage becomes a master-slave flip-flop referred to as registered, and referred to as readout of this data if the data is on Output of the slave stage appear.

ii. Shift register:

A shift register; which is formed from a plurality of master-slave flip-flops is also simply referred to as a "shift register". The mere term "register" is not referring to a shift register limited, but also includes a system that is capable of capturing information or a Register part of information.

iii. Time control: «

Signals which occur at different output terminals of the respective shift register differ i

differ from each other, and such output signals are generated in response to the clock pulses. Since the clock pulses have a constant frequency, it is possible to view the output signals of the shift registers as a function of time. The output of the shift register 60 is represented by a symbol "DATA " (x, t) , which is a function of the position χ and the time /. The time t is also referred to as "time control". The output data of the shift register ring 58 are output periodically in pulsed form and then fed to the display driver or the additional system. At this point

it is incorrect to say that the signal is a function of time, but rather it should be denoted by the number of clock pulses. In the present description, however, the term “time control” is used in the usual manner. The time control signals A T \ and A Τ & Φ \ should also be able to be designated by the term “time control”.

iv. Data:

Where information or data stored in the shift register ring 58 is in response? <If the clock pulses are read out from any output terminal of the shift register, the read out information is referred to here as "data". The number 60 in the designation of the output DATA 60 gives

to the number of outputs of the flip-flops that form the shift register ring. Sometimes DATA (x ■ tj is abbreviated as "DATA x" or as "f DATA", where the χ following the designation DATA means that the data should be fed to the xth data input of the shift register. The symbol D \ also means $ DATA the content of the data in the number Αβ- It is therefore appropriate to express this fact as DieDATA 60. The xth output of the shift register is designated as Qx .

Thus DATA 60 corresponds to ζ) 59. In other words, the 59th output of the shift register is connected to the 60th data input terminal of the shift register.

The counting mode is explained below using a word 1 / 256th of a second as an example.

If the output signal Qi, which is fed to the input α of the adder 62a, is a binary "1" and the binary signal "1" is fed to the input β , the S output Q% 5 is a binary "0" and the C is -Output generates a binary "1" as the output signal. The shift register 62Z) writes in the binary "Ia" and reads out the signal "1"<when the clock pulses are at the high level "H", and it supplies an output signal which is delayed by one bit via the gate 62c to the input of the adder 62a. At this time, addition and carry are carried out according to the following relationships:

_ _

aß + aß = S. aß = C

For example, if 4 bits of the D \ data, which are designated by the timing of A and are passed through the shift register ring 58, are binary output signals "0" and if the output digits are the binary digits "0", "0", "0""," 0 "along the time axis, the information is added by the adding circuit 62 at a time on A Ti. As a result, the Α data becomes the binary digits "1", "0", "0", "0". After 1/256 seconds, when the next piece of information is added to the time of ATi, the relationships a = 1 and β = 1 are maintained, so that a binary digit "0" is provided as the output signal at the S output. At this time there is also a relation α β = 1. A binary signal "1" is delayed by one bit by the shift register 62 £> and supplied to the input / of the adder 62a at the time of D T. At this time the relationships * = "0" and β = "1" apply in such a way that the output signal generates its binary output signal "1". At the same time, the relationship a = 0 applies in such a way that output C becomes the binary digit "0". As a result, the Α data which has been passed through the adder circuit 62 i becomes the binary digits "0", "1", "0", "0". In this way, the content of the A data changes before »1« »1« »0« »0«, »0« »0« »1« »0«, »1« »0« »1« »0« , »0« »1« »1« »0« ... in chronological order every 1/256 seconds. In other words, the four bits of the A data change their binary states between "0" and "1" every 1 / 25b see. 2/256 s, 4/256 s and 8/256 s, each in such a way that 1/256-second digits are displayed.

If the Α data has the binary state »1«, »1«. "1". "1". reached, if the information was added at the time of A T \ , the binary state is changed to "0", "0", "0". "0". The D data, which through time

are denoted by Ai, the binary states become "0". "0", "0". "0" to the binary states "1". »0«,)

"0", "0" transferred at the time of D ₂ Tt . The four bits of Α data are at 1/16 see, 2/16 see, 4/16 see and ψ

Changed 8/16 sec each to represent 1/16 second digits. u

In this way, the shift register ring 58 is enabled to serve as a 4-bit counter with 16 digits,

in addition to its function of storing data. For example, the data change dv. ■ through the time of ATi denotes Di data every second, and it represents a one-second signal.

As is known per se, a clock is counted as follows: The digit units of a second, one minute and one day are based on the maximum values for the "ones" and "tens" digits. Seconds and minutes require a range from 0 to 9 in the "ones" position and from 0 to 6 in the "Tens digit", hours and months a range from 0 to 9 in the "units" digit and from 0 to 2 in the “Tens digit. and days of the week require the range from 1 to 7. Thus, the shift register accordingly Can take over the function of a clock, it must be arranged in such a way. da3 the digits are more appropriate Counts are brought to the appropriate counting units.

Whether or not a transfer should be carried out depends on the nature of the information content. A transfer takes place in the following way:

For example, the four-bit information of Α data represents the weight of 1/1 second, 2/1 second, 4/1 second and 8/1 second of the second unit represent, so that when the ArData is in the binary state »0« »1« »0« »1« are displayed for 10 seconds. In this case it is necessary to use the four bits of Set Α data to "0" and use the carryover for the 10-second digit. For example, if The four bits of A data are "0" "0" "1" "0", it is necessary to carry over to "1" "0" "1" "0"

raise. In other words, the process of carrying over is carried out in the following way:

(a) simultaneous determination of the information of four bits of the same digit,

(b) sensing whether the information is a prescribed one or not,

(c) Conversion of all four bits of the data into the binary state "0" and

(d) Add a "1" to the following digit, which is delayed by one bit.

In the embodiment according to the invention, as shown in FIGS. HA and UB, the output files ζ) 62, Q 63, Q 64 and Q & 5 are scanned by a data scanning unit 70, and a transfer operation is carried out as a function of executed on the scanned contents.

\\ According to the above embodiments, the data sampling unit 70 includes a transfer request detector 72, and has a data detector 74, which different output signals which are to necessary to actuate the control unit according to the invention, in which it scans the inner states of the system

The carry request detector 72 has matrix gate circuits 166,168,170,172 and 174 which with are connected to the inputs of the flip-flops 64a, 646, 64c and 64t of the shift register 64, respectively. the Matrix gate circuit! 66 responds to the digit pulse Di5 and determines the content of the data, which in are stored in the shift register 64 so that it serves as a decoder to carry out a carry from Hour, month, etc. from 1? To effect digits. More specifically, gate circuit 166 determines the high Level of input Di 5, d. H.,

D ₁₅ ■ ((QS5 ■ ζ) 64 · ζ) 62) + (Ό 65 · ζ) 64 · ζ) 63)) = »Η«.

what di: rch the shift register 64 is read out at the time of the timing pulse Τ & Φ \ u, .d is delayed by one bit. The delayed signal is derived from an output signal IVi which has a width which corresponds to a bit between the beginning of the next digital pulse A ₆ , which occurs synchronously with the clock pulse Φ ₂ , and the falling part of the digit pulse Di 6. The output signal W ₁ represents the counts 13, 14 and 15 of the hour digits of the alarm time, and it is fed via the OR gate 162 and the inverter 160 to the input of the AND gate 66, through which the hour digit of the alarm time is in the state » 0 «is brought. The alarm time is represented by the 12 digits, which run from (0 to 12). In this way the output signal! Wi used to bring the hour digit of the alarm time to the "0" state.

The matrix gate circuit 168 is used to determine the count "0" of the 10-day digit in response to the digit pulse Dn, and it also determines a month digit and the counts 13, 14 and 15 of the hour digit of the alarm time, in response to the digit pulses Di2 and D7. The gate circuit 168 also determines the count "7" of the day of the week (1-7) of the day of the week digits when timing the pulse Τ% Φ \ in response to the digit pulse Dg. The payment "0" for the one-day digit is determined by the timing of the pulse Τ ^ Φχ in response to the digit pulse Di 1. In other words, such a determination is carried out by the timing pulse Τ% Φ \ if the following relationship holds:

η r \ tie r \ tiA u \\ ■ V / DJ · VOT

and an output signal W ₂ is generated. This output signal W ₂ is generated when the counts "0", "13", "14" or "15", one of the hour digits of the current time, a month digit, a weekday digit are determined. The output signal W ₂ causes its own digit to be deleted and a "1" to be added to its own digit, and it does not contribute to the carryover for the next digit.

The output signal W ₂ is fed to the AND gate 66 via an OR gate 162 and the inverter 160, so that the own digit is thereby erased. At the same time, the output signal W _{2 is} fed to an input of an AND gate 184 via an OCER gate 182, the output of which is fed to the OR gate 68 as output Z via an OR gate 186 of the circuit 890. The output signal Zw is fed to the OR gate 68 which adds an I to its own digit. Such an addition also causes the day digit of "I" to start counting. Since the transfer of the month digits is not performed by the shift register ring 158, ^w: -d the output signal W to an AND gate 188 supplied, which is a logical product of W ₂ ■ You ■ Φ, as the output signal A / Kerzeugt which a flexible circuit 82 is supplied to control a script year. zo

The matrix gate circuit 170 is used to determine the count "4" of the 10-day digit, and it also determines the count "6" of the 10 minute digit. the 10-second digit and the 10-minute digit of the alarm time, in each case in response to the digit pulses Dn, Dt ,, De and Dm. The gate circuit 170 also determines the count "10" of the one-second digit, the one-minute digit, the one-day digit and the one-minute digit of the alarm time, in each case in response to the digit pulses D3, D5. Dio and Dn, and it determines the count "2" of the PM marker digit in response to the digit pulse De. An output signal Wi is thus generated which is used to erase its own digits and to provide a carry over to the next digit. The output signal Wj is fed through the OR gate 162 to the inverter 160 to cause its own digits to be erased. At the same time, the output signal W3 is fed to the control unit, which generates an output signal X which is fed to the adder circuit 62 of the shift register 58 so that a carry over to the next digit is brought about.

The output signal Wj from the matrix circuit 170 is fed to an input of an AND gate 190 which provides an output signal in synchronism with the digit pulse D \ . This output signal is fed to an OR gate 192. The output signal of this OR gate 192 is ve.rögert by one digit by a shift register 180, and generates an output signal W4, so that this output signal W ₄ it is used to serve as a carry for the next digit. In addition to the PM marking number as a carry-over to the one-day number, the weekday number is also treated accordingly.

The matrix gate switch 172 stores the count "11" of the hour digit of the alarm time in a memory.

chopping cycle in response to the digit pulse D15. The matrix gate circuit 172 determines the change between the count "11" and the count "12" and generates an output signal which is fed to the OR gate 192 in order to generate the output signal W * which is used as a carry for the next PM- Number is used.

When a second zero control signal So is supplied to the matrix gate circuit 174 , namely, when the second digit is on the order of 30 seconds, 40 seconds and 50 seconds, a carry signal for carrying out a carry becomes the minute number of the current time and a carry signal delayed by one digit to carry out a carry to the PM digit of the current time, namely by the shift register 180 to form the output signal W ₄ and in this way activate a carry to the next digit.

The matrix gate circuit 176 determines long and short months in order to generate an output signal W% for controlling the one-day digit, the ten-day digit and the month digit. Furthermore, the matrix gate circuit 176 is connected to latch circuits 194, 196, 198 and 204, which determine and store the data relating to February, 20 days, 30 days and short months (February, April, June, September and November), respectively. The conditions that are detected in order to generate a word carryover and to change the display for the first day of the following month are:

(i) February 29th in a normal year:

(ii) February 30th, or counts higher than 30;

(iii) 31st day of the short months;

(iv) 32nd day and above for the long and short months.

The results of items i, ii, iii and iv above are summed to produce an output signal W5.
The signal W ·, is used as a carry signal to form a carry to the next digit after the own digit has been deleted (one-day digit). In the case of February, the W $ signal is used to create a carry over to the 10-day digit, so that February 31st is converted into February 41st. In this case, the 10-Tagcs digit is immediately reset to zero and a carry-over sign is made! the month digit, and this is how the first of March is displayed. In the case of a short and a long month, the result is the 41st day, so that "!" Is added to the month number by carrying over the 10-day number and in this way the 10-day number is reset to zero . In February, a carryover is made on the 28th day. Under normal conditions, no time setting is required and the display will be shown as March 1st after February 28th. However, if a switch is operated to indicate February 29th after February 28th, a carry disable signal will be generated causing the carryover to March 1st. Accordingly, February 29th is displayed, and when it reaches February 30th, the display is changed to March 1st, which is after the scanning mode of (ii). This precaution is used to enable the manual setting of February 29th in a leap year without the need for an additional counter for a leap year.

A data detector 74 is formed by a matrix gate circuit 202 which counts "0" in a digit for 1/16 see. "One" and "tens" of a second, and "one" of a minute are determined in response to the digit impulses Di. D ₂ . D? and D ₄ . to generate an output signal. This output signal is delayed by one bit by the shift register 180 , so that a signal [B] is generated which is used as a time synchronization signal. The signal [B] also serves as a reset signal of a timer circuit and a logic level setting circuit of the control unit, whereby the logic level of the input terminals connected to the switches is controlled. Furthermore, the signal [B] is used to generate intermittently modulated output signals in the modulation unit. The logical product B D5 of the output signal [B] and the digit pulse Dj delivers a one-minute signal, and the logical product B Dt of the output signal [B] and the digit pulse Da delivers a 10-second signal.
In response to the digit pulse D \ \, the matrix gate circuit 202 determines the count "0" of the 10-day digit and generates an output signal (OSUP) to suppress the count "0" of the 10-day digit. The display of the count "Ö" of the 10-second digit and the 10-minute digit is not critical, but the display of the count "0" of the 10-day digit gives the user a strange impression. It is therefore desirable to suppress "0" when the 10-day digit is displayed. Of course, »Ο« is not suppressed when the 10-second digit is displayed. Incorrect identification can also be prevented by suppressing "0" in the 10-minute digit. For this reason the circuit is arranged in such a way that the count "0" is only suppressed for the 10-day digit as an example. It should be noted, however, that various modifications in the circuit arrangement are possible in order to suppress the count "0" in any desired digit. The Signa] (OSUP) is fed to the data modulation unit in order to modulate the data in such a way that the count "0" of the 10-day digit is not displayed.

The matrix gate circuit 202 determines the count "0" of the 1/256 second digit in response to the output ζ) 62 of the flip-flop 646 of the shift register 64 and generates an output signal. This output signal is delayed by one bit by the shift register 205, which generates an output signal (CONTA)

Furthermore, the matrix gate circuit 202 is connected to a locking circuit 204, which determines the count "0" of the hour digit of an alarm time in response to the timing pulse Ό ^ Τ ^ Φχ , and they

μ generates an output signal (A TO) which indicates that the alarm time has not been set

The matrix gate circuit 206 determines a signal which has a weight of 2 ^{2 of} the 1/256 second digit, ie the output signal Q64 of the flip-flop 64d. The output signal Q 64 is activated by a latch 207 at the time of the timing pulse DiTg ^ i read out, and a 32 Hz signal is generated for the

Driver indicators generated.

In FIGS. 11 λ and HB, an input signal! LK shown, which indicates a leap year and which is supplied by the external control element of a switch. Upon actuation of the switch, a carry-over inhibit signal i / is generated by the controller and used to control the February 28th signal. An AT-ERASE signal is fed to the OR gate 162 from the alarm unit when the mom ^ Manc time and the alarm time coincide while the alarm time is temporarily set. The ERASE signal is used to clear the Alarinzcit data through gate 66. During this deletion process, only the hour digit is deleted and all minute digits, hour digits and PM digits are deleted. In this embodiment, the circuit is so constructed that the alarm time data is cleared in the normally displayed state.

Table I shows the relationship between the digit pulses A through D ₁₆ and the outputs VKi through W ₅ from the data sampling unit 72. In Table I, the symbol ⁺ means that when a carry is made to the next digit, a carry over is made from the day -Digit to the 10-day-digit is executed and the transfer from the day-digits to the month-digits at the end of the month. In this case, the own digit is set to "1" after the carryover to the next digit has been carried out. The ⁺⁺ symbol means that a carryover from a weekday digit to a one-day digit has been carried out. The symbol ^{+ + +} means that the transition between the counts "11" and "12" of the hour digit has been determined and a carryover to the next digit or to the next PM marking digit has been carried out. The symbol "-" means that the output signals W are not generated.

Table I.

Daien He count Max. Digit, to Output Y Exit Z Output X exit averaged Min. which one own own Carry over to Digit Transfer" Digit 0 Digit +1 next digit made 15th became 1/25 * "see A. 0 D ₂ not not 15th necessary necessary l / 16sec D ₂ 0 D ₃ not the same the same - 9 necessary 1 see D ₃ 0 5 D ₄ necessary the same necessary W ₃ 10 see D ₄ 0 9 D ₅ the same the same the same W ₃ 1 min D ₅ 0 5 D ₆ the same the same the same W ₃ 10 min D ₆ 0 12th D ₁ the same desgi. desgi. W ₃ hour D ₇ 1 1 D ₈ the same necessary necessary * ^{+ +} W ₂ ,
U /. + + -i- PM D ₈ 0 D ₉ . Ao the same not necessary ^{+ +} W ₃ 7th necessary Weeks D ₉ 1 no the same necessary not W ₂ Day 9 Digit necessary ITag Ao 0 3 Ai the same necessary necessary + W ₃ 10 days A. 0 A ₂ the same not necessary W ₃ 12th necessary month A ₂ 1 9 (NY) the same necessary not
necessary
necessary W ₂ AT-I min A ₃ 0 A ₄ the same not W ₃ 5 necessary not AT-10 min A ₄ 0 no necessary not necessary W ₃ 12th necessary necessary AT hour As 0 1 A ₆ the same the same not W ₁ AT-PM D ₁₆ 0 no the same the same necessary - 28-31 necessary Date Ao, A, 1 A ₂ the same the same W ₅ digit D, 2

The conditions for generating the signals Y, Z and X can be summarized as follows:

1. Deletion of previous data:

Y = W ₃₊ W ₂ + W ₁ + W ₅ + S ₀ + Di (T ₂ + T ₄ ) + ERASE + DATA-CL

2. Put "1" in your own number: Z = (W ₂ + W ₅ ) T ₁ + DATA-IN

3. Carry over to the next digit:

X = {(DTs W ₃ + W ₄ + W ₅ ) - (carry lock + (HOLD) - D ₁ + 5i /, '} - T ₁ + [SU ₂ ']

10

15th

20th

25th

30th

35

40

45

50

55

Figure 13 shows an example of the flexible circuit 82 formed by a flip-flop counter which is used to provide a more flexible or versatile standard timing device in accordance with the invention. An output of a gate 206 is normally held high "H" but is momentarily driven low "L" 8 times per second. During these low-level intervals, the_flip-flops 208 and 210 are preferably set such that FB = "L" and FC - "0". When the Fr signal is brought high "H" by grounding, the gate 206 is shorted for a brief time interval in which the Tr signal goes low "L" when the switch is released. However, since the short-circuit period is short, it is possible to limit the average current to be less than 100 nA. Under the short-circuit conditions, ie Fk = "H", the flip-flops 208 and 210 carry out counting operations. Assuming that F, \ = "L" and Fu - "L", the following relationships apply when counting "0":

when counting 0 F ₀ = "L" Fc = "L" when counting 1 F _n = "H" Fc = "L" when counting 2 F ₀ = "L" Fc = "H" when counting 3 Fb = "H" Fc = "H"

Terminal Fr is used as a signal source for a signal of 8 Hz. When the terminal Fr is grounded to the high level "H" and the output signal NY is supplied to the terminal Fa , it is possible to account for a leap year by means of a 4-digit counter which is formed by the flip-flops 208 and 210. Although the consideration or setting of the leap year is somewhat laborious, it is possible to make an adjustment simply by confirming the carryover to February 29 and further causing the December 31 to be sampled in such a way that a signal NY is generated for a new year.

The F i g. 12 shows a preferred embodiment of an electrical circuit for the control unit 30. The control unit 30 is connected to a plurality of switching input terminals SH, SM, SK, SD, SUO, SUT, SU ₁ and SU ₂ , and corresponding input signals are fed to these terminals, to thereby generate various control signals to control the timing register 32 and to control the data modulation unit 36. SUO and SUT are input connections for electrical "unlocking" which make the control unit 30 operational so that switches SH, SK, SM and SD enable new time data to be set in order to set the correct time. SU \ and SU ₂ provide the data inputs Si and S _2, respectively. The input terminals SH, SM, SK and SD are used to control the storage locations for the data to be transmitted. These input terminals are connected to output terminals of a circuit for setting a logic level, which is designated by 214 and is designed in such a way that the input terminals are brought to a logic level "L". The input terminal SH directs the data input signal 51 to the digit 12 or 13 when SH = "H". When SM = "H", the data input signal 51 is routed to the 60 digit or to the 28, 29, 30 and 3i digits, respectively. When SV = "H", the data input signal 51 is supplied to the data, month and day of the week digits. When Sd = "H", the data input signal 51 is applied to the second, minute and hour digits, and the PM flag digit of the current time is applied. SUO and SUT represent input terminals of an unlocking switch device which enables the time to be set on the clock, and SUi and SU2 represent data input terminals which serve to supply the data input signals S 1 and S _{2, respectively.}

Table II shows an example of the relationship between the modes of the switches SM, SH, SK and SD. and it illustrates the data setting modes of the watch as well as the display modes. For example, in the "Time setting" section, you can see that a combination of SH and SK, when these are at "H" levels, causes the current hour display to flash and this data to be updated. (The table is followed by an explanation of symbols).

60

65

Table IJ

F. instcllmudus

counter

LOCKED TIME ADJUSTMENT mode

S. DAY M. M. Il 1 S. M. 11th I. T I) M. 0 DATE K. / / N ο / / N A. Λ υ ANZI-I- / Λ Λ Il K K U G T N GE Λ T T T T U Λ T M. T

SM

SH

SK

SD

UL

OIOIOIOIOIOIOIOI 0OII0OII00IIO0II OOOOIIII0000IIII I 1 1 1000000001 III

0000000000000000 OIOIOIOIOIOIOIOI 00I100II00II00II OOOO0OOOIIIII11I III100000000I-III

ι ι ι ι ι ι ι ι ι ι ι: ι ι ι ι

SU,

SlU H- + 1 i + + ι i ++ i i + +1+ + + I + +1+ + +

2.2SEC

Ό '

SEC MIN

DAY

DATE MONTH M IN / AT H / AT

MPM

MDD

MALS

MDLY η π

(MULTI-ALARM)

Cl

Cl

Explanation: Normal time display STANDARD either 1 or 0 + second zero setting So counter Sw Transfer blocked Cl renovation U flash η second SHC minute MIN hour Il Day of the week DAY

DATE Date of the month

MONTH month of the year

M / AT minute of the alarm time

H / AT hour of the alarm time

MKJAJ Marking the alarm time

INH Entry blocked

"0" as soon as the counter is set to NuIf,
the counting is done from zero

I high level

0 low level

15th

According to the above, each of the input terminals SH, SM, SK, SD, SUO, SUi and SU 2 is connected to the circuit 214 for setting the logic level, which sets the input terminal of the switch to a low level "L" when the switch is open. According to FIG. 15, the circuit 214 for setting a logic level has an inverter 214a and a NOR gate 2146, which are connected in a ring form. The input of the inverter 214a is connected to the output of the NOR gate 214i> and the input terminal. while the input of NOR gate 2i4b is switched to receive the output of inverter 214a and a timing pulse B-Dj- 7g · Q 62. In other words, this circuit has a memory circuit which has a positive DC voltage feedback circuit and a terminal for setting a predetermined logic level. This terminal is connected in such a way that it receives an intermittent pulse which has a small width in order to adapt the memory circuit to the specific

~ to set the logical state. In this example, the special logic state corresponds to the low level and

one pulse B Di T ₈ . which has a width of 64 usec, is applied to the terminal every 1/16 of a second, so that the low level "L" is supplied. The low output impedance at the low level is around 100 kilo-ohms in the C / MOS scheme shown. It is possible to easily set the input terminal to the high level "H". When the terminal is set to the high level. the output of the memory circuit is short-circuited each time the pulse B Di Tg is brought to its high level. However, a corresponding current flow is extremely small and does not cause any serious trouble. Thus, an input terminal for the clock is designed in such a way that it has an average power consumption which corresponds to 100 kilo-ohms χ (1/16 msec / 64 ysec) and a low impedance of 100 kilo-ohms. This circuit has proven to be advantageous in suppressing noise which has frequencies of more than 16 Hz. The switch input terminals SK. SD, SUO. SUT and SUt are connected to a timer or timing device 216. When a signal which controls an unlocking is fed to the timer device 216 via the input terminals, the timer 216 generates an unlocking signal UL which unlocks the locked state. The input terminals SUi and SU2 are connected to differentiating circuits 218 and 220, respectively, which differentiate the data input signals which are supplied to the switch input terminals SUi and SU2 and which generate _{differentiated signals S 1} and S ₂ depending on the number of operations of the switches. The signals S ₁ and S 2 correspond to the differentiated signals of the signals SUi and / SU :. and their respective rising parts are arranged in synchronism with the rising part of the digit pulse D _t . These differentiated signals each have a width which is equal to the repetition frequency of the digit pulse D \ .

The input signals from the input terminals SH, SM, SK and SD and the unlock signal UL from the timer 216 are fed to the input terminals of the matrix gate circuits 222, 224, 226 and 228. The matrix gate circuit 222 serves to select the digits to be corrected in response to the digit pulses and input signals provided by the input terminals. The digit pulses Da, Db. There. Dn. You and you correspond to the minute digit and the hour digit of the current time, the date digit and the month digit as well as the minute digit and the hour digit of the alarm time.

The minute digit of the current time is selected when the input applied to the gate circuit 222 is in a state in which the relationship holds:

SH sM ■ SK SD UL = "1".

and the gate circuit 222 generates an output signal U. This output signal is delayed by one digit by a shift register 180 which is supplied by a data flip-flop register, after which this signal is fed to an input of an UN D gate 230. At this time, the differentiated signal Si also becomes that

4j AND gate 230 which supplies a minute digit correction signal in response to the timing pulse T. The minute digit correction signal is fed to an OR gate 232, which supplies a corresponding output signal. The output signal χ is fed to the adding circuit 62 of the timing register 32 in order to add a "1" to the minute digit.

In a similar way, the hour digit of the current time is selected if

SH JM SK JD-UL = "1".

The D.itums / iffer is chosen if
S7 / SM SK SK SD UL = »I«.

The month / iffer is chosen when
SV / JM SK SD Ul = "1".

The minute digit of the alarm time is selected when

SH SM JR-JD-UL = "U".

The hour digit of the alarm time is selected when
SH JM JK SD ty /. = "I".

The gate circuit 224 generates a carry disable signal when the minutes or hours, etc. are to be set or corrected. For this purpose, various input signals from the input terminals unlock the signal UL and digit pulses Dg, D \ o, Di, Di 2 and D \ 5 are fed to the gate circuit 224. The digit pulses Dq and Dw correspond to the weekday digits and the date digits. In response to these digit pulses, the gate circuit 224 generates output signals for disabling the carryover of the weekday digit and the date digit to the next digits when the PM mark as indicated is changed to the AM mark as indicated. This digit impulse Di corresponds to the hour / iffer of the current time. The gate circuit 224 is responsive to this digit pulse and generates an output signal to disable the carry over to the hour digit when the minute digit of the current time is corrected. The digit pulse D \ 2 corresponds to the month digit. The gate circuit 224 responds to the digit pulse Du and generates an output signal to inhibit the carryover to the month digit when the date is corrected. The digit pulse Di 5 corresponds to the hour digit of the alarm time. The gate circuit 224 is responsive to the numeric pulse D ₁ 5 and generates an output signal for inhibiting the carry to the hours digit, so as to avoid the fact that the hour is corrected when the minute digit of the alarm time is corrected. The carry inhibit signals generated in this way are fed to an inverter 234, which invents the output signal from the gate circuit 224. Thus, AND gate 236 is closed to prevent the carry signals from being applied to gate 232. The gate circuit 236 generates an output signal for setting a daily or temporary alarm time and an output signal for Er. setting of the days of the week. The timing pulse Dg Ti is used to set the days of the week and the timing pulse D15 Tg is used to set the daily alarm time.

When the input terminal SU 2 is brought to a high level "H", namely when

SH SlW SK SD- UL = "H"
or

JR Ml SlC W- UL = "H"

and the differentiated signal 52 is generated, the gate circuit 226 generates output signals for setting the days of the week and for setting the daily alarm time. When the input terminal SU2 is set to a high level "H", namely when

ST) -SJi-SK-SD-UL = "H"
or

SK SD = "H".

an output signal 5b is generated to set the seconds to zero. This output signal So is fed to the input of the gate 66 of the timing register 32, so that the second digit is set to zero.

FIG. 16 shows an example of an electrical detailed circuit of the timer 216 which is used in the control unit 30 shown in FIG. 12. The timer unit is arranged such that when the input terminal SUTaui is brought to a high level "H", a start occurs. When the input terminal SUT is brought to a high level >> H «, an output signal of an OR gate 242 is applied to an input for setting a flip-flop 224 of the first stage, which is indicated by a one-minute signal BD =, T ₈ <£ or a timing pulse SDSK is reset . A flip-flop 256 is set to a high level "H" after a time interval of less than a minute when the output Q of the flip-flop of the first stage 248 has reached a high level "H". The output Q of the flip-flop 248 of the first stage, the output Q of the flip-flop 256 of the second stage and the signal SUO are fed to an OR gate 260 which generates an unlock signal UL. To activate the setting of a time, a corresponding switch SUT is actuated. The output Q of the flip-flop 256 of the second stage and the signal 5ί / ι are fed to an AND gate 258, which generates an output signal by which the clip-flop 248 of the first stage is set. When the input terminal SU \ is brought to a high level "H". when the timer is set, the output signal UL is generated continuously for a further minute. The timer 260 is forcibly reset when 5D · JK = "H". This timer 216 is particularly advantageous when the date is entered by using a pushbutton. When the level of the terminal SU \ is changed alternately between "L" and "H" after the input terminal 5 £ 7T has been brought to a high level "H" and then brought to a low level "L". thus it is possible to set the time in a simple manner by pressing an appropriate combination of keys. Fig. 17 shows an example of a perspective view of an electronic watch. which is designed according to the invention. FIG. 18 shows a switching device which is used in the electronic watch shown in FIG. FIG. 19 is a sound diagram illustrating the operation of the timepiece shown in FIG. In Fig. 17, a crown 262 is provided on one side of the electronic watch. This crown is mounted so that it is movable in two stages, namely a rear and a front stage, and the crown 262 can also be rotated in each stage. The electronic watch also has a marker setting switch for setting a corresponding display 264 and a manual slide switch 266 for setting multiple alarm times. The switch 266 can also be used as a push button to turn on a lamp. At 268 a display area is shown on which the time information is presented. The hours and minutes, e.g. B. 12:38, are shown on the display 268 along with the PM mark. When switch 262 is depressed, the date and day of the week are displayed. This is done when one of the switches

262, 264, or 266 does not print. When switches 264 and 266 are depressed, the display is not changed and the current time is not affected. However, when switches 264 and 266 are depressed together, the seconds digit is set to zero. 18 the crown 262 assumes either the forward position or the second rearward position, the input terminal SD for the date, day and month is grounded and brought to a high level "H". At this time, a lever 268 is operated by a shaft 269 connected to a contact 270. When the crown 262 is in one of the first and second rearward positions, a lever 270 engages a contact 272 which is consequently grounded. In this situation, the input terminals SK and SUTi for the current time information are connected to ground potential and brought to a high level »Ha

ίο When the crown 262 is rotated clockwise, a toothed segment 274 is also rotated, also in a clockwise direction, whereby the rotation takes place by means of a toothed wheel 276 over a predetermined angle.Then the toothed segment 274 rotates freely and presses a spring 278 against a contact 280. At this time, the spring 278 comes into engagement with the contact 280, and the input terminal SH is brought to a high level. On the other hand, if the crown 262 is rotated counterclockwise, the gear segment 274 is rotated clockwise so that the spring 278 is connected to the contact 282 comes into action so that SH is brought to a high level "H". When the crown 262 is rotated, the shaft 279 is rotatably connected thereto. Gear 276 is fixed in place and rotatable with shaft 269. A cam 284 is attached to gear 276. A lever 286 is normally pressed against the cam 284. When the cam 284 is rotated, the lever 286 is moved toward a contact 288 so that the input terminal SLJi is grounded and brought to a high "H" level. Since the lever 286 is pressed by its spring force against the cam 284, the lever 286 is kept in a stable position at a distance from the axis of the cam 2S4, namely at a minimum distance when the crown 252 remains in its normal position. The spring 278 is directly coupled to the sector gear 274 and is not engaged with any of the contacts 280 and 282 when the crown 262 remains in its normal position. When the spring 278 is engaged with either of the contacts 280 or 282, the Crown 262 rotated somewhat Even if the crown 262 is rotated beyond an extent at which a predetermined angle is exceeded, and if the part 274 is disengaged from the gear 276, the spring 278 is still kept in contact with the two contacts . One end of a lever 290 is connected to the shaft 269, and it pushes the shaft 269 in the axial direction. The lever 290 is provided at its upper end with grooves 292 which are designed to be engaged with a stationary pin 294. When the user lifts his finger off the crown 262, in a forward held position, the crown 262 is returned to its normal position by the action of the lever 290. When the crown 262 from its normal position to the rear When the position is pulled out, the crown 262 will remain in this extended position. A lever 296 associated with the switch 264. When the switch 264 is depressed, it engages a contact 298 so that the tight terminal SU 2 is brought high. Likewise, when a lever 300 is engaged with contact 302, input terminal MSIN comes on, a high level.

Fig. 19 shows an example of the modes of operation of the crown and switches shown in Fig. 18. According to the above, when the crown 262 is moved forward, a date is displayed. Conversely, when the crown 262 is moved to its first rearward position , the input kit me SK is brought to a high level and the input terminal SD is brought to a low level »L«. Since the input terminal SUTmh is connected to the input terminal SK , it is possible to set the current line by pulling the crown to its first rearward position. When the crown 262 is rotated counterclockwise, i.e. upwards as shown in FIG. 19, the display of the hour digit is made to flash or light up. If the crown is turned further, the hour digits will be corrected. If, on the other hand, the crown 262 is rotated clockwise, ie downwards as shown in FIG. 19, the display element of the minute digit begins to flash or light up. If the crown 262 is rotated further in the same position, the m minute digit is corrected. Since the digits to be corrected are displayed on the display surface, there is | no risk of erroneous correction. If switch 267 is depressed without rotating crown 262, the second digit will be set to zero. If the seconds display shows 0 to 29 seconds while the seconds are being zeroed, the second digit a ' is set to zero. However, if 30 to 59 seconds are displayed during zero adjustment when the second second digit is set to m

NuI! is set, a carry signal is generated at the minute 'iffer. In FIG. 19, |

Two modes of operation are shown, the first mode of operation is to depress crown 262 and simultaneously operate switch 262 in the normal display position / u , and the second mode of operation is to depress switch 264 while the crown 262 is held in its first rearward position Accordingly, it is possible to use the watch according to the user's preferences and environmental conditions. When, after setting the time, the crown is fully pushed to the front position 11 which shows the date, a compulsory electrical lock is generated so that accidental finger contact does not affect the current time. If the trigger switch is not fully depressed, a timer works in such a way that the electrical interlock is automatically applied after a predetermined interval. When the crown is pulled to its second rearward position and turned counterclockwise, the month digit can be set in the same way, while the date can be set when the crown is turned clockwise. Under these conditions, if the switch 264 is depressed without rotating the crown 262, the days of the week can be set. When crown 262 is pulled to its second rearward position, the month digit can be set and the date digit can be set with the day of the week indicators flashing

to be brought. When the crown 262 is rotated at the same time, the flashing of the display elements becomes the Weekday digit is stopped and only the display elements of the other digits start to light up, which depends on the direction of rotation of the crown This indicates that the digit is being corrected can.

When the crown 262 is pulled to its first rearward position, the setting means for the current time is unlocked in such a way that when the crown is returned to its normal position, the input terminal SUT to a low potential immediately after the current time setting direction is unlocked "L" arrives so that the unlocked position is maintained. Accordingly, an alarm time is displayed and it is possible to set the alarm time. Under these circumstances, if crown 262 is rotated counterclockwise, the hour digit of the alarm time can be set, while clockwise rotation of crown 262 allows the minute digit of the alarm time to be set

If only the switch 264 is depressed without rotating the crown, it is possible that the alarm time in is discontinued on a daily or temporary basis. A second switch 266 is used to set the alarm times while moving this switch manually. Thus it is possible to do a review whether the alarm times are set or not. Every time the switch 266 is depressed, the registered alarm data is read out and displayed. If under these circumstances turned the crown 262? a correction or setting of the displayed alarm time can be made be made possible. If switch 266 continues to be depressed for a period of more than 1.5 seconds instead of depressing switch 266 each time the displayed alarm time is changed, a plurality of stored or registered alarm time data are changed at a speed shifted by 1 Hz and displayed continuously. The shift stops. WC? the desk 266 is released.

Furthermore, the circuit is thawed in such a way that when it is desired to set an alarm time, immediately after the display was switched from the display mode to the current time, the Alarm time of a free address of the register is displayed, which is automatically searched for again display free register. When the register is filled with the alarm data, the finally set Data displayed to end the automatic search. Automatic search requires a maximum time of 0.5 seconds.

In the clock according to the invention or the time measurement system according to the invention, the state of the display surface the clock switched between three possible positions, d. h "either the current time is displayed or the alarm time is displayed or a date is displayed. In addition, the display mode changed to make it easier to identify the time information. The decoder for the display driver circuit is constructed to identify a variety of conditions and to display reversed, deleted or modified by modulating the displayed data. Farther the arrangement is chosen so that the user can easily judge which digit is corrected or corrected because the indicator of the corrected or updated digit flashes or flashes. This can be done with the aid of the FIGS. 20A and? 0B shown data modulation unit is reached will.

First, the display system itself is discussed. There are many ways to get time information a'jf a Display face or a display surface of a clock. The time display is as essential as that Timing. Since there are many types of display devices, the display driving circuit depending on the display system used.

Furthermore, it is necessary for the main circuit to provide certain information to the display circuit transmits, taking into account the type of display system. According to the invention, a selected data information that is to be displayed is transmitted to the display unit, and in addition, the display data is chopped into pulsed data streams before transmission.

More precisely, according to FIG. 2L.A and 2OB, a signal DATA 60 is modulated by a data modulator 350 and then passed through a chopper circuit 352 as a data output signal. The data modulator 350 has, as shown, an AND / OR gate circuit 354 and a matrix gate circuit 356. However, both gate circuits can also be designed as conventional gate circuits or can be combined to form a single matrix circuit. However, the use of a matrix circuit is advantageous because it is easy to see the matrix structure and because it is inexpensive and compact ”. Read-only memory matrix can be achieved using C / MOS integrated circuits. It is also possible to incorporate various gate circuits into the matrix, which are labeled 356, 358, 360 and 362. As an example, a U * signal is used to control the flashing or lighting of the entire correction digit by controlling the pulse width of an input signal Correcting a digit (Signa; U) is increased, which is done by the circuit shown in Fig. 20B. The gate circuit 362 is controlled by switches SK, SI), UL and SU2 to switch the data to be displayed , 1. D, _o and D-, are selected to display the alarm time and to display the data and the current time, respectively, and the circuit is constructed so that the data to be displayed depending on the phase of the The selected digit signal is passed through one stage of the shift register 366 to delay it by one digit and by the waveform m of the digit signal accordingly. In this way, after a peak of the waveform and a slight delay have been removed, the digit signal is then sent out. In the digit signal selection circuit 368, a signal is selected which has a phase which is advanced by an angle corresponding to a delay of one digit. A gate circuit 370 is used to generate an intermittent chopping signal, which has a frequency of 16 Hz, from a CO / vT / l signal. The data stream leaving the shift register 388 is controlled by the chopper signal

of AND gate 389 chopped into periodic pulse trains. The 16 Hz chopper signal is used to recover the timing data from the chopped data in response to a signal that is synchronous with the chopper signal. The retrieved time data is displayed as explained below. If the CCWT / 4 input cycle (a continuous input terminal) receives an "L" signal, an intermittent signal is generated; if the signal is "H", data and clock pulses are transmitted continuously. Gate circuits 372, 374 and 376 control the generation of the intermittent signal. A signal synchronous with the signal Φ 2 is multiplied by a signal on line 378 in synchronism with a signal Φ \ , and a signal synchronous with the signal Φ \ is multiplied by a signal Φ2. The signal synchronous with the signal Φ 1 is generated by the latch circuit 380. By

ίο the transmission of the data in pulsed form will save a considerable amount of energy for the driver and Additional circuit achieved.

The following Table III shows a truth table of the display decoder which the display modulation is equivalent to.

15 Table HI

No input

.., .. .. _γ , " ₄ "

Output (digital block) ä b 'dd e>,

Output (analog block)
S " Λ '50' 51 '52' 53 '54' 55 '56'

0 0 1 1

0 0 1 1

0 0 1 1

0 0 1 1

0 0 0 0 1 1 1 1 0

0 0

1 1 1

0 0 0 0 0 0 0 1 1 1 1 I 1 1 1

0 1 0 1 1 1 1 1 1 0

0 0 0 0 0 0

0 1 0 0 0 1 0 1

0 1 0

i 0

0 0

0 0

1 1 1 1 1 0 0 0 0

υ 0 1 0 0 0 0 0 1 1

0 1 1 1 1 0

0 0 1

0 0 0 0 1 1 1 0 1 1 1 0

0 0 0 0 1

0 0 0 1 1 1 1

0 1 1 0

0 0 0 0 0 1

0 0 1 1 1 1 1

0 1 0

Explanation:

Exit "!" means lighting up,

"0" means deletion for the display segment outputs, "0" corresponds to the low level and 40 "1" to the high level at the series-parallel converter outputs.

The data modulation can be carried out according to the following methods and analog methods:

(1) a method in which the content of the data to be changed is not changed, but the Display mode is changed (the display of the second digit is changed from white to black or

vice versa):

(2) Without changing the content of the data to be displayed, the display lights up or the display becomes deleted (e.g. the day of the week display lights up);

(3) the content of the data to be displayed is changed (e.g., a date alarm display);

(4) the display is made by using markers (for example, a black mark for displaying an alarm line).

These methods are carried out in the following way:

(1) Information regardless of the content of the data to be displayed is displayed (for example becomes an alarm coincidence due to flashing of the display area and a mismatch of an alarm is displayed in the same way).

(2) The appearance of the display is changed by changing the background of the display area so that it is possible to see at a glance the type of data presented (to For example, to show a time, a marker that contains the time is shown brightly, while the date is displayed by lighting a marker, soft the Date included).

(3) A display scale is displayed (for example, a weekday scale is displayed).

(4) The Λη / eigeeinncit is displayed (for example, a character is displayed which indicates a month or to includes a date).

(5) The display of the content of the displayed data is supplemented (for example, a Mrzj signal is displayed and a / Vfos signal is displayed to illustrate PM and AM).

20th

These ads are controlled as follows:

(1) By a switching operation (in which the display area is switched,

(2) by the content of the digit to be displayed (for example, deleting a minute digit in a Alarm time 0),

(3) by the information entered from the outside (for example a control which is carried out by data, entered from the DIN input).

According to this description, the data modulation unit in connection with a time-series shift register is used, it should be apparent that the invention is applicable to any system other than a time series shift register is applicable. For example in connection with a parallel system which uses a static flip-flop circuit.

According to FIG. 20A.B, on the right-hand side of the rows of the matrix 356, the reasons for the selection of the crossing points on the rows of the matrix and their object are explained. The output DATA 60 from the shift register ring is delayed by 4 bits more than the output Q \ from the shift register ring, which is used as a reference for the clock system according to the invention, so that the indices attached to the digit signals of the matrix 356 are one greater than those Indices attached to digit signals, which are used for a carry or the like, so that they represent signals delayed by one digit. The output from gate circuit 354 is combined to the output of matrix circuit 356 so that the display signals are modulated will. Km signal of Φ 1 Hz is generated by a locking circuit shown in FIG. 20A is uargesieiii, and it is converted into signals Φ 1 and Φ \ G by the gate circuits 352. F causes the entire display to flash in the event of an alarm and C represents a flashing or flashlight blocking signal, which is dependent on the one shown in FIG. 8A shown control unit is sent. The signals D 14 and D 15 are logically added, so that the μ minute display of alarm data is deleted when the alarm hour data is set to zero. If the PM marking is to be suppressed during the display, timing pulses D9T1 are sent to $ 25! Given matrix. "

Where the display of the second is inverted by a timing pulse D ^ Tg , although a day of the week and a 10-second signal are alternately displayed on the same area of the display area, as can be seen from the codes shown in Table III, the codes are as follows constructed that in the case of a linear display of numbers of 6 or 8 digits with the signal Ts at the "H" level, the states of the illuminated parts and the non-illuminated parts are reversed. In this system, only a predetermined portion is illuminated in the 10-second display and only a predetermined portion is illuminated to indicate the days of the week, so that by marking it in this way, it is possible to quickly and easily determine that the contents of the Ads are different.

If a 10-day digit is to be suppressed by a digit pulse D \ i , the digit signal Dn is added to the data in order to suppress the 10-day digit of the data if this digit is equal to zero. Ordinarily a user is familiar with the calendar, so it is advantageous not to suppress the 10-second digit in the same digital display, rather suppression of the data is undesirable. Since watches are not only measuring instruments, they are also worn by the users it is necessary to take such circumstances into account. 40 Sj

To clearly differentiate between the hour-minute display on the one hand and the month-date display on the other hand if.

when the month display is suppressed but the date display is supplied, namely when the date is set, the month is also displayed. However, in view of the need for constant display of the date, only the date and day of the week are displayed. If the switches So, S ~ K are at a low level "L", a date and a week are displayed alone, while if the 45 j

Switches Sp and SH are high, the month, date and day of the week are displayed. For this reason, when the switches Sd and Sk are at the high level "H", the suppression of the month digit is carried out by adding the signal On to the data.

In order to make the display of the weekdays flash or flash, the signals D \ o and Φί G are added to the data, namely in the state in which the digit is not selected,

u ßHSM + SH-STti = "L"), I

so that the day of the week digits or flashes under normal conditions. Such flashing or flashing can lower operating costs and increase commercial value. Following the principle of flashing the digit to be updated, the flashing stops when a certain digit is dialed. The blinking of the 10-second digit, which is caused by signals ϋίΤ & ΚτΦ 1 C , does not select any digit in the same way as the blinking process for the days of the week and requires a single flash. Since the signal Tg is at the "H" level to reverse the display, it is added to the product of the signals Tb and Ds .

In order to cause the display of the one-second digit to flash, in the embodiment shown, the display driver circuit only marks the P _M digit mark, such as 10 minutes, one minute and 10 seconds. However, to provide a digital indication of the second using the auxiliary unit, one second data is modulated in a manner similar to that used for the one second digit

In order to cause the correction number to light up or flash, a signal is sent to select the Correction digit data input signal from the shift register delayed by one digit, which is used for this to determine a correction block (e.g. a one-minute figure is used as a Correction data input signal selected However, the lighting or flashing should be for the 10-minute digit

\ J \ J

and the one-minute digits that are affected by the correction). A logical product of Φ 1 Hz is added to the specified block (which is two digits wide).

In order to light up or flash the daily alarm mark, the date mark and the PM mark, the signal for actuating these markings is modulated by a reproduced signal of Φ 1 Hz.

A continuous activation terminal 384 is normally brought to the "L" level by the output signal Q from a reset flip-flop SSo, which is continuously held in the reset mode by a narrow 1 Hz signal SDj Tg. In the circuit shown in FIGS. 20A and 20B, the output signal CONTA can be maintained by determining a moment in which the shift register of the Λ-eitmeßregister assumes a comparable status in which its 1/16 second digit is »0 " will. This output signal is used by the latch circuit 386 to form an output activation signal which is one memory cycle wide, or about 4 milliseconds wide, which is delayed 1/2 bit more than the instant at which the predetermined 1 / lb The second digit becomes "0".
This release signal is stored or locked with the clock Τ & Φ 1 in 388 'and is used periodically

generate chopped data pulses as well as chopped clock signals which do not contain any pulses with false transitions. For this purpose, the signal is passed through the OR gate 370, and a continuous enable signal is obtained by setting CONTA to the "H" level. By means of the AND gate 376, pulsed clock pulses Φ 2 are obtained. The delay circuit 370 also achieves this in the following cycle (see FIG. 8) after Φ 2 for Φ \ x and for <PS.

2ö Thus, through the gcpüistc outputting of data, the energy consumption of the subsystems that these data received, can be greatly reduced by adding to the subsystems, which the entire system arrangement for Form transmission of the intermittent signal, which can also be transmitted spontaneously, a frequency converter device is added to produce a low frequency output signal, or by adding a device which serves to send out only the variable part when an information changes, thereby sending a signal at a high speed to the entire system is applied by a system that operates at a higher speed, the Display system or the auxiliary system is not required to run continuously at high speed work.

In FIGS. 20A and 20B, the signals which are marked with a symbol "d" represent , for example, the signals Γ84 Φ \ Δ. Φ2Δ and DATA, intermittent signals which have a frequency of 1/16. Such intermittent data signals are advantageous because where a plurality of integrated circuit dies are electrically connected to one another, energy loss due to the charge and discharge of a stray capacitance of the terminals is increased.

The F i g. 21 shows an example of a circuit arrangement of the alarm unit 34, in which the data flip-flop circuits which form the shift register ring of the timing register are numbered as described above, the 60th data input being identified by the designation "DATA 60". Similarly, the data input to the 28th flip-flop of the shift register (which is the same as the output from the 29th flip-flop) is labeled DATA 28. The non-coincidence of the logical values of DATA 60 and DATA 28 is determined by an exclusive OR gate 404, so that a current time tKT and an alarm time tAT are compared with one another. The phase of the DATA 60 signal is delayed by one digit by the DATA 64 signal. Because the DATA 28 signal has been delayed 32 bits or 8 digits more than the DATA 60 signal every time Df ₁ , Dj is timed. Dg uit ⁴ O9, the DATA 60 signal represents the minute, 10-minute, hour and PM marking of the current time, while the DATA 28 signal represents the minute, 10-minute, hour and PM symbol as well as other symbols of a corresponding alarm time illustrated

The time coincidence is determined in that a flip-flop with preparation reset terminal 400 is set to "H" at ΰ $ Τ & Φ and that the flip-flop 400 is reset by the output signal indicating the non-coincidence from the exclusive OR gate to determine the non-coincidence will. If tKT - tAT, the flip-flop 400 is turned on during the timing of the signals Dt - D? held in the set state. More specifically, until the timing of the signals Dg, Ti and Φ 1 is completed, the current time signal tKT and the alarm time signal tAT are compared with each other. The content of the output signal from the flip-flop 400 is read out by the data flip-flop circuit 402 at a timing of the signals ßj, Tg and Φ 1, but there is a time difference or delay between the comparison between the current time tKT and the Alarm time tAT. supplied by the gate circuit 404, and the reading of the flip-flop circuit 402 consists, the signals DA TA 60 and DATA 28 are compared with one another during an interval of De T ₂ Φ 1 to Dg 7i Φ 1. Although the value of the timing of the signal DA TA 26 by Dg T ₂ Φ 1 and the value of the timing signal of the signal DA TA 2S by Dg T ₂ Φ 1 are normally held at the low level "L" when the contents of the shift register forcibly from is set externally via the DATA-IN terminal, which is shown in FIGS. 11A and 11B, it is possible to establish a relationship which is: DATA 60 Φ DATA 28 by D) T ₂ Φ \.

An alarm coincidence can be indicated by the fact that the logic output from flip-flop 402 is at "H" level. Since minute units are compared during an interval in which tKT '= tAT, the logic output increases continuously for only one Minute the level "H", and in the remaining interval it assumes the level "L" at the moment of the change from "L" to "H" of the flip-flop 402, so that the flip-flop 406 is triggered in this way that it is set. The output signal from this flip-flop controls the actuation of an audible alarm. According to the invention, the alarm signal is modulated in two ways, namely by a signal which has a frequency of 2045 Hz and a duty cycle of 25%. this signal having a frequency of 1 Hz. If that in double

If the modulated alarm signal is further modulated by a signal of a few Hz, an audible alarm is produced which resembles the chirping of a cricket, and this is an alarm which, although not irritating, draws the attention of the user of the watch. The rising portion of the output signal from flip-flop 406 triggers flip-flop 408 in such a way that it is set. The output signal F from flip-flop 408 controls the lighting or flashing of the display surface of the clock. Both the flip-flop 406 and the flip-flop 408 are preferably set by the input data signals S \ and 52 and by the STOP input signal for the clock. As a result, the user can transmit a signal to the watch indicating that he has acknowledged the alarm, whereby the watch will respond to that signal by turning off the alarm. Even if such an alarm acknowledgment signal is not given, the circuit is so constructed that the alarm is automatically turned off after one minute. This is done with regard \ i * on limiting the energy consumption of the battery to a minimum and avoid unnecessary noise. In this case, however, the flashing will continue until the alarm is acknowledged by the user. The flip-flop circuit 406 is connected to receive a signal from the gate circuit 410 one minute after the alarm coincidence, whereby the flip-flop circuit 406 is reset. Since the alarm output signal is generated by modulating a boost signal of 2048 Hz with a signal with a duty cycle of 25% and a frequency νυη 1 Hz, it has a frequency in the range from 1 kHz to 2 kHz, which for the human ear is audible. Furthermore, due to the 25% modulation by a signal of 1 Hz, the energy required to activate the acoustic alarm can be greatly reduced, so that the service life of the battery is extended as a result. An output signal ALS is applied to the base of an NPN transistor with a grounded emitter through a resistor of 100 kilo-ohms, and the working coil of a piezoelectric buzzer is connected in series with the collector of the transistor. Instead of using a piezoelectric buzzer, a dynamic buzzer can also be used. In any case, the increase in current required to activate the acoustic alarm is only about 10%.

The output of flip-flop 402 is delayed by data flip-flop 406. Gate circuit 410 is used to sample the non-coincidence of the logic values in the output signal from flip-flop 402 and flip-flop 412 as well as the rising portion of the coincidence signal (which is one minute wide) for tKT = tAT . using the output from flip-flop 402 at this time. The signal DATA 28 is used to determine the setting of the daily alarm time with the timing of Dq Ts Φ 1, so that in this way an erasure inhibit signal ERASE is formed, which is supplied by the alarm coincidence signal ALDET of the flip-flop 406 and a logic one Negative output signal QER of the erasure lock signal, of a correction unlocking signal U6, of a digit time control signal and a signal 5 ATO, which represents an alarm time 0 according to the following equation:

ERASE = (Dh + D15 + O ₁₆ + DiT ₈ ) ■ TJL ■ (ATO + QER ■ ALDET)

Even if the alarm time coincides with the current time, the cancellation will only occur under a normal condition (ie UL - "H"). Unless a UL logical product is used, setting a temporary alarm becomes extremely difficult. If, when setting an alarm time, such a setting is made after the current time, the alarm data would be deleted by the setting.

Usually, the information concerning the alarm flag is included in the flag digit of the alarm data, but according to the invention, special flags of the alarm flag digits are used, that is, the daily flag and the alarm setting flag, which are expressed by the instantaneous time display mode. This enables the user to continuously check the status of the alarm setting. The daily marking is determined and stored by a locking circuit, and it is fed to the output DATA as a time control signal for the current time DgT ^. The sampling of the QDLY signal and the modulation of the display of DLY are shown in FIG. 10A. The alarm setting flag is a signal which is achieved by inverting a signal generated when an "hour 0" of the alarm time digit is sampled, and this signal is derived as signal ALO (alarm not set), and it is then activated by the interlock circuit passed through. The alarm not set signal is sampled by the circuit shown in FIGS. 11A and 11B and the signal for the alarm not set is sampled in FIG. 21 to serve as a display modulation signal.

The F i g. 22A to 22C show details of the FIG. 4 shown display driver 20. In the circuit according to FIG. 22A and 22C show liquid crystal display elements which are driven by a source AL , and a level shifter 40 is also provided. Examples of the level shifter? are shown in FIGS. 24A and 24B illustrated. The level of the data is changed by the level shifter 40 and the data is then passed through a bit serial parallel converter 42 formed by the shift registers 502, 504 and 506 to give output signals P _u P2, Pa and P5 produce. Combinations of these output signals are read out by a Ziffem series-parallel converter 46 when Tg is timed.

Decoders 508 and 510 are used to decode the 4-bit parallel signals, each of which contains four bits, the decoder 508 serving to provide a 7-digit digital display, while the decoder 510 is used to provide a 7-part analog deliver linear display. A transfer switch arrangement 592 is used to switch the decoders 510 and 508 such that the analog display output signals So through Sf serve as a 7 digit digital display. The truth value of the decoder is shown in Table III

The Ziffem serial-parallel converter 46 is formed by a plurality of latch circuits 514-526

are formed, of which the latch circuits 514-524 serve to convert digital serial decode output signals into perfectly parallel signals. These latch circuits continuously supply a signal which has a constant level as long as the time information does not change. The latch circuit 526 functions as a delay circuit to provide an output signal obtained by slightly delaying the input signal Φ LCI.

As in FIG. 24D, the display driver 20 has a plurality of AND-NOR gates the number of which corresponds to that of the latch circuits and which operate to generate a signal identical to the signal Φ COM when the Interlocking outputs are at the low level, while a signal is supplied that is slightly delayed compared to the Φ COM signal,

ίο when the interlock outputs are high. In FIG. 24D, the display element, which is arranged between an output ΦCOM and the output Φ dg of the driver circuits, is applied with a voltage of zero volts when the latch output is at a low level and with a voltage which has a frequency . which is equal to that of output Φγομ when the lock output is high

A timing pulse reproducing circuit 530 has shift registers 532, 534, 536 and 538 for generating timing pulses D \ TsGi. DiΤ & Φ \. ΠΗΤβΦ \. Ω $ ΤζΦ \ and ΌϊΤ & Φ \ as well as gate circuits 540. The timing pulse _{D 5} + ΤζΦ is applied to latch circuits 514 and 516 to serve as a clock signal. Similarly, the timing pulses Dt, + T & \. Ι> ι + Τ $ Φ \, D ₂ -VT ^ _x and Di + ΤβΦι the interlocking \ lung circuits 518,520,522 and 524 each respectively.

Da =. Signa! from the output terminal Mdd is used to light up the colon markings shown in FIG. 25 , for example the marking 561. which provides a time display. The signal from the output terminal Mp \ λ is used to light up a marking . which indicates that a daily marking has been set, for example a marking 56Z which is shown in FIG. while the output from the output terminal Mm. is used to bring a Alarmeinstellmarke to light, such as a marker 564. At the appearance of the output signals at the output terminals 562 and 564, the daily marking and Alarmeinstellmarkierung be displayed even when an alarm time is set, ^r then ode when the ''hr shows a current time under normal conditions. The output signal from the output terminal Mod is used for this. Light up letters such as a marker 566 indicating a date, or a weekday marker 568, or a period. The output signal at the output terminal Μρκι is used to illuminate a part 570 which, when combined with a part 572 which is illuminated by an output signal from the output terminal Mm , distinguishes between the states of Pm and Am indicates. 574 represents a second scale which is also made to light up by the output signal which occurs at the output terminal Mm> . The output terminal Mc- _ä , is switched in such a way that a part 578 (dz) , which is illustrated in FIG. 22C, is illuminated. If a 7-digit display is specified When the driver circuit according to the invention is added to a normal clock, it shows 10 minutes or the 10th day because the second display digit contains the parts ai to gi. the state of lighting of the parts ai and di is always the same. For this reason, an output for the part dt can be omitted. When the drive circuit is used in a time recorder or a desktop electronic calculator, it is necessary to drive the parts at independently. The leftmost digit or the O-th digit of the display device shows a marking, the first digit 580 provides a digital display through the parts at to g-, and Λι. the / broad digit 582 provides a digital display through the parts a? through gi, the third digit 584 provides a digital display through parts ay through gj, the fourth digit provides an analogue display through parts Sb through St, or a 7-digit digital display 586. if

• »5 the Signa! Snt is so trained. that it is high.

(> emaü the above, the potential of the current supplied to the drive circuit signal between V ·. ■ (O volts) and Vss ι (-1.5 volts) is changed, however, a level shifter according to the invention 40 to ve ^r w the potential V _ss ends to bring ι on V \ _s j (-5 volts), thereby to create a logical amplitude. as shown in the F ι g. 24A, the level converter 40 by a C / MOS-type flip-flop for setting and resetting a negative Logic is formed which has two NAND gates with the transistors 601-609, the output in one gate being connected to an input of the other gate, and the other input being driven by the elementary ring input. The MOS-FET transistors 602 and 604 are designed in such a way that they are not brought into a »pinchoffa state due to their gate potentials. If the input logic level is switched from » Hu (Vm)) to »L« (V _ss ι), then changes the output level from V / «to Vn. ■ due to the power paths durc h the transistor pair 601, 607. The transistor 606 is opened or switched off by switching the flip-flop low. Fig. 24B shows another embodiment of the level converter. Thus, there become two or an even number of inverters. which are driven by a voltage source that has a logical amplitude. in the form of a ring with resistors. and the gate potentials of the inverters are made equal by independent field effect transistors which serve to effect setting and resetting, an odd number of inverters being arranged between two points which are used for setting and resetting. Since a logic level converter occupies a large space in an integrated circuit arrangement, it is necessary to reduce the number of converters. On the other hand, in order to reduce power consumption, it is necessary to increase the number of integration operations per unit time in the number of logical ones

b5 to limit changes to the logic level converter to a minimum. The number of logic circuits can be reduced by arranging them immediately after the input terminal.
With the signals SET for setting and RES for resetting it is not always necessary that the

sion relationship SET = RES is fulfilled in a perfect way, this relationship can rather also have terms which contain logical products from the common clock pulse signal Φι \. In the case of the FIG. 22A, the level shifter 40 is connected directly to the input terminal. The rectangular blocks, which are constructed similarly to the logic level converter 40, represent similar logic level converters.

In FIG. 22A, the data input signal DA TA -IN of time series signals is converted into parallel signals by a shift register which includes flip-flops 502, 504 and 50fi, and the parallel signals are supplied to the decoder 508. The output codes of the decoders 508 and 510 are shown in Table III. Each of the decoders 508 and 510 includes an array of AND gates and OR gates and forms signals for 8 sections or segments or digits a to g for digital display and for 7 parts of a to analog display of 2 ¹⁴ combinations of four bits (P \, Pj. Pi and P \).

If the decoder is constructed as a dynamic decoder from C / MOS integrated circuits, with a matrix of field effect transistors only of the P or N type being constructed, a capacitor of extremely small capacity is first discharged, then charged by the matrix circuit which contains AND-OR field effect transistors, and the result is immediately read by the latch circuit, so that it is possible to manufacture the decoder as a compact unit. The F i g. 24C shows an example of such a decoder. In the circuit according to FIG. 22A to 22C ', the transmission circuit 512 is controlled by a digital, analog transmission control signal Sde so that the signal is thereby freely transmitted to the latch circuit 524 between digital and analog signals. This is because it can be advantageous to replace the decoder 50 with an S-bit decoder which contains a combination of the transmission circuit 512 and the decoders 510 and 508. The digital display has been made determinable or determinable because it is desirable to use the same digital display driver circuit as the integrated circuit even in the event that it is desired to display the data with digital digits, thus reducing the cost of the integrated circuit can be reduced by mass production and also the number of integrated circuits can be reduced, which are required for a specific case when a lot of digital display data are required, as in the case of the preferably provided time recording. The latch. ^ Circuit 526 is used to give an AC drive pulse Φι (a suitable delay. If the delayed signal Φι χ is denoted by Φκ, an AND-OR gate 580 sends the signal Ißi.c to the terminal of a to light up to growing part, and further the signal Φκ. to the terminal of a part to be deleted. If the signal Φη a common electrode signal Φιομ is added, an equal potential to the segment to delete or out to delete part of what / u the The result is that this display element is short-circuited with its associated Elcnicnt.A potential (Φκ - κ) is applied to a segment or a section that is to be made to light up, so that an alternating voltage, which has an amplitude which is equal to half the source voltage is applied, while at the time of switching the applied voltage is applied to a short circuit which is the source of the driver circuit does not include, is formed for a short time, so that the capacitive display elements are thereby discharged. For this reason, it is possible to reduce the display power by 50% as compared with a case where the charging current flows through the source as in a conventional arrangement.

An example of the auxiliary system 12 according to the invention is illustrated in a block diagram in FIG. 25, wherein the additional unit is combined with a standard unit 10 of the clock system. Different Control signals are transmitted between the standard unit and the additional unit via terminals 13 011, 13 012, 13 021 and 13 022 as well as via the conductors 13 041 and 13 042, the direction of the signals through Arrows is set. which sit h refer to the ladder 13 041 and 13 042.

leather of the ladder 13 041 and 13 042 can be omitted. If these conductors are absent, it means however, that the two units are opposed to each other without connection, and it becomes such a case not included in the invention. At least the standard unit should be cm continuously working Uniersysicm (including the watch system 1). An entrance mine 13 061 is only for the additional system provided, but in some cases this terminal can be omitted.

A main operating system 13 031 has a storage register if a multiple alarm is preferably intended is. Alternatively, cmc operation unit, a memory register and a pulse generator can be provided if a Jutomali lead / lag correction is intended! is. Alternatively, an operating unit and a storage register if the addition is intended to be a computer. Alternatively, a Detector, a Dutenkonverter and a Speicner register are provided, if .ils addition a blood pressure measurement is intended. A control unit 13 032 is available. When a multiple alarm addition is intended. the control unit 13 032 generates a signal for a progressive comparison of a plurality of signals with the current time and a control signal for a continuous display of the alarm time information, which in are stored in the memory register on the display area. When a lead / lag correction is intended is. the control unit 13 032 generates a signal for designating the start of an error measurement or a Operating control signal, which is used to cause a pulse generator circuit in the additional unit to that it generates a fast-slow correction pulse which is necessary to correct an error.

If a computer addition is intended, the control unit 13 032 generates a signal, which the output

exchange of signals between the computer and various registers controls, depending on of various operation control signals such as x, + +, =, etc. In addition, the control unit 13 032 also be structured in such a way that it stores the operation of the entire Einheil: or a part of the unit or that part of the standard unit is controlled by the additional unit via the signal conductor 13 041. For example are in the case of a multiple alarm auxiliary system at a coincidence of the time of the alarm data and the current time, the data stored in the additional unit is automatically deleted, then the switching

The device for transmitting the signal from the auxiliary unit 12 to the standard unit is closed and a Signal generated by the control unit, which is used to send a clock pulse to the shift register of the additional unit iu deliver. At this time, alarm time data, which just coincides with the current time, supplied to the register of the standard unit which contains an alarm time from the additional unit, so that this sets the alarm time data in the standard unit. A minute later, the Feeding of the clock pulse from the additional unit to the standard unit resumed so that sequentially other alarm data are transmitted from the additional unit to the standard unit. If the normal Time display is changed to an alarm time setting status by adding an external actuator is, the control unit generates a signal indicating the start of scanning or finding an empty one

ίο Register controls If an empty register is found or a prescribed time, e.g. 0.5 sec have elapsed, a signal is generated which terminates the search for an empty register. If an empty Register is found, a signal is generated to feed the clock pulse to the shift register of the To interrupt or terminate the main operating unit, whereby the empty register contains the register contents of the Additional unit transmits v / which stores the last data which at the time of termination of the search for

are shown for a certain time. Furthermore, the transmission of the alarm data to the main operating unit of the auxiliary unit is also terminated, and a transmission circuit from the standard unit to the auxiliary unit is formed, and the operations of the register of the main operating unit of the auxiliary unit and the register of the standard unit are synchronized in such a way that the data the empty address or register, v. ; l which contains the data last displayed at the time, if the search for a certain interval! has been completed, can be the same as the alarm data sent from the standard unit to the additional unit. As a result, a control signal is generated which makes the setting or correction of the alarm data in the standard unit in such a way that it corresponds to the setting or correction of the data contained in the corresponding register of the additional unit. In the case of an add-on computer, a clock pulse at a high frequency (e.g. 1 megahertz) is sent to the computer for a short time longer than a certain time, e.g. one second, immediately after data input or an operation control signal , so that this puts the computer in the position ι to work at a high speed. Thereafter, the frequency of the clock pulse is reduced to the range of a limit of, for example, 8 kHz. The clock pulse can also be terminated so that the data to be displayed are thereby fed to the standard unit. If an operation command is given or data is entered after the additional unit has been triggered by the high-frequency clock pulse signal, operation data which were contained in the standard unit are transmitted to the additional unit. After the result of the operation has again been transferred or data has been input to the standard unit, the clock frequency of the computer add-on can be reduced to a low value or to zero. With \

With the construction described above, it is possible to reduce the operating power of a conventional computer from a few milliwatts to 1 μW, which corresponds to a reduction of 10 ³ .

More specifically, the combination of the standard unit and the auxiliary unit including the Conductor 13 012 for the transmission of signals from the standard unit to the additional unit, conductor 13 011 to the Transmission of signals from the additional unit to the standard unit, the control unit 13 032 and the Main operating unit 13 031, so that signals are exchanged automatically or manually, in the same way how the clock pulses are controlled by the control unit, which is extremely advantageous because thereby the energy consumption can be reduced and at the same time the number of components can be reduced, because the signal for the timer or for the clock pulses can be supplied by the standard unit. It is a status sensing block is provided, of which a status indicating the relationship between the additional unit and of the standard unit indicates the status of the additional unit itself, the status of the standard unit (e.g. the status a battery) as well as the status of the external environment can be scanned. Especially where it is desirable to increase the number of external operation elements or the number of operation states It is necessary to reduce certain operational elements by the standard unit and the additional unit to use together. By determining these states, it is possible to obtain a satisfactory arrangement the standard unit and the additional unit.

For example, in an automatic fast-slow additional device, the input terminal SlJ] of the standard unit and the input terminal lh of the additional unit are connected together with the operational switching element of the standard unit, and the normal input signal for correcting the seconds and the input signal for controlling the automatic Fast-slow operation are differentiated from a signal for setting the marker display of the multiple alarms. For a multiple alarm addition, the status of the control of the standard unit is scanned by its external control in that the information is determined which determines the display data and the scanned signal is used for this purpose. Exchange data between the additional unit and the additional multiple alarm system, which are required for the standard system. In such a case, a multi-alarm auxiliary system is required to receive only the data de ^r Marm / EIT, which are formed by the standard unit. It is also possible to set up the control unit 13032 in such a way that it can control the display and the time unit signal in the standard unit. For example, where the data relating to the month and the date are to be set, a control signal is used in the case of a Viclfachalarm addition to light up a "dot", which indicates that the displayed digit represents a date, and a letter DATE is used to delete a colon which is used to indicate an hour. In the case of an automatic fast-slow accessory, a fast-slow correction signal is supplied to a timing pulse generator which constitutes a standard unit of time so that the timing operation is controlled by the clock. The signal conductor 13 042 is used not only to transmit the data, but it is also used to transmit various clock pulses and timing pulses as well as to transmit an electrical one

Current. For example, while in this example the standard unit works with clock pulses Φ \ and Φ-> , which have a frequency of 16 384 kHz, intermittent Taki pulses ΦΙ and Φ { , which have an average frequency of 1024 Hz and, through intermittent interruption of the clock pulses <P \ and Φ2 are generated with an interval of 1/16 second, fed to the additional unit. In this way, although the standard unit and the auxiliary unit operate at different clock frequencies, they exchange synchronous signals. This arrangement eliminates the need to provide an independent clock pulse generator for the additional unit, so that the energy consumption is reduced! because it is not required. use an oscillator / u. Furthermore, the signals 0UC \ and ΦΙΚ'2 for the delivery of a Boost-Kncrgic and for the transmission of a signal for the reproduction of a digit pulse are transmitted from the standard unit to the additional unit. In the additional unit, the signal is rectified and amplified by a diode constant circuit, and the amplified output signal is fed to the display driver. It is also possible to operate the additional unit by using the boosted or raised voltage or a DC voltage which is derived from an intermediate point of the diode rectifier circuit.

In accordance with the above, a system which comprises the combination of the one shown in FIG. 4A Additional unit and the standard unit includes a number of features which are not in each of the Units can exist because such a combination has a unique combination of characteristics guaranteed by both units

The F i g. Fig. 26 shows a basic block diagram of an example of an auxiliary unit that performs multiple alarm and fast-slow functions. For the sake of simplicity, the wiring is for the 7-digit pulses, the timing pulses. the clock pulse, the iS-Irripulse and the timing signals, which includes the compilations of two or more of them, are not there. Table IV shows the classified radio waves of the respective blocks shown in Figures 27A, 27B and 27C. In Table IV, the main pulse feeds, labeled a, show a group of devices for reproducing or zv-synthesizing basic pulse signals required to operate the auxiliary unit. The status scans labeled b show a group of devices for scanning different states, which offer the possibility of indirectly controlling the additional unit through the standard unit and bringing about changes in the states. The control signal generation labeled c shows a group of devices for generating a signal which determines the control of the additional unit. In some cases, not only the additional unit but also the standard unit and such a control signal generation play an essential role in the operation of the additional unit. The gate systems or the logical combination systems, which are designated by d , are such logical combination systems which are provided in connection with main operating elements and are controlled by signals which are supplied by the main operating unit or by the control signals of the status detector, or they are main supply sources or others Gate systems. The main operating systems denoted by e correspond to the device for measuring the mean frequency deviation of the time unit signal in the case of the automatic fast-slow control, while they correspond to the register circuits in the case of the multiple alarm system. From the comparison between FIG. 26 and FIG. 25 it can be seen that FIG. 26 shows an example of a system which is controlled by the clock pulses sent out by the standard unit because the Ha_ptimpuls supply device 13 069 is controlled by the signals supplied by the standard unit 13 010 and because the main pulse supply device 13 069 a Signal 13 065 supplies which is composed of an input signal 13 050 to the status detector device, the control signal generating device 13 063 and the main operating unit 13 064. FIG. 26 corresponds directly to that in FIGS. 27A, 27B and 27C so that, as shown in Table IV, groups abc d and e. which the in the F i g. 27A, 27B and 27C also include blocks 130f3, 13 062, 13 063 and 13 064, o> in FIG. 26 are shown.

Table IV

Classification group No.

symbol

Contents of outputs (inFig. 27A-27C)

Main group
Supply group

1430 Qi-RR-a

1431 Tj-RP-a

1451 Φ-GEN-a WlDTH-a

1454 TPG-a

composite digital Q \ -Qtb playback signal

Timing pulse playback Ti-Ts, Tu, T ₂₄

^ -Signal form, synthesis from Φ \ -Φ4

Signal transmission and WKT. WDT,

Receive pulse width WATI, WATO

Synthesis of timing signals ex. Φ \ You 7 « Φ of different combinations

status

Scanning

1410 QHAT

1411 QOH

1424 DET-DT

1425 DET-AT

1427 AT-DISP-DET

1429 KT-DISPDET

1482 DT-GATE

Alnrm-0- time sampling
Alarm-O-time status scanning

Sampling of the coincidence of the date alarm and the date

Sampling the coincidence of the
Alarm time and the current time

Alarm tim »• Display status scanning

Current time display status scan

Fast-slow operation,
which the date sampling
certainly

OHAT

QOHER

~ EARTHED

DETAT. QERAT

QA.QΦ3ATi _l

QKT

DGOK

steering

signal

generation

1402 SB-c

1403 SA-c

1420 MAN-SHIFT-C

1426 SRG-STOP-C

1452 MARK-SET-C

1483 ANALYSIS-C

Gate system
Combined with
Main component

Output control
Input control
manual shift

Register stop

Setting the marker

Fast-slow setting
to determine the operation

1401 OUT-CONT-a data output gate

1408 CLOCK-CONT-d clock gate

1409 DATA-DOMOD-d input modulation gate

1407 DIU-GATE-d

J406 ALi-d

1405 AL ₂ -d

1404 DT-ER-d

1480 ADT-PE-d

e 1490 SRG-RING-e

Main operating system

1480 COMP-e

Data entry age
Mark input gatteij
Mark input gate 2
Date data clear gate

Gate for fast-slow setting pulse generation gate

Data storage register
Surgical facility

28 Süu SB ₂ , CB ₃ SA

Mc + \ Ms + 2 count Φ

ALI ₁ , ALI ₂ , ALD _x , ALD ₂

P ₁

DOUT, Dcl Φ \, Φι

DINX ₁ DIN'2, D / A / 3

1407- OUT

SRG-44S-IN

SRG-43S-IN

ΑΧΟ

FSO

SRG-OUT (111,121,311,441)

<? 3Ι - <? 36

In the description of the structure and the mode of operation of the embodiment of the additional unit according to FIG. 27A, 27B and 27C, the overall function of the unit will first be explained. The additional unit has a shift register ring 1490 with 64 bits, which is designed in such a way that it can receive alarm time data, a group of gate blocks 1401 to 1454 including various gate circuits for controlling the shift register ring and a device for generating various signals for actuating the gate circuits, an automatic one Fast-slow setting block 1480 and an additional gate block 1470. The <»■■? Bits of the shift register ring 1490 can hold four alarm time data for hour and minute. It is possible to increase the number of data by adding more shift registers. It is also possible to set an alarm for a month, a date, an hour and a minute. The alarm time data can distinguish between AM and PM, and you can either select the daily alarm mode, in which an alarm is given every day at a certain time, or you can select the temporary alarm mode, in which the coincidence of the set time and the current time only is scanned once, and actuate an alarm device, while thereafter the set alarm is automatically cleared. The setting of the multiple alarm data of the auxiliary unit is carried out by using the standard unit, so that it is not necessary to add an external actuator to the auxiliary unit.

With the fast-slow system, it is possible to use the vibration frequency of a mass-produced product.

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tor or correction capacitor is used. Such matching accuracy leads to an error of 2 see per month, which is smaller than the error of the os / illator. the one adapted by the manufacturer Quartz crystal used. In this embodiment, it is possible to immediately perform the fast and slow operations adjust with high accuracy by taking the result of measuring an average frequency error. caused by the effects of ambient temperature continues to be the result of behavior of the user and the aging of the quartz oscillator over a week in relation to a standard watch in the ^ must be taken into account. 25 i

In fact, with the clock according to the invention, a frequency adjustment can be so extraordinarily high Accuracy can be achieved by the user (to the extent that it cannot be achieved by a professional can be), which the "seconds" reset button twice at an interval of one week presses, e.g. B. according to an exact time signal, as it is transmitted on the radio. By such a Measure will be a compensation for the running speed depending on the one week related error scored. It has been shown that a precise fast-slow setting made which quartz watches other than the clock according to the invention can not be achieved.

The gate circuits 1404, 1405 and 1406 are provided for the shift register ring 1490 and are used for Purpose to supply the necessary data in a short time in a semi-parallel arrangement, and this gate switch 35,

Settings are used to set an alarm flag digit and clear the data, as S

will be explained below. The output signal SRG-WX is transferred from the additional unit to the standard unit j

sent, under the timing of the impulses D \ until you during normal use of the watch. The |

The output signal SRG- \ 2 \ is used to change the number of shift pulses per unit of time of the shift register 1490 under normal conditions and a status in which an alarm time has been sent when alarm time data has been passed from the additional unit to the standard unit, around the alarm time to adjust. For this reason, the position of the derivation of the data is shifted by one bit. The output signal SRG-44i is used to compare the month and date information sent by the standard unit with the date alarm data, which is stored in the shift register 1490 *

are stored, while the SRG-311 output signal is used to display the real-time information stored in the standard 45 I

Standard unit is stored to compare with the alarm time, which is stored in the alarm unit of the additional unit. Basically the time system according to the invention is of a time series type so that it is possible to process all data by deriving a signal from one point of the shift register ring. However, according to the invention, since the clock pulse is given intermittently, it is impossible to process the information unless it is processed in parallel. Accordingly, the flow of the main signals of the alarm system will be discussed in connection with the main operating unit. More precisely, the data which the -

Input terminal DIN are fed, are fed into the shift register ring 1490 with 54 bits via a gate circuit 1407, which controls the writing of the information in the shift register and the memories located therein, and via a data modulation block 1409. The gate circuit 1407 writes information into the shift register ring 1490 in Depending on an input determination signal SA on , 55 _

which is supplied by an input data control block. Signals from the output terminals SRG- |

111 and SRG-tH of the shift register ring are used as the DOi / T signal with the help of |

a gate circuit 1401, which controls the information output, the signals to the input DATA-IN f

fed to the standard unit are shifted by clock pulses Φ \ * and Φ ₂ * , which of clock pulses Φ, |

and Φ2 have been generated from the standard unit by the clock pulse control circuit 1408. It is 60 |

possible to increase the capacity of the shift register ring 1490 by placing a 64 (n-1) bit shift register 1494 between its output terminal AXO and the input terminal AXI , where it represents a natural number

According to FIG. 27A, 27B and 27C, the additional unit receives signals from the standard unit at its clock pulse input terminals Φ \ and Φι, on the data input terminal DIN, on the reference number signal input terminal D _n , on the display reference number terminal Da on the input terminals Φι / c 1 and & uc 2 for a composite time control signal input at the input terminal MSIN for a manual shift signal! and at the marker setting signal input terminal UDII. An output terminal DOUT of the additional unit is connected to a

Input terminal DIN of the standard unit is connected, and an output terminal Dcl is connected to an input terminal Dcl . In this way, information is exchanged between the standard unit and the additional unit via the corresponding input and output terminals.
The additional unit also has an output terminal FSO for pulse signals which set the speed of the watch, this terminal being connected to an input terminal FIN of the standard unit which uses the pulse signals to correct the frequency of the timing unit signals. The additional unit also has an output terminal AXO and an input terminal AXI , which enable additional shift registers to be installed in order to increase the capacity of the multiple alarm memory in the additional unit. While a direct short circuit of these terminals AX1 and AXO allows four different alarm times to be set, eight data are added by providing an additional 64 bits and 16 data are added by providing an additional 256 bits. Please note that for data above 16, the CONT terminal of the standard unit must be kept at a high level. to use the clock pulses in a continuous mode.

Input and output terminals of the gates and flip-flops are also provided for the purpose of providing the clock with appropriate flexibility. In the F i g. 27A, 27B and 27C is shown with a dashed line a booster circuit 1470, which uses logical combination switches with a view to flexibility. The inverters have N-channel transistors, the substrates of which are electrically different from the substrates of other Vs, ¹ . GperaticnstransistGrcri are isolated. The source of a P-channel transistor is; connected to Vvs ί. The pulses (PÜQ and ΦΙίϋι. Soft by a gate 14 703 designed complementary to each other, are clamped by the combination of a capacitor CX and a diode D 1, or by a combination of a capacitor C2 and a diode D 2. This is done in such a way that their high levels become equal to the level Vvs 1. The output pulses clamped in this way are applied to the output terminals of the inverters which are connected in positive feedback in a cross connection such that a negative potential equal to the width of the! pulse voltage is developed on the negative voltage source cnscitc of the corresponding inverter, the source potential Vy, -1 of the field effect transistor being at its base, so that a negative potential V «2 is supplied, which corresponds to 2 V _S s 1. The output Vss 2 is able to supply a boosted or boosted voltage to the display drive circuit with efficiency of more than 95%.
Ysw denotes a terminal which serves to control part of the function of the additional unit, and Ysw further denotes a terminal which serves to define the initial conditions of part of the counters in the additional unit. While the terminal Ysw , when set to a high level, enables the alarm time of the month, day, hour and minute and that of the usual hour and minute to be set to the same time, it then enables when it is set to a low level, the hour and minute setting alone. Terminal Xsw is used to set the starting positions of a static electronic servo system that controls the speed of the clock. If the terminal Xsw is held high for a short period of time, the counts in the counters making up the servo system quickly reach zero and the positive and negative control areas become substantially equal in width to each other on this point.

The signals fed to terminals Φ \ and Φ-> as well as DIN occur in a pulsed manner, ie intermittently when the CONT terminal of the standard unit is at a low level, and they occur continuously when this is not the case. The clamps you. 0 £ ΛΓΐ and 0 £ / G supplied signals are always continuous. The additional unit is designed so that it can be operated properly, regardless of the mode in which the signals Φ \, Φι and Ο / Λ / occur.

Such data, which are fed from the standard unit to the terminal DIN of the additional unit, are fed to a shift register ring circuit 1490 via a data modulator block 1409. The data modulator block serves to cancel the influence of the display modulation from the signal supplied by the standard unit.

The data are supplied to the shift register ring 1490 via a gate 1407 which is controlled by a control signal SA which is generated by a data input control block 1403. The outputs SRC-til OUT and SRG-i2i OUT of the shift register ring circuit are received in the form of an output DOUT via an output gate 1401. The output gate 1401 is controlled by control signals SB 1 and 552, which are fed from a data output control block 1402, while an output signal SB 3 of the control block 1402 in the form of an output signal DCL is applied in order to delete |

to control the data in the standard unit. |

The shift register ring has shift registers with a total of 64 bits and is able to store four different j

save the alarm time data. |

The clock pulses Φ \ and Φι with different phases are diluted by a clock control circuit 1408 to the pulses Φ \ ⁺ and ^ ⁺ , which are then fed to the shift register ring 1490 in order to control its operation. The clock control circuit 1408 is controlled by a signal CONT Φ , which monitors the passage of the clock pulses. The control signal ΟΟΝΤΦ is generated by a manual shift block 1420

The input signal Dn controls the display of the month and the day of the month and the week. The date can be displayed constantly by using the Signa! D \ < an input terminal DD of a display driver

h5 sound is supplied, which is provided separately.

A playback circuit 1430 for Qi is designed in such a way that it derives composite digit signals from the signals 0UCi and 0UC ₂ , while the signal D _n serves as a reference for the digit pulses. Such composite signals are represented by Q, = D \ + D ₁₊ 1, where; "= 1,2, .... 16 and Q \ i = Qx- Es iss

It should be noted that the signals <PUC \ and Φυθ _{2 were} also originally generated for the purpose of boosting or amplifying.

A reproducing circuit 1431 for TiJ reproduces a signal which is synchronized with the rising part of the timing signal Ti from the signals (PUQ and OUC ₂ , and synthesizes timing _{signals T 2} , T4, Te and Ti of various phases in response to clock pulses Φ \ and Φ ₂ , on the basis of a signal reproduced using the shift register. The timing pulses T \ to Te, which were reproduced in this way using the clock pulses Φ \ and Φι , occur intermittently, which under these circumstances also the clock pulses Φ \ and Φι do. the circuit 1431 is also composed Zeitsleuerimpulse Tu and T24 again. here the relationship Tn = Ti + T2 and T24 = _T2 + T4 are, and because the timing pulses Ti to Tg of the composite timing pulses Tu and T24 are reproducible, to the interconnection can be within the integrated circuit substantially simplified. A timing signal generator TPG-A 1454 is such excl e forms that it selects arbitrary signals from reproduced digit signals Qi and from the timing signals T ₁ and the timing signals ψ \ to φ *, which are discussed below, and also from the clock pulses Φ \ and Φ ₂ , so that a logical product signal such as q> iD \\ T% 0 \ is synthesized or compounded.

The timing of the signal exchange between the standard unit and the additional unit under different conditions is controlled by control signals Wkt. Wdt. Wm ι and W ^ i 0. which by block 145? ores " ¹ , wcrclcn

Mil 1428 Isi denotes a circuit for generating timing signals φ for synchronization. The outputs of the standard unit are subjected to the display modulation to perform the blinking or flashing with IH / when there is a coincidence of the correction digit or the alarm, so that trouble is caused when the information is based on the blinking phase Since this can be prevented in that only the standard unit is provided with an additional data output terminal DA TA OUT , which is free from modulation, this terminal can be provided for display purposes in addition to the data output terminal , which are used exclusively for the additional unit, are omitted because this saves output terminals in the integrated circuit, and instead a signal gh. which is synchronized with the falling part of 1 Hz and a signal g> \ 2, which is a product from Ip ₂ and gn , thereby synthesized or combined That the signal φ ^ is formed from a memory cycle width and is synchronized with the falling part of a 2 Hz signal of the timing data by selecting a phase which is free from the influence of blinking or flashing. If the signal q> i as the term of the logical product is multiplied by the sampling pulse, which is used to determine the content of the data signal, the information can only be read out at a high level of φι , so that interference is avoided in this way are. The signal φ * is delayed by one memory cycle with respect to the signal g> i.

A circuit 1429 of a circuit KT-DISP-DET-b for sampling the state of the current time display is designed in such a way that the data which coincide with the month and the day of a month-day alarm are deleted, and only if the current time puf is displayed on the display surface of the clock to find the relationship DD = D ₆ .

A circuit 1427 of a circuit AT-DISP-DE-TECT-b for sensing the state of an alarm time display is responsive to the alarm setting mode of the watch, and when this mode is detected, empty data and controls of the direction of signal transmission between the standard unit and the auxiliary unit become empty specified. The circuit 1427 supplies two signals, namely Q 3A T 1 and Q 3A T2, which have a phase shift of one memory cycle with respect to one another in order to sample the memory cycle immediately after the display mode has been switched to the alarm time, and it also forms a signal QA for the Display A is the logical product of the two signals. Circuit 1427 indicates blank data when signal Q <p3AT \, Qp3AT2 is high. The signals ζ) 3ATl and A3AT2 are fed to a circuit for manual shifting, which is designated by MAN-SHIFT , for shifting the clock control signal, and also to the block for generating the signals SA and SB for the input and output data to switch.

An alarm time coincidence detector circuit AT-AET-b 1425 is used to determine the coincidence of an alarm time, which is stored in the additional unit, with the current time which is supplied by the standard part. The circuit A T-AET-b compares an output signal from SRG 311 with the current time, and in the event of a coincidence the alarm time, which is stored in the corresponding shift register, is deleted immediately using a signal () £ 7? AT within the same Storage cycle. The coincidence signal denoted by DFT is also fed to a block SRG-STOP in order to thereby stop the operation of the shift register.

In the same way, a month-day alarm coincidence detector circuit compares month-day information with corresponding alarm data in normal time display mode. A coincidence signal from this one Circuit deletes the marking that connects the alarm times with the above alarm data, and through the use of gate 1402.

The circuit SRG-STOP 1426 is related to an output of the circuit 1425 and an automatic specification of an empty address. The stop control signals contain an alarm time coincidence signal D £ T4T and an automatic index control signal QqßATX · Qg> 3AT2, while the stop release control signals consist of a signal 60 S \ and a sampling signal OHAT for an empty address. With regard to the coincidence in the alarm time, this means that the transmission of the alarm time signal to the standard unit is interrupted by 1 minute on the side of the additional unit. with a watch that triggers a single alarm

A gate 1410 of OHAT-bist is designed so that it determines an output signal of an empty address of the circuit SRG-STOP. If an empty address is determined in the alarm setting mode, the standard unit modifies the corresponding alarm data output signal to the cleared state. When the additional unit receives the corresponding deleted data and transmits it to the standard unit, errors can occur in the upper digits of the standard unit because the four bits of the minute digit are all at high levels. To avoid this, a gate 1411 is used, for example a gate such as gate 1405 in the additional unit, which deletes the 10-minute digit of the corresponding data to NuIi

A manual shift circuit MAN-SHIFT-c 1420 feeds a clock pulse control signal to the key control block 140S in order to change the relative synchronization of the shift register ring circuit 1490 and the shift register circuit of the standard unit. The manual shift circuit 1420 applies a control signal MSf 2 to a

Output control circuit 140Z to create the possibility that new data can be manually transferred from the additional unit \

can be transferred to the standard unit. A terminal SY / V / is equipped with an alarm monitoring switch tied together.

A marker setting block 1452 is adapted to set the daily, temporary, monthly and time of day as well as an alarm of the additional alarm data, and adjusts these markers depending on the number of changes in the level of the input signal UDII . The marker set block 1452 is also operable to clear the extra alarm time.

A signal / WS © is passed from the manual shift block 1420 to the marker setting block 1452 in order to thereby bringing the count in a counter for the above-mentioned marker setting to zero, whereby the mark setting operation can be easily carried out with accuracy.

An example of a multiple alarm additional aging is shown in FIGS. 28A and 28B illustrated. A shift register, which is shown in the middle part of the drawing, has 64 data flip-flops, which are designated with 111 to 448. The shift register ring is shown interrupted by two terminals, Axo and -Αχ, to allow for additional shift registers 1494 to be added as required. The terminals Axo and Ax \ are connected directly if the 1494 shift registers are not available. An output DOUT is connected to the DATA-IN terminal of the standard unit, while an output DCL is connected to the DATA-CL terminal (see Fig. 8). The DATA OUT terminal of the standard system is connected to a DIN input terminal of the additional unit. With Φι * and CONTΦ are reserve signals which are available in connection with another additional system. Since the signals DIN, Φι and Φι occur intermittently, appropriate precautions must be taken to distinguish when the additional unit is addressed in combination with the standard unit. The additional unit is designed in such a way that it can normally be actuated independently of the signal mode, that is to say regardless of whether an intermittent or a continuous signal mode is present.

The input data from the outside are converted into a signal DIN 1 by means of a corresponding waveform shaping, specifically by two inverters which are present in a data processing block 1409, and they are fed to the shift registers via the input gate 1407. The gate 1407 is controlled by a control signal .S ', 4 which is generated by the file input control block 1403. The input data is written with the high level of the signal SA and circulates in the ring of shift registers with a low level. An output signal of the shift register ring is taken from the output of the shift register SRG-XW or SRG-MX and fed to the output terminal DOUT via the output control block 1401. from VO the signal to the DATA IN terminal of the basic timing block 203 is applied. The output gate block 1401 is controlled by output control signals 551 and 55 2, which are generated by the output control block 1402, respectively. Data for the display of the markings are generated by the output control block 140t and also transmitted from it. The data for the marking display is information prepared in a special way, which is continuously fed to the data elements only during the alarm setting, whereby they remain permanently at the low level of the marking digits, or there are j the data Dg and Dk, in the basic timing system, ie Data elements Di _b T and DihT *. so that

50 thereby a practical setting of the alarm data is facilitated.

While the month-day data of a month-day alarm are set in accordance with the explanations below, a data signal D \ f, Ti for displaying the data marking is supplied to the input terminal DIN of the standard unit 10 in order to indicate that it is at andelt the data ^h to month-day data.
The data component D ^ T * is structured in such a way that when a month-day alarm is set

ss it can be confirmed whether the shift registers of the additional unit can receive two alarm data. In the If a monthly / daily alarm is set, an alarm time is set first and then the Monthly day data set, which are linked to the alarm data. In this context it is essential, -u know whether any addresses are open for setting the month-day data. in the Considering the fact that in the system of the present invention the alarm set flag is turned on.

when an alarm time is set, an alarm setting flag is supplied to the DIN terminal of the standafd unit 203 by means of the timing signal from D ^ T *, even in the state in which no alarm times have been set, the alarm setting flag thus remaining off, where it is indicated that no month-day data can be entered in the following addresses, since they already contain other alarm times.

The shift register ring 1490 is driven by clock pulses Φ \ * and Φι * which are supplied by the controlled clock pulse generator block 1408. The clock pulses Φ \ * and Φι * are supplied by diluting the clock pulses Φ \ and Φι , which are supplied by the standard unit, in order to assign the relative phase between the shift register ring 321 and the shift register ring (64 bits) to the standard unit 203

steer. The thinning or narrowing of the clock pulses takes place at a low level of the signal "ONT". The output signal SB 1, which is generated by the output control block 1402, is

forms that it controls the transmission of a signal S /? G-III-O {/ Tst. in that the gate 1401 is opened when data are transmitted from the additional unit 12 to the standard unit 10 in accordance with the embodiment according to the invention in the normal mode. On the other hand, the signal SB 2 is designed in such a way that it transmits the data displayed in the event of monitoring or the activation of an alarm from the additional unit to the standard unit. The control signals SB 1 and SS 2 are derived in phase by 4 bits with respect to each other. The signal SB 3 represents the logical sum of the signals SB 1 and SS 2. And it is used to delete the data supplied by the additional unit and are stored in the shift registers of the standard unit 10. In the shift register ring 1490, there are gates 1405 and 1406 by which identification flag data are set using the setting element of the standard unit, these data being inputted into parts corresponding to D \ _b Ti and D \ _b T *, the remain unused while setting alarm data. In the illustrated embodiment, since processing on a time-series basis does not find sufficient capacity due to the thinned or narrowed pulses, time-parallel processing is partially carried out by the gates 1405 and 1406 with a view to setting the identification mark data. A gate is denoted by 1404, which serves to delete the monthly-daily data at 12 noon of the day on which the month and the day coincided with the corresponding alarm data.

It is useful at this point in the description of a preferred embodiment to describe the relationship in explain the synchronization between the standard unit and the additional unit.

The shift register 1490 of the additional unit and the shift register ring of the standard unit do not always work in full synchronization with one another. The shift registers of the standard unit require 1/256 see for a single cycle, and thus they cycle 256 times per second. The auxiliary unit's shift registers 1490, on the other hand, rotate 16 times per second. Thus, the standard unit and the additional unit are synchronized in their cycle only once every 16 cycles of the standard unit. If you look at the standard unit from the side of the additional unit, the standard unit works for the 15/16 second, during which the shift registers of the additional unit are not in circulation, in a short time interval between two clock pulses Φ \ and Φι , in the additional unit, as can be seen on a "sequential axis of the coordinates" of the additional unit. For this reason, and because Φ \ + Φ ₂ aiif are at a low level, namely in the above-mentioned interval, the additional unit does not cause any problems. The "sequential axis of the coordinates" here refers to the axis of the coordinates, which results when the relationship in the course of logical processes of a sequential logical system is plotted according to the sequence on the basis of a measure which here is not the absolute "second" but the number of clock pulses that drive the serial system. When the optional unit is viewed from the standard unit side, the data transfer from the optional unit to the standard unit can be carried out synchronously although the former unit intermittently

animal way works because both units with synchronized clock pulses at least during the Operation of the auxiliary unit. In the example shown, new alarm data, which are in the additional input |

are stored, in the normal state only once in each storage cycle of the additional unit to the standard unit transferred, d. H. in 16 memory cycles of the standard unit. The 40 | circulates in the standard unit

Alarm data, which are fed in this way, until the subsequent data reach them, ie for 15 memory cycles. When the CONT terminal of the standard unit 10 is grounded to attain a high level, the clock pulses from the standard unit are continuously supplied so that the standard unit and the auxiliary unit become fully synchronous. However, this is not disadvantageous for the functioning of the system. In other words, the relationship between the standard unit and the auxiliary unit can be viewed under the scale of the clock pulses, except for the marker formation in the output marker block 1401. In this exceptional part, ··: marker signals in the | Alarniciristcllmodus from the additional unit / u of the Si.mard unit transferred, unu / was under the time controls Si genes of D \ _h Ti and Di * T ₄ . without distinguishing between the mode of occurrence of the clock pulses. wherein the relationship in signal transmission between the additional unit and the standard unit when viewed from the first side is variable. which depends on the mode of occurrence of the clock pulses on the sequential axis. However, the above relationship remains unchanged when this part is viewed on the Zeitach'-e.

In tkr standard unit as shown in Fig. 1IA. the output signal Qi of the shift register, which is fed to the adder, is used as a reference signal, and this single signal Oi has its timing, which is determined from D \ to D \ _b , the number for l / 25b see the timing signal D ₁ assigned. The signal O, has a delay of 4 bits in the upper digit detector means. which is passed through gates for the solution or for the input of an external data signal, whereby it is generated in the form of an output signal O4 7 ~ / 4-Of / 7 "after it has been delayed by a further 4 bits in a data modulator The data output signal DOU of the standard unit is delayed by two digits m with respect to the digit pulses of the standard unit, and the data input signal DATA-IN and the data delete input signal DATA-CI of the standard unit are each delayed by one digit

Illustrative embodiment are the digit signal and the Zcitsteuersignal in the additional unit with the same I

Indices as denoted in the standard unit, and the digit signal Di & of the additional unit is synchronous with the digit signal Di _{6 of} the standard unit with respect to the absolute time. The standard unit transmits 16 digits of data from the V / 256 sec digit to the alarm mark, which corresponds to the 16 digits of the additional unit from the digit signal Di to the digit signal Di to D16. It should therefore pay attention to the fact __

that the indices of the digit pulses in the additional unit are two digits from those of the standard |

unit when processing shared data. The delay is one digit if data can be transferred from the additional unit to the standard unit. This means the timing

WATI = D ₁₅ + D \ 6 + Di + D ₂ ,

wherein an alarm data signal is fed from the standard unit to the additional unit, and the timing
WATO = D _H + Du + D _n + D ₁₁ ,

whereby data is transmitted from the auxiliary unit to the standard unit, both of which are controlled by the timing

D ₁₃ + you + D ₁₅ + D ₁₆

the alarm data of the output signal Qi differ in the standard unit.

Below are various ways of transferring information between the standard unit and the additional unit.

(1) In the normal state, alarm data is transmitted from the auxiliary unit to the standard unit. The alarm files are replaced by different alarm data in each memory cycle of the additional unit.

tO \ Im Δ liij-in-FinctAllmriHiic / in Hi ¹ In HlP AInrmvfMtHatf ^ n ailftTf ^ fliXt wf * rHi ¹ n \ Inufpn Hi * »* ir» hi * »h <* r ** cyictf» r Ae * r \ ~ j .... ... _H .... _...-— _v .. _{o o} . ■ -. j _o - -.

Standard and additional unit synchronized. The same set of alarm data is then repeatedly transmitted and displayed by the standard unit. Since the same data stream is transmitted to the auxiliary unit and the display unit and the data is normally modulated at a low frequency in order to display some of the % 25 data flashing, these transfers only take place when the synchronization pulse cfa is high

'"' Level. Φι has a frequency of 2 Hz and - as shown in Fig. 53 - only has a high level if

there is no blink modulation.

(3) In the alarm data setting mode (with multiple alarm options), it is possible to set the alarm data displayed to display all alarm times saved in the additional unit. This is done through

f 30 Pressing the manual slide switch, which turns the alarm time saved in the standard system into

Additions' ^ is transmitted, namely to their shift register synchronously with qn. Then the data in the shift register ring to the additional unit are shifted by four words in relation to the time sequence of the Star.dard system and transmitted once bti MS © to the standard system. The two shift register rings are then set synchronously again in the following storage cycle. So only one new set of alarm time data is continuously displayed. If the slide switch is pressed continuously, the above process is repeated so that a new alarm time is displayed every half second.

(4) When the alarm time coincides with the current time in the normal state (current time display mode), the data transfer from the additional unit to the standard unit is interrupted for one minute, and after this one minute has passed, the data will be transmitted in the same direction resumed.

(5) When the system changes its state from the normal state to the alarm setting state, an empty address of the auxiliary unit data (data at zero o'clock) is first indexed. If there is an empty address in the auxiliary unit data, the shift registers of the auxiliary unit are turned off so that the empty address data is synchronized with the standard system, whereupon the empty address data is transferred from the auxiliary unit to the standard unit. As a result, alarm information is transmitted from the standard unit to the auxiliary unit in synchronism with the timing pulse ^ ₁ . This is a function that was built into the system in order to be able to set an alarm signal quickly and easily. If no empty addresses are found, the automatic indexing operation is stopped in 0.5 seconds, whereupon the synchronized data is transferred from the auxiliary unit to the standard unit. In this state, the system is in an alarm warning mode.

Thus, a manual shift or an automatic shift is used. For an automatic shift, the manual shift input terminal 266 (Fig. 18) is set to a high level, in a continuous manner for more than one second, from where the alarm data of the accessory / unit one after the other at a rate of one data record per Second, the shifting will be stopped when the input terminal is brought back to a low level .

(6) When the system is in its operation mode, which is changed to the normal state by an alarm indication, the signal transmission from the auxiliary unit to the standard unit is carried out after alarm data is transmitted from the standard unit to the auxiliary unit in synchronism with the timing pulse q> 2 : the.

While in the above description the signal transmission has been carried out in such a way that it takes place in synchronization with the timing pulse φ $ for the purpose of avoiding the influence of blinking or flashing of the data, such synchronization with the timing pulse q> ± disregarded if a terminal DATA-OUT is available which is free from the influence of the blinking or flash modulation , so that it is independent of the terminal DATA ^J-OUT. In the illustrated embodiment, the blinking data is used alone for processing because it is desired. to reduce the number of output signals from the slanching unit. Furthermore, / usiil / lichc can also crojiize

J4

1494 can be incorporated in the illustrated embodiment. In the event that a considerable number of shift registers are to be added, the CONT terminal of the standard unit is terminated to the unlocking terminal ULO or ULT of the switch in such a way that a number of data can be set by using continuous clock pulses only during one Alarm setting can be used and in the normal state the time error (on the order of one second) required for sampling an alarm time coincidence can be used to serve as intermittent clock pulses. As a result, a saving in the electrical energy used is achieved. Alternatively, continuous clock pulses can only be used for one second with each revolution in one minute in order to save electrical energy. In addition, the use of a computer, if it is desired as an add-on and is operated with intermittently occurring clock pulses, will only allow a low computing speed and thus be unsustainable in practice. A mode of operation at high speed and lower energy consumption can, however, be achieved when using a computer in that continuous clock pulses are only supplied when the computer is in operation or only during the calculation. The fact that the clock pulses can be controlled to occur either intermittently or continuously makes the basic timing system of the present invention extremely advantageous.

The following is a circuit block for providing a signal to operate the shift register ring Described in 1490.

According to FIG. 28A. 28B and 28C, a signal CONTΦ, which is fed to the clock control block 1408 , is latched by a clock pulse Τζ, Φχ so that it has a delay which is slightly less than 1 digit. The logical product of the delayed signal CONTΦ and the signal Φ is generated as a signal Φ without peak noise occurring. Similarly, a signal Φ \ "is generated which has a slight delay in relation to the signal Φ *. The signal CONT Φ must therefore be a signal which is one digit ahead of the timing at which a clock pulse This oignal CONTΦ is generated by the manual shift circuit 1420 .

The input terminal MSIN of the manual shift circuit 14Γ.0 is connected to the terminal SU ₂ or SUT of the standard system or to an alarm monitoring switch for exclusive use at the terminal MSIN , so that the circuit 1420 is operated in connection with the switching operation in the standard unit . ] Every time the input terminal MSIN is brought to a high level in the alarm data display mode, a manual shift signal MS \\. which has a width which corresponds approximately to one memory / cycle, generated synchronously with the timing pulse q> \ , whereupon the signals MS 2 \ and MS 3 f are generated one after the other at intervals of one memory cycle each. These signals are shown in the FIG. 38 is generated. Since the MSIN terminal is kept low for more than a second, the shift signals MSX \ to MS3 f occur one after the other once per second. The generation of these signals is stopped immediately after the level of the terminal MSIN is changed from a high to a low level. The clock pulses which have passed through the gate circuit 1408 , which is controlled by the signal CONT Φ , appear with a timing which is 12 bits away from Di to D ₂ via Di _{6 in the normal state.} which in the alarm display mode is 4 bits away from Di5 to D ₂ via Die, which is 4 bits away from Dn to Di in the following one memory cycle, which is 8 bits away from Di 1 to D _{2 in the following one memory cycle and} which is then 4 bits from Dy- to D ₂ removed. Because the signal CONTΦ per se "ni has to lead one digit ahead of the occurrence of the above-mentioned clock pulse. It is generated by a synthesis or combination of the digit pulses, the indices of which in the number were reduced by one. In the normal state, the clock pulses which are in the shift register ring in the auxiliary unit auftreten.4 digits of insgec amt-16 digits, so that the data / wipe the standard unit and the auxiliary unit by 4 different digits ^r -Ind or according to a Alarmd ';' ens.it/ in bc / ug of a storage cycle of the clock pulses applied by the standard unit. As a result, new alarm data are progressively exceeded by the additional unit / u of the standard unit, (λ suppose that the slatus of the system has changed from normal display to al-irman / cige the shift registers of the additional unit can be activated in such a way that they revolve in the normal mon, "ntancn time mode, and / w ar me a speed which i'it three times as great as that in the alarm display mode. Thus, the data from the additional unit, which are synchronized with the ZciiMeurnmpuls g \ in the alarm display mode, are also synchronized with the time control mode ψτ, in the normal mode. It follows that when the normal state is switched over to the alarm display synchronously with the time control pulse ψι , the alarm signals with the standard unit are synchronized with the corresponding alarm files in the additional information. If these data are transmitted to the additional unit synchronously with the target control pulse ςη, and / was after a correction or setting, the corresponding data are also corrected or set in the additional unit. If in the additional unit an empty address is determined by the gate 1410 , whereupon the data circulation in the shift registers is interrupted and after the data which represent the empty address are in the standard unit ·; were written, the data of the empty address was transferred from the standard unit to the auxiliary unit under the timing of ζπ. In short, correspondence between the alarm data in the standard unit and that in the auxiliary unit is established within 0.5 seconds, which is the frequency of the timing pulses g? I when the normal state is switched to the alarm display. The switching of the data transmission paths between the standard unit and the additional unit, which result from a change in the operating mode, can therefore take place without destroying the alarm data which were previously set in the additional unit. When the alarm time data displayed on the standard unit is corrected, the data stored in the auxiliary unit and which corresponds to the alarm time is also corrected through data transmission from the standard unit to the auxiliary unit. If the

manual shift takes place for the purpose of setting a further alarm time, after an alarm line is set, the previously set alarm data is transferred in the standard unit to the additional unit, under the timing from Du to D ₂ , synchronous with the timing pulse φι, and then the data which corresponds to an address following the one in which the previously set data is stored is transferred from the additional unit to the standard unit under the timing from Dm to D ₁ in the immediately following storage cycle of Additional unit. In a further memory cycle of the additional unit, which follows the above cycle, clock pulses corresponding to a data record or 4 digits are added in such a way that the data in an address that follow the previously set alarm data with the alarm data in the Standard unit in accordance

It can be brought into tune in response to the following timing pulse qn and synchronously with it. Since the alarm in the standard unit has already been delivered with the data from the additional unit in response to the manual shift signal MS2 \ , the same data are stored in the standard and in the additional unit, which correspond to one another. The indexing of the empty address, which was shown and described in this embodiment, proves to be particularly advantageous when the number of alarm data is increased. In particular, when additional shift registers are installed and the status of the system is changed from the normal state to the alarm setting state, a status of an empty register is immediately displayed to prepare for the alarm timing, thereby enabling a new alarm timing to be set quickly. If the shift registers are filled with alarm data, unnecessary data is also selected and reset via a manual or a p.iücniK'.ische Yor shift. This operation of indexing an empty address is possible to clearing initial values in various auxiliary units including a hemadynamometer and a calculator, and it can be easily carried out by detecting a switching signal from a normal state to an auxiliary unit.

55 shows relationships between output clock pulses (Φ \, Φ ₂ ), clock pulses (Φι *, Φ ₂ *) which occur in the normal alarm mode and in the manual shift mode, output data of the standard unit and input and output data of the additional unit.

A marker setting block 1452 is adapted to generate control signals for processing alarm time data and includes a control input terminal J $ W. If this has an "H" level, date alarm times can be entered, otherwise hour or minute alarm times can be set. A counter provided in the block is operated by a signal UDII , which here comes from the terminal SU2 of the standard system. With each transition from L to Η level of the signal UDII , the bit sequence of the outputs ALI 1. ALI2 and ALD2 changes, as can be seen from Table V. These signals are used to disable or set data for gates 1405 and 1406 of shift register ring 1490. The bit input at time D ^ T * through ALD 2 means that previous alarm time data immediately follow the following date data. The bit D ₂ T ₂ set by ALD 1 means that a symbol indicating a date number is to be displayed when this data is displayed.

Table V

T ₁ 7 * 2 74 0 0 0 7 * 8 7-, D ₂ T ₂ ALI 0 7-4 7 * 8 ALD count ALDI 0 0 0 ALD 1 1 Data entry 0 0 0 0 0 0 0 0 1 0 0 0 0 0 ^Γ ι ^Ί
ι Ι ι
II 0 1 0 0 0 1 0 0 1 0 0 ALI 2 0 0 0 0 0 2 1 I. 1 1 1 0 0 ALI 3 1 data 0 0 0 0 0 activation 0 0 0 0 1 0 input 1 0 0 0 1 0 2 0 0 0 1 0 3 enterable data set dates

Comment III level
0 1st level

Täkiiinfniise. which correspond to only 4 digits, are fed to the shift registers of the additional unit during the setting of an alarm line.In order to set a marking that extends from a first data set to a second data set, the clock pulses are grounded in the shift registers at various points under the control of the time control signal supplied from D ₂ with respect to the currently displayed alarm time data

the timing of D15 with respect to the data being located in the following address. The signal t

QF.RA T, which is fed to the marker setting block 1452 , is arranged to clear the alarm time in the additional unit which has coincided with the current time in the standard unit. When the alarm data address is empty and when it is zero o'clock, data is transferred from the auxiliary unit to the standard unit, with the 1-minute and 10-minute digits being undesirably modulated to clear the minute digits. The signal QOHER prevents this by deleting the minute-digit section, where the data are suppressed when they are transferred from the standard unit to the additional unit by manual shifting.

In the Fi g. 36 and 27B, 1451 denotes a gate or a logic combination circuit which is used to determine the widths of the timing pulses which are used for data transmission between the additional unit and the standard unit. As shown in the circuit arrangement in FIG. 27B, the signals WATO and HM77 are timed from Du to Di and from lh; to D _h are only generated when clock pulses are supplied from the standard unit. On the other hand, the signals WKT and WDT determine the timings at which data are transmitted from the standard unit to the additional unit, and they are derived from a composite digit pulse, which in turn is composed of continuous boost pulses Φ UC \ and Φ UCi . The signals WKT and WDT are thus free from the influence of the intermittent clock pulses. These signals WKT and WDT are each used in a continuous form, since no problems arise from the point of view of the circuit arrangement.

Denoted at 1427 is a circuit which is used to scan the alarm display mode. The status of the alarm display can be determined by comparing the signals DD (which numerical signals are and for which D \ ₄ = DD and D _b = DD applies in the alarm state or in the normal state). However, because the changes in the signal transmission between the additional and the standard unit when switching from the normal display to the alarm display must be timed by the pulse q »i , as was already discussed above, the operating mode is initially activated by a signal 5 'iDiiT ₈ eö, scanned and then after locking by a Signa! read out into a signal Qqi ^ ATX , so that interruptions in the switching timing of the signals between the additional unit and the standard unit are free from the influence of the switch-on sampling outputs. The signal Qq '\ AT \ is locked again and read out by a signal ^ DiT ₄ (A, j

to lower a signal Qq '\ A T2 , so that a signal is formed which is synchronous with the pulse q> \ , but lags behind the signal Qq <\ AT \ by 0.5 seconds. The signals QpiATl and QgnAT2 are combined to form a logical product QA , so that the signal switchover from the combined additional and standard system is completed in 0.5 seconds after the actual switchover from the normal current time display to the alarm time display. The signals QA. Qq ^ ATi and Qg> jAT2 are used in the respective blocks 1420 (manual shift), 1402 (output control), 1403 (input control) and 1426 (shift register otop) which participate in the signal switching operation.

With 1429 a circuit is referred to, which is used to sample that the display of the normal instantaneous Time, this circuit is constructed in the same way as the alarm display sampling circuit except for timing.

Furthermore, 1425 denotes a circuit which compares an alarm time setting in the additional unit with the current time which is supplied by the standard unit and which deletes the corresponding data in the additional unit in the event of a coincidence. In order to erase the corresponding data in the same memory cycle as when the coincidence was sampled, the comparison should be made under the timing from Di to Dio in the normal status, while current time information is being transmitted from the standard unit, assuming that the erasure occurs at the time control from Di5 to D ^ takes place in the normal status. For this purpose, the flip-flop, which was set by the signal QA · Q ₄ according to FIG. 14B, is used when determining a difference between the data input signal from the standard unit and the signal SRG-31 \ OUT via an exclusive OR gate the time control of WK T or D? reset to Tue _0. However, since the flip-flop is not reset if the two data sets or the times are the same, a logical product is formed from the flip-flop output signal and the signal which has a width of Di 5 to D? or W / 4 T / is applied to gate 1452 as an alarm data clear signal.

A designated 1424 month-day coincidence sampling gate is similar to the alarm coincidence detector 1425 constructed However, since the timing T2 of the month-day data is the marking point at a high level, the conditions that the for the coincidence between the data of Standard unit and the data stored in the additional unit are required, including the conditions that

SRG- 111 OUT

is at a low level. When deleting the month-day data in the additional unit by the coincidence signal, the data in the following address have their sections, which _{correspond to T 4} (which indicates the connection with the month-day data) and T _{8 of} the marking number in the Way that the alarm time associated with the month and day becomes temporary alarm time data which can be compared with the current time. When comparing the time stored in the additional unit with the current time, the marking of the month-day data (a high level for Tt) and the month-day connection data (a high level for Ti) will never coincide with the current time, since all the values 71 to Tg in the marking part of the alarm time data in the additional unit are compared with the low levels at Tj and T _{s of} the data supplied from the standard unit and with those at Ti and Ti _n which are set in the additional unit.

With 1426 a shift register stop block is referred to, which is designed in such a way that it stops the operation of the shift registers in the additional unit for one minute, during which the standard unit stores the alarm data in the event that an empty address in the Additional unit is indexed and a coincidence occurs in the alarm time in the normal status. As for the indexing of an empty address, the flip-flop is set when the time from zero o'clock is within 0.5 sec, which is an interruption between the normal display and the alarm display, and it is reset when the signal Qg >} AT2 goes high. The flip-flop for stopping the shift register is also controlled under the timing ΰ \ αΤ% Φι of the DETA signal (supplied by the circuit 1425 ) in the normal state. An output from the; Flip-flop is locked by a signal ΰιΤ% Φ \ , in the following memory cycle of the

ίο additional unit, and it is transferred to the manual shift block. When determining the coincidence between the alarm time data and the current time data, the clock pulse clears the alarm data which are stored in the additional unit, whereupon the shift registers in the additional unit are stopped. One minute after this point in time, a signal QqboST (which represents an interruption in the minute digits) is received via a circuit 1483, whereupon the flip-flop 1426 is reset in order to be able to resume a cycle of the data in the shift registers.

The data processing block 1409 forms a data input signal from the standard unit to the auxiliary unit and forms signals DIN 1 and DIN 2 through the circuit illustrated in FIG. 14B. The DIN 1 signal is the same as the input data. A modified data signal is fed from the input data to the marking part of the current time for display purposes, so that the data which indicate the actual line are only effective at T \ (a timing control which PM indicates), and the remaining signals Tj bib Ta must be at a low level. For this purpose, the signal DIN 3 is supplied, in which Ti to Tg of the marking number (which corresponds to a time control D \ o ) are set to a lower level in the additional unit. The signal DIN2 is formed by the circuit illustrated in FIG. 14D. The in the F i g. 30 shown circuit is constructed and designed in such a way that the output signal DIN 2 remains at a high level only when an uncorrected state of the clock is detected, so that the date gate pulses are counted in the automatic fast-slow control part that is determined because "PM" of the current time data exists in the normal state of the watch.

A signal DIN \ ■ Dw Τ & Φ \ attains a high level when the timer 7g of the weekday digit is at a high level. A blinking or blinking of the weekday number occurs in the uncorrected state as well as in the totally blinking state (which is caused by a coincidence in the alarm), the blinking is sensed and a signal QFL is generated. The signal DIN2 is thus formed on the assumption that the blinking of the weekday digits in the current time display is normal. The phase designation between the timing pulses g> \, qn and q> \ and the flashing is shown in FIG. 53 illustrates. If it appears appropriate, a circuit according to FIG. 54 can be used, in which a gate is designated by 1463 ' which is the gate 1463 of FIG. 46 is replaced, while in combination the circuit which leads from DIN 2 to 1463 is replaced by the circuit shown in FIG. 54 illustrated circuit can be replaced.

The block 1430, which reproduces Qi , is designed so that it reproduces digit pulses from the continuous signals Φυα and Φϋ € 2 . The Signa! 0UC ₁ is the sum of D ₁ , D ₃ , ... and £? ·,;. The Signa! On the other hand, Φ1) € ι is delayed by a shorter time period compared to the signal Φί / Q , which is equal to the difference between the signals Φ \ and Φ7 . Thus, if two clock pulses Φα = ΦϋΟ \ ■ ΦυΓι and Φ / i = ΦίΙΟχ ■ ΦΙΙϋι are present, 16 latch circuits generate a composite signal Qi (Qi = Di + Di + 1, / and Q _n = Q).

Shift registers 1494 are used in addition to the existing shift registers if desired. to increase the number of alarm data.

1480 is a block for automatic is loss-gain setting referred to, which is formed from the elements of 1481,1482,1483 and 1484th of which 1482 is a date gate block. The counter has an octal counter. which detects changes in the date in response to the time information supplied by the standard unit, which continues to open the automatic setting gate on the eighth day and which inverts another flip-flop ζ) 43 on the ninth day to establish a waiting status. The data gate returns on the first day to begin counting in response to an unamplified input signal supplied before or after the eighth day. A slow-fast control input can pass through the gate on the eighth day, and when control is complete, a signal is provided to the data counter which then returns to the first day. These measures are shown in FIG. 56 illustrates in FIG. 56, the wide arrows indicate the advancement of one step per day in response to the current time data, while the narrow arrows indicate the incremental advancement caused by the control inputs.

The identification gate 1483 is adapted to detect the case where the second remote reset switch is brought to a high level for more than 4 seconds and less than 20 seconds in the normal state, thereby producing an identification signal P \ in one minute the determination is generated. The |

Fig. 57 shows the relationship between the signal P \ and the input signal UDII. j

The circuit 1481 (FIG. 48) comprises a divider-60 counter 1465, the counter reading of which is kept constant over a week while the lead / lag correction takes place. Another counter 1466 of this type counts the units of the seconds data of the starting time Counter 1465 and the seconds count of the current time (in register 58, FIG. 4) are set to zero at the beginning of the lead / lag calculation Week, if the running seconds count is zero, any counter reading in counter 1466 that may deviate from zero will display the lead or lag in seconds, and rwar is based on the period of a week. As a result, the reading of the counter 1465 is added to the counter 1466 , which is subtracted from the initial counter reading stored within a week. The outputs of the counter

146b, ζ) 31 to Q 36 serve to control the generation of an error correction feedback pulse FSO which are given to the timing crimp generators of the standard system. An increase by +1 in the counter 1466 means that the standard time measuring system will last an additional second in the next week. In order to subtract the count of 1465 from that of 1466, a pulse / 'ι a (Jutler opened at the end of the calculation / eil diircl *, whereby a high-frequency pulse / ug of Tu' / 'is simultaneously applied to the last two ί counters The control signal P \ drives the counter 1465 forward rapidly, and / was with a high I'Ycqucnz, until the count in the counter 1465 reaches zero the initial count of 1465 remains.

Circuit 1484 generates feedback pulses that correspond to the count in counter 1466. That Feedback signal is generated in that existing time pulses are combined with one another without a frequency divider is used. It is assumed that the following relationships hold:

Ö2 \ ■ Qn ■ Qn- Q- (Qk + Qit) = A. 8 Hz | = ß;

<H ■ Tt ₂ ■ T ₂₄ Q, _b -Qx- ¹ Px = F, = Β ^ Ω, ΤαΦ,

ηι ■ T ₂₄ ■ Q _[a ■ Qu ■ Φχ = F ₂ = BtP ₂ D ₁₁ (T ₂ + Τ ₄ ) Φ,

'/ 1 ■ Qu -Qx * - Φχ = F ₄ = Βφ ₂ D ₁₀ (T, + T ₂ + T * + Τ _& } Φ,

Tu ■ T ₂₄ ■ Q _Jb ■ Q \ ■ Φ \ = F ₈ = BD _x T ₂ Φ,

7V, · Q, _t · Q, ■ Φ, = F. «. = RD.JT, + ΤΛΦχ

φι ■ Qu · Qx ■ Φχ = _{Fj 2} = D ₂ (T _x + T ₂ + ' T ₄ + Ts) Φ, ■ Ip ₂ ■ B

it is further assumed that the frequency of the signal FSO is equal to fso and that the frequency of the signal FSI is 0 Hz; then applies:

F ₁ I Hz F ₂ 2Hz F ₄ 4Hz F ₈ 8Hz F ₁ e 16Hz Fig. ₆ 28Hz

Since the logical product of any two signals from signals Fi to F32 is at a low level, frequency addition is possible if they are added by the OR gate. The average frequency of fso of the signals Fso can be printed out as follows:

35

fso = 1/20 (2 ° · <? "+ 2 ¹ ■ Qu + 2- '· Q" + 2 ^J · Q ₁₄ + 2 ⁴ · (? ₃₅ + 28 · QlJ (Hz)

where Qii through (? j _{b are} either 0 or 1.

Adding 1/20 Hz to the 32,168 Hz timing frequency makes it possible to change the clock in a week about 1 see, which means that the system according to the invention automatically detects the weekly error presses to less than 1 see after the pre-run / run-on setting process has ended.

Counts 33 to 59 in counter 1466 can be matched with -27 to -1 when, in use, the weight of signal Q ₂ e is not 32 but is -28. Assuming that the high level of the signal indicates "-28" and the low level indicates "0", then the counts 0 to C in counter 1465 can be used as 0 to 31 and -28 to -1. This enables the weight of the signal ζ) 36 "to be viewed as" -28 "so that 56 Hz corresponds only to the frequency of the signal Fj2 at a high level of the signal T ^. The signals 8 Hz f and Qf ₂ have a common storage cycle and are built up on one line. although the frequency of the first signal is 8 Hz and that of the last signal is 1 Hz. Thus, if the signal </> ₂ as a term of a logical product is added to an input part of the gate which _{corresponds to the signal F 32} , only that part which _{corresponds to the signal Fj 2} is supplied with a frequency of 7/8 Hz .

In FIGS. 28A and 28B, a preferred embodiment of a detailed electrical circuit for the shift register ring 1490 is shown, which is shown in FIGS. 27A, 27B and 27C is illustrated. According to FIG. 28A and 28B, the shift register ring 1490 comprises 64-bit shift registers, which are designated 111,112,114, Iil8,121,122 ..., 448. These shift registers are driven by intermittently modulated clock pulses. The intermittent modulation of the clock pulses takes place during a time interval between the clock pulse Φ \ and the clock pulse Φ ₂ , ie when Φ \ ■ Φ ₂ = "L". More specifically, each of the shift registers is composed of a main-sub-data flip-flop which has a main stage latch circuit of a dynamic memory and a sub-stage latch circuit of a static memory. The shift register ring 1490 has a plurality of input terminals and a plurality of output terminals , which e> i are designed so that data can be input and read out in parallel in the shift register ring 1490 for appropriate processing within a time unit which is determined by the intermittently modulated clock pulses are read out in response to the digit pulses D ₁ 5 to D ₂ . those data which correspond to the alarm time are read out from an output SRGA 11 -OUT of the shift register ring 1490 in response to the same digit pulses Dt ₄ to D _2.

The signals from the electronic clock are supplied to the auxiliary system in response to a synchronization signal φι. which has a pulse repetition frequency of 2 Hz. with a pulse duration of one

Storage cycle. At this point it should be noted that the alarm signal which is read out from the SÄG-111-oui output of the shift register when the digit pulses D \ 5 to Dj are timed is also referred to below as the first data record.

While ars setting operation of the alarm time only 16-bit shift registers are driven by the Taktinipulse. The digit pulses D, 5 to Eh are supplied to the shift register ring 1490 when it receives the data from the electronic watch, while when the shift register ring 1490 supplies the data to the electronic watch, the clock pulses Φ \ * and Φ2 *. which correspond to the four digit pulses Du to Di are fed to the shift register ring 1490. The shift register ring 1490 receives data from the electronic watch in response to the digit pulses Di5 through D2. ie Sa. = H. On the other hand, the shift register ring 1490 supplies the data to the electronic watch under the timing of the digit pulses Dm b's Di in response to a signal SBZ generated by the signal generator SB 2 in response to an input signal MS 2 which is from the manual Shift part is fed.

In a normal state, the shift register ring 1490 is driven by the clock pulses for 48 bits during the period of the digit pulses Eh to D2. The alarm data are sent to the input Stiemme DIN of the electronic clock under the timing of the digit pulses D14 to Dj and zwax before the output signal! of the standard timing system by one digit. For this purpose, the alarm time data are derived from the SRG- 12 l-out output

Under normal conditions, the data from the outputs SRG-2W and SRG-ZW-out of the shift register ring 1490 at the time controls of the digit pulses D ^ to D ₂ are still stored therein and they are hereinafter referred to as first and second alarm time data. With the timing of the digit pulses Dt to D _n . which are faster than the time controls Du to D2. around eight digits, the current time data stored in the minute digit and the marking digit are supplied from the electronic watch. It is thus possible to determine the coincidence in the logic level between the data of the output SRG-lW-out and the data fed to the input terminal Din , so that the first alarm time data are compared with the current time data for the time controls from Di to Dio . If at this moment the first alarm time data coincide with the current time data, the first alarm time data for the time controls from D ^ to Di are deleted by an O.iMer 1406, which is arranged between the input SRGA4S and the output SRG-iW-out of the shift register 1490 is. An input signal ALU is fed to gate 1406 for this purpose.

The month and date data are transferred from the electronic clock to the time controls of Tue; Delivered up to Dm. If the data which are read out from the output SRG-WX at the timings from Dn to Du are referred to as first advance data with respect to the first alarm data which can be taken from the output SRG-221 , the advance data and the Month and date tai.s in the phase around a digit. Namely, the digit pulse Dt 2 corresponds to the ten digits of the

J5 minute in the preliminary data, while in the month and date data the digit pulse D] 2 corresponds to the one-day digit. It is therefore necessary to enter the data from the output SÄG-441. which are delayed by one digit more than the data of the output SÄG-111. to be compared with the month and date data. The compared result is sampled in response to the downward control of the digit pulse Du. ur, d thereafter, the month and date alarm data, which were stored in the auxiliary system, are released in response to the digit pulses Dm to Di. It should be noted that when the clear gate / wipe is placed between the SRGAW output and the SRG 348 input. the data stored in the four digits, ie the one-day digit up to the marking digit of the alarm month and the date data, can be completely deleted. This is because the preliminary data are stored in the shift registers SRGAW to SRG 44 $ under the timing of the down-control of the digit pulses Dm. In the embodiment shown, however, the delete gate 1405 is arranged between the output SRGA4 \ and the input SRdAiS in order to delete the data / u which are stored in the 16 bits that are stored in the 2 bits for the connection marking and the 2 ^J bits for the daily marking are contained in a / wide advance data record which is stored in the shift registers SRG 348 to SRGiW. and in a one-minute digit (a day), still in a 10-minute digit (10 days), still in an hour digit

so (months), still in a 2 ° bit for the PM marker and in e ^; nem 2 'bit for the date marking in the first preliminary data, wc: he are stored in the shift registers SRG4W to SRG 448. If the 2 ² bits for the connection marking of the alarm time data in the second advance data set / store an "I", the month and date data in the first advance data set are connected to the alarm data in the second advance data set. With the alarm time connection marker supplied in this way, the coordinates / iden / / between the alarm / time data and the current time data are never scanned. However, if the alarm time connection flag is cleared in the second advance record, then the alarm time in the second advance record is changed to a normal temporary alarm which is automatically cleared. after the audible alarm signal has been generated temporarily.
The gates; I4O5 and 1406 are used to set the marking indicator number. Upon receipt of the output signals from the marker setting circuit 1452, the marker data is stored in the shift register ring 1490 in the manner shown in Table IV. In Table IV, the symbol ALU indicates that the "1" in the first data represents the input signal for the daienmarkiming. Similarly, the symbol ALD 1 indicates that "I" and "0" of the input data represent those data which are supplied as minitang signals. "I" of ALI 2 represents the input signal for the first preliminary alarms

h »and the symbol AI.D2 represents the data in this input signal. The symbol» M <indicates the number of cases. in which { IDII / between a low and a high level is changed. The table IV zcigl. that the display of the data mark is not changed when JV = O _{1, however,} the setting of the first alarm and the setting of the continuous alarm are unlocked when / V = 1 and N = 2, and the

The month and the dates of the first alarm are set and the first pre-alarm is set with the month and I.

linked to the data of the first alarm.

The shift register ring 1490 also has a gate 1410 which is designed such that it determines the digit zero of the alarm data in the additional system. This gate 1410 thus produces an output signal OHAT which indicates that the hour digit of the alarm data is equal to zero, i. h "a free address. If the output signal OHATat gate 1410 is read out during the timing of q $ D \ Tn <P \ , it is possible that it is determined that the shift register for the wide alarms is unoccupied. The gate circuit 1401 allows cm (! All for a marking display / <_ ige. Which a marking signal for the timing control. I), TaQ. \ Through. When the wide alarm is set and stored in the shift register, an alarm flag setting signal is supplied to the display device to display the alarm flag. The gate circuit 1401 also has a gate to which the timing signal D \ T ₂ aQa is applied to sample the date setting flag. An output is generated at the timing of D \ T2 * Q * and supplied to the display of the electronic watch to display the date mark thereby indicating that the date setting alarm is set. While the data which are fed to the input DlN of the time measurement register 32 of the electronic clock under the time controls of D \ Ti and D \ T ₄ are cleared by the gate 66 of the time measurement register 32 (see Figs. 11A and 11B) , if ' 2s possible to control the functions and the display mode of the electronic clock by continuously supplying the time control signals D \ T ₄ or Di T2 in order to scan the coincidence between the current time and the alarm time and the time signal D \ 7? for the special display such as a month and a date marking etc. in the input DA TA-INacs time measuring register 32 of the electronic clock.

The gate 1411 is used to determine the status "15", ie (1,1,1,1), namely in the number for the ten minutes of the alarm ride. and it generates an output signal QOHER for clearing the status "15" in the | '

stored data in the auxiliary system. In the event that the alarm time is displayed in the electronic Uhi |

the shift register is free for the alarm time. d. H. the hour digit is "0". In this case the |

The one-minute digit and the ten-minute digit are deleted by a signal which corresponds to the binary code "1.1.1.1", whereby this signal is fed back to the shift register of the additional system. Then this spc / iclic signal is fed to the timing register of the electronic clock, and therefore the ten-minute digit is transmitted to the hour digit through the gate 68 of the clock register 32 of the electronic clock in such a way that the hour digit is the alarm /.eit changes from "0" to "1" The output signal UOHHR from gate 1411 is used to delete the special codes in the ten-minute digits for the "unoccupied" data in the auxiliary system. This is done by gate 1404 in response to the inverted signal ERDT provided by marker setting circuit 1452 in response to the output signal QOHER.

FIG. 29 illustrates an exemplary embodiment of a detailed circuit of the clock pulse generator 1408. According to the illustration, the signal CONTΦ. which is supplied by the manual shift circuit 1420, fed to the input of the clock pulse generator 1408. This signal is fed to a latch circuit and latched at the time of Τ% Φ \ so that an output signal CONTΦ. which is delayed by 3'Λ bit and is synchronized with the clock pulse Φ, is generated. The signal CONTΦ is fed to an AND gate, which is also fed with the clock pulse Φ2 , so that a clock pulse Φ * _{2 is} generated. The signal CONTΦ is also fed to a latch circuit and is latched therein by the clock pulse Φ2 to be delayed by half a bit. Thus, a clock pulse CONTΦ 'is generated, which is synchronized with the Taklimpuls Φι. and it is fed to an AND gate /. which generates a clock pulse Φ ' in response to the clock pulse Φ . The clock pulses Φ \ and Φ'2 are fed to the shift register 1490 to drive it.

The I i g. 30 illustrates an embodiment of an electrical Dctailschallung for the Datendcmoduliilionsschaliung 1409. The Datenmoduierungsschallung 1409 has an even number! of Invcrtern. which serve to shape the waveform of the input data accordingly, so that a signal Di \ 1 is supplied, which is fed to the various components of the additional system, for example the gate 1407, the timing pulse generator 1454 and the frequency setting circuit 1484. The demodulation circuit. The treatment 1409 is constructed in such a way that it determines a state in which the waking day digit is flashing and a signal Qi 1 is generated, which is connected to an AND gate. This AND gate generates data D / v 2 in the normal "state only when the current time and the weekday digit are flashing. This output signal /> /% ■ is fed to the date gate 1482 / ug. So that the date gate for automatic setting is not disadvantageous The data demodulating circuit 1409 also generates an output signal D / vt by clearing D \ nT _: to DmT _{8 of} the output D / v, since the signals corresponding to the timing control signals DioT> to DioT « b / w. data is the data of the alarm time which is related to the current time, the above data is deleted when the stored alarm time data is compared with the current time data, and a correct current time format is reproduced for this purpose the output D / v * connected to the comparison circuits 1425 and 1426.

FIG. 31 shows an example of a detailed electrical circuit for the composite digit pulse regeneration circuit 1430. This circuit 1430 has input terminals U ₁ \ and Uc 2. to which the Taklimpulscn Φι «\ and Φι« 2 are applied in each case. According to FIG. 9, the clock pulse Φικ \ is synchronized with the clock pulse T \. The clock pulse Φαν 2 is delayed compared to the clock pulse Φι «\ , and it has an inverted waveform. Thus, the Taklimpulse Φ _χ and Φ, ι , which correspond to the clock pulses! #, And b5 Φ \ χ , through the logical product of the clock pulses Φι « ι and Φι« ι and the logical product of the inverted clock pulses Φιιι ι and Φικ ι- to this end, the composite pulse digits Regcncricrschaltung 1430 sixteen cascaded latch circuits. The digit pulse

Dn is written into a first latch in response to the clock pulse Φ / and an output of the first latch is written into a second latch as a data input in response to the clock pulse Φ _Λ . Thus, an output pulse Q _{1 is} generated which has a pulse width which corresponds to the two digits. The signal Qh, which is regenerated from the continuous digit pulse O, ι and the continuous clock pulses Φικ ι and Φι / c ι , is a continuous signal which is generated by the intermittent modulation of the output signals from the electronic watch is not adversely affected.

The F i g. 32 shows an example of a detailed circuit for ie timing pulse regeneration circuit 1431. This circuit is supplied with the output signal Φ , which is the logical sum of the clock pulses Φ \ and Φ7 ,

ίο and is used to regenerate the timing pulses Tu and Th. If the clock pulses Φ \ and Φι are generated intermittently, the output signals of the interlocks are influenced by the intermittently modulated clock pulses and therefore the timing pulses Tj, T> and T ₄ are converted into intermittent signals that are synchronous with the clock pulses Φ; be built up and dismantled. The timing pulse 7 * 12 is the logical sum of the timing pulses T ₁ + / 2. and the timing pulse T24 is the logical sum |

of the timing pulses T ₂ + Ti. If there is a gap between the downward movement of the timing pulse- "

ses Tj and the upward control of the timing pulse Ti is present, the timing pulse Ti.? a noise signal which adversely affects the auxiliary system. To overcome this problem, the OR gate is additionally supplied with a pulse which arises in response to the clock pulse Φ \ when the timing pulse Ti is at level "H", and which is reduced when the timing pulse T2 is at the Level "H" is so that a noise-free signal T12 is regenerated. The timing pulse / 24 is regenerated in the same way. The composite timing pulses T12 and T24 are advantageous because the number of circuit connections is reduced.

The F i g. 33 shows an embodiment of a detailed electrical circuit for the current time display sampling circuit 1429. The digit signal Dp. which represents the display data also indicates the display of the current time. if D..n = Di ₆ , however, it indicates the display of the date. when D _n = D _M and it indicates the display of the alarm time when Dp = Dm. Thus, the current time display sampling circuit 1429 is applied with the signal Dp as a lock input, which is locked under the timing of ΑΛ, thereby sampling the status of the display of the current time. |

35 shows an example of a detailed electrical circuit for ώ; Alarm line scanning circuit 1427. f _t

According to the above, the display status of the alarm time in the electronic watch is sampled under the timing of D \ by the latch circuit which takes Dp as an input. When the alarm time is displayed, it means that the alarm time has been set. The fact that under these conditions it is imperative to maintain the synchronous relationship between the electronic watch and the additional system, the signals are thereby transmitted in a highly reliable manner in one direction and in the other. For this purpose, the status of the display is sampled by the timing of (pzD \ s, TtfP \ , and an output signal is generated by a first latch circuit. This output signal is fed to a second latch circuit and under the timing g> \ D \ TtfI> \ is scanned, so that an output signal Q ,,] at \ is supplied. This output signal v. ird is fed to a third latch circuit and read out under the timing of ψ \ Ο \ Τό, Φ \ , so that an output signal Q _q i <\ n is generated. the output signals Q _q i * T \ and Q ,, in 2 to an aND gate to be supplied by which an output signal Q \ "is .rzeugt to scan the status of the alarm time. Du-Ausgangssignalc Q ,, i \, 1 and Q, _i i \ t2 are fed to the shift register stop circuit 1426 to indicate the unoccupied shift registers during the setting of the alarm time in a manner which will be explained in detail below Starting si gnals Q ,, im ι and the inverted output signal Q, im 1 are synchronized with the pulse q> \ and held at level "H", and / was for half a second, which indicates that the alarm time has been set.

Fig. 3b shows an example of a detailed electrical circuit for D'C Impiilsgcncratorschalliing 14Sl. which is designed such that the pulse signals W * /, W ,, /. W ₁ ,,, and Ww, are generated. The Inipulssign.i
Ie Wki and W ₁ , / own sections of the current Zcitdatcn and Dalumsdaieii in the output data of the electronic clock.

The signals W _K , and W _n , are determined by a logic summing gate according to the following equations cr / eugl:

Q ₇ + φ, = D ₇ + Dr χ + Dq + Dm = Wi, j
Q 12 H- Q _n = AJ ₁ 2 + Du + D ₁₄ = W _n ,

The pulse generator circuit 1451 also generates timing signals W-tro and Ww 1 · The timing signal Wnro is used to open a gate / u to supply signals from the auxiliary system to the electronic watch, and the timer signal Wa 1 1 is used used to open a gate in order to feed the output data γυη of the electronic clock to the additional system. These timing signals are required to be intermittently modulated when the clock pulses c Φ \ and Φ2 and the Zeilstcuerimpulse Ti to T «are modulated intermittently. Similarly, the Zeitstcucrsignalc W, \ ro and W. \, ι are required to be continuously present when the clock pulsesc Φ \ and Φ2 are continuous. For this purpose, the pulse generator 1451 has a clip-flop which generates an intermittent signal which is controlled by the timing of

ii ^r i Q \: 'l \> is established and is dismantled under the time control of Q \. This intermittent signal is (! Altern / itiu'führl. Through which two intermittent signals Ww <> and Ww 1 in response to the signals Q ₁ iiiul f,) | 1 sometimes CiVeUpI, which each have reduced pulse widths. The / eilsteuersigiial Ww 0 builds up in response to the Aufwiirissteuening of the numerical imptile D < and is in response to the

Downward control of the digit pulse D \ reduced. The time control signal W \ i ι builds up in response to the upward control of the digit pulse D \ ·, and is reduced in response to the downward control of the digit pulse Di.

The Fig.41 shows a preferred embodiment of an electronic detail circuit for the output data control circuit 1402, a signal SB soft generated which allows the transmission of data from the ^r> adjunct to the input terminal Din of the electronic clock in synchronism yj to the pulse . The data output control circuit 1402 has a gate which scans the normal state, ie 0.14 7 2 = "L" and the state in which the shift register is not stopped. ie Qstp = 0, and it generates a signal SB I ₁ which is directed so that the data from the output SRG- \ 2 \ -out of the shift register ring 1490 is delayed by one digit compared to the data at the output SRG-lii-out of the to input terminal D _t \ of the standard timing system at the times of D | ₄ to Di are supplied one digit faster than the output data of the alarm time in the standard timing system. The data output control circuit 1402 also has a gate which generates a signal SB 2 in response to a signal MS2 which is so directed. that the new data of the output SRG-Ui are supplied to the standard timing system, namely at the times from Di ₄ to Di when the manual slide switch is operated, and to supply the new data, which are stored in the additional system, to the standard timing system. The data output control circuit also has a gate which generates a signal SB 3 if SB 1 = "H" or if Sß2 = "H". The signal SB3 is applied to the DCL terminal of the standard timing system in order to resolve the alarm time data stored therein.

40 shows a preferred embodiment of an electrical detail circuit for a data input control circuit 1403 which is constructed in this way. that it generates a signal SA. The data from the standard timing system is passed to the auxiliary system via gates 1407 when SA = "H" (see Figure 14B). The signal SA is generated by a gate in response to the signal W \ j , that is, at the times from Di- to Ö2 of the alarm time data supplied by the standard timing system when half a second has passed. after the alarm time is set, ie

QA = (), ΜΠ · Ο _ν ) ΛΙ 2 = "H".

in response to the pulse signal φι. This signal SA is applied to 1407 which passes the data other than the data represented by Di (Ti + Tt) , that is, the data including the date mark bit for the alarm, the PM mark bit and the digits of hours, tens of minutes and one-minutes. However, when SA = "L", the shift register ring 1490 is closed to form a ring circuit in which the stored data is shifted.

The F i g. 34 shows a preferred embodiment of a detailed electrical circuit for the pulse generator 1428 which is constructed to generate a signal.

The standard timing system and the additional system are synchronized with each other by the signal φι, which has a pulse width that is equal to that of a memory cycle, and which is synchronized with the downward ιε-tion of the 2 Hz signal of the timing register of the standard timing device. The signal Din ι is fed to a first locking circuit as an input signal which is _{read out at the time of D 4} T ₄ ^ i, so that a 2 Hz signal is derived in response to the signal 1> αΤαΦ \. This 2 Hz signal is fed to a second latch circuit and read out at the time DtT ₂ ¹ Pi. The inverted output signal O ^from the second latch circuit and its input signal are fed to a Gauer which generates a signal c / ί which is synchronized with the downward control of the 2 Hz signal. In this exemplary embodiment, the digit pulse D _{4 is sent to} the gate as a blocking signal! is supplied, and thus the signal η 1 is built up in response to the upward control of the digit pulse Di and decayed in response to the downward control of the digit pulse D ₁ . Similarly, the signal D / v 1 is fed to a third latch circuit as the F. input signal and is read out at the time Ο * Τ% Φ \ , so that a 1 Hz signal is derived A second gate is supplied, which generates a signal ψ2 of 1 Hz when the 1 Hz signal is at level "L", ie within 0 to 0.5 seconds at the current time. The 1 Hz signal is also fed to a fourth gate which is a Signa! q> \ generated when the 1 Hz signal is at level "H", ie within 0.5 to 1 see. The signal φι is fed to the fourth latching circuit and read out at the time OjTg ^ i, so that a signal φα is delayed by one Spe jhsr cycle compared to the signal φ-i . This Signa ¹ φ * is used to sample the unoccupied state of the next shift register. Referring to Fig. 15C, the signal φ \ is a 2 Hz signal which takes a position in Phcse, the signal φ \ being unaffected by the modulated data output signal which is displayed by the standard measuring system and which has a position after changing in occupies the seconds of time. It is therefore advisable to read out the output data from the standard timing system synchronously with the signal φι in order to read out the corrected data which have not suffered from the display modulation. It should be noted that if a common time multiple for a data cycle in the shift register ring of the standard timing system has to be chosen to be 0.5 seconds, the relationship between relative phases of the shift registers bo of the standard timing system and the additional system with respect to the pulse φι is kept constant weii.

In FIG. 44 shows a preferred embodiment of an electrical detail circuit for the shift register slope circuit 1426, which is constructed in such a way that it generates a signal Qs γρ which is used to perform the shifting operation of the shift register ring. To stop in 1490. The shift operation of the shift register ring 1490 is halted under the following conditions: b5

u. If the hour digit of the alarm time data is zero, i.e. H. if

OHAT ■ D, Τ _Λ Φ, = »Η«,
during clo: r time period of 0.5 sec if
· CVi <u 2 = »Η«,

ie during the line period in which the unoccupied shift register is automatically indexed, specifically just after the alarm time has been displayed and
b. when the alarm time data coincides with the current time, ie when

D, o7 ~ ₈ 0 ₂ · D ₁ TAT = "H".

in the normal state
(QvW 2 ~ "l.").

d. h .. when the current time is displayed.

The shift operation of the shift register ring 1490 is permitted by the signal Q ,, i. \ T2 when 0.5 seconds has elapsed after the alarm time was displayed, that is, when Q ^. \ Tz = "H". When the alarm time data coincides with the current time, the shift operation of the shift register ring 1490 is stopped in the following W.jise. When the alarm time coincides with the current time provided that the normal current time is displayed, this coincidence therebetween is determined at the time of ΰιοΤκΦ: and the alarm time data which coincides with the current time is determined by the auxiliary system as a standard time measurement system supplied from you to tue. At the same time, the alarm time data is passed through the shift register of four bits and cleared by the auxiliary system at the times from Du to D ₂ , and thereafter the clock pulses Φ * \ and Φ * 2 are prevented from being fed to the shift register ring circuit 1490, see above that the moving operation thereof is stopped. The verse>. The operation of the shift register ring circuit 1490 is started again when 60 seconds have elapsed after the alarm time with the current time by the Signa! Q56O S coincides.

The supply of clock pulses Φ * 1 and * Φ ₂ is stopped at the times from D3 to _D6 under normal conditions and at the times D) to you on the condition that the alarm time is displayed. The signal Qsrp is generated by the latch circuit in response to the signal DjTe ^ i.

F1g 4.i illustrates a preferred embodiment of an electrical detail circuit for the date alarm data coincidence sampling circuit 1424, which is constructed in such a way that it generates a signal ERDT. The data output SrtG-441 and the Signa! Dm s are compared by three digits, that is, you to you. and at the same time, the month and date data of the alarm time and the link mark of the advance alarm time are cleared by the four digits, that is, D15 to D ₂ . The deviation between the month and date data of the alarm time and the month and date data of the current time is _{sampled for the second from Di 2} to Du , that is, if Wdt = T. and for the same line: the level »H «Of the data at the data bit, ie the bit 2 ^{1 of} the marking digit of the month and date bits of the alarm time scanned by using the data from the output SRG 111 -out. Finally, when one of the signals to the level "H" passes, the one flip-flop is reset, which "has been set at the time of you the current time display. The signal ERDT is the logical product of the output of the flip-flop and the signal ν / _λΤΧ , ά. H. of the timing signals D | ₅ to D ₂ , and it is used to clear the month and date data of the alarm time, and the data of the connection mark of the alarm time are cleared through the gate 1404

The F i g. 42 shows a preferred embodiment! an electrical detail circuit for the alarm clock coincidence sampling circuit. which is so constructed that it generates a signal with which the alarm time data is deleted when the alarm time data coincides with the current time data. The instantaneous time data which are fed to the input Dim 3 and the data from the output SRGSii-out of the shift register R-ns circuit 1490 are fed to a comparison device such as an exclusive OR gate and are compared with one another _{by this at times D 6 to Dg, ie} W _K r = "H". If at this time the alarm time is not set, ie if Qa = "L", a flip-flop is nicked by the output of the exclusive OR gate which serves as a sampling device for the non-coincidence between the alarm time data and the current time data. If on the other hand the alarm time data coincide with the current time data, the output of the flip-flop will be at the "H" level during a time period represented by D, ₀ Ti to D _4. The corresponding output signal is fed to an AND gate which is also supplied as an input signal Wati , so that an output signal QejMr is generated.

This output signal is fed to the marker setting circuit 1452, which consequently generates an output signal ALI ₁ which is fed to the gate 1406 of the shift register ring circuit 1490, thereby clearing the alarm time data. The output DETAT of the flip-flop is supplied to the shift register L-r stop circuit 1426.

uic F 1 g si / eigi a preferred embodiment example ¹ . an electrical detail connection for manual |

»I Shift-St: haltir>] i 1420. The manual shift circuit 1420 works in such a way that it generates an output signal * ΓΟΝΤΦ which is used to control the supply of the next clock pulses Φ * \ and Φ ' . ·> to the sliding ring cleavage f register 1490 is used, whereby, when the normal present time is displayed, the A! a ^r mzeitdate-n. which are to be fed to the standard timing system in each storage cycle, correct

gicrl, while when the alarm time is displayed, the alarm time data that has been displayed is renewed in response to alarm / time data which control a signal brought about by the operation of the manual operator will. In the normal display country, the relation Q, \ = "L" is used. When Q. \ = "L", the signal Q- \ ■ Q. \ ■ Q: which is established in response to the upward control of the digit pulse Db and which is decayed in response to the downward control of the digit pulse D \ , is passed through a gate in the form of the output signals CONTΦ hind-jych, which are fed to the clock control circuit 1408, whereby the clock pulses Φ ⁺ \ and Φ * 2, which correspond to the four digits from Ds to Di , are not generated. Provided that the alarm line is displayed, ie if Q, \ = "H", the signals Dj to De are blocked because MS] 2 - "L", in the normal display state. Uiiddas signal W.wo. which is built up in response to the upward control of the digit pulse Dm and released in response to the downward control of the digit pulse Di is passed through a gate of the manual shift circuit 1420 in the form of an output signal CONTΦ . The shift register ring circuit 1490 is supplied with the clock pulses Φ '\ and Φ * 2 at times Di5 to D2, and / was in response to the signal CONT0 which is established in response to the upward control of the digit pulse Du and in response to the downward control of the digit pulse Di is reduced, so that when the alarm time is displayed, the data for four digits are shifted, ie one data set in one storage cycle. The manual shift circuit 1420 has an input MSIN, which for this purpose, the Aiufiii / t'iUiiiieii u / vt. to move or scan the aim ιΊΊ / .ciiddiuiii which is supplied to the external control element such as a manual slide switch 266, which is shown in FIG. 18 and which is normally released. In the normal on / eigestatus the input terminal MSIN is kept at the level "L." and / was by the reset signal ϋιΤ ^ Φχ. When the manual slide switch 266 is pressed, the finger clamp MSIN is at an "H" level. When the logic level at the input terminal MSIN is held at the "H" level. and over a time interval of more than one second, if Q _g i \ T2 = "H", provided that the alarm time is displayed, then the level "H" at the input terminal MSIN under the timing of g ^ D \ T ^ P \ read out in a first locking circuit , whereby a gate 1422 generates a signal MSIN. The output of the first latch circuit is read out by a second latch circuit at the time of ςηΟ- ^ ΆΦχ so that an output signal delayed by about one second is generated. The output signals from the first and second latch circuits are supplied to an AND gate 1421, which is also supplied with the input signal to the first latch circuit and the signal qy> , so that one of the output signals MS \ 1 is generated.

The input terminal MSIN is brought to a low level in order to manually sample the alarm time data. The flip-flop for storing the manually set input is normally reset in response to the signal, which is the logical product of the signal gn and the signal ΰ ^ Τ ^ Φχ . If the input terminal MSIN is set to a high level, if ψ \ - "L", the flip-flop is set and the Signa! yjDsTsCfy re ^r rückgesteüt. The logical product of the equalizing signal de * · flip-flops in its set state and a signal cps is a signal which is obtained by sampling the high level of the input terminals MSIN in synchronism with the signal q> \ . Under a condition in which the outputs of the first and the second latch circuit are at a high level, the input MSIN is set to a high level! fed to gate 1422 as a manual scan input.

The output signal MS J! is delayed by a third latch to the line from D \ Ttf> x by one memory cycle, and a signal MS f 2 is generated. The MS \ 2 signal is used to feed new data from the auxiliary system to the standard timing system in the next memory cycle after the manual shift operation has just been carried out. In this case, since there is a need to supply clock pulses Φ * 1 and Φ * 2 to the shift register ring circuit 1490 for 16 bits between Dia to D ₁ , the signal CONTΦ enables the pulses to be supplied which have a width corresponding to 16 bits , and only if MS f 2 = "H". The signal MS] 2 is supplied to a fourth latch circuit, by which the signal MS] 2 is delayed by one memory cycle at the time of D3T1 Φ \ , so that a signal MS \ 3 is generated. If MSj 3 = "H", the signal W _A ra which is built up in response to the upward control of the digit pulse Du and decayed in response to the upward control of the digit pulse D \ , and the signal which is generated in response to the upward control of the digit pulse Ao and released in response to the downward control of the digit pulse Dn are added to each other, and thus the signal CONT Φ is generated. The CONT Φ signal is used as a control signal to supply the clock pulses to the shift register ring circuit 1490, thereby causing the data therein to be shifted. Due to the supply of these clock pulses, the data in the shift register ring circuit in the additional system is advanced by one data record, which corresponds to 16 bits, and that further than the data in the standard timing system with regard to the pulse gti. The signal MS j 1 is the data mark "

kierungs setting circuit 1452 is supplied, in which a marker set counter reset to zero \

so that the data newly stored in the shift register ring circuit by the manual shift operation is not adversely affected. The manual shift circuit 1420 is supplied with the signal Qstop , which is synchronized with the signal Ο ^ ΤζΦχ from the shift register stop circuit 1426, soft the clock pulse sleuersignai synchronous with the signal D ₃ T ₈ !?! In the case of the manual shift circuit 1420 constructed in this way, the shift register ring circuit 1490 is not supplied with the clock pulses which correspond to the digits Dz to D &, ie 16 bits in the normal state in which the current time is displayed, so that the shift mode of the data in the auxiliary system is shifted by 16 bits, which corresponds to one record in each storage cycle, and other alarm data is supplied from the auxiliary system to the standard timing system in each storage cycle at the timing from Du to D \ . Under the condition that the alarm time is displayed, however, the data in the additional sys-

stem moved forward by 16 bits, which corresponds to the one data record, and more specifically than the data in the standard timing system in each memory cycle. At this time the data entered into the Slandard timing system is fed back to the auxiliary system twice per second in synchronism with the signal (P ₃ (= "H"). Because the signal φζ is determined in such a way that it has a period of 1/2 sec, which is a common multiple of the time, ie 1/256 sec, which is required for one cycle of the data in the shift register ring circuit of the standard timing system, as well as the time which is required for one cycle of the data Accordingly, required in the shift register ring circuit in the auxiliary system, so that it is specified, the relative relationship between the data in the Standardzeitmeßsystem and the data in the auxiliary system. was then when the level of the input terminal MSIN from "L" to "H" changed will or if the

ίο input terminal MSIN is still held at level "H" for more than a second, the data in the shift register ring circuit of the additional system is shifted by 16 bits, which corresponds to one more data record in the shift register ring circuit of the standard timing system, so that a certain data record is renewed and displayed.

39 shows a preferred exemplary embodiment of an electrical detailed circuit for the marker setting circuit 1452. According to the illustration, the marker setting circuit 1452 has two flip-flops, by means of which a marker setting counter is formed. As mentioned above, the alarm time data is renewed and displayed by the manual shift operation. When the UDH exit key is depressed three times , the UDH key line generates the signals ALIi, ALD], ALh, and ALDi in a manner as shown in Table IV. to display the month and date alarm mark and the connection mark which inhibits the sampling of the coincidence of the alarm time data and the current time data. The marker setting counter is reset in response to at least one of the signals MS] 1, which corresponds to the state in which the alarm time is not set and the level "L" of the terminal Y. If Y = "L", the marker is Setting counter forcibly reset to zero making it impossible to set the month and the data alarm. _{Assume that the counts 0, 1, 2} and 3 of the marker setting counter are Nq, N ,, N 2 and Nj , and then the following equations hold:

= N ₁

ALh- = (N ₁ + N ₂ + / V ₃ ) * PzD ^ n + <? I6 * QOHER

ALD, = AZ ₃ · qnD ₂ T ₂ ALD ₂ = (N, + N ₂ + Nz) ■ Jp ₃ D ₂ T ₂₄ + QERAT.

46 shows a preferred embodiment of an electrical detailed circuit of the date gate 1482 . The date gate 1482 has a counter 1467 which is used to count to 8 (0 to 7). When the count 7 is determined by counter 1467 , a trigger input pulse is applied to a second counter. When the count 8 is detected by the first counter 1467 , the first counter 1467 is set to "0" and the second counter is set to "1 ". The setting input to the crs ^y en counter 1467 is blocked. If DGO = "H" (ie ~ DÜ0 = "L"), the first counter 1467 counts the number 8, and in this state the date gate is opened. The first counter 1467 is reset by one of the following input signals, namely

P \ (P \ ~ Q ~ c $>] = "H"),

which will be explained in detail below, and a calculation start signal from a gate 1462 (Fig. 48), the second counter being reset by the input signal Pi. As shown, the date gate circuit 1467 also includes a gate 1463 which determines the downward control of the signal which the

so indicates PM mark data, and the sampled down control signal is input to the first counter fed

The F i g. 48 illustrates a preferred embodiment of a detailed electrical circuit for the computing circuit 1481. The computing circuit 1481 has a first counter 1465 and a second counter 1466 , both of which count up to 60 (0 to 59). The arithmetic circuit 1481 also has first and second flip- flops 147ί and 1472 which are connected to the first counter 1465 and the second counter 1466 , respectively. The count above 60 is stored in flip-flops 1471 and 1472 , and the outputs of flip-flops 1471 and 1472 are fed to the reset inputs of counters 1465 and 1466, respectively, which are reset to "0". The computing circuit 1481 has an input terminal X which is normally brought to an "L" level. When X - "H", the output signals of the flip-flops 1471 and 1472 are fed to the first counter 1465 and the second counter 1466, respectively, which are consequently reset to "0". The arithmetic circuit 1481 also has a third flip-flop 1473 which is set by the inverted signal DGO from the date gate circuit 1482 and the arithmetic control signal P ₁ supplied by the input analyzing circuit 1483 so that counting starts. The arithmetic circuit also includes a gate 1461 on, which signals "^ DjTs ^ and q> \ zugefühu be, in such a way that a 1-Hz signal is generated which is synchronized with the timing Τ% Φχ A gate 1462 is supplied with the signals Τ% Φ \ and Qc and generates a 64 Hz signal which is fed to the first counter 1465 and the second counter 1466 . This signal is also fed to a gate which generates a reset signal which is to be fed to the reset input of the counter 1467 of the date gate circuit 1482

When the switch is depressed to start the arithmetic circuit 1481 when DCO = "H", an input signal Pi is generated when one minute has passed after the switch was depressed. Since actuation of the switch automatically zeros the seconds display in the standard timing system, the first counter 1465 of the arithmetic circuit 1481 is reset and the count in the seconds counter of the standard timing system coincides with the count in the counter 1465 of the arithmetic circuit 1481. In this case, the count in each of the counters is "0", and thus the date gate circuit 1467 is reset. If the next input signal Pi is generated a week later, when DCO = "H", the third flip-flop 1473 is the Arithmetic circuit 1481 is set and generates a signal Qo ie Qc = "H" and consequently the counts or contents in the first counter 1465 and the second counter 1466 are shifted at a higher speed in response to the Τ »Φ \ , so that the count or the content in the first counter 1465 goes to "0". At this time, the third flip-flop 1473 is reset to "0", and the second counter 1466 stores therein the calculated count therein at Qf = "L". The reset signal is also supplied to the gate date counter 1467 of the Daturns gate circuit 1482, so that the inverted output signal DCO becomes higher. Assume Ks that the count of the second counter 1466 calculated in response to the first timing signal P \ is Ki and that the count G of the first counter 1465 is zero after the first timing input P> is applied. It is further assumed that the count of the first counter 1465. which was calculated in response to the second time input signal Pi is G, so that there is a situation that the electronic watch in the illustrated embodiment is advanced by Ci seconds within one week . Now, when the second timing input signal Λ is applied to the third flip-flop 1473, the output signal Qr goes high, and therefore a number of (60 -G) pulses are applied to the second counter 1466, which is consequently based on the number (K \ + 60 — G) counts. Since the second counter 1466 is constructed in this way. that an overflow occurs when the calculated result exceeds the count of 60, the resulting count in the second counter is equal to (K \ - G) - If the circuit arrangement is so constructed that it generates a correction signal, about the time in a week advance by one second when the count of the second counter 1466 is incremented by one, the count stored in the second counter 1466 is decremented by G seconds, thereby accurately setting a gain loss.

In FIG. 47, a preferred embodiment of the electrical circuit for the input analysis sound 1483 is shown. The output analyzer circuit 1483 includes a gate which generates an output signal in response to the signals UDI and QKT. This output signal is fed to an inverter 1464 which generates an output signal UDII *. This initial signa! is fed as an input signal for automatically resetting the seconds display to zero in the current time display to a first locking circuit and locked _{by a composite digit signal Q b.} The inverted output signal of the first interlocking sound and the output signal UDII * are fed to a gate through which a differential pulse UDlI is synchronized with the upward control of the output signal UDII * . The Signs! L ¹ D // is fed to a return input of a flip flop. The output of the first latch circuit is also fed to a second latch circuit by which the signal of the four second bite is sampled in the standard timing system in response to the signal ^ DsTsJ ⁵ I · Din 2 and is latched for reading the output signal from the first latch circuit. It is assumed that the state UDII - "H" is maintained for a time interval beyond 4 seconds. The second interlocking circuit scans the state that the 4-second bits are at a high level, while the input signal UDII ⁺ , which is fed to the first interlocking circuit, is held at a high level. As a result, the inverted output signal Q goes from a high level to a low level, so that the flip-flop is set and consequently produces an output signal of a high level. In other words, if the status UDII * = "H" is continued for a time interval longer than 4 seconds, the gain loss setting signal is stored as an input signal in the flip-flop. When the signal UDII * goes low after the time interval has exceeded 4 see, the signal DIN 2 is used as a data signal in a third latch circuit in response to the signal (l> \ D _b T * <I> \ and an output signal which corresponds to the bits of 40 see in the current time is latched. Thereafter, the change in minutes of the current time, which is represented by the downward control of the signal of 40 see, is sampled by a fourth latch circuit the change in minutes is referred to as signal 60S \ . 605 \ ■ UDII * denotes a signal which indicates that one minute has just passed after the signal i / D // for the time interval of more than 4 see was held high in the second mode of reset to 0. The control signal Pi is the logical product of the signal 60 5 | ■ ^{UDII +} and the output signal QsD ₆ T ₂ A of the flip-flop, and it becomes used as a control signal to start the calculation of the adjustment gain loss. The output signal, which is the logical product of the signals 60Sf- UDII ⁺ and Q ₉ , is fed to the reset input of the trigger-set flip-flop. The output of the trigger-set flip-flop and the output signal 60 51 · UDII ⁺ are fed to a gate which generates an output signal which is fed to a further gate to which a signal Qg is also fed. This gate generates an output signal DGR which is fed to the reset input of the flip-flop of the date gate circuit 1482, so that the date gate circuit is reset to its initial state, that is to say it is brought into the status of the first day.

When the switch for resetting the seconds display to Nu !! is not printed for more than 4 seconds, the The trigger-set flip-flop of the input analyzer circuit 1483 is not triggered, and therefore a signal is which controls the setting of the gain loss is not generated. As stated above, the output signal Pi is not generated within one minute after the switch is pressed, and accordingly, it is possible to stop the supply of the gain loss adjusting signal by adjusting the signal

I * - to swipe to a high level within a minute. The F i g. 49 shows a preferred embodiment of a frequency adjustment pulse generation circuit. This circuit has already been discussed above and therefore does not need to be explained in detail.

For this purpose 49 sheets of drawings

t 48

Claims (8)

Patent claims: 1. Electronic watch, comprising: a frequency standard delivering a relatively high-frequency signal, a frequency converter responsive to the high-frequency signals, which emits a relatively low-frequency time unit signal which is fed to a time measuring device for counting the current time, a memory for additional data, a display unit for Display of the current time and the additional data as well as an external control element which, when actuated, generates a signal for influencing the additional data, characterized in that an additional register device (1490) stores several additional data groups and that a device (1420) upon receipt of an input signal ίο generates an index signal from the external control element (266) which controls the additional register device (1490) in such a way that one additional data group after the other is transferred to the memory (58) for successive display. 2. Clock according to claim 1, characterized in that the device (1420 ) generates a single index sigm-1 (MS ©) for each input signal from the external control element (266) 3. Watch according to claim 1 or 2, characterized in that said means (1420) is generated for generating the index signal upon receipt of an input signal from the external control element (266) in a predetermined operation mode, a plurality of index signals (MS ©, MS ®), which the correspond to additional data groups. 4. Clock according to one of the preceding claims, characterized in that depending on the Auftreieo an index signal a device (1402 ) generates output command signals (SB O, SB ©, SB ©) which are sent to an output control gate (l40l) for outputting the additional data groups the additional register device (1490) . 5. Clock according to one of the preceding claims, characterized in that the additional data groups are a plurality of alarm time data and that an external control element (264) is provided via which the Display unit (22) can be switched in an alarm time display mode. 6. Clock according to one of the preceding claims, characterized in that the additional register device (1490) can be placed in an alarm time indexing mode in which all alarm times are transmitted from the additional register device (1490) to the memory (58) for additional data, whereby the content of the memory (58) can be corrected and the corrected data can be returned to the corresponding register of the additional register device (1490) . 7. Uhi according to claim 2, characterized in that a device (1402) for generating an output ^{command signal from '-i} ingig is provided from a single index signal via which an additional data group for an update in the memory ( 1490) from the additional register device ( 58) is transferable 8. Clock according to one of the preceding claims, characterized in that one or more index signals are generated by the device (1420) depending on the duration of the actuation of the external control element (266).