DE2548903A1 - Semiconductor memory element - of long stability with differential insulating layers in field effect structure (NL040576) - Google Patents

Abstract

A semiconductor memory element with long-term stable storage characteristics has over the source region an second insulating layer (SiO2) of greater effective thickness than the first insulating layer which it adjoins. A third insulating layer over the drain region also adjoins the first and has a greater thickness than the first. A metal film over the first insulating layer acts as the charge storage element. A gate is arranged above it; electrodes are joined both to the source and to the drain. This results in a field-effect memory element which stores information over long periods. It requires small WRITE and CLEAR fields. Threshold voltages far apart from each other ensure an easy read-out. Very short channel lengths give fast access and high storage density.

Description

Long-term stable semiconductor memory and method for # its Production The invention relates to a long-term voltage-independent stable Semiconductor memory of the type mentioned in the preamble of claim 1 and a method for its production. In particular, the invention relates to a memory component on a semiconductor basis, in which information is optionally written and from which the stored information can optionally be deleted, with the stored Long-term information stored in the memory, even in the absence of external voltage stop.

Writable and erasable semiconductor memory components are for example from US-PS 3,500,142 and The Bell System Technical Journal, 46 (1967), 1288-1295. The known semiconductor structure is a field effect transistor (hereinafter FET) with isolated and electrically floating control area. This FET consists of a semiconductor substrate on which a thin, e.g. 5 nm thick, insulator coating to electrically isolate a metal electrode from the control area which is referred to as the "floating control electrode" in the context of this description is. The thin insulator layer therefore electrically insulates the floating control electrode compared to the semiconductor substrate. There is also a control insulator layer intended, the floating control electrode against the semiconductor substrate and the environment electrically isolated, these being both against those on the control insulator layer lying control electrode and is isolated from the surrounding areas. Of the FET also commonly includes a source area, a sink area, a source electrode and a Senkenele] #rode, which after that for MOS structures commonly used type are made.

When impressing sufficiently large positive or negative voltages A charge transfer between the semiconductor substrate takes place at the control electrode and the floating control electrode, which charges them negatively and positively, respectively will.

This state is retained even when there is no more voltage is on the control electrode. The applied charge state of the control electrode is maintained until a sufficiently high counter voltage is applied to the control electrode is placed. This charge conservation is achieved through as complete an insulation as possible of the electrode against the environment.

The induced on the surface of the semiconductor substrate in this way The amount of charge is different from the amount of charge induced in the channel area the impressing of the control voltage. This is because of these different functions the current flowing through the channel between source and sink is controlled.

The main difficulty with FET memory elements of this type lies in the fact that the imposed charge is not very stable. In addition, there are semiconductor components with memory functions that have the same characteristics, not technically feasible. This is due to the fact that the floating control electrode is on both the canal area as well as, separated by the thin insulator layer, is over part of the source area and the sink area.

The source area and the sink area are commonly used by diffusion doping or by doping with ion implantation in the semiconductor substrate Manufactured in this process cannot be avoided on the surface the source and the sink precipitates are enriched by dopants. In addition, the surfaces of the source and the sink have a high concentration of crystal defects on. This results in the on the surface of the source area and the sink area lying insulator layer has a higher density of impurities than the same layer having other surface areas of the semiconductor substrate. This leads to, that the insulation between the floating control electrode and the source and the sink is negatively affected. This in turn leads to premature drainage the information charge stored on the floating control electrode.

In view of this prior art, the task of the invention is to be found based on creating a semiconductor memory device that is also characterized by long-term guaranteed information storage, through small writing and erasing fields, for easier readability through widely spaced threshold voltages and with regard to fast access and high storage density through extraordinary short channel lengths. The invention is also intended to provide a method of manufacture create such storage elements.

To solve this problem, a memory of the type mentioned at the outset is used Art proposed, which in claim 1 mentioned features having.

The invention thus creates a long-term stable storage Semiconductor memory component which is on a semiconductor substrate of a first conductivity type is constructed.

In this substrate, the source and drain are of opposite conductivity type "second line type" incorporated.

The canal lies between the source and the sink. On the surface of the A first insulating layer is located on the semiconductor substrate in the channel region. A second Insulator layer lies on part of the exposed in the substrate surface Surface of the source area. Both insulator layers adjoin one another. the effective thickness of the second insulator layer is greater than that of the first insulator layer.

A third insulator layer lies on part of the substrate surface exposed surface of the sink area. This third insulating layer is also adjacent on one side of the first insulating layer. Also the effective thickness of the third insulator layer is greater than the effective thickness of the first insulator layer. The structure shows furthermore a charge storage element, which is formed from the semiconductor substrate by the first insulator layer can store migrated charges. At least at first Insulator layer and a control electrode is arranged over the charge storage element. The structure is completed by a source electrode and a drain electrode.

In the context of this description, ~ Effective Thickness "refers to a Layer thickness whose dielectric characteristics match the dielectric characteristics of an in as specified are the same as the SiO2 layer. The effective thickness teff a layer consisting of an oxide other than SiO2 is at least in good first approximation given by the following expression: Teff = (Tx / Ex) ESiO2 In this equation, Tx is the thickness of the oxide layer and Ex is the dielectric constant the oxide layer and ESiO2 the dielectric constant of the Si02 layer. If the Oxide layer is built up in several layers, in particular, for example, a double layer or is a triple layer, Teff = (Txl / Exl + Tx2 / Ex2 +, ....., + Txn / Exn) ESiO2 In the above equation, the additional indexing refers to the first, second, ...., i-th, n-th layer.

According to a development of the invention, the effective thickness is the first insulator layer preferably in the range from 1 to 10 nm, particularly preferably in the range from 1 to 5 nm.

The effective thicknesses of the second and third insulator layers are to choose at least so large that they prevent the charges from flowing out of the Prevent charge storage element. According to the invention, this is always the case if the effective thicknesses of both layers, i.e. the second and the third insulator layer, are greater than the effective thickness of the first insulator layer. After further training the invention is the difference in effective thicknesses between on the one hand the first and on the other hand the second or third insulator layer, preferably 0.5 nm, but particularly preferably at least 1 nm.

Each can be used as a charge storage element purpose known structure are used, preferably the floating control electrode described above with the memory function described above or one of the following structures serve: MIMOS (TheBell Systems Technical Journal, 46 (1967), 1288), FTMIS (IEEE International Devices Meeting, 24.2 (1972)), an interface between the various insulator layers in MNOS technology (RCA Review 30 (1969), 366) or MAOS (Elektrochemical Society 118 (1971), 1993-1999).

The semiconductor device of the invention is manufactured in such a way that that one is first at a certain distance from one another in the surface of the semiconductor substrate creates the source area and the sink area. This is also the The area between the two areas is defined as the channel area. On the surface An insulator layer is applied to the semiconductor substrate, with an insulator layer that arises over the source area and the sink area stronger than on the remaining surface areas of the semiconductor substrate is formed.

The insulator layer obtained in this way is etched in such a way that straight the thinner layer areas are completely etched away. In this procedure the surface area of the semiconductor substrate corresponding to the channel area is exposed. With this etching, the thicker areas over the source and the Depression reduced in thickness. Then it is applied to the surface prepared in this way Again an insulator layer is made so that it at least covers the channel area covered. This insulator layer is formed so that its effective thickness less than the effective thickness of the insulator layers on the source and drain is. This is followed by the charge storage element or the charge storage layer applied at least to the surface area of the control insulator layer. These charge-storing layer or layer structure will then after the Apply so far away that it touches the surface of the insulator layers on the Q ~ lle and the sink partially releases. The control insulator layer lying on the channel area however, remains completely covered by the charge-storing layer. By the uncovered areas of the insulator layers lying on the source and drain then the contact window for the source and sink is opened. Eventually be Electrically conductive layers serving as contacts and conductor tracks on the charge storage element at a location overlying the canal area and on the surfaces of the source and sink applied across the board, the individual conductor areas being electrical are isolated from each other.

The difference in the impurity concentrations is preferably at the Surface of the semiconductor substrate and on the surfaces of the source region and of the sink area relatively large. The higher the impurity concentration of the semiconductor material the thicker the insulating layer on the semiconductor substrate must also be At the same time, however, the difference between the layer thickness should also be formed the insulator layer on the semiconductor substrate or on the control area on the one hand and the insulator layers on the source area and the drain area on the other hand be as large as possible. A semiconductor substrate with an impurity concentration is therefore preferred of less than about 1 x 1019 cm 3 is used in the source area and drain area with an impurity concentration of greater than 1 x 1020 cm 3 in the surface areas are trained.

The insulating layers are preferably made by atmospheric water vapor oxidation carried out at an oxidation temperature of less than 900 ° C. Included an insulator layer is obtained overlying the source area and the drain area thicker than is formed on the other surface regions of the semiconductor substrate. Under these conditions there are particularly great differences between the two Maintain layer thicknesses.

In summary, taking into account the invention provides more preferred Training so a semiconductor memory device, which is characterized by a qualitative, storage characteristics that are particularly stable in quantitative and, in particular, in terms of time excels. The memory is preferably constructed on an n-Si substrate, in the source and drain formed as p-regions at a certain distance from one another are. Between these two areas, the remaining substrate area acts as a Canal area. A first SiO2 layer with a thickness is placed on the channel area of about 2.5 nm applied. A second SiO2 layer is made with a thickness of 100 nm is applied to the part of the surface of the source area that is adjacent to the first SiO2 layer is adjacent. A third SiO2 layer, which is also 190 nm thick, is applied to that area of the surface of the depression area that is also on the opposite side is adjacent to the first SiO2 layer. On the first SiO2 layer (the first insulator layer) the charge storage element is applied, which, according to a preferred embodiment of the invention, is a metal layer which is on the first SiO2 layer. A fourth layer is then placed on top of this metal layer Insulator layer and on this in turn the control electrode is applied. In the end source and sink are contacted. In this structure charges or information in the form of charges can be stored for practically any length of time.

The invention is illustrated in the following on the basis of exemplary embodiments Describe the connection with the drawings in more detail, They show: Fig. 1 shows an embodiment of the invention; Figures 2 to 8 different stages of the Production of the component shown in FIG. 1; 9 shows a further embodiment of the invention and FIG. 10 graphically depicts the source and drain oxide layer thickness as a function of the oxidation temperature.

In Fig. 1 is a cross section in a schematic representation shown first embodiment of the invention. On the surface of a p-Si substrate 1 are an n-source 2 with an impurity concentration of 5 × 1019 cm and a n-well 3 formed with an impurity concentration of also 5 x 1019 cm 3 Substrate has an electrical resistivity of 1 Ohm'cm. At this The substrate area located between the source 2 and the sink 3 acts as an arrangement as channel 4. A first insulating layer 5 made of SiO2 lies on the channel 4 in one Thickness of 2.5 nm.

A second insulating layer 6 made of SiQ2 with a thickness of 100 tun lies on the surface of the source 2 and is immediately adjacent to one side Insulator layer 5 on.

A third insulator layer 7, also made of SiO2, has a thickness of also 100 nm and lies on the surface of the depression 3. This insulator layer too adjoins directly on the side opposite the second insulator layer to the insulator layer 5. An electrically floating one Control electrode 8 made of polycrystalline silicon has a thickness of 75 nm and lies on both the first insulator layer 5 as well as on the adjacent edge areas of the second Insulator layer 6 and the third insulator layer 7.

A control insulator layer 9, which also consists of SiO2, rests on it the floating control electrode 8 and further areas of the second insulator layer 6 and the third insulator layer 7. A control electrode 10 made of aluminum is on the control insulator layer 9 is applied. A source electrode 11 and a drain electrode 12 make the electrical contact to the surface of the source 2 or the sink 3 here.

In the specific exemplary embodiment described above, the Threshold voltage at -1.2 V, this threshold voltage to a value of +2.0 V is shifted if a voltage of +15 is applied to the control electrode 10 for 1 ms V.

After disconnecting the control voltage and short-circuiting the control electrode 10 against the semiconductor substrate 1 is still a control voltage after 24 hours measured at +1.9 V.

A semiconductor memory device shows under the same conditions of the type described above, a value that corresponds exactly to the initial value the threshold voltage, in this case a value of -1.2 V.

If one applies 0.5 / us to the control electrode 10 of the previously described Storage element of the invention has a voltage of -30 V, the threshold voltage shifted from a previously impressed value of +2.0 V to a value of -8.0 V. The negative value of the threshold voltage remains even after the control voltage has been disconnected obtain.

If one assigns the logical value to the threshold voltage of +2.0 V. H and the threshold voltage of -8.0 V to the logical value L, then an extraordinary get reliable and fast working binary storage element.

In FIGS. 2 to 8, a is in various stages of manufacture Process for producing the structure shown in FIG. 1 is shown.

In the 1 ohm-cm-p-Si substrate 1 are in the appropriate places formed by diffusion, the source 2 and the sink 3, which between them Define channel 4. The concentration of impurities in the source and sink is -3 -1 x in20 cm. After the diffusion mask has been completely removed, the substrate surface becomes in the atmosphere for 100 min at about 900 C, preferably about 10 C below this temperature, oxidized with water vapor. The SiO 2 layer 13 thus formed is on the surface of the source area 2 and drain area 3 0.43 µm thick and on all others surface areas of the substrate 1 0.32 / µm thick (Fig. 2).

These differences in layer thickness are due to the fact that thermal oxidation is a function of the growth rate of the layer Surface impurity concentration is. The greater the surface impurity concentration is, the greater the rate of growth of the thermal oxidation Oxidation layer (Journal of the Electro-chemical Society, 112, 149).

The SiO2 layer is then treated with an etching liquid for 5.5 minutes Etched from 49 pointer aqueous HF and H20 in a ratio of 1:10. The thin areas of the Si02 layer, in particular the Ski02 lying on the channel 4 Layer, completely removed from the substrate surface while on source and Sink SiO2 layer areas with a thickness of about 100 mm remain. These Regions serve as second # insulator layer 6 and third insulator layer 7 (Fig. 3).

A first insulator layer 5 made of Si02 is with a thickness of about 2.5 nm is applied to the exposed surface of the semiconductor substrate 1. In addition one sets the surface of the structure to that of a source of a solidifying gelaisch from liquid oxygen and liquid nitrogen vaporize oxygen, the is carried along by nitrogen, and heats the structure for 15.5 minutes to 1000 OC. This method is described in detail in JA-OS 48-30379.

On the surface of the first insulator layer 5, the second insulator layer 6 and the third insulator layer 7 is then a 75 nm thick polycrystalline Silicon layer 14 produced. For this purpose, a gas mixture of nitrogen, SiH4 and Argon brought into contact with the structure at 600 ° C. for 10 minutes. The nitrogen will set to a flow rate of 30 1 / min. The argon stream containing 4% SiH4 is set to a flow rate of 0.2 l / min. The structure obtained is shown in fig.

The polycrystalline Si layer 14 is then etched so that the first insulator layer 5 completely covered and on edge areas of the second Insulator layer 6 and the third insulator layer 7 overlaps the surfaces however, these two insulator layers are otherwise exposed (FIG. 5). Through this One step is the electrically floating control electrode, which is also insulated from the environment 8 received.

On the exposed surface areas of the second insulator layer 6 and the third # insulator layer 7 and on the surface of the floating control electrode 8 will a SiO 2 coating 15 with a thickness of 75 nm in the previous one described manner applied by oxidation with steam for 20 min at about 900 ° C (Fig. 6).

Through this SiO2 layer 15 and the underlying SiO2 layers 6 and 7 are then, while maintaining the mechanical and electrical insulation of the floating control electrode 8 next to this window 16 and 17 on the surface the source 2 or the sink 3 open (Fig. 7).

The entire structure is then preferably made with a Metal layer 18 made of aluminum coated, serve as shown in Fig. 8 Way by making contact down to the source and sink. These Finally, metal layer 18 is selectively etched in such a way that the control electrode 10, the source electrode 11 and the drain electrode 12 in that shown in FIG Way to be formed.

Another embodiment of the invention is shown schematically in Cross section shown in Fig. 9. As a charge-storing element, there is no switching element Electrode used. The component shown in Fig. 9 is also on an n-Si substrate 20 built. The substrate has an electrical resistivity of about 10 ohm.cm. The p-source 21 and the p-well 22 have in their surface areas a 19 impurity concentration of 1 x 10 cm e between source 21 and sink 22 a channel area 23 is defined. A first insulating layer 24 made of SiO 2 is 2.0 nm thick. It covers the entire surface of the channel 23. Adjacent to this first one Insulator layer 24 is on the source 21, a second insulator layer 25 with a Thickness of 40 nm and on the depression 22 a third insulator layer 26, which is also 40 nm thick. A fourth insulating layer 27, which preferably consists of Al 2 O 3 and is 50 nm thick, lies on the first insulator layer 24 and the adjoining edge regions of the second insulator layer 25 and the third insulator layer 26. On this fourth insulator layer 27 is preferably made of aluminum Control electrode 28 applied. Also the source electrode 29 and the drain electrode 30, which establish the electrical contact to the source 21 or to the sink 22, exist preferably made of aluminum.

In the semiconductor memory device constructed in this way, the charge storage element is the phase interface between the first insulating layer made of SiO2 24 and the fourth insulator layer 27 consisting of A1203.

The component constructed and manufactured in the manner described 9 has an initial threshold voltage of + 1.0V on. When a voltage of +30 V is applied to the control electrode 28, the threshold voltage becomes raised to a value of +7 V.

If a voltage ton -40 is then applied to the control electrode 28 V is applied, the threshold voltage can thereby be shifted to a value of 0 V. will.

The semiconductor component shown in FIG. 9 is produced essentially in the same way as described in connection with FIG. Only the four insulator layers 24, 25, 26 and 27 are adhered to others Process parameters produced: the second insulating layer 25 and the third insulating layer 26 are oxygenated by oxidizing the surface of the Si substrate 20 with water vapor manufactured. The contact time is 50 minutes at a temperature of about 900.degree. The layer thickness on the surfaces of the source and the sink is 0.19 / µm, while the Si02 layer is on the remaining areas of the substrate surface is only 0.15 / µm thick. The SiO2 layer produced in this way is etched in such a way that the Surface of the Si substrate is exposed in the channel area.

The first insulator layer 24 is made in the manner previously described produced by oxidation with oxygen, which is a solidifying source from a Oxygen-nitrogen mixture originates and is carried along by the evaporating nitrogen will.

The substrate is heated to 1000 ° C. for 10 minutes, with the exposed Si substrate surface forms the Si02 layer. The insulator layer produced in this way is then etched so that it covers the entire surface of the channel area covered.

The fourth insulating layer is produced by means of Ri cathode sputtering. A sintered aluminum oxide and argon are used as the atomizing gas. The sputtering is carried out for 5 minutes at an Si substrate temperature of 180 ° C. The sputtered aluminum oxide is then heated to 700.degree. C. for 30 minutes. the The resulting aluminum oxide layer is then etched in such a way that it is the first Insulator layer completely and the second and third insulator layers adjoining this partially overlapped.

Instead of the previously described charge storage elements in training According to Figures 1 and 9, as already mentioned, MbIOS, MAOS and MNOS structures can be used in the context of the invention.

As a material for the first, second and third insulator layers In principle, any materials can be used. Is essential to the invention however, that the required difference between the effective thicknesses between the first and the second and third insulator layers in the manner described is adhered to.

The difference between the effective thickness of the first insulator layer versus the effective thickness of the second and third insulator layers should be at least about 0.5 nm, preferably 1.0 nm. To clarify the situation are in. Table 1 for a memory device of the type shown in FIG the threshold voltages after 24 h as a function of the difference in the effective thickness of the insulator layers. In those described above in connection with the figures In the exemplary embodiments, this difference in the effective layer thicknesses is 97.5 nm respectively.

35.0 nm. The values shown in Table I are the first Insulator layer and the second insulator layer thermally grown SiO2 layers.

Table I Difference in threshold voltage, threshold span effective Layer- after positive voltage after 24 h thick the 1st and 2nd Voltage on the insulator layer Control electrode (nm) (V) (V> 90.0 +2.0 +1.9.

35.0 +2.0 +1.9 1.0 +2.0 +1.9 0.5 +2.0 +0.6 0.2 +2.0 -0.6 0 +2.0 - 1.1 (-0.4 after 1 h) Also need in the area of the surfaces of the source and the sink not the impurity concentrations of 5 × 1019 cm mentioned in the examples 3 and 1x 1019 cm must be adhered to as long as it is ensured that the impurity concentrations in these areas are higher than the impurity concentration in the substrate.

Particularly powerful components are obtained if one is preferred impurity concentrations in the surface areas of the source and the sink of greater than -3 1 x 1020 cm -3 is set, while at the same time in the Hal # conductor substrate, At least in the surface areas of the semiconductor substrate, disruptions have occurred sets ions smaller than 1 x 1019 cm. These conditions are special easy to produce insulator layers on the substrate surface in the area the source and the sink are thicker than on the remaining surface areas. In 10 is a graph of the dependence of the on the surface of the source area and the drain area formed by the insulator layer thickness Oxidation temperature shown. The layers are thermally grown SiO2 layers. The impurity concentration is in the surface area of the source and the sink 1 x 1020 cm- 3 * oxidation is carried out as steam oxidation. The one in the Curve A shown in Fig. 10 gives the layer thickness of the insulator layer on the source area and the depression area again, while curve B shows the layer thickness on the rest Reproduces surface areas of the substrate. The conditions are set so that at higher oxidation temperatures the insulator layer on the source and sink The thickness of Den in FIG. 10 is 0.15 and on the remaining surface areas 0.1 1 / μm The curves shown can be seen that the difference between the two thicknesses the insulating layer becomes larger, the lower the oxidation temperature becomes. This tendency becomes particularly evident when the oxidation temperature is lower than about 900 ° C noticeable. For the production of the second and the third insulator layer is therefore preferably an oxidation temperature of set less than 900 QC.

Claims (13)

P a t e n t a n s p r ü c h e 0 ne # I-lead memory component with long-term stable storage properties, consisting from a semiconductor substrate of a first conductivity type, in its surface Source area and a drain area of an opposite to the first conductivity type second conduction type are formed, with a channel area between source and sink is defined, on the surface of which a first insulator layer lies, g e k e n n z e i c h n e t by a second insulator layer with an effective thickness the is greater than the effective thickness of the first insulator layer, the second Insulator layer lies on the surface of the source and to the first insulator layer adjoins, by a third insulator layer, which is on the surface of the sink area and is also adjacent to the first insulator layer and has an effective thickness which is greater than the effective thickness of the first insulator layer, by means for charge storage, the at least the surface of the first insulator layer cover, by a control electrode, the charge storage over the means zer and by a source electrode connected to the source and a well electrode connected to the well. 2. Semiconductor memory component according to claim 1, characterized G I do not know that the difference in the effective layer thicknesses of the first insulator layer on the one hand and the second and third insulator layer on the other hand is at least 0.5 nm. 3. A semiconductor memory device according to claim 2, characterized in that it is g e k e n It is not noted that the difference in the effective layer thicknesses is greater than 1.0 nm. 4. Semiconductor memory component according to one of claims 1 to 3, in this way it is indicated that the means for storing a charge are a Contain conductor layer which lies at least on the first insulator layer, and furthermore a control insulator layer lying on this conductor layer contains the de control electrode is applied. 5. Semiconductor memory component according to one of claims 1 to 3, in this way it is indicated that the means for storing a charge are a fourth insulator layer, made of a different material than the first insulator layer consists, the fourth insulator layer at least on the surface of the first Insulator layer lies, with the control electrode on the outer surface of this fourth insulator layer is applied. 6. Semiconductor memory component according to claim 4, characterized G Note that the effective thickness of the first insulator layer ranges from 1.0 to 10.0 nm. 7. A semiconductor memory component according to claim 4, characterized in that g e k e Note that the effective thickness of the first insulator layer in the area from 1.0 to 5.0 nm. 8. Semiconductor memory device according to one of the claims 4, 6 or 7, it is noted that the conductor layer consists of metal. 9. Semiconductor memory component according to one of claims 4, 6 or 7, it is noted that the conductor layer is made of a semiconductor consists. 10. A method for manufacturing a semiconductor memory device, not be indicated by the following process steps: In the surface of a Semiconductor substrates of a first conductivity type are at a predetermined distance from one another a source area and a drain area of a second opposite to the first Line type formed to form a channel area between both areas; by heating in the presence of steam, the Substrate surface an insulator layer is produced, which due to the increased surface impurity concentration thicker on the source area and on the sink area than on the other surface areas of the substrate is; this insulating layer is etched without a mask in such a way that exposing the surface of the channel area the insulator layer of all Surface areas of the substrate with the exception of those remaining with reduced thickness Insulator layer areas on the source and drain are removed; on the exposed On the surface of the channel area, a further insulator layer is formed in such a way that that their effective thickness is less than the effective thickness of the reduced thickness there are insulator layers left on the source and drain; at least on the The surface of the insulating layer lying on the channel becomes a layer or a Layer structure applied to store electrical charge; about this charge storage structure a control electrode is placed on a surface corresponding to the channel area and finally to make the electrical contact to source and Drain a source electrode and a drain electrode are formed. 11. The method according to claim 10, characterized in that g e k e n n z e i c h -n e t that in the source area and in the sink area an impurity concentration of greater than 1 x 10 20 cm at least in the surface area and in the semiconductor substrate an impurity concentration of less than 1 x 101.9cm can be set. 12. The method according to any one of claims 10 or 11, characterized g e k e It is noted that the insulator layer on the substrate surface at a Temperature of less than 900 Or is produced. 13. The method according to any one of claims 10 to 12, characterized g e k e n n æ e i c h n e t that on the insulator layer lying on the channel area a metal layer or a semiconductor layer, on top of which a further insulator layer and on this in turn the control electrode is attached. Blank page