DE2547052C3 - Data processing equipment - Google Patents

Description

The invention relates to data processing devices with a data storage arrangement, a A large number of comparison devices which can be operated in such a way that they make comparisons between a data printout, which is read from the memory arrangement, and make corresponding key values, and with an evaluation device for the logical combination of the comparison results,

There is an increasing need for data processing equipment, with the help of which information from large databases can be retrieved selectively. Such databases are in general organized into files and records that are interlinked in complex ways. Such facilities must be able to make data quickly and effectively discoverable. About that in addition, it is desirable to have multiple access to the facility, i.e. multiple users to enable the facility to be queried independently of each other.

Previous solutions (e.g. GB-PS 11 78 429) are this Problems with processing large databases are associated with the use of appropriately programmed all-purpose computers requires that have various peripheral devices such as B. disk files or Magnetic tape units. The records have generally been found by the fact that was addressed according to the spatial memory locations in the facility. This has the use of various Required indexes to locate the records containing specific characteristics. The creation, use and updating of such indexes, however, represents significant problems and results in poor efficiency. It also brings the requirement

w cause considerable problems after multiple access such facilities.

One method proposed to avoid this problem of indexing is to use the addressing records based on their content rather than their spatial storage locations put in order. For example, it has been suggested to scan a file in full, each recording in turn with a predetermined search criterion in order to decide whether this recording is being played back

• to win or to be processed in any other way. The object of the invention is to create more flexible evaluation devices for processing the comparison results.
According to the invention, in a data processing

• 15 management device of the generic type proposed, that the evaluation device has a number of microprogram-controlled processing elements, namely one for each comparison device, that each processing element has first inputs which are connected to the outputs of the corresponding comparison device and that a Second input of each processing element with the output of the preceding processing element (if available), which forwards the result of the preceding processing element, in Is connected in series.

Further refinements of the invention are the subject of the subclaims.

Such a facility is able to save a file

M) and browse each record in the file with a search criterion to examine that consists of a logical combination of the results of a number of individual There are comparisons.

The use of a variety of comparative

hi directions and a variety of processing elements, which all work in parallel enables a high overall processing speed to be achieved. The fact that the processing elements

are stored, program-controlled processing elements, results in considerable flexibility in the Evaluation of different types of search criteria. In addition, there is further flexibility as a result possible that the processing elements and the comparison devices with each other on different Wise grouped: they can all work together to make an evaluation of a individual, relatively complicated search criteria, or they can be divided into groups, so that different, simpler search criteria can be evaluated at the same time.

The invention is described below in conjunction with the drawing using an exemplary embodiment explained The figures show:

F i g. 1 shows an overall block diagram of a data processing device with a number of disk files, a multiplexer, comparison facilities, a control logic for the comparison devices and a search evaluation device, F i g. 2 the data format for the disk files,

F i g. 3—5 the multiplexer device,

F i g. 6 the format or structure of a recording medium,

Fig. 7-14 the control logic,

15-18 show one of the comparison devices together with a logic that is common to both such institutions,

Fi g. 19 a possibility of using the facility, and jo

F i g. 20-25 the search evaluation device.

In Fig. 1, the device comprises a plurality of magnetic disk file devices 1. Each of these devices consists of a stack of magnetic disks, a read / write head being assigned to each r> recording surface for reading data from or for writing data into a track on the surface. The heads can be adjusted in the radial direction so that a desired "cylinder" of tracks can be selected from these disks. Some of the devices labeled S are designed so that only a single head can be turned on at a time, thus providing only one output data channel. The other devices M are able to switch on a large number of their heads simultaneously and thus achieve a large number of parallel output channels (in this example, ten channels each).

Data that are stored in the data devices 1 are logically organized in files. Any file can for example consist of a given cylinder or span several cylinders (and possibly even over several disk devices). On the other hand, different Files exist in a cylinder. Each file has a number of records and each Record has a number of fields. For example, a file can be a list of on hold represent held parts, there being a record for each part, and each record m> can contain fields that e.g. B. the part number, the price, the stock quantity, the delivery time, etc. represent.

The data channels that are read from the file devices are given to a switching device 2 which selects up to twelve of these channels and gives them to the twelve inputs of a multiplexer device 3. The multiplexer device 3 combines these twelve data channels together and generates a time division multiplex signal on a data multiplexed line 4. Not only are the data switched to multiplex mode, but also the control information that is present on each track process twelve data channels, thus minimizing the number of devices required. However, each channel is treated independently of all other channels. Therefore, the channels that multiplex with one another can all be completely independent of one another and do not need to be synchronized with one another in any way. Thus, if derived from separate surfaces of one of the multiple devices M , it is not necessary that the data be in any way aligned on those surfaces. In addition, the multiplexed channels can be derived from separate file facilities.

The multiplexer also provides the following Control signals to identify the data on data bus 4: A channel number that indicates from which channel the Daicri are derived, and a physical address indicating where the data came from on the disk.

The data present in multiplex operation on the data multiplex line 4 are parallel to a bank of 16 comparison devices 5 (only one is shown) given up. These devices share a control circuit 6. Each comparison device is switched on in time-sharing mode between the twelve data channels and works completely independently for each channel. In the case of a certain data channel, the principle of operation is as follows: The comparison device compares each data field appearing on the data bus 4 with a stored one Key value. The results of these comparison processes are collected (e.g. using OR gates connected to each other) and at the end of the recording in a memory in the comparison device saved.

At the end of a recording, the saved results that are suitable for the recording are transmitted to a search evaluation device 7. This facility performs logical operations on the Results depending on a saved program, so that it is decided whether the Recording a certain search criterion is sufficient. To ensure that the comparison results cannot be obtained more quickly than the search evaluator can evaluate it, becomes a minimum Recording length (in this case 16 bytes), and is designed so that the longest evaluation sequence in the search evaluation device does not use more than 16 byte periods.

The data on the data trunk 4 is shared along with the tag control features as well a retrieval device 10, the purpose of which is to find specific information expressions retrieve from the records that meet the search criterion. As a record of the Search evaluator is not processed until it has been scanned, the retrieval device must 10 buffers that temporarily store the special expressions until the Evaluation has been completed.

The retrieved information is collected together with the assigned physical address of a control processing device 8. she is a

conventional, small processor that controls the operation of all parts of the facility described so far coordinated. In addition, the control processor can access the database via an access device 9 with direct access that is parallel to the rest of the system, but independent of this operates and direct access to the disk file devices I via the switching device 2 owns.

The entire device described so far can be used as a connection device to a conventional main computer are considered, the corresponding output stage commands of the control processing device 8 as a function from user programs.

Panel format or panel structure

In Fig. 2, the format of data in the file devices 1 is shown. Each data track contains 15 data blocks, referred to as data areas DA, which are equally spaced along the track. Each data area contains 384 data bytes with eight bits each. These data areas DA do not correspond to the records identified above: each data area can contain several records or, on the other hand, each record can extend over several data areas on the same track.

Each data area DA is preceded by a marking scheme which is nine bytes long and which is referred to as a counting area CA , which uniquely identifies the data area within the file facility. Each counting area thus contains:

a) a number of cylinders, which is the radial ·? Position of the track identified,

b) a head number that identifies which head the track corresponds to,

c) a counting range number (from 0-14) indicating the circumferential position of the area within the track.

Each data area DA or counting area CA is immediately preceded by the following holge:

a) An introduction PA, which consists of eight bytes with eight binary ones each, which is used to synchronize clock circuits,

b) an address mark AM, which is a single, fixed, predetermined scheme of bits with a length of seven bytes and which serves to mark the beginning of the following counting area or data area,

c) a synchronous byte S, which identifies the type of the following area (e.g. counting area or data area).

Each data area DA or counting area CA is immediately followed by two cyclic check bytes CC , which are used during reading in order to verify the data read out from this area. The first cyclic byte is the same as the exclusive OR function of a byte consisting of all ones, with every second byte in the area starting at the first byte. Similarly, the second cyclic check is an exclusive-OR function of a byte of all ones, with every other byte in the range starting from the second byte.

The hatched areas in FIG. 2 represent columns in which no information is recorded

M ultiplexer device

The F i g. 3-5 show the multiplexer device 3 in FIG individual.

In FIG. 3, the original data from the twelve channels that have been selected by the switching device 2 are given up to twelve channel devices CHQ-CH 11. The data speed at this point is the speed of the read data from a track on the disk and is nominally 2.5 megabits per second.

One of these channel devices is shown in detail in FIG. The device has a demodulation circuit 11, which demodulates the original data and extracts a clock signal from the data (this Clock signal is and is only generated during reading out of the actual recorded areas during the Undefined column).

A selector circuit 13 is provided to select either this data clock signal or a clock signal an internal clock generator 14 (which has a clock speed slightly lower than the data clock, that will serve as the master clock signal for the channel setup. This main act signal will abandoned a counter 15 with a divider eight, so that it is scaled down from the bit frequency to the byte frequency will.

The modulated data on path 12 is applied to address marker display circuit 16 of conventional form which is adapted to recognize the byte scheme representing an address mark AM Byte follows a byte consisting only of ones) a "start" signal is generated.

The demodulated data are also given to a serial-parallel converter 17, which converts them from bit-serial into byte-parallel form. The output of converter 17 is given to a pair of buffer memories B 1 and B 2 , and each of these memories is a 16 byte direct access memory. These buffer memories are controlled by a bistable circuit 19, which are connected as a counter inii Tciici Zwei so that the buffer memories are switched on for alternate writing. Conveniently, the buffer memory which is currently switched on for writing is referred to as the current buffer memory, while the other is referred to as the non-current buffer memory. The data outputs from the buffer memories are applied to a data selection circuit 20, which is also controlled by the bistable circuit 19, so that data from the non-current buffer memory are selected for output on a path 21.

The addressing of the buffer memory is also carried out by the bistable circuit 19 via a switching arrangement 18 controlled in the following manner: The non-stream buffer memory is controlled by a four-bit Address read signal is addressed on a path 22 while the stream buffer is through the content a four-bit counter 23 is addressed. This counter is driven by the byte rate clock signal from the counter 15 switched on. The overflow of the counter 23 indicates that the Current buffer memory is filled with data and therefore to switch the bistable circuit 19 in the opposite state is used to reverse the roles of the buffers. The overflow

Abgabe also generates a request signal on a line 24 provided that an AND gate 25 isi Approved.

In Fig. 3, the inquiry lines 24 from the / wolf channel devices of a channel selector device 26 abandoned, each of which serves an outstanding request at the same time that a channel release signal the corresponding channel device via a Jer twelve lines 27 is fed. the Channel selector setup also produces a sequence of Address read signals from 0 to 15 representing the address paths 22 of the channel facilities are abandoned in order to keep the contents of the non-stream buffers, and one byte after the other, can be read out.

This reading takes place at a speed of 235 nanoseconds per byte. As in Fig. As shown in Fig. 4, the channel enable signal affects a set of AND gates 28 in the selected channel device, whereby data from the non-current memory is transferred to pinpn AiiscriincrsnfaH 29 ^ν ΟΠ B ^ .cbrcl'.C ϊπ ^ ^α ? ' ^{ρ <: ρη} become. As shown in Figure 3, the signals on paths 29 are combined in a wired OR connection to produce a multiplexed signal on a common output path 31 one byte wide.

The speed with which data is read from the buffer memory is slightly faster than twelve times the speed at which they are read. This gives a gap of one Byte between data from different channels, so that there is time available for the Switch the following parts of the device from one channel to the other. This also makes small ones Fluctuations in the speed of rotation of the disks are allowed, which can lead to data being lost from the Plates are read out faster than at nominal speed. The order in which the data channels are operated in multiplex mode is not necessarily predefined, as they are determined by the channel selector is determined as a function of request signals, rather than on a fixed, cyclical basis.

According to FIG. 4, each channel device contains a cyclic shift register 32 with six stages, which as Sorter is called, who does the working of the Facility controls. At any given point in time, one of these levels contains a one, and the others contain all zeros so that the sorter has six consecutive stages. These six stages basically correspond to the following six areas on the plate (Fig. 2):

CA SYNC: Synchronous byte that precedes a counting area.

CA: counting area

GAP: Gap that follows a counting area

DA SYNC: Synchronous byte that precedes a data area

DA: data area

DACC: Cyclic check bytes that follow a data area.

Initially, the sorter is preset to the CA SVTVC level before an address mark AM preceding a count area is received. In this state, the address mark display circuit 16 is made operative so that when the beginning of the address mark AM is displayed, a START signal! is produced. This sets the counter 23 to a value of eight and makes it effective. The counter then counts upwards, so that the address mark AM and the subsequent counting range synchronization byte 5 are gated into bytes 8, 15 of the current buffer. An inquiry signal is then generated on line 24 which interrogates the channel selector to read the contents of the buffer. At the same time, the counter overflow signal causes the buffers to be swapped and also shifts sorter 32 to the C / 4 state.

In the C / 4 state, the counter 23 continues counting and has the effect that the counting area CA and the cyclic check bytes CC are gated into bytes 0-10 of the current buffer. When the count has reached ten, the selector is switched to the internal clock signal. The count continues until 15. A query is then generated and the sorter 32 shifted to the C ^ P state.

Counting is continued in the C4 /> state. In this state, however, the request signal ¹⁷ CSPC ¹ Tt. de dss gate 25 ineffective err ^rt! 2cht i ^{cl cn} that no information is read out to the output path 29th The length of the gap and the frequency of the internal clock are chosen so that when the counter 23 overflows the next time, the introduction PA, which precedes the next address mark, has started to arrive from the disk, so that the data clock signal again to the Available. The overflow signal thus causes the selector 13 to switch back to the data clock signal. At the same time, the sorter is shifted to the DA SV / VC state and the counter 23 is made ineffective.

In the DA SVWC state, the address tag display circuit 16 is made operative again. When the beginning of the address mark is indicated, a START signal is thus generated which sets the counter 23 to eight and makes it effective. The counter then runs and gates the address mark and the data area synchronization byte in bytes 8-15 of the current buffer. If a counter overflow occurs, an inquiry signal is issued and the sorter is shifted to the D / A state.

In the D / 4 state, shifting of the sorter is blocked by a shift inhibit signal. The counter 23 thus counts repeatedly from zero to fifteen and has the effect that successive groups of 16 bytes of the data area DA are stored in alternating buffers. As before, a request signal is issued at the end of each group of bytes. The shift inhibit signal is maintained until the last group of bytes in the data area has been gated into the current buffer, after which it is removed and the sorter can be shifted to the D / ICC state.

In the Dy4CC state, the counter 23 continues and gates the two cyclic check bytes CC in bytes 0 and 1 of the current buffer. When the count has reached one. a signal is generated which switches the selector 13 via the internal clock. The counting process then continues until a counter overflow occurs, which results in another request signal and causes the sorter to be shifted back to the initial CA S YNC state. At the same time, the selector 13 is switched back to the data clock and the counter 23 is made ineffective. The channel facility now waits for the next address tag to arrive, as before.

It follows from this that the channel device receives the data from the corresponding data channel in a Arranged in a series of groups of 16 bytes each.

The data area DA, which consists of 384 bytes, is divided into 24 such groups of bytes, | cde address mark and the following synchronous byte are arranged together in bytes 8-15 of a group and the other bytes are left blank. Similarly, each count area and the cyclic check bytes are arranged in bytes 0-10 of a group, the other bytes being omitted, while the cyclic check bytes for the data area are arranged in bytes 0 and 1 of an otherwise empty group.

As shown in FIG. 4, the AND gates 28 block also the status of the sorter on receipt of a channel-effective signal for generating a channel State signal that is in a wired OR connection with similar signals from the combined with other channels.

Fig. 5 shows the channel selector 26 in detail. The selector has a priority circuit 33 which is one selects the request signals on lines 24 for maintenance and a channel active signal on the corresponding line of the lines 27 generated. At the same time, the identity of the chosen channel becomes encoded by a circuit 34 and generated a channel number of four bits.

The priority circuit 33 then activates a four-bit counter 35 based on a multi-line clock signal is operated from a clock circuit 36. The counter 35 counts from zero to fifteen, generates one Sequence of read address signals for reading out a group of sixteen bytes from the selected one Duct setup. If the counter overflows, it stops and gives a signal to the priority circuit 33 by adding the selection of the next request is initiated. The signal that reads out a group of bytes is referred to as the START-GOB signal, while the overflow signal is at the end of the group of Bytes is referred to as the end GOB signal.

The channel selector further comprises a counter 38 for counting the number of groups of bytes which have been read out from a data area; this counter is incremented by one with each START-GOB signal if the channel status signal is on- '/ cigi that the selected KutKii licti DA-Z.uiiainl assumes. In order to keep up with the multiplexer circuit of the channels, the contents of this counter 38 are stored in a memory 39 with direct access which is addressed by the channel number at the end of each group of bytes. and the counter is filled from memory at the beginning of each group of bytes. It follows that the counting is completely independent for each channel. The output of the counter 38 is applied to a decoder circuit 41 which indicates when the count value reaches 22 for the currently selected channel, with the result that the second to last group of bytes in a data area is read from the non-running buffer in that channel. This means that the last group of bytes in the data area is written into the stream buffer of this channel. Therefore, the output of decoder 41 is used to remove the shift inhibit signal from the enabled channel sorter.

The output from the counter 38 is called a GOB number denotes and represents part of the physical address that holds the data on the data bus 4 qualified.

With reference to FIG. 3 becomes the Ka.ial state signal used to determine what to do with the signals on path 31, in in the following way:

If the channel state to the CA or CA indicating SVWC state, a comparison circuit 400 is made effective, which compares the Zählbcreich and Gleichlaufbyte with the output of the memory 401 with direct access. This memory is divided into twelve areas, one for each data channel, one of these areas being selected by the channel number. Each of these areas contains the expected value of the count area synchronous byte and the count area corresponding to a data area that is to be scanned. If the comparison circuit 400 indicates a mismatch for the smooth byte or the count range, the sorter of the activated channel is reset to the CA SVWC state.

On the other hand, when the comparison circuit 400 for the count area and the synchronous byte makes an adjustment indicates, a signal is sent to the Steuerververarbeitungein direction, which this fact is communicated. The control processing device then uses up the corresponding area of the memory 401 thereby the latest status that the corresponding details of the next counting range to be adjusted, be enrolled. In this way, the control processing means can have any desired sequence of data areas to be scanned by the system, the number being independent for each Channel is carried out.

Another memory 402 is also used in the G4 state with direct access enabled so that the byte on path 31 that contains the count range number into the Place of the memory 402 is written, which is addressed by the current channel number. The contents of the continuously addressed location of this memory result in a signal that is referred to as the GA number, which (together with the GOB number) represents the physical address that the data on the data bus 4 qualified.

When the DA SK / VC condition occurs, the group of bytes present on path 31 becomes. in

Fifteen on a hardwired value is checked to determine if it is a valid data area synch byte acts. If not, an error signal is sent to the control processing device given.

When the D, 4 state occurs, the consecutive Groups of bytes appearing on path 31 onto data bus 4 (FIG. 1) and thus given to the comparison device 5.

The data on the path 31 are also applied to a check byte generation circuit 43, the check bytes on each counting area and the cyclic check bytes, and on each data area and the cyclic check bytes generated. Normally the check bytes generated in this way all become zero. the Circuit 43 has an associated memory 44 with direct access. This memory is used by the Addressed channel number and is used to check the status of the check byte generator at the end of each group of To store bytes and to fill it in at the beginning of each new group of bytes so that it is guaranteed that the generation of check bytes for different channels is done independently.

When the CA or the DACC state occurs, a comparison device 45 is activated which

causes the check bytes generated by circuit 43 to be compared to a wired all-zero scheme. If an error adjustment η is indicated to the DACC state, an error is signaled to the control processing device. On the other hand, a mismatch in the C4 state causes the sorter of the activated channel unit to be reset to the CA SVTVC state. The control circuits of FIG. 3 to adapt the counting ranges, to check the synchronous bytes etc. work in parallel between all twelve channels, so that the cost of control units is reduced.

Recording format

Fig. 6 shows the format of data in a record. The record has a sequence of Data fields. Each data field consists of:

a) F.in an identifier byte /. that is the type of data field For example, ιϊτϊ would be the abundance of Inventory file the identifier byte / a code that specifies "part number / Ie", price ", etc.

b) A length byte L that represents the length in bytes of the data field including bytes / and L.

c) A value part of variable length that contains the actual value of the data. if For example, if the identifier byte / the "number of parts" represents, the value part V contains the number of parts itself.

Each record becomes a supplementary field completed, which consists of a special identifier byte / with a value in the range 240-255 and a Length byte /, consists.

Part of a typical file consisting of a number of such records is shown in Table I below. In this table, the fields of a record are shown on the same line for clarity. Identification bytes are denoted by the letters X, Y, Z , while the fields are denoted by the symbols Xl. Y \, ZX , etc. are designated. The designation X = X \ thus represents a field with a identifying byte X and a value X I. Length bytes and additional information have been omitted from the description.

Table 1

Record no.

fields

X = X \

x = xi

X = Xl X = X 1

Y = YX Y = YX Y = YX

Z = Zl Z = Zl Z = ZZ Z = Zi,

Table 2

Record no.

fields

X = XX

Y = YX

Y = Y2

Z = Zl Z = Zl Z = Zi Z = ZA

This means that the number of fields stored has increased from twelve in table I to seven in table 2 has been reduced, so that a substantial reduction in the required memory space is achieved will.

When data is stored in this way, precautions must be taken to maintain a reminder of information from one record to the next as the file is scanned. For example, in Table 2, fields X = - X 1 and Y = Vl in Record I must be remembered as they must be treated as if they were in Record 2 (see Table 1). In the above example, each scan of the file must be started with recording 1, otherwise errors will occur. For example, if the scan started on record 2, fields X = Xl and Y = YX would not have been remembered and there would be no way of knowing that they should appear in record 2. In order to overcome this difficulty, the present invention uses a special field, called the recording location, which is spaced between recordings to indicate possible starting positions. The data are then arranged in such a way that the information does not have to be remembered at the recording locations, ie the first record after each recording location does not have any omitted fields.

Table 3 shows another part of an uncompressed file.

Table 3

Record fields
application no.

From this table it can be seen that certain fields are repeated in successive records will. For example, the field X = Xl appears in all four records. This trait occurs frequently in files. For example, in the case of the inventory system, consecutive records refer to parts used in the same subgroup, etc. As below carried out, the inventive system enables such a file to be stored in a more compact form by eliminating the repeated fields from successive records. Under Using this principle, the file in Table 1 can be compressed into the form shown in Table 2.

X = X2
X = X2
X = X2

Y = YZ

Z = Z5

Z = Zl

In this case it turns out that the K field is actually supposed to be missing from records 2 and 3. Thus, when this file is compressed, a way must be created to prevent the Y = YZ field from being remembered by Record 1. This is accomplished by using a special null field to indicate that the field is not in the record. The file shown in Table 3 would therefore be compressed to the form shown in Table 4.

Table 4

Record fields
application no.

X = X2

Y = YZ Z = Z5 V = NuIl Z = Z6 Z = Zl

The zero field can be remembered in the same way as a normal field, as in the case of the Record 3 of Table 4 above is shown

F i g. 6 shows the format of a recording location. This consists of the special identifier byte 1, without Length byte or value part. Fig. 6 also shows a NuII-PeId, which consists of a normal field identifier byte / and the length byte 2, but no value part. This figure also shows a dummy field that consists of the Identifier byte 0 exists, which can be used to fill spaces in data areas.

As will be described below, the device according to the invention can operate in two modes. The first operating mode becomes the normal operating mode and in this state the facility can only process uncompressed files, as shown in Tables 1 and 3 shown

The second mode of operation is called the reminder mode, and in this state the device can effectively "remember" and can "remember" the results of comparisons made in fields therefore work with compressed files as they are in Tables 2 and 4 are shown.

Control logic for the comparison device ₂ _

The control logic 6 for the comparison device is shown in detail in FIGS. 7-14. The timing of this control logic is controlled by a main clock signal ck which is derived from the multiple line clock signal (FIG. 5). The clock signal ck is only present when the channel status indicates that a data area is present on the data multiplexer 4.

Referring to Fig. 7, the control logic includes two bistable circuits 110, 111 of the D-type. The bistable » When it is set, the circuit UO generates an identification signal which indicates the presence of an identification byte on the data bus 4. the The bistable circuit 111, when set, generates a length signal indicating the presence of a length byte on the trunk.

The bistable circuit 110 is set at the beginning via an OR gate 112 by a D / l-start signal which is derived from the channel status (FIG. 3) and which indicates the arrival of a first byte in the data area 4>, which will always be an identifier byte. As explained, the OR gate has other inputs for setting the bistable circuit 110 for subsequent identifier bytes. The bistable circuit 110 is reset with the first clock pulse ck after the vi output of the OR gate 112 returns to "0"

The bistable circuit 111 receives the identifier signal from the bistable circuit 110 and is ck at the first clock pulse following to this signal, set if not simultaneously v aufgenom- a reset signal, is men. The bistable circuit 111 is reset at the first clock pulse ck after the identification signal has been removed

According to FIG. 8, each data byte on the data multiplexer line 4 is sent to a decoder 113, which so as is designed to display bytes equal to 0, t and 2. The 0 output of decoder 113 is in an AND gate 114 combined with the identification signal to set a bistable circuit 100, which is a μ when an empty identification occurs Empty output signal generated. Similarly, the 1 output of the decoder becomes an AND gate 115 combined with the identify signal to form a to set bistable circuit 101, and to generate a pick-up point output signal upon occurrence of a pick-up point identification. The signals »empty« and "pick-up point" are given to the OR gate 112 in such a way that the bistable is prevented from being Circuit 110 is reset on the next clock pulse. This is necessary because the next byte, the aul a blank or pick-up point identification will always be followed by a different identification byte. The signals After an inversion, "empty <" and "pick-up point" also become the reset input of the bistable Circuit 111 abandoned so that it is prevented that this bistable circuit is set because an L er field or a recording point does not have a length byte

The 2 output of the decoder 113 is combined in an AND element 116 with the length signal so that that a bistable circuit 102 is set and a zero output signal when a field occurs a length byte equal to 2 (i.e. a null field) is generated. The zero signal is also sent to the OR gate 112 abandoned, so that the bistable circuit HO at the next clock pulse ca, i.e. at the arrival of the next byte, the identifier byte of the next field following the zero field is set again will.

According to FIG. 9, each byte on the data bus 4 is sent to a comparator 103, wc it is compared to a threshold in the range 240-255. The comparator has two Outputs “not less than” and “equal to”. One or the other of these outputs is controlled by a control frame selected and given up to an AND gate 104 together with the identification signal. When the AND gate 104 is activated, it sets a bistable Circuit 105 which generates an end-of-record signal indicating the presence of a supplement identifier

The threshold is obtained from a direct access memory 106 determined by the channel number is addressed so that a certain threshold value is selected for each channel. Similarly, there becomes: Control bit obtained from a direct access memory 109 addressed by the channel number

In operation, the control processor fills the memory 109 with bits to determine which Output of the comparator is to be used for each channel and fills the memory 106 mil the desired threshold values for each channel. The setting of this memory determines which identi ments can be recognized as supplementary identifications for each channel. For example, if the Sthwellwerl is set to 248 for a certain channel and the output "not smaller than" is selected for this channel will only identify identifications in the range 248-25i recognized as supplementary identifications and generates a recording end signal.

It follows that by changing the contents of the memories 106, 109 the limits of the Records in the facility can be effectively modified.

According to FIG. 10, the control logic also has a counter 117. which is set to NuI by the identification signal and is biased with a byte from the data multiplex line 4 by the length signal. The counter is decremented by one with each clock pulse ck . It follows that the counter 117 is filled with the length byte and then decremented when successive bytes of the field occur. Wenr

the counter 117 has thus reached a counter value of 2, the last byte of the field must be present on the data multiplex. The count 2 state becomes displayed by a decoder 118, es a bistable circuit 107 is set and an end-of-field output signal is generated. The end-of-field signal is given to the OR gate 112, so that the bistable circuit 110 (Fig.7) again on the next clock pulse is set, i.e. on arrival of the next byte, which is the identifier byte of the next field will be.

In order to be able to adapt to the data provided in multiplex mode on the data multiplex line 4 obtained, the contents of the counter 117 are stored in a memory 108 with direct access at the end of each Group of Bytes Stored on the Multiple Line The memory 108 has twelve storage locations and is addressed by the channel number so that it is ensured that the contents of the counter 117 for different Channels are always saved in separate memory locations. At the beginning of each new group of bytes the counter is pre-loaded with the output from the currently addressed memory location According to FIG. 11, the control logic also has another counter 119, the output of which results in a byte address that is used to address the key memory in the comparison devices 5, as described below. This counter is linked to a reference value from a memory 120 direct access liked when an identify signal occurs. The memory 120 is identified by the channel number addressed so that different reference values can be used for different channels.

Weiisrhin is provided with a memory 121 for adaptation to the data provided in multiplex mode direct access addressed by the channel number for storing the contents of the counter 119 at the end of each group of bytes, as well as for filling the counter 119 again at the beginning of a new group provided by bytes. Referring to Fig. 12, the pickup point signal sets a bistable circuit 122 which is subsequently reset by the next recording signal. It follows that the A set output of the bistable circuit 122 marks the first recording after a recording point

The operating mode of the system is controlled by a mode signal which is "I" when normal operation is desired and "0" is when reminder operation is required. This signal is derived from a register 124 which has a plurality of individually addressable bit storage locations , whereby one of these memory locations is selected by the number of channels. This means that some channels work in No.T mode, while others work in reminder mode. The output of the bistable circuit 122 and the mode signal are combined in an OR gate 125 to form a signal which is referred to as the reminder signal. This signal indicates to the comparison devices whether they should remember the results of the comparison or not: In normal operation, the warning signal is always "1", which indicates that no reminder occurs, while in reminder mode the reminder signal is "0 «Is, with the exception of the first recording after a recording point, when, as mentioned above, a reminder is not required.

The control logic circuit of Figures 7-12 contains various bistable circuits 110, 111, 100, 101, 102, 105, 107 and 122, which contain a control transformation relating to a particular data channel because of the multiplexing of the channels must the states of this bistable circuit am End of each group of bytes from one specific channel can be saved and then re-filled with information for the next one Channel is appropriate and which appears on the trunk. The way in which this is done is in

13 shows a memory 126 with direct access has twelve word memory locations, one for each channel, identified by a channel number When an end GOB signal occurs, the contents of the bistable circuits are addressed

As referred to above, the currently addressed word of memory 126 is written. If, conversely, a start GOB signal occurs, the contents of the currently adne ^ ated Word into the corresponding bistable circuits

gated before the beginning of the first byte in the group According to FIG. 14, a control logic also generates a set of clock signals «!, which are designated as clocks 1 and 2 and clocks A, B, C. Clocks 1 and 2 are derived from the basic clock signal ck with the help of a tapped delay line 127 derived, the delay for clock 2 being greater is derived from the clock 2 via an AND gate 128 that is blocked when the length signal is present Clock B is from the clock 1 over a AND gate 129 derived however during the Inclusion of both the identifier and length bytes suppressed. Measure C is also over from measure 1 an AND gate 130 derived which is only made effective when the length signal is present Another signal, referred to as the preset signal, is received from clock 1 via a AND gate 131 derived which is only made effective when the identification signal is present.

Comparison facilities

The F i g. 15 and 16 show one of the comparison devices 5 in detail. According to Fig. 15, each Comparison means a memory 230 with direct access to, which is referred to as a key memory and which contains the key values for the comparison with the incoming data on the trunk line 4 records. Each key memory takes up 256 bytes and is derived from the byte address from the control logic addressed. The format of a key value in Key storage is identical to the ei -, es data field according to FIG. 6, d. H. it has an identifier byte Longer byte and a value part of variable length. each key store can have different ones Key values included, each key value is in

v> sequential byte storage locations within the Key memory stored, starting with a reference value address which corresponds to one of the reference value addresses in the reference value memory 120 (Fig. 11).

Mi If a data field arrives via the data multiplex 4 from a certain channel, a Key value corresponding to the channel from the key memory in each comparison device (and one byte at a time) with the data field

tv '· read out aligned, d. that is, the identifier byte of the key value is read out at the same time as the identifier byte of the data field on the Multiple line appears, etc.

Each comparison unit contains a different one similar direct access memory 229, referred to as mask memory and also used by the Byte address is addressed. The output of this memory is in a set of AND gates 228 the data byte on the multiple line 4 is combined, and the result is applied to an input of a comparison device 231, the other input of which is the The output byte from the key memory 230. The mask memory thus provides the possibility of cover selected parts of a data field, d. H. to ignore.

The key memory and the mask memory can be brought up to date during operation as required by the control processor. The comparison device 231 compares the two input bytes and generates one of three output signals, depending on whether the first input byte is larger, smaller or equal to the other byte.

According to FIG. 16 is at the beginning of each data field a bistable lock 232 is set by the preset signal. At the same time, the identifier byte of the field is compared with the corresponding byte of the key value. If the two bytes are unequal Have values, a NAND gate 227 at clock A by the inverse value of the equality output of the Comparison device 231 is made effective and causes latch 232 to be reset. she then remains reset until the beginning of the next field and this effectively ends the comparison for the existing field.

If one assumes, however, that the identifier byte matches, the latch 232 remains set and the comparison is continued. The length byte is ignored since the clock A is suppressed; but if a byte in the value part of the field does not match the corresponding byte in the key value, the interlock 232 is reset at cycle A. Before this occurs, however, the output of the comparison device (greater or less than) is introduced into one of the two bistable interlocks 235 and 23 * by clock B via NAND gates 233 and 234 Latches 232 exist and the output of the comparator becomes "equal" when the end of the field occurs. This results in another NAND gate 237 coming on, which sets another latch 238. The three locks 235, 236 and w 238 are collectively referred to as the field locks and are all reset at the start of the first record and ready to begin the next record at the end of each record. Y,

Since clocks A and B are both suppressed while the length byte L of each field is being recorded, this byte is effectively ignored for comparison purposes and cannot affect latches 232,235,236 and 238. bo

In the following, the operation of the comparison device, as far as it has been described so far, is how summarized as follows: At the beginning of each data field, the identifier byte is stored with that of the Key value compared. This is done for each field in b> the recording repeatedly. At the end of the recording, if none of the fields in the Recording has resulted in an identification adjustment, all unset This state thus indicates that the type of field in question is in the record does not exist, however, if one of the fields (with the exception of a null field) results in an identifier adjustment, the value part of this field is compared with that of the Key value compared. The result is saved in the field locks and remains there until at the end of the recording.

The length of each field comparison (ie the number of bytes read from the key memory for comparison with the data field) is determined by the length byte L of the data field, since this byte defines when the end of the field signal is generated. For example, if the key value in the key memory has a length of eight bytes and the length of the data field is only six bytes, only the first six bytes of the key value are used for comparison and the other two are neglected

Another lock 239 is assigned to the field locks. The lock 239 is also used reset at the end of each recording and when a zero field occurs with an identification / set that matches that of the selection key This is achieved by a NAND gate 240, which is the set output of the latch 222, the clock C, and receives the zero signal from the control logic

The contents of the various latches 232, 235, 236, 238 and 239 in the comparator are stored in a direct access memory array similar to that of FIG. 13 at the end of each Group of bytes saved and reloaded at the beginning of each new group.

When the latch 239 is reset, three AND gates 241, 242 and 243 are made effective, which connects the output of the field interlocks to the data input of a memory 244 with direct access associate. The memory 244 has twelve three-bit word storage locations a; if and is through the number of channels addressed The output from the currently addressed word of this memory is given to the search evaluation device and provides the results of the the comparison carried out by the comparison device.

The write enable input of the memory 244 is connected to the output of an AND gate 247; One input of this AND element 247 receives the end of recording signal from the control logic, and the other input receives the output of an OR element 248. The OR element has five inputs, four of which are "set" outputs of the three Feldverklinkun ^ en and the pawl 23 9 are connected, while the fifth receives the reminder signal from the control logic.The output of the element 247 after the inversion also gives a signal to reset the latches 235, 236, 238 and 239 at the end of each recording .

The operation of the comparison device in the two operating modes will now be described below ben.

In normal operation, memory is always equal to "1". Thus the output from the OR gate 248 is always "I", and thus the AND gate 247 at the end becomes a each record is enabled so that a write enable signal in memory 244 is asserted. Since zero fields are not used in this mode of operation, latch 239 remains reset and makes the AND gates 241, 242 and 243 effective.

It follows from this that in this operating mode the Memory 24 * is brought up to date at the end of a recording by the fact that the contents of the Field links are transferred into it.

In the reminder mode, the first recording after a recording point is again equal to "1", so that the memory 244 is brought up to date in the normal way. For subsequent recordings, however, the reminder becomes "0". When a match is obtained for the identifier bytes of one of the fields in such a subsequent record, one of the latches 235, 236, 238 (or the zero latch 239 if the field is a zero) is set and thus becomes the OR gate 248 activated In this way, the memory 244 is brought up to date at the end of the recording (in the case of a zero field, the AND gates 241-243 are deactivated and the memory 244 is brought up to date by zeros, whereby it is indicated that the field in question is "not available"). On the other hand, if no identification match is obtained during the scan of the record, the field latches and zero latches remain reset and therefore the OR gate 248 and consequently the AND gate 247 are disabled The output of the comparison device is exactly the same as if the field which the identification adaptation generated in a previous recording had been repeated in the subsequent recording, as is the result of the search evaluation device .

As a result, the use of the "reminder" mode enables a file that has been compressed in the manner described in connection with Tables 2 and 4 to give the same results from an associative search operation as if it were in its uncompressed form after the Tables 1 and 3 would be present.

The system also offers the possibility of comparing two data fields with different ones Identifier bytes that appear in the same record. This option can be used, for example, with a credit system used to secure the Compare each customer's current total spend against their personal credit limit. These Opportunity is referred to as a substitution search operation and uses a pair of comparators, hereinafter referred to as comparators A and B, whose key memory begins with the identifier bytes of the two fields that are to be compared with each other are filled.

The substitution search mode is controlled by a logic circuit that is assigned to the two comparison devices A and B and is shown in FIG. 17 shown is. This logic circuit and the two comparison devices are expediently on the same basis Control panel arranged

Referring to Figure 17, the substitution search logic includes a Pair of D-type bistable circuits 250 and 251, both clocked by the output of an AND gate which takes the length signal and the clock 1 The bistable circuit 250 takes as Input the set output of the bistable circuit 232 (Fig. 16) in the comparison unit A; this Signal is referred to as "present (A)". In a similar way The bistable circuit 251 receives the corresponding output “present (B)” from the comparison unit B.

The substitution search mode is initiated by a substitution signal sent to the two AND gates 253, 254 is abandoned together with measure B. The AND gates 253,254 also take the set ones Outputs of the bistable circuits 250, 251. The outputs of these AND gates are signals that are called

ίο write control signal (B) and write control signal (A) are designated.

According to FIG. 18, the write control signal (A) is applied to a NOR gate 255, the output of which is the write control connection WE of the key memory chers 230 of unit A is abandoned. this enables data to be entered into memory from data bus 4 via an OR gate 256 (the other input to the NOR gate 255 is a change signal that is used is det is when the memory from the "expensive processing equipment brought up to date is to be, with the data for advancing the memory to the OR gate 256 via a path 257 abandoned if there is no data on the Data trunk line 4 are present). The write control signal (B) is the key memory of the Abandoned Unit B in a similar manner.

According to FIG. 17 become the outputs of the bistable Circuits 250, 251 correspond to NAND gates 258,259 also given up, each of which also receives the substitution signal and the presetting signal. The outputs of the elements 258, 259 are corresponding bistable circuits 260, 261 of the D-type abandoned, the outputs of which in turn the

j5 corresponding NOR gates 262, 263 supplied will. These NOR gates also receive an input from an AND gate 264, which as Inputs the substitution signal, the length signal, Clock 2 and the inverse values of the outputs of the bistable circuits 260,261 are abandoned. the Outputs of the NOR gates 262, 263 become the reset inputs of the bistable circuits 232 (Fig. 16) in units A and B abandoned.

The way the system works in the substitution Search mode is described below. to At the beginning of each recording, all become bistable Circuits 250, 251, 260 and 261 by the inverse The value of the end of recording signal is reset. Assume that an identifier match

first indicated by the unit A. This results in the bistable circuit 250 at clock 1 in the following length byte is set. The AND gate 253 is "thus made effective and generates a sequence of write control (B) signals, one at a time with each clock B-pulse, whereby the value part of the Data field from the data multiplex 4 is written into the key memory of the unit B. There Both bistable circuits 260 and 261 are reset, the AND gate 264 is at cycle 2 during the Length bytes made effective; thereby the NOR gates 262 and 263 are made effective and tfamit the bistable circuit 232 in the unit A is reset. This means that all further comparisons in of unit A blocked during this data field. to At the beginning of the next data field, a presetting signal is given to members 258, 259 and there the bistable circuit 250 is still set at this point, element 258 is activated and the bistable

Circuit 260 is set and remains set until the end of the recording. The link 262 is therefore made effective and blocks all further identification adaptations in unit A until the beginning of the next recording. The bistable circuit 250 is reset with the next clock 1 pulse and prevents further write enable (B) signals from being generated.

It is now assumed that an identification adaptation by the unit B for a subsequent Data field is displayed in the same recording. A comparison is therefore made between the one in that Key memory in the unit B stored field value and the value part of this subsequent Data field, and the result of this comparison is stored in the field locks of unit B in normally saved.

When the identifier match is indicated in unit B, the bistable circuit 251 is set and causes Write! Generate (A) signals so that the second field value is written into the memory of unit A. However, it does just to maintain the symmetry of the circuit, and the stored value is not actually used by the Unit A is used because that unit is now prevented from making further comparisons. the bistable circuit 261 is set at the end of the field and a reset (B) signal, which all further comparisons in unit B until the end of the recording locks, generates.

Thus, at the end of the recording, the memory 244 of unit A (the first unit to be a Identifier Adjustment is updated with a "Not Present" indicator (i.e. all zeros) brought while the memory 24 of the unit B with the result of the comparison of the two field values is brought up to date. These memories are then available for the search evaluation device in the manner described above.

Since the circuit of FIG. 17 is symmetrical with respect to unit A and unit B, a similar result can be obtained if the unit B

sung would be. In this case, unit B gives the "not available" indicator and unit A shows that Result of the value field comparison.

In accordance with the multiplexing of the data, the contents of the interlocks 250, 251, 260 and 261 in direct access memory at the end of each group of bytes in a similar manner as in connection with FIG. 13 is saved

In practice, the timing of the comparison devices and the associated logic is one byte in delayed with respect to that of the multiplexer device, so that delays in the signal propagation time, etc. are possible are. Thus, the control signals channel number, GOB start and GOB end, which get from the multiplexer to these other devices, delayed by this value. Because of the delays in the comparison, it is also noted that the number of channels given to memory 244 (FIG. 16) is to be delayed by about 11/2 bytes.

An illustration of the use of the key stores in the comparators is given below in connection with F i g. 19 given. In this figure, the key memories of the sixteen comparison devices are shown side by side and each Column represents a key value. Assume that That information should be processed from four files, each file having a different set of key values. Therefore, four reference values DO-D 3 are entered into the reference memory 12 (Ί (FIG. 11). These values divide the key memories into four areas (not necessarily the same size), one for each file, as in FIG. 19 Each key saliva can therefore contain four key values (every ^5th small rectangle in Fig. 18 represents the area available for a key value).

In addition to the above-mentioned "horizontal" subdivision of the key stores, the comparison devices can also be classified as "vertical" in groups

π can be viewed as subdivided. In this example! the facilities are divided into four groups of four each, as indicated by the thick vertical Lines is shown. Each group of comparison devices can then have a separate search output ir

> o be assigned to the same files. From this it follows that in this example the horizontal and vertical subdivision with one another enables sixteen separate search tasks performed simultaneously, four tasks for each file

2> can be.

The division of the comparison devices into groups is determined by the manner in which the search evaluation device processes the results from the comparison devices.

Search evaluation device

The search evaluator will now be described in detail in conjunction with FIGS. 20-25.

si According to FIG. 20, the search evaluation device 16 has processing elements P (O) -P (i5), specifically one for each comparison device 5. The processing elements have a common control device 300, selection function devices 301 and quorum function devices 302. Each processing element can transfer data to the following element one after the other (the last element in the sequence can iifiaHanim mi " Aom 0T-ClAn v""rKlin / fon CMn cr \ / IaR Ain

closed circle is formed by elements).

F i g. 21 shows the structure of one of the processing elements P (N). This element has three interlocks 303-305 which contain the relevant information (greater than, equal to, less than) from the result memory 244 (FIG. 16) of the associated comparison device to take. These results are in the locks clocked in by an evaluation start signal

The processing element has an instruction memory 306 which contains one or more sequences of Microinstructions of nine bits each, up to one Can hold a total of 32 microinstructions The maximum length of a given sequence is 15 microinstructions. The reason for this is that the longest sequence must be completed within sixteen byte periods (the minimum record length).

Microinstructions are read out individually from the instruction memory 306 by instruction address signals from the control device 300 and are given to a logic device 307. The output of device 307 is a binary signal R (N), which can be stored in a lock 308 called a result memory. The logic device takes the contents of the three interlocks 303-305, the output S (N) from the result memory,

and the output R (N- 1] ι from the logic unit of the preceding processing element P (N- I) as data inputs.

Figure 22 shows logic device 307 in detail. Appropriately, the symbols 61 - 69 to represent the nine bits of the current Micro instructions used while the symbols "Coarser than", "less than" and "equal" represent the outputs of the corresponding interlocks 303-305.

The facility has two modes of operation. In the first operating mode, which is determined by 65 = 0, the output R (N) W \ t follows:

8. 69

R (N)

S (N)

00
01
10
Il

where X represents an OR function of the comparison information from latches 303-305. The exact nature of this OR function is determined by 6 1 -63. Even if 64 = 1, the "Select" output from the selection function device is included in this OR function.

In the second operating mode, which is determined by 65 = 1, the output R (N) w \ e follows:

61.62

R (N)

00
01

ΊΟ

S (N) UHD R (N- 1)
S (N) R (N -1)
S (N) ORR (N-])

Bit 67 = 1 causes the result R (N) to be written into the result memory, while bit 66 = 1 causes the output S (N) of a result memory to be inverted. (see Fig. 21).

Π i η 2 ** ü "" ^c ?

310 addressed. The first location in this sequence is designed so that it contains a threshold value of seven bits, while the subsequent memory locations contain a set of scored values.

During the first microinstruction in the sequence is executed by the processing elements, the threshold value is read out from the memory 310 and is introduced into a register 312. The instruction address is then incremented, the counter 319 is set to zero and the multiplexer means 311 made effective.

While the next microinstruction in the sequence is being carried out, the first digit of the Memory 310 is read out, while the multiplexer device 311 simultaneously selects the output 5 (0). If 5 (O) = I a set of AND gates 313 is made effective, which turns the place value into a Accumulator register 314 is gated, where it is added to the contents of the accumulator (provided that since it was initially set to zero).

This process is continued for each subsequent address so that outputs 5 (0), 5 (1), 5 (2) etc. be logically AND-switched one after the other with their corresponding place values and the total can be added in the accumulator.

The accumulated total value is continuously stored in a circuit 315 with the threshold value in the register 312 is compared and if the threshold is exceeded a quorum signal is generated. As in Fig. 23 displayed, the signal is available for selection by the selection function means in the same way as each of the result memory outputs is available.

The quorum function thus gives the possibility of a number of evaluated results from the individual Add processing elements together and determine whether the sum is a threshold exceeds. Not all processing elements have to contribute to this total: The importance of the Items that are not required are set to zero.

Each result memory must be programmed in the required way before it can be used by the quorum

Punlrtirtn uprwpnHpt wirH Γ) ίρ RpurprttincrcfnlcTP fur Hat

301 a memory 309 with direct access, which has 32 word locations which are addressed by the instruction address from the control device. Each of these memory locations contains an address which specifies one of the processing elements P (N) and is decoded so that the result memory output S (N) of this element is selected as the output signal "Select". This signal is given to all processing elements, as above in connection with F i g. 22 explained

The selection function device thus makes it possible to retrieve information from the result memory any selected processing element to the logical facility of any other Transfer element.

According to FIG. 24, the quorum function device has a memory 310 with direct access, which has 32 word storage locations which are addressed by the instruction address. This unit also has a multiplexer device 311 which selects one of the outputs S (O) -5 (15) from the processing elements in accordance with the contents of a four-bit counter 319

Since each sequence of microinstructions is carried out by the processing elements, a corresponding sequence of storage locations in the memory

Processing element P (N) cannot take longer than N + 1 microinstructions. For example, the evaluation sequence for the processing element P (Q) may only use one instruction. Since the quorum function takes the equivalent of N + 1 microinstructions to evaluate the outputs from W processing elements, the quorum output for these N elements cannot be selected up to the / V + 2nd microinstruction of the selector.

As an example of the application of the quorum function, assume that it is necessary to determine whether the results of the evaluations carried out by any four of the first eight processing elements are made, are genuine. The rank values for these eight elements are all set to one while the remainder is zero and the threshold is set to three. In this case the score is the The quorum function is completed after nine microinstructions and the quorum can be given by the tenth microinstruction of the selection function can be selected.

FIG. 25 shows the controller 300 having a memory 316 with direct access by the the number of channels is addressed and the start address of a microprogram in each memory location

which contains the channel in question is equivalent to. Each memory location also contains a sequence length.

The operation of the control device is initiated by a recording signal which (provided that the Auswerts'cueinrichtung is not stressed too much) causes an instruction counter 317 is provided with the appropriate start address for the channel in question, and causes a Sequence length counter 318 is provided with the corresponding sequence length. The instruction counter then becomes so enlarged that a sequence of instruction address signals is generated which is sent to the processing elements, the selection engine and the quorum engine are transmitted. At the same time will the length counter declines, and when it reaches zero, the sequence is ended and a ready signal is given. This indicates to the retrieval device 10 (FIG. I) that the evaluation of the results for the in milling Coming recording is now complete and for inspection in the result memories of the processing elements is available.

Since the search evaluation device consists of a number (16) Processing elements that work in parallel, it has a significant processing capacity because one Number of different operations to be performed for each microinstruction step can. In addition, the processing elements can be divided into groups, each group performs a separate assessment task. For example, that mentioned in connection with FIG. 19 is mentioned Arrangement considered. In this case, the processing elements are divided into groups of four, each group evaluating the comparison information from the corresponding flu from key stores. In this example, each processing element contains four sequences of macro instructions, namely one for each file corresponding to the four horizontal divisions in Fig. 19th

Some possible modifications

For example, the number of data channels that are operated with one another using the time division multiplex method be changed. The limitation is that the comparators are capable have to cope with all of the information. Similarly, the number of comparison devices can also be changed according to requirements.

Another possible modification is the double buffer arrangement in each channel device to be replaced by a memory of the type "first-in, first-out ripple through memory". With another possible modification, the comparison devices can be modified so that the comparison of a the given data field is terminated when the length byte of this field is smaller than the length byte, contained in the key store, which is desirable in some cases. This can be done by it is achieved that cycle 2, length signal and the "smaller than" output of the comparison device 231 (Fig. 15) are operated together in AND circuit that this with the output of the gate 227 (Fig. 16) are operated in ODKR circuit, and that the result is used to reset the latch 232.

llicr / u 12

Claims (5)

Claims; 1. Datenververarbeitungetnrichtung with a data storage arrangement, a plurality of comparison devices which can be operated so that they make comparisons between a data printout which is read from the storage arrangement and corresponding key values, and with an evaluation device for logically combining the comparison results, characterized in that the evaluation device (7) has a number of microprogram-controlled processing elements (P), one for each comparison device (5), so that each processing element has first inputs (>, =, <) which are connected to the outputs of the corresponding comparison device (5) are connected, and that a further input of each processing element with the output of the preceding processing element. " _t it (if any), which passes on the result of the preceding processing element, is connected in series. 2. Data processing device according to claim 1, characterized in that the evaluation unit (7) has a control unit (300) which is common to all processing elements (P) in order to generate a sequence of instruction addresses for transmission to all processing elements, these addresses in an instruction memory (306) in each Element are abandoned so that a sequence of instructions is read out for execution. 3. Data processing equipment according to claim 2, characterized in that the data storage arrangement (1) contains a multiplicity of data channels and the control unit (300) has a memory (316) which is addressed by a channel number signal, and that a counter (317) connected downstream of the memory (316) in the control unit (300) forwards a start address and the subsequent addresses to all processing units (P) which simultaneously process the data of the channel determined by the respective channel number signal. 4. Data processing device according to claims 1-3, characterized in that a selection function unit (301 ) selects the result of the operation of one of the processing elements (P) and transfers this result to all processing elements. 5. Data processing device according to claim 4, characterized in that a quorum function unit (302) compares a weighted sum of the results from a selected combination of the processing elements (P) and this sum with a threshold value and forwards it to the selection function unit (301) .