DE2547052A1 - DATA PROCESSING DEVICE - Google Patents

Description

PATENT Attorneys 2 5 4 / P ^ ^

Dipl.-Ing. A. Wasmeier η

Dipl.-Ing. H. Graf

Patent Attorneys 8400 Regensburg 2 P.O. Box 382

All that ^{D 8400 REGENSBURG 2}

German Patent Office Greflinger Strasse 7

TELEPHONE (0941) 54753

Munich 2 telegr. begpatent rgb.

TELEX 6 5709 repat d

Your reference Your message Our reference Day 5 · Sept. 1975 W / He

Your Ref. Your Letter Our Ref. Dafe

I / p 8269

INTERNATIONAL COMPUTERS LIMITED, ICL House, Putney, London SW 15,, England

Data processing equipment

The invention "relates to data processing equipment.

There is "an increasing need for data processing equipment, with their help selectively information from large databases can be found again. Such databases are generally organized in files and records, the are interconnected in a complex way. Such facilities must be able to process data quickly and effectively to make it discoverable. In addition, it is desirable to have multiple access to the device, i.e. multiple Allow users to query the facility independently of one another.

Previous solutions to this problem of processing large data

onbasen have the use of corresponding programmed All-purpose computing equipment that requires various peripheral Devices such as disk files or magnetic tape units. The records are, in general, thereby

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Ko: ■. Bayerische Vereinsbank (sort code 750 200 73) 5 804248

Pos .: ieckkonto Munich 893 69 - 801 place of jurisdiction Regensburg

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found again that addressing was carried out according to the spatial memory locations in the device. This has the use various indexes required to keep the records, that contain special features. The creation, use and updating of such However, indexes pose significant problems and result in poor efficiency. It also brings the requirement after multiple access there are considerable problems with such devices.

One proposed to avoid this problem of indexing Method consists in the records to be addressed based on their content rather than their spatial storage locations. For example, a file to scan completely, to check each recording one after the other with a predetermined search criterion in order to decide whether this Record recovered or otherwise processed shall be.

It is an object of the present invention to provide an improved device of this type.

According to the invention, a data processing device has a data storage arrangement, a plurality of comparison units, parallel to the implementation of comparisons between a printout of data read out from the memory arrangement, and corresponding key values are treated, and an evaluation unit for logically combining the results of the comparisons on, wherein the evaluation unit a plurality of stored, program-controlled processing elements, namely one for each comparison unit, and where the Elements can be acted upon in parallel so that logical processes take place the comparison results from the corresponding comparison units and on the results of the logical operations of the others Elements are carried out.

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Such a facility is able to search a file and each record in the file with a search criterion to consider, which consists of a logical combination of the results of a number of individual comparisons.

The use of a large number of comparison units and a large number of processing elements, all of which work in parallel, enables a high overall processing speed to be achieved. The fact that the processing elements are stored are program-controlled processing elements, there is considerable flexibility in evaluating different types of Search criteria. In addition, further flexibility is possible in that the processing elements and the comparison units are grouped with one another in different ways: They can all work together to achieve an evaluation of a single, relatively complicated search criterion, or they can be divided into groups so that several simpler search criteria can be evaluated at the same time.

The invention is explained below in conjunction with the drawing using an exemplary embodiment. The figures demonstrate:

1 shows an overall block diagram of a data processing device with a number of disk files, a multiplex unit, Comparison units, a control logic for the comparison units and a search evaluation unit,

2 shows the data format for the disk files,

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Figures 3-5 the multiplex unit,

Mg. 6 the format or the structure of a recording medium,

Figures 7-14- the control logic,

Figures 15-18 one of the comparison units together with a logic, the two such units are common,

19 shows a possibility of using the device, and FIGS. 20-25 the search evaluation unit.

In Fig. 1, the device comprises a plurality of magnetic disk file units 1 on. Each of these units contains a stack of magnetic disks, with a read / write head for each recording surface for reading out data from or for writing data into a track on the surface. the Heads are adjustable in the radial direction so that a desired "cylinder" of tracks can be selected from these disks can. Some of the units labeled S are designed so that only a single head is turned on at a time and thus only results in one output data channel. The other units M are able to have a large number of their Heads can be switched on at the same time and thus a large number of parallel output channels (in this example each ten channels) can be achieved.

Data stored in the disk units 1 are logically organized into files. For example, each file can be consist of a given cylinder or span multiple cylinders (and possibly even multiple plate units) extend. On the other hand, different files can exist in one cylinder. Each file has a number of records and each record has a number of fields. For example, a file can be a list of on hold

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represent held parts, keeping a record for each Part is present, and each record can contain fields indicating the part number, price, stock. ™ close, delivery time etc. represent.

The data channels that are read from the disk units are given to a switching unit 2, which can hold up to 12 of them Selects channels and gives them up to the twelve input points of a multiplex unit 3. The unit 3 combines these twelve data channels with each other and generates a time division multiplex signal on a data multiplex line 4. It is not only the data that is multiplexed switched, but also the control information that is present on each track. This enables the control devices treat this control information simultaneously under all twelve data channels and thus reduce the number of devices required to one Lower the minimum. However, each channel is treated independently of all other channels. That is why the channels that interrelate work in multiplex operation, all be completely independent of each other and need to be synchronized with each other in a way to be. If they are thus derived from separate surfaces of one of the multiple units M, it is not necessary to ensure that the data is aligned in some way on these surfaces. In addition, they can be multiplexed working channels can be derived from separate disk units.

The multiplex unit also provides the following control signals to identify the data on the data bus 4: One Channel number, which indicates from which channel the data is derived, and a physical address indicating where the data came from on the disk.

The data available in multiplex mode on the data multiplex 4 are submitted in parallel to a bank of 16 comparison units (only one is shown). Use these units jointly a control circuit 6. Each comparison unit is in Time-sharing operation switched on between the twelve data channels

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and works completely independently for each channel. For a certain data channel, the principle of operation is as follows: The comparison unit compares each data field that occurs on the data multiplex 4 with a stored key value. The results of these comparisons are collected (e.g. connected to one another by an OR circuit) and stored in a memory in the comparison unit at the end of the recording.

At the end of a recording, the saved results that are suitable for recording are transferred to a search evaluation unit (SEU) 7 transferred. This unit carries out logical work

v
passes through the results as a function of a stored program so that a decision is made as to whether the recording satisfies a certain search criterion. In order to ensure that the comparison results are not obtained faster than the search evaluation unit can evaluate them, a minimum recording length is specified (in this case 16 bytes) and is designed so that the longest evaluation sequence in the search evaluation unit does not take longer than 16 Byte periods.

The data on the data multiplex 4, together with the identification control signals, are also sent to a retrieval unit 10 abandoned, the purpose of which is to retrieve specific information expressions from the records that meet the search criteria suffice. Since a recording is not processed by the search evaluation unit until it has been scanned the retrieval unit must contain 10 buffers, which hold the special expressions temporarily until the evaluation has been completed.

The retrieved information is stored along with the associated physical address of a control processing device 8 supplied. This is a conventional, small processor, who coordinates the operation of all parts of the facility described so far. In addition, the Steuex processor can have a Access to the database via an access unit 9 with direct

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Access will be given in parallel with the rest of the system, however works independently of this and has direct access to the disk files 1 via the switching unit 2.

The entire device described so far can be used as a connecting device to a conventional main computer are considered, the corresponding output stage commands of the control processing unit 8 depending on user programs.

Panel format or panel structure

In Fig. 2, the format of data in the disk units 1 is shown. Each data track contains 15 data blocks, which are referred to as data areas DA and which are equidistant around the track are offset. Each data area contains 384 data bytes each with eight bits. These data areas DA do not correspond to the records mentioned above: Each data area can have several Contain records or, on the other hand, each record can extend over several data areas on the same track.

Each data area DA is preceded by a marking scheme consisting of nine bytes is long and is called the counting area OA, which uniquely identifies the data area within the disk unit. Each counting area thus contains:

(a) A cylinder number that identifies the radial position of the track ,

(b) a head number which identifies which head the track corresponds to ,

(c) a counting range number (from 0-14) indicating the circumferential position of the Identified within the track.

Each data area DA or counting area OA is immediately preceded by the following sequence:

(a) An introduction PA, which consists of eight bytes with eight binary ones each, which is used to synchronize!
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/O

(b) an address mark AM, which is a single, fixed This is a scheme of bits with a length of seven bytes and which serves to mark the beginning of the following counting range or To mark the data area,

(c) an equal! aufbyte S, which is the type of the following area (e.g. counting area or data area) identified.

Each data area DA or counting area CA follows directly two cyclic test bytes CO on, which are activated during the reading can be used to verify the data read from this area. The first cyclic byte = the exclusive ODEE function a byte consisting of all ones, with every other byte starting in the range of the first byte. In a similar way The second cyclical test is an exclusive-OR function a byte made up of all ones, with every other byte in the range starting from the second byte.

The hatched areas in Fig. 2 represent columns in which no information is recorded.

Multiplex unit

Figures 3-5 show the multiplex unit 3 in detail.

In Fig. 3, the original jump data from the twelve channels that have been selected by the switching unit 2, twelve channel units CHO-CHIl abandoned. The data speed on this Digit is the speed of the read data from a track on the disk and is nominally 2.5 megabits per second.

One of these channel units is shown in detail in Fig. 4-. The unit has a demodulation circuit 11 which demodulates the original data and extracts a clock signal from the data (This clock signal is generated only during reading out of the actual recorded areas and is during the Undefined column).

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ΛΑ

A selector circuit 13 is provided to either select this data clock signal or a clock signal from an internal clock generator 14- (which has a slightly slower clock speed than the data clock

zuentpricht owns), selects that as the main clock signal for the Channel unit is used. This master clock signal is applied to a counter 15 with a divider eight, so that it is based on the bit frequency the byte frequency is reduced.

The demodulated data on the path 12 becomes an address marker indicating circuit 16 abandoned conventional form, which is designed so that they represent an address mark AM byte scheme recognizes. When the circuit 16 indicates the beginning of an address mark (namely that a byte consisting of all envelopes follows a byte consisting only of ones) becomes a "start" signal generated.

The demodulated data are also given to a serial-parallel converter 17, which converts them from bit-series to byte-parallel Porm. The output of the converter 17 is given to a pair of buffer memories B1 and B2, and each of these memories is a 16-byte direct access memory. These buffer memories are controlled by a bistable circuit 19 which is connected as a counter with a divider 2 and two in such a way that the buffer memories are made effective for alternate writing. Conveniently, the buffer that is being activated for writing is referred to as the stream buffer, while the other is referred to as the non-current buffer. The data outputs from the buffer memories are applied to a data selection circuit 20, which is also controlled by the bistable circuit 19, so that data from the overflow buffer memory are selected for output on a path 21.

The addressing of the buffer memory is also controlled by the bistable circuit 19 via a switching arrangement 18 in the following way: The non-current buffer tank is made by one of four

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Addressed address read signal on a path 22 consisting of bits, while the stream buffer is addressed by the contents of a four-bit counter 25. This counter is through the byte speed clock signal from the counter 15 is advanced. The overflow of the counter 23 indicates that the current buffer the memory is filled with data and is therefore used to switch the bistable circuit 19 to the opposite state is to swap the hells of the buffers. The overflow delivery also generates a request signal on a line 24, provided an AND gate 25 is enabled.

In Fig. 3, the inquiry lines 24 are made up of the twelve channel units abandoned a channel selector unit 26, each of which serves an outstanding request at the same time in that a channel release signal is fed to the corresponding channel unit via one of the twelve lines 27. The channel selector unit generates also a sequence of address read signals from 0 to 15 »den Address paths 22 of the channel units are given up so that the Contents of the non-stream buffers, one byte after the others to be read out. This reading takes place at a speed of 235 nanoseconds per byte. As shown in Fig. 4- the channel enable signal affects a set of gates 28 in the selected channel unit, thereby removing data from the stream memory can be read out on an output path 29 of byte width. As shown in FIG. 3, the signals are on the paths 29 combined in a hard-wired ODEE connection so that a multiplex signal on a common output path 31 with a Width of one byte

The speed at which data is read from the buffers is slightly faster than twelve times the speed at which they are read. This gives a gap of a byte between data from different channels, so that time is available for the following! parts of the Switch setup from one channel to the other. In order to

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also, small fluctuations in the rotational speed of the Disks allowed, which can result in data being removed from the disks can be read out faster than at the nominal speed. The order in which the data channels are multiplexed is not necessarily fixed, as it is determined by the channel selector depending on request signals, rather than on a fixed, cyclical basis.

After Pig. M- Each channel unit contains a cyclic shift register 32 of six stages, called a sorter, which controls the operation of the unit. At any given point in time, one of these levels contains a one, and the others

so
hold all the envelopes that the sorter has six consecutive stages. These six stages basically correspond to the following six areas on the plate (Pig. 2):

CJ / SYNC: Synchronous byte that precedes a counting area.

CA: counting area

GAP: gap that follows a counting area

DA SYNO: Synchronous byte that precedes a data area

DA: data area

DAOC: Cyclic check bytes that follow a data area.

will

At the beginning, the sorter is preset to the GASXNC level before an address mark AM preceding a counting area is recorded. In this state, the address mark indicating circuit 16 is made operative so that when the beginning of the address mark AM is indicated, a STAKD signal is generated. This sets the counter 23 to a value of eight and makes it effective. The counter then counts upwards, so that the address mark AM and the subsequent counting range synchronization byte S are gated into bytes 8, 15 of the current buffer. An inquiry signal is then generated on line 2M- which interrogates the channel selector unit in order to read out the contents of the buffer. At the same time, the counter overflow signal causes the buffers to be swapped and also shifts the sorter 32 to the OA state.

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«Μ

In the CA state, the counter 23 continues counting and "causes that the ZähTbereich OA and the cyclic check bytes CC are gated in bytes 0-10 of the current buffer. When the count When it has reached ten, the selector is switched to the internal clock signal. The count continues until 15. then a request is generated and the sorter 32 on the GAP state postponed.

Counting continues in the GAP state. In this condition however, the request signal is blocked because the gate 25 is ineffective is made so that no information is read out on the output path 29. The length of the gap and the frequency of the internal clock are chosen so that when the counter overflows the next time, the introduction PA, that of the next Address mark precedes, has begun to arrive from the plate, so that the data clock signal is available again. The "overflow signal thus causes the selector 13 to respond to the data clock signal switches back. At the same time, the sorter is shifted to the DA SYNC state and the counter 23 is made ineffective.

In the DA SYÜTC state, the address mark display circuit 16 becomes made effective again. When the beginning of the address mark is displayed is, a START signal is thus generated, which the counter 23 takes care of it and makes it effective. The counter then runs and gates the address mark and the data area synchronous byte in bytes 8-15 of the current buffer. If a counter overflow occurs, a request signal is issued and the Sorter moved to the DA state.

In the DA state, the sorter can be shifted by a shift inhibit signal locked. Thus, the counter 23 repeatedly counts from zero to fifteen and causes successive ones Groups of 16 bytes of the data area DA can be stored in alternating buffers. As before, at the end of each group of bytes issued a request signal. The shift lock signal is maintained until the last group of

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4f

Bytes in the data area gated into the current buffer has been, whereupon it is removed and the sorter can be moved to the DACC state.

In the DACC state, the counter 23 continues to run and gates both of them cyclic check bytes CC in bytes O and 1 of the current buffer. When the count has reached one, a signal is generated which switches the selector IJ via the internal clock. The counting process is then continued until a counter overflow occurs, which gives a further request signal and causes the sorter in the initial CA SlUC state is shifted back. Simultaneously the selector IJ is switched back to the data clock and the counter 23 made ineffective. The channel unit is now waiting the arrival of the next address mark, as before.

It follows from this that the channel unit collects the data from the corresponding data channel in a series of groups of 16 bytes each arranged. Each data area DA, which consists of 384 Bytes is divided into 24 such groups of bytes. Each address mark and the following synchronous byte are put together arranged in bytes 8-15 of a group and the other bytes left blank. Similarly, each count area and the cyclic test bytes arranged in bytes 0-10 of a group, the other bytes are left blank, while the cyclic check bytes for the data area in bytes O and 1 are one otherwise empty group can be arranged.

As shown in FIG. 4, the gates 28 also gate the status of the sorter upon receipt of a channel-active signal for generation of a channel status signal that is in a wired OR connection is combined with similar signals from the other channels.

Fig. 5 shows the channel selector 26 in detail. At: Voter has a priority circuit 33 which selects one of the request signals on lines 24 for maintenance and a channel active signal

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generated on the corresponding line of lines 27. Simultaneously the identity of the selected channel is encoded by a circuit 34 and a channel number is generated from four bits.

The priority circuit 33 then activates a four-bit counter 35 from a multi-line clock signal from a clock circuit 36 is operated. The counter 35 counts up from zero! Fifteen, generates a sequence of read address signals for reading out a group of sixteen bytes from the selected channel unit. When the counter overflows, it stops and gives a signal to the priority circuit 33 by selecting the next Request is initiated. The signal that initiates the reading of a group of bytes is referred to as the STAEÜD-GOB signal, while the overflow signal at the end of the group of bytes is referred to as the end GOB signal.

further
The channel selector has a counter 38 for counting the number of groups of bytes read out from a data area; this counter is incremented by one with each START GOB signal if the channel status signal indicates that the selected channel is in the DA status. To keep up with the multiplexing of the channels, the contents of this counter 38 are stored in a direct access memory 39 addressed by the channel number at the end of each group of bytes and the counter is taken from memory at the beginning of each group of bytes filled. It follows that the counting is completely independent for each channel. The output of the counter 38 is applied to a decoding circuit 41 which indicates when the count value reaches 22 for the currently selected channel, which means that the second to last group of bytes in a data area is read from the non-running buffer in this channel. This means that the last group of bytes in the data area is written into the stream buffer of this channel. Therefore, the output of the decoder 41 is used to switch off the lock-out signal

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to the sorter of the activated channel.

The output from the counter 38 is referred to as the GOB number and represents part of the physical address that qualifies the data on the data bus 4.

With reference to Pig. 3 the channel status signal is used, to determine what to do with the signals on path 31 should, in the following way:

If the channel state indicates the OA or the CASYNO state, a comparison circuit 400 is made effective, which the count range and the synchronous byte with the output of the memory 401 compares with direct access. This memory is divided into twelve areas, one for each data channel, one of these ranges being selected from the channel number. Each of these areas contains the expected value of the count area synchronous byte and the count area corresponding to a data area to be scanned. When the comparison circuit 400 for the equal byte or the counting range is a misadjustment indicates, the sorter of the activated channel is reset to the GASyHO state.

On the other hand, if the comparison circuit 400 for the count range and the synchronous byte indicates an adjustment, a signal in is sent to the control processing device, which is notified of this fact. The control processing device then brings the corresponding area of the memory 401 is up to date by the fact that the corresponding details of the next counting area, to be customized. In this way, the control processing means can do any desired Select a sequence of data areas for the system to scan, the selection being made independently for each channel will.

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Another memory 402 with direct Access enabled to have the byte on path 51 containing the count range number written into memory 402 location addressed by the current channel number. The contents of the currently addressed location in this memory result in a signal called CA number, which (together with the GOB number) represents the physical address, which qualifies the data on the data multiplex 4.

When the DA SYNG condition occurs, the group of bytes present on path 31 is put into a compare circuit gated where byte fifteen against a hardwired value a check is made to determine whether it is a valid data area synchronous byte trade. If not, an Ierror signal is sent to the control processor.

When the DA state occurs, the consecutive Groups of bytes appearing on path 31 onto the data bus 4 · (FIG. 1) and thus gated to the comparison units 5.

The data on path 31 also goes to a check byte generation circuit 43 abandoned, the check bytes spring counting area and the cyclic check bytes, and generated on each data area and the cyclic check bytes. Usually those on this Way, check bytes all generated zero. The circuit 43 has a allocated memory 44 with direct access to. This memory is addressed by the channel number and is used to store the status

Lands one
of the check byte generator at each group of bytes and to fill it at the beginning of each new group of bytes, so that it is ensured that the generation of check bytes for different channels takes place independently.

When the OA or the DAOC state occurs, a comparator 45 is activated which causes the check bytes, generated by the circuit 43 with a wired

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Total-zero scheme can be compared. If there is a mismatch in the DACC status is indicated, the control processing device is signaled an error. A mismatch in the CA state "On the other hand, causes the sorter of the activated channel unit to be reset to the GA SOTC state. The control circuits according to Pig. 3 to adapt the counting ranges, to check the synchronous bytes etc. work in parallel between all twelve channels, so that the cost of control units is reduced.

Recording format

Fig. 6 shows the format of data in a record. The record has a sequence of data fields. Each data field consists of:

(a) An identifier byte I, which represents the type of data field. For example, in the case of the inventory file, the identification byte I would be a code, the "part number", "price" etc. indicates.

(b) A length byte L, which represents the length in bytes of the data field including bytes I and L.

(c) A variable length value part V containing the actual value of the data. For example, if the identifier byte I represents the "number of parts", the value part V contains the number of parts itself.

Each record is completed by a supplementary field, which consists of a special identifier I with a value im Area 240-255 and a length byte L.

Part of a typical file made up of a number of such records is shown in Table I below. In this table are the fields of a record of clarity

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due to shown on the same line. Identifier bytes are through denotes the letters X, Y, Z, while the field values are denoted by the symbols Xl, Yl, Zl and so on. The designation X = Xl thus represents a field with an identification byte X and a vert Xl. Length bytes and record additions are off omitted from the table.

Table 1 Recording ITr. fields

1 X = Xl Y = Yl Z = Zl

2 X = Xl Y = Yl Z - Z2

3 X «Xl Y = Yl Z« Z3

4 X = Xl Y - Y2 Z = Z4

This table shows that certain fields in successive Records are repeated. For example, the field X = Xl appears in all four records. This feature often occurs in files. For example, in the case of the legacy system, consecutive records can relate to Refer to parts used in the same subgroup, etc. As will be explained below, the invention enables System that such a file is stored in a more compact form by the repeated fields of consecutive Records are eliminated. Using this principle, the file in Table 1 can be transformed into that shown in Table 2 Shape to be compressed.

Table 2 Record no. fields

1 X β Xl Y - Yl

4 Y - Y2

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X4

It follows that the number of fields stored is from twelve in Table 1 has been reduced to seven in Table 2, so that a substantial reduction in the required memory space is achieved.

When storing data in this way, precautions must be taken can be taken to get a reminder of the information from one record to the next as the file is scanned will. For example, in Table 2 the fields X = Xl and Y = Yl in Record 1 as they must be treated as if they were in Record 2 (see table 1). In the example above, each scan of the file must be started with recording 1, otherwise errors will occur. For example, if the scan started at record 2, the fields X = Xl and Y = Yl would not have been remembered, and it there would be no way to tell that they should appear in Record 2. To overcome this difficulty, will in the present invention uses a special field, referred to as pick-up parts, which are between records is arranged at intervals so that possible starting positions are displayed. The data is then arranged so that the Information at the recording points does not have to be remembered, i.e. the first record points to each recording point no omitted fields.

Table 3 shows another part of an uncompressed file.

X Tabel Y - Y3 fields - Z5 Recording Mr. X Z - Z6 1 X = X2 Z - Z7 2 - X2 Z 3 «X2

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In this case it turns out that the Y field is actually from the Records 2 and 3 should be missing. When this file is compressed a way must thus be created to prevent the field Y = Y3 from being remembered by record 1. This is achieved by using a special null field which indicates that the field is not in the record. The file shown in Table 3 would therefore be compressed to the form shown in Table 4-.

Table 4- Record no.

1 X = X2

The zero field can be remembered in the same way as a normal field as in the case of recording 3 <3.e; r above Table 4- is shown.

Fig. 6 shows the format of a receiving station. This consists of the special identifier byte 1, without length byte or value part. Figure 6 also shows a null field which is composed of a normal field identifier byte I and the length byte 2, but no value part exists. ' This figure also shows a dummy field that consists of the identifier byte O, which can be used to fill spaces in data areas.

As will be described below, the system of the present invention work in two modes. The first mode is called the normal mode, and in this state the system can process only uncompressed files as shown in Tables 1 and 3.

Y3 fields Z5 Y = zero Z - Z6 Y = Z = Z7 Z »

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The second mode of operation is called the reminder mode, and in this state the system can effectively act on the results "remember" comparisons made on fields and can therefore work with compressed files, as shown in Tables 2 and 4-.

Control logic for the comparison unit

The control logic 6 for the comparison units is detailed shown in Figures 7-14-. The timing of this control logic is controlled by a master clock signal ck derived from the multi-line clock signal (Fig. 5) is derived. However, the clock signal ck is only present when the channel state indicates that a data area is available on the data multiplex 4-.

To. Fig. 7 contains the control logic of two bistable circuits 110, 111 of the D-type. The bistable circuit 110 generates, when it is set, an identification signal that the presence of an identifier byte on the data bus 4 indicates. The bistable circuit 111, when set, generates a Length signal that indicates the presence of a length byte on the multiple line.

The bistable circuit 110 is initially via an OR gate 112 is set by a DA start signal, which comes from the channel status (Fig. 3) and which indicates the arrival of a first byte in the data area, which will always be an identifier byte will. As explained, the ODEE gate has other inputs for setting the bistable circuit Ho for subsequent identifier bytes on. The bistable 110 is reset at the first clock pulse ck after the output of the OR gate 112 returns to "0". * Circuit - -

The bistable circuit 111 receives the identification signal from the bistable circuit 110 and is ck, which follows this signal, set if rises at the same time

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Reset signal is recorded. The bistable circuit IH will reset at the first clock pulse Ok after the identification signal is removed.

Referring to Figure 8, each byte of data on the data bus becomes 4-one Abandoned decoder 113, which is designed to display bytes equal to 0, 1 and 2. The O output of the Decoder 113 is combined in an AND gate 114 with the identification signal to set a bistable circuit 100 which if an empty identification occurs, an empty output signal generated. Similarly, the 1 output of the decoder is combined in an AND gate 115 with the identify signal to to set a bistable circuit 101, and a pick-up point output signal upon occurrence of a pick-up point identification

en

to create. The signals "empty" and "pick-up point" were given to the OR gate 112 in such a way that the bistable is prevented from being Circuit 110 is reset on the next clock pulse. This is necessary because the next byte that is on a blank or Pick-up point identification follows, there will always be a different identification byte. The signals "empty" and "pick-up point" are also the reset input of the bistable after an inversion Circuit 111 abandoned, so that this bistable circuit is prevented from being set because an empty field or a pick-up point no length byte occupied.

The 2 output of the decoder 113 is in an AND gate 116 with the length signal combined so that a bistable circuit 102 is set and a zero output signal when a field occurs is generated with a length byte equal to 2 (i.e. a zero field). The zero signal is also applied to OR gate 112 so that the bistable circuit 110 on the next clock pulse Ok, i.e. on the arrival of the next byte containing the identifier byte of the the zero field following the next field is set again.

Referring to Figure 9, each byte on data bus 4 becomes one Comparison device 103 abandoned where it is with a threshold value

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is compared in the range 240-255. The comparison device has two outputs "not less than" and "equal to". The one or the other of these outputs is selected by a control bit and applied to an AND gate 104 together with the identification signal. When gate 104 is enabled, it sets a "bistable 105" which generates an end-of-record signal that

indicates the presence of a supplementary identification, ♦ switching

The threshold value is obtained from a memory 106 with direct access, which is addressed by the channel number, thus a specific one Threshold value is selected for each channel. In a similar way Veise is the control bit from a memory 109 with direct Get access addressed by the channel number.

In operation, the control processing device fills the memory 109 with bits to determine which output of the comparator to use for each channel and fills the Memory 106 with the desired threshold values for each channel. The setting of this memory determines which identifications are recognized as supplementary identifications for each channel. Venn, for example, the threshold for a particular channel is set to 248 and the output "not less than" is selected for this channel, only identifications in-range are used 248-255 recognized and generated as supplementary identifications an end of recording signal.

themselves
As a result, by changing the contents of memories 106,109, the boundaries of records in the system can be effectively changed.

According to FIG. 10, the control logic also has a counter 117 which is set to JTuIl by the identification signal and with a byte from the data bus 4 by the length signal is biased. The counter is at jsdem clock pulse Ck by one Unit decreased. It follows that the counter 117 with The length byte is filled and then reduced when successive bytes of the field occur. When the counter 117 thus

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has reached a count of 2, the last byte of the field be present on the data multiplex. The count 2 state is displayed by a decoder 118, a "bistable 107" is set and an end-of-field output signal becomes generated. The end-of-field signal is applied to the OR gate 112, so that the bistable circuit 110 (Fig. 7) is again set on the next clock pulse, i.e. on arrival of the next byte, which will be the identifier byte of the next field. *Circuit

In order to adapt to the data provided in multiplex mode on the data multiplex line 4-, the Contents of the counter 117 in a memory 108 with direct access stored at the end of each group of bytes on the trunk. The memory 108 has twelve storage locations and is addressed by the channel number, so that it is ensured that the contents of the counter 117 are s.tets for different channels stored in separate memory locations. At the beginning of each new group of bytes, the counter is turned off with the output preloaded the currently addressed storage space of the memory. According to FIG. 11, the control logic also has another counter 119 whose output results in a byte address that is used to address the key memory in the comparison units 5, as described below. This counter is filled with a reference value from a memory 120 with direct access, when an identify signal occurs. The memory 120 is addressed by the ■ channel number, so that for different Channels different reference values can be used.

It is also used to adapt to the multiplex mode Data a memory 121 with direct access, which is addressed by the channel number, for storing the contents of the Counter 119 at the end of each group of bytes, as well as for refilling the counter 119 at the beginning of a new group by bytes-provided. According to Fig. 12, the pick-up point ^ sigial is set

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a bistable circuit 122 which is subsequently reset by the next recording signal. This results in, that the set output of the bistable circuit 122 marks the first recording after a recording point.

by
The mode of operation of the system is controlled by a mode signal which is "1" when normal operation is desired and which is "0" when reminder operation is required. This signal is derived from a register 124 which has a plurality of individually addressable bit storage locations, one of these storage locations being selected by the number of channels. As a result, some channels work in listening mode, while others work in reminder mode. The output of the bistable circuit 122 and the mode signal are combined in an OR gate 125 to form a signal referred to as the reminder signal. This signal indicates to the comparison units whether they should remember the results of the comparisons or not: In normal operation the reminder signal is always "1", which indicates that no reminder occurs, while in reminder mode the reminder signal is "0", except for the first recording after an aujjpunkt when, as mentioned above, a reminder is not required.

The control logic circuit of Figures 7-12 contains several bistable circuits 110, 111, 100, 101, 102, 105, 107 and 122, which contain control information that is located on a specific data channel. Because of the multiplex operation of the channels, the states of this bistable circuit must end of each group of bytes from a particular channel and then filled again with information relevant to the next channel is appropriate and appears on the trunk. The way in which this is done is in! "Ig. shown. A memory .126 with direct access has twelve word storage locations, one for each channel, the are addressed by a channel number. When an end GOB signal occurs, the contents of the bistable switch to which

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"is referred to above" in the currently addressed word of the memory 126 is written. Conversely, if a start GOB signal occurs, the contents of the currently addressed Word gated into the appropriate bistable circuits before the beginning of the first byte in the group. To In FIG. 14, the control logic also generates a set of clock signals called Clocks 1 and 2 and Clocks A, B, 0. the Clocks 1 and 2 are converted from the basic clock signal Ck with the help of a tapped delay line 127 derived, the delay for clock 2 being greater. The measure A becomes from the measure 2 via an AND gate 128 from &, which is blocked if the length signal is available. Measure B is derived from measure 1 via an AND gate 129, but both during recording the identifier as length bytes suppressed. The clock O is also derived from the clock 1 via an IMD gate 130, which is only is made effective when the length signal is present. Another signal, called the preset SLgnal, is derived from the clock 1 via an AND gate 131, which is only is made effective when the identify signal is present.

Comparison units

Figures 15 and 16 show one of the comparison units 5 in Detail. Referring to Figure 15, each comparison unit has a direct access memory 230 called a key memory and which holds the key values for comparison with the incoming data on the trunk line 4-. Any keystore holds 256 bytes and is addressed by the byte address from the control logic. The format of a key value in Key memory is identical to that of a data field according to Fig. 6, i.e. it has an identifier byte, a length byte and a Value part of variable length. Any key spear can contain several such key values, each key value is in sequential byte locations within the

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Key memory stored, starting with a reference value address "which corresponds to one of the reference value addresses that are held in the reference value memory 120 (Fig. 11).

When a data field is thus output via the data bus 4 arrives on a particular channel, a key value corresponding to the channel from the key memory in each comparison unit (one byte at a time) is in alignment with the Data field read out, i.e. the identifier byte of the key value is read out at the same time as the identifier byte of the data field appears on the multiple line, etc.

Each comparison unit contains another similar memory

229 with direct access called mask memory and which is also addressed by the byte address. The output of this memory is in a set of UITD gates 228 with the Data bytes are combined on the multiple line 4-, and the result is given to an input of a comparison device 231, the other input of which is the output byte from the key memory

230 records. The mask memory thus makes it possible to cover selected parts of a data field, i.e. to ignore them.

In operation, the key store and the mask store can be updated as is done by the control processing means is required. Db comparison device

231 compares the two input bytes and generates one of three output signals, depending on whether the first input byte is greater than, less than or equal to the other byte.

According to Fig. 16, a bistable becomes a bistable at the beginning of each data field Latch 232 set by the preset signal. At the same time, the identifier byte of the field is matched with the corresponding Byte of the key value compared. If the two bytes do not match, a NAND gate 227 is reversed at clock A through The value of the equality output of the comparison device 231 is made effective and causes the latch 232 to be reset It will then remain reset until the beginning of the

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next field and this "effectively ends the comparison for the Field.

However, if one assumes that the identifier byte matches, "the Latch 232 is set and the comparison continues. That Length byte is ignored because clock A is suppressed; but if a byte in the value part of the field does not correspond to the corresponding byte is adjusted in the key value, the lock 232 at Clock A reset. However, before this occurs, the output of the comparison device is (greater or less than) by the Clock B via NAND gates 233 and 234 into one of the two bistable Latches 235 inid 236 gate. On the other hand, if none If a mismatch occurs during the comparison process, the latch 232 is set anyway and the output of the comparison device becomes "equal" when the end of the field occurs. This results in the activation of another NAND gate 237 » whereby another latch 238 is set. The three locks 235) 236 and 238 are collectively referred to as the field locks and are all reset at the beginning of the first recording and finished by the end of each recording for the start of the next recording.

Since clocks A and B are both suppressed while the length byte L of each field is being recorded, this byte becomes effective is ignored for comparison purposes and cannot affect latches 232, 235, 236 and 238.

The operation of the comparison unit, as far as it has been described so far, is summarized as follows: At each At the beginning of the data field, the identifier byte is compared with that of the stored key value. This is done for each field repeated in the recording. Remain at the end of the recording thus, if none of the fields in the record have a ,. Identify adjustment has resulted in all unset. This condition thus indicates that the type of field in question does not exist in the record. However, if one of the Fields (with the exception of a null field) an identifier adjustment

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the value part of this field is created with that of the key value compared. The result is saved in the field locks and remains there until the end of the recording.

The length of each field comparison (i.e. the number of bytes that the keystore stores to compare with the data field read out) is determined by the length byte L of the data field, as this byte defines when the end of the field signal is produced. For example, if the key value in the key store has a length of eight bytes and the length of the data field is only six bytes, only the first six bytes of the key value are used for comparison and the two remaining neglected.

Another lock 259 is assigned to the field locks. The lock 239 is also reset at the end of each recording, and when a Hull field occurs with an identification I which is adapted to that of the selection key. This is achieved by a KAH ^- D gate 240, which receives the set output of the latch 222, the clock 0, and the zero signal from the control logic.

The contents of the various locks 232, 235, 236, 238 and 239 in the comparison unit are stored in a memory array with direct access similar to that of Fig. 13 is stored at the end of each group of bytes and at the beginning of each reloaded to a new group.

When latch 239 is reset, three AND gates become 241, 242 and 243 made effective, which interlocks the output of the field with the data input of a memory 244 with direct Connect access. The memory 244 has twelve word storage locations each comprising three bits and is defined by the channel number addressed. The output from the currently addressed word of this memory is given to the SEU and provides the results of the the comparison carried out by the comparison unit.

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The write enable input of memory 244 is with the output an AND gate 247 connected; an input of this AND gate 247 receives the end of recording signal from the control logic, and the other input is the output of an OR gate 248. The OR gate has five inputs, four of which with the "set" outputs of the three field latches and the latch 239 are connected, while the fifth picks up the reminder signal from the control logic. The output of the gate 247 results after the Inversion also provides a signal to reset latches 235, 236, 238 and 239 at the end of each recording.

The operation of the comparison unit in the two operating modes will now be described below.

In normal operation, memory is always equal to "1". Thus, the output from the OR gate 248 is always "1" and thus becomes the AND gate 247 enabled at the end of each record, so that a write enable signal in memory 244 is asserted will. Since zero fields are not used in this mode of operation, latch 239 remains reset and makes the AND gates 241, 242 and 243 are effective. As a result, in this mode of operation, the memory 244 is at the end of a recording is brought up to date by transferring the contents of the field links into it.

In the reminder mode, reminder is again equal to "1" for the first recording after a recording point, so that the memory 244 is brought up to date in the normal way. However, reminder becomes "0" for subsequent recordings. When a Adjustment for the identifier bytes of one of the fields in a subsequent record is obtained, becomes one of the Latches 235, 236, 238 (or the zero latch 239 if the field is a zero) is set and OR gate 248 is thereby enabled. In this way, the memory 244 is am End of recording brought up to date (in the case of a zero field, AND gates 241-243 are disabled and memory 244 is updated by zeros

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which indicates that the field in question "does not exist"). On the other hand, if no identification match is obtained during the scan of the record, the field latches and the zero latches remain reset and therefore the OR gate becomes 248 and hence the AND gate 247 made ineffective. It follows that the memory 244 is not brought up to date, but retains the result of the comparison from the previous recording. The output of the comparison unit is, as shown by SEU, exactly the same as if the field that generated the identifier match in a previous record is in the subsequent one Recording would have been repeated.

It follows that the use of the "reminder" mode enables a file that has been compressed in the manner described in connection with Tables 2 and 4 to contain the gives the same results from an associative search operation, as if the uncompressed form according to Tables 1 and 5 are available would.

The system also provides the option of comparing two data fields with different identifier bytes occurring in the same record. This possibility can for example Used in a credit file system to keep track of the total ongoing expenses of each customer with his or her personal Compare credit limit. This possibility is called a substitution search operation denotes and uses a pair of comparison units, hereinafter referred to as comparison units A and B. whose key memory begins with the identifier bytes of the two fields to be compared with each other are filled.

The substitution search operation is controlled by a logic circuit assigned to the two comparison units A and B. and shown in FIG. This logic circuit and the two comparison units are expediently on the same basis Control panel arranged.

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To. Figure 17 contains the substitution search logic for a pair of bistable Circuits 250 and 251 of D-type, both through the output an AND gate are clocked, which receives the length signal and the clock 1. The bistable circuit 250 takes as Input the set output of the bistable circuit 252 (Fig. Ι in the comparison unit A; this signal is referred to as "present (A)". Similarly, the bistable circuit takes 251 the corresponding output "present · (B)" from the comparison unit B on.

The substitution search operation is carried out by a substitution signal initiated that the two AND gates 253, 254- together with the Bar B is abandoned. The gates 253, 25 ^ - also take the set ones Outputs of the bistable circuits 250, 251. The outputs of these gates are signals that act as write control signals (B) and write control signal (A).

According to Fig. 18, the write control signal (A) is a NOR gate 255 abandoned, the output of which is given to the write control connection WE of the key memory 230 of the unit A. This makes possible, that data into memory from the data bus 4- can be written in via an OR gate 256. (The other input to NOR gate 255 is an change signal that uses when the memory is to be brought up to date from the control processing device, the data to the update the_ memory to OR gate 256 be abandoned via a path 257 if there is no data on the data multiplexing line 4-). The write control your signal (B) is posted to unit B's key store in a similar manner.

According to Fig. 17, the outputs of the bistable circuits 25Ο, 251 corresponding NAND gates 258, 259 also given up, each of which also receives the substitution signal and the preset signal. The outputs of gates 258, 259 become corresponding abandoned bistable circuits 260, 261 of the D-type,

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their outputs in turn to the corresponding NOR gates 262, 263 are fed. These NOR gates also take an input from an AND gate 264, which are given as inputs: The substitution signal, the length signal, measure 2 and the inverse Values of the outputs of the bistable circuits 260, 261. The outputs of the NOR gates 262, 263 become the reset inputs of the bistable circuits 232 (Pig. 16) in the units A and B abandoned.

The operation of the system in the substitution search mode is described below. Be at the beginning of every recording all bistable circuits 250, 251, 260 and 261 by the inverse The value of the end of recording signal is reset.

Assume that an identifier match is indicated by unit A first. This results in the bistable Circuit 250 is set at clock 1 in the following length byte. The AND gate 253 is thus made operative and generates a ! Sequence of write control (B) signals, one for each clock B pulse, whereby the value part of the data field of of the data multiplex 4- is written into the key memory of unit B. Since both bistable circuits 260 and

261 are reset, AND gate 264 is enabled on clock 2 during the length byte; this will make the NOR gates

262 and 263 are made effective and thus the bistable circuit 232 reset in unit A. This completes all further comparisons locked in unit A during this data field. At the beginning of the next data field, a preset signal is given Gates 253, 259 given up and since the bistable circuit 250 is still set at this point, the gate 258 becomes effective made and the bistable circuit 260 set and remains set until the end of the recording. Gate 262 therefore becomes activated and blocks all further identification adaptations in unit A until the beginning of the next recording. the bistable circuit 250 is reset with the next clock 1 pulse and prevents the generation of further write enable (B) signals.

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It is now assumed that an identifier adaptation by the Unit B is displayed for a subsequent data field in the same record. There will therefore be a comparison between made the field value stored in the key memory in unit B and the value part of this subsequent data field, and the result of this comparison is stored in unit B's field locks in the normal manner.

When the identifier match is indicated in unit B, the bistable circuit 251 is set and causes write enable (A) signals are generated so that the second monetary value is written into the memory of the unit A. this happens but only in order to maintain the symmetry of the circuit, and the stored value is not actually used by the unit A. used because this unit is now prevented from making further comparisons. The bistable circuit 261 is at the end of the field and a reset ^ B) signal that blocks all further comparisons in unit B until the end of the recording, generated.

Thus, at the end of the recording, the memory 2ΡΛ of unit A (the first unit to receive an identification adjustment) is updated with a "! Not present" display (ie all zeros), while memory 24 of unit B is updated the result of the comparison of the two monetary values is brought up to date. These memories are then available for the search evaluation unit (SEü) in the manner described above.

Since the circuit of FIG. 17 with respect to the unit A and the Unit B is symmetrical, a similar result would be obtained if unit B was the first unit to achieve a Identifier adaptation would be. In this case, unit B gives the "view available" display and unit A gives the result of the value field comparison.

In accordance with the multiplexing of the data, the contents of the latches 250, 251, 260 and 261 are stored in their own memory

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with direct access at the end of each group of bytes in a manner similar to that described in connection with FIG. 13 " .

In practice, the timing of the comparison units and the associated logic is one byte with respect to that of the multiplexer delayed so that delays in the signal propagation time etc. are possible. Thus the control signals must channel number, GOB start and GOB end, which get from the multiplex device to these other units, are delayed by this amount. Because The comparison of the delays also shows that the number of channels given to the spaicher 244 (FIG. 16) is reduced by about 1 1/2 Bytes should be delayed.

An illustration of the use of the key memories in the comparison units is given below in connection with FIG. 19 given. In this figure, the key memories of the sixteen comparison units are shown side by side, and each Column represents a key value. Assume that information from four files is to be processed, each File has a different set of key values. Four reference values DO-DJ are therefore stored in the reference memory 120 (Fig. 11) entered. These values subdivide the keystore into four areas (not necessarily the same size), one for each file, as shown in FIG. Each key store can therefore hold four key values (each small rectangle in Fig. 18 represents the range available for a key value).

In addition to the aforementioned "horizontal" subdivision of the key memory, the comparison units can also be called "vertical" divided into groups. In this example the units are divided into four groups of four units each divided as shown by the thick vertical lines. Each group of comparison units can then can be assigned to a separate search output in the same files. It follows that in this example the horizontal «

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and vertical subdivision together allows sixteen separate search tasks to be performed simultaneously, four tasks each for each file, can be done.

The division of the comparison units into groups is determined by the manner in which the search evaluation unit the Processed results from the comparison units.

Search results

The search evaluation unit (SEU) is described in detail below in Connection described with Figures 20-25.

20, the SEU has 16 processing elements P (O) -P (15), one for each comparison unit 5 ». The processing elements have a common control unit 300, selection function unit 301 and quorum (quorum number) functional unit 302. Each processing element can access data Transfer the following element one after the other (the last element in the sequence can in turn be connected to the first, so that a closed circle of elements is formed).

21 shows the structure of one of the processing elements P (N). This element has three latches 303-305 that the record relevant information (greater than, equal to, less than) from the result memory 244 (FIG. 16) of the associated comparison unit. These results are in the locks clocked in by an evaluation start signal.

The processing element has an instruction memory 306 which carries one or more sequences of microinstructions nine bits each, up to a total of 32 macro instructions can hold. The maximum length of a given sequence is 15 macro instructions. The reason for this is that the

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longest sequence within sixteen byte periods (the minimum Record length) must be completed.

Macro instructions are taken from the instruction memory 306 one by one are read out from the control unit 300 by instruction address signals and are given to a logic unit 307. Of the The output of the unit 307 is a binary signal E (N), which is in a Lock 308 can be stored, which is referred to as the result memory. The logical unit takes as data inputs on: The contents of the three latches 303-305, the output S (N) from the result memory, and the output E (N-I) the logical unit of the preceding processing element P (N-I).

22 shows the logic unit 307 in detail. Appropriately the symbols bl-b9 are used to represent the nine bits of the current microinstruction, while the symbols " as "," less than "and" equal to "represent the outputs of the respective latches 303-305.

The unit has two modes of operation. In the first operating mode, which is determined by b5 = 0, the output E (N) as follows:

b8, b9 E (N.

00 S (N) ΌΉΌ Χ 01 X 10 S (N) 11 S (N) OR X

where X is an OR function of the comparison information from the Represents latches 303-305. The exact nature of this OR function is determined by bl-b3. Even if b4 = 1, the output is "Select" from the selection function unit in this OR puncture locked in.

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Bit b7 = 1 causes the result R (N) to be saved in the result memory is written, while bit b6 = 1 causes the output S (N) of the result "memory to be inverted (compare FIG. 21).

Referring to Fig. 23, the selection function unit 301 has a memory 309 with direct access to, which has 32 word locations that are addressed by the instruction address from the control unit. Each of these memory locations contains an address that specifies one of the processing elements P (N) and is decoded in such a way that that the result memory output S (N) of this element is selected as the output signal "Select". This signal will abandoned all processing elements, as ■ above in connection explained with FIG. 22.

The selection function unit thus provides the possibility of information from the result memory of any selected processing element to the logical unit of any to transfer other element.

According to FIG. 24, the quorum functional unit has a memory 310 with direct access to, which has 32 word storage locations that are addressed by the instruction address. This unit also has a multiplexer 3H, one of the outputs S (0) -S (15) from the processing elements in accordance with the contents of a four-bit counter 319.

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Since any sequence of microinstructions from the processing elements is carried out, a corresponding sequence of memory locations in memory 310 is addressed during operation. The first store place of this sequence is designed so that it contains a threshold value of seven bits, while the subsequent memory locations a set of

During the first macroinstruction in the sequence by the processing elements is carried out, the threshold value is read out from the memory 310 and introduced into a register 312. The instruction address is then incremented, the counter 319 on Hull is set and the multiplexer 311 made effective.

While the next micro instruction is carried out in the sequence the first place value of the memory 310 is read out, while the multiplexer 311 simultaneously selects the output S (O). When S (O) = I, a set of AND gates 313 becomes activated, whereby the place value is gated into an accumulator register 314- where it corresponds to the contents of the accumulator is added (assuming it was initially set to zero).

This process is continued for each subsequent address, so that the outputs S (O), S (I), S (2) etc. one after the other with their corresponding values are logically switched to UKD and can be added to the total in the accumulator.

The accumulated total value is continuously compared in a circuit 315 "with the threshold value in register 312, and if the A quorum signal is generated. As indicated in Fig. 23, the signal is available for selection by the Selector function unit in the same way as each of the result memory outputs to disposal.

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The quorum function thus gives the possibility of a number of to add the evaluated results from the individual processing elements and to determine whether the sum is a Exceeds threshold. Not all processing elements have to contribute to this total: The rankings of the elements that are not required are set to Full.

Each result memory must be programmed in the required way. before it is used by the quorum function. The evaluation sequence for the processing element P (N) must not take longer than 3ÜT + 1 macro instructions. For example, may the evaluation sequence for the processing element P (O) can only break one instruction. Because the quorum function is the equivalent from N + 1 microinstructions for evaluating the outputs The quorum output can take up N processing elements for these N elements up to the N + 2 th macro instruction of the Selector Function Unit cannot be selected.

As an example for the application of the quorum function it is assumed that that it is necessary to determine whether the results of the evaluations made by any four of the first eight processing elements are real eight elements are all set to one, the remainder is zero, and the threshold is set to three. In this case the evaluation of the quorum function is completed after nine microinstructions, and the quorum delivery can be completed by the tenth Macro instruction of the selection function.

Fig. 25 shows the control unit 300. The unit has a Memory 316 with direct access to which is addressed by the channel number and which in each memory location is the start address • contains a microprogram sequence that corresponds to the channel in question. Each memory location also contains a sequence length. . ·

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The operation of the control unit is carried out by a recording signal initiated, which (provided that the SEÜ is not stressed too much) causes an instruction counter 317 with the corresponding start address is provided for the channel in question, and causes a sequence length counter J18 with the corresponding sequence length is provided. The instruction counter is then increased so that a sequence of instruction address signals which is transmitted to the processing elements, the selection functional unit and the quorum functional unit will. At the same time, the length counter is reduced and when it reaches zero, the sequence is ended and a ready signal is given submitted. This indicates to the retrieval unit 10 (Fig. 1) that the evaluation of the results for the record in question is now complete and available for inspection in the result memories of the processing elements.

Since the search evaluation unit (SEU) consists of a number (16) processing * elements that work in parallel, it has a significant processing capacity because of a number of different work processes performed for each microinstruction step can be. In addition, the processing elements can be divided into groups, with each group having a separate rating drinking would perform. For example, consider the arrangement mentioned in connection with FIG. In this case it will be the processing elements are divided into groups of four, each group taking the comparison information from the corresponding one Group of keystores rated. In this example, each processing element contains four sequences of microinstructions. one for each file corresponding to the four horizontal divisions in FIG. 19.

Some possible modifications

For example, the number of data channels that are operated with one another using the time division multiplex method can be changed. The limitation is that the comparison units in the

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Must be able to handle all of the information. Similarly, the number of comparison units can also can be changed according to requirements.

Another possible modification is to replace the double buffer arrangement in each channel unit with a memory of the type "first-in first-out ripple through ¹ * /. In another possible modification, the comparison units can be modified so that the comparison of a given data field is terminated when the length byte of this field is smaller than the length byte contained in the key memory, which is desirable in some cases. Output of the comparison device 231 (FIG. 15) are operated together in an AND circuit, that they are operated in an OR circuit with the output of the gate 227 (FIG. 16), and that the result is used to reset the latch 2J2.

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it

Claims (6)

25A705? .5.9. 1975 W / He I / p 8269 Patent claims: Data processing device having a data storage arrangement and a plurality of comparison units which operate in this way can be that they make comparisons between a data printout which is read out from the memory arrangement and corresponding Performs key values, characterized in that an evaluation unit (7) for logically combining the results of the comparisons is provided, which has a plurality of stored, program-controlled processing elements (P), one for each comparison unit (5), and that the elements can be operated in parallel so that they perform logical operations on the comparison results from their respective comparison units and on the results of the logical operations of the other elements (P). 2. Data processing device according to claim 1, characterized in that that the evaluation unit (7) has a control unit (300) which is common to all processing elements (P) in order to a sequence of instruction addresses for transmission to all processing elements to generate, with these addresses an in-. instruction store (306) in each element are abandoned, so that a sequence of instructions is read out for execution. 3. Data processing device according to claim 2, characterized in that that the data storage arrangement (1) contains a plurality of data channels and the control unit contains an index table (360) which is addressed by a channel number signal indicating which channel is currently evaluated, so that a start address is obtained for a sequence of instructions which this channel is equivalent to. 4. Data processing device according to claims 1-3, characterized characterized in that the processing elements (P) in a 709824/0416 1547052 5-9.1975 W / He I / p 8269 Sequence are ordered and that each processing element the result of its processing operation to the next neighboring element subsequently feeds. 5 · Data processing protection according to claims 1-4, thereby characterized in that a selection function unit (301) selects the result of the operation of one of the "processing elements (P)" and transfers this result to all processing elements. 6. Data processing device according to claims 1-5, characterized characterized in that an interrogation engine (302) evaluates a sum of the results from a selected combination of the processing elements (P) and compares this sum with a threshold value. 7 · Data processing device according to claims 5 and 6, thereby characterized in that the selection function unit (301) is operable to obtain the valued sum from the quorum function unit (302) and transmits them to all processing elements (P). 709824/0 ^ 16