DE2526451C3 - Message transmission method and double push-pull modulator for its implementation - Google Patents

Description

The main application relates to a method for the additional transmission of pseudo-ternary coded digital Signals over at least part of a plurality of symmetrical or coaxial line pairs one for the transmission of voice-frequency and carrier-frequency analog signals set up with a cable Transmission range of the carrier-frequency signals, which is the baseband of the digital signals in terms of frequency overlaps and the pseudo-ternary on the transmitting side

encoded digital signals in η (with η = 1, 2, 3 ...) stages by multiplication with one or more clock signals acting as carrier waves, one of which has a pulse repetition frequency equal to half the bit repetition frequency of the

ho has the pseudo-ternary coded digital signals, and from the new pseudo-ternary encoded digital signal resulting from the frequency conversion Main energy range, which is above the clock frequency, is screened out and transmitted.

ds The subject after the main registration is in briefly explained below. For the additional transmission of digital signals together with carrier frequencies Signals via symmetrical carrier frequency widespread

kehrskabel becomes a pseudo-ternary coded digital one Input signal with the bit rate / "o in one digital modulator is modulated with a clock pulse acting as a carrier, the pulse repetition frequency of which is the corresponds to half the bit rate of the pseudo-ternary encoded digital input signal.

A pseudo-ternary coded digital signal is generated at the output of the digital modulator. which can also be regenerated in this form. For signal transmission over the transmission path, for example the symmetrical wide area cable, the new pseudo-ternary coded digital signal becomes the components in the frequency range between 0.5 f ₀ and 1.5 / "0, i.e. 0.5 and 1.5 times the This is the upper sideband resulting from the modulation and represents the actual transmission signal. This transmission signal is distorted by the attenuation of the cable, which increases with increasing frequency. Before regeneration, it must therefore first be equalized and converted back into a regenerable signal will.

The equalization takes place in a known equalization network with a connected amplifier, the conversion into the regenerable signal can either be done by a new modulation with a Oscillation with a frequency equal to half the bit rate, which can also take place in two stages, or by recovery and addition of the lower sideband.

Investigations have led to the knowledge that for an optimal signal-to-noise ratio at the input of a regenerator, the recovered regenerable signal has a sinusoidal transition between two immediately successive pulses and when jumping from logic level "0" to logic level "1" or from logic level "1" must have ^{a sinus 2} -shaped curve to the logic level "0". In order to achieve this, the transmission pulse shape that occurs at the output of the digital modulator, the cable attenuation and the equalization function must be coordinated with one another. Since the cable attenuation is usually fixed, there are only options for coordination with regard to the equalization function and the form of the transmission pulse. It has been shown that the least amount of effort for line equalization is achieved and the least necessary gain for the amplifier coupled to the equalizer network is achieved if the total attenuation from cable attenuation and equalizer attenuation increases with increasing frequency -

network that does not completely cancel out the low-pass filter character of the cable in the transmission range. Such an equalizer also has the smallest effective noise bandwidth, but it can only together with a suitable transmission pulse shape

ίο use.

The object of the invention is therefore to provide a transmission method of the type mentioned at the beginning frequency-wise converted pseudo-ternary coded digital signals, in which the cable attenuation

is, together with the equalizer network on the receiving side, results in a low-pass filter and the pulses to be regenerated ^{should have a sinusoidal or sinus 2} -shaped course, a suitable transmission pulse shape and methods and arrangements for their generation

2o find.

According to the invention, the object is achieved in that the pulses of the resulting from frequency conversion new pseudo-ternary coded digital signal have a duty cycle of less than 1: 1.

2_s In the following, for the sake of simplicity, the Pulses of the new pseudo-ternary coded digital signal also referred to as the transmission pulses. Under the duty cycle is the ratio of the pulse duration to divided by the number of pulses per bit

\ o Bit duration understood. The advantages of the method according to the invention are in particular that there is a considerable overall reduction in the effort involved in the transmission of the pseudo-ternary coded digital signals and that the zero point distribution in the frequency-dependent power density distribution of the transmission pulses up to about the fourth zero point of the zero point distribution in the frequency-dependent power density distribution of the Corresponds to received pulses.

A particularly little effort and in many cases feasible variant of the method according to the invention is characterized in that a simple Frequency conversion is made with a carrier wave and the power density distribution i

of the new pseudo-ternary coded digital signal for random Pulse trains depending on the normalized frequency of the relationship

S [U) =

( cos (1 -A) -HU- cos Bn- U \ ² {■■■■ ■■ ,, J

(i + cos 2.τ

is sufficient and A is equal to the sum of the pulse gaps at the beginning and at the end of a bit transmitting a logical "one", B is the pulse gap between the two individual pulses of a bit transmitting a logical "one" and the normalized frequency Ω = f: fa and thereby / Ό is the bit rate of the original pseudo-ternary encoded digital signals and / "is the frequency under consideration in each case.

With a view to the lowest possible interference of the low-frequency and carrier-frequency signals transmitted simultaneously over the transmission link, it is advisable to achieve a greater frequency difference between the baseband and the upper sideband of the pseudo-lernally coded digital signal by means of an n-level frequency conversion. Since, in addition, a direct current-free transmission is simultaneously applied, there is a variant of the method according to the invention in which the new pseudo-ternary coded digital signals resulting from frequency conversion contain 2n successive pulses of alternating polarity in 2n identical bit sections in each bit and each of the successive ones lowing pulses is arranged symmetrically around the center of one of the bit sections.

Another, somewhat simplified variant de; The method according to the invention results from the fact that: the new pseudo-ternary coded digital signals per Br, created after a simple frequency conversion from mutually identical pulses alternately ci

LH- * '

(ο

7 8

There is polarity and the relationship for the frequency-dependent power density distribution 55

, 'COS I 1 -. ·! I rr Il - ■ COS .4 π <J \ ²

Ss [U) = ( _n ) Il + cos 2.7. '.')

enough.

The setting of the clock ratio of the transmission pulses, i.e. the pulses of the new pseudo-ternary encoded digital signal can, depending on the generation of this signal, in a simple manner Use of input signals can be made that already consist of pulses with a certain Duty cycle exist.

In a preferred variant of the method according to the invention, in which the setting of the pulse duty factor the impulses of the new pseudo-ternary coded digital signal by a further multiplication with an additional unipolar clock pulse with a pulse rate equal to 2n times the bit rate of the original pseudo-ternary encoded digital signal and that the duty cycle of the unipolar clock pulse determines the pulse duration of the output signal, a time and a amplitude regeneration of the impulses. This has the advantage that the phase position of the unipolar clock pulse is freely selectable within certain limits.

A further development of this method according to the invention results from the fact that the phase of the additional unipolar clock pulse is set so that during the occurrence of a single pulse this Clock pulse neither a change of state of the original pseudo-ternary coded digital signal nor one of the carriers occurs.

A modulator according to the invention for carrying out a preferred variant of the invention Method in which the setting of the clock ratio of the pulses of the new pseudo-ternary encoded digital signal by a further multiplication with an additional unipolar clock pulse results by the fact that a double push-pull modulator consisting of a gate network and a transformer is provided, which encoded a first pair of input terminals for the original pseudo-ternary digital signal, a second input terminal pair for a first carrier, a third input terminal for the unipolar clock pulse, eight NAND gates each with two inputs and one as output transformer contains acting push-pull transformer and the one with the first input of the first input terminal pair the first input of the first NAND gate and the second input of the third NAND gate is connected, in which the second input of the second NAND gate and the second input of the fourth NAND gate is connected to the first input terminal of the second input terminal pair is the second input of the first NAND gate and the first input of the fourth NAND gate is connected to the second input terminal of the second input terminal pair, the first input of the second NAND gate and the first input of the third NAND gate is connected, in which the outputs of the first and the second NAND gate with the inputs of a fifth NAND gate and the outputs of the third and fourth NAND gate are connected to the inputs of a sixth NAND gate, in which the output of the fifth

15th

40

55 NAND gate is connected to the first input of a seventh NAND gate and the output of the sixth NAND gate is connected to the first input of an eighth NAND gate, in which the second inputs of the seventh and eighth NAND gate to a third input terminal for a unipolar clock pulse and the outputs of the seventh and eighth NAND gates are connected to the outer connections of the primary winding of the output transformer and in which the two connections of the secondary winding represent the output connections of the modulator and the center tap of the primary winding of the first transformer is connected to a supply voltage is.

Because of its uniform structure, this modulator is made up of eight NAND gates, each with two Inputs easy to implement by replacing the push-pull output transformer with an electronic one Push-pull circuit is also used in these and also in the two modulators described below easy integration possible.

A simplification and cost reduction of the modulator described above through use of four NAND gates each with three inputs leads to an arrangement in which a digital double push-pull modulator is provided, which has a first pair of input terminals for the pseudo-ternary encoded digital signal, a second pair of input terminals for the clock signal acting as a carrier and a third input terminal for the unipolar clock pulse, four NAND gates with three inputs each, contains two AND gates, each with two inputs and one output transformer, in which the the first input terminal of the first input terminal pair, the first input of the first NAND gate and the first input of the third NAND gate is connected, in which the second input of the first Input terminal pair with the third input of the second NAND gate and with the third input of the fourth NAND gate is connected, in which the first input terminal of the second input terminal pair with the third input of the first NAND gate and with the first input of the fourth NAND gate is connected, in which the second input terminal of the second input terminal pair with the first input of the second NAND gate and with the third input of the third NAND gate is connected and in which the third input terminal with the second inputs of the first, second, third and fourth NAND gate, in which the outputs of the first and second NAND gates with the two inputs of a first AN D gate and the outputs of the third and fourth NAND gate are connected to the inputs of a second AN D gate, where the outputs of the first and the second AND gate to the two outer connections of the primary winding of the second output transformer are connected and in which the center tap of the primary winding with a Operating voltage and the two connections of the secondary winding of the output transformer with the Output terminals are connected. A further development of this arrangement with a view to use

■ 7

i Cl

Commercially available TTL components that contain AND and NOR gates are used instead of the four NAND gates at the input four AND gates and instead of the two AND gates two NOR gates if otherwise identical Links.

A further reduction in the cost of the modulator results from the fact that two AND gates can be used with three inputs each. The result is a structure in which a digital double push-pull modulator is provided, which encoded a first pair of input terminals for the original pseudo-ternary digital signal, a second pair of input terminals for the clock signal acting as a carrier and a third Input terminal for the inverted unipolar clock pulse are provided, with which four NAND gates two inputs and a first and a second AND gate each with three inputs and one Push-pull transformers are included as output transformers and with the first input terminal of the first input terminal pair the first input of the first N AND gate and the first input of the third NAND gate is connected, in which the second input terminal of the first input terminal pair to the second input of the second NAND gate and to the second input of the fourth NAND gate is connected, in which the first input terminal of the second input terminal pair with the second Input of the first NAND gate and is connected to the first input of the fourth NAND gate, at the second input terminal of the second input terminal pair with the first input of the second NAND gate and is connected to the second input of the third NAND gate, in which the Outputs of the first and the second NAND gate with two inputs of a first AND gate and the two outputs of the third and fourth NAND gate with two inputs of a second AND gate are connected, in which the third input terminal for the inverted unipolar clock pulse with the second inputs of the first and the second AND gate is connected and in which the outputs of the first and the second AND gate, each with an outer connection of the primary winding of the Output transformer is connected, while the center tap of the primary winding with a terminal for a supply voltage and the two connections of the secondary winding with the outputs of the double push-pull modulator are connected.

The invention is explained in more detail below with reference to the drawings. It shows

Fig. 1 with power density distributions as a function of the frequency for different transmission pulses different tactile conditions,

Fig. 2 shows a general case of digital modulation of impulses,

3 shows the two-stage digital modulation of a signal with two carriers according to an inventive method Proceedings,

F i g. 4 a first digital double counter clock modulator according to the invention, which is constructed with the same gates,

FIG. 5 shows a further double push-pull modulator according to FIG Invention and

F i g. 6 shows a third double push-pull modulator according to the invention, which is further reduced in terms of complexity.

In FIG. I, the power density distribution is shown as a function of the frequency for different transmission pulses. These transmission pulses all have a rectangular shape, and the pulse duty factors used are noted on the curves. The three families of curves marked I, II and III represent the different sidebands of the transmission pulses marked with the respective duty cycle. The bottom curve in each of the three areas represents the power density distribution Si; as a function of the frequency for the desired received pulse shape is that of the relationship

3 Γ7

cos - .7 iJ - cos U 2 <J {\ -iß)

(1 + cos2.-i.01

enough. It can be seen that the power component at high frequencies with decreasing duty cycle increases, this is physically due to the greater proportion

yo can be explained in shorter transmission pulses at higher frequencies. Furthermore, the lowering of the high frequency components in the transmission pulses required by the frequency-dependent cable attenuation and the equalizer to generate the desired ones is clear

reception pulses can be recognized. The functions are in the representation in each case shown normalized to the same power density at these frequencies. The reference point OdB corresponds to the normalized power density for the normalized frequency ß = 1 and a pulse duty factor the transmission pulses of 1: 1. A random distribution of the Pseudo-ternary coded digital signals assumed, with periodic sequences other power density distributions result.

4S It can be seen that for the same peak transmit power i.e. the power of the fundamental wave of a permanent 1 sequence all power density distributions of the transmission pulses run through the same reference point at Ω = Ι. Around To achieve this, one must move from one

so transmit pulse shape to another the amplitude de; Transmission signal can be corrected. In Table 1 shown below, the correction quantities are for i various square-wave pulses on the transmit side with different duty cycles shown, besides ss are for a peak transmit power of 5 mW (+ 7 dBm the required amplitudes of the square-wave signals on the transmitter side are given at a resistor of 75 ohms ben.

Duty cycle of the square wave transmission pulses 1: 1 2: 3 1: 2 1: 3

Relative power density at Ω = 1 in dB for the same power at 0 +2.27 +3.01 +3.5:

Relative power density at Ω = I in dB for the same transmit amplitudes 0 -3.52 -6.02 -9.5 '

Correction quantity of the rectangular amplitude in dB for the same transmission 0 1.25 3.01 6.02

Top performance

Amplitude of the PCM transmission signal for a peak transmission power 0.68 V 0.78 V 0.96 V 1.36 A.

of + 7 dBm at R = 75 Ω

^ν -ί ^λ .

S3 be ear

In practice it has been shown that transmission pulses with a pulse duty factor of 1: 2 are the easiest to achieve ■ ealize. As also from FIG. 1 can be seen, the energy content of the is in the frequency range from 0 to 3.5 Ω, the first lower sideband related to the energy content of the s in the frequency range of 0.5 up to 1.5 Ω lying first upper sideband with increasingly narrow transmit pulses smaller and smaller. As a result, a carrier frequency signal transmitted, for example, in the frequency range from 0 to 0.25 Ω is from the simultaneously transmitted digital pulses are less disturbed, so that the demands on the usually very complex transmission filters can be reduced accordingly. For transmit pulses with a test ratio of 1: 2 results in a reduction of the interference by 3 dB compared to transmission pulses with the Duty cycle 1: 1.

In the general case of the digital modulation of pulses shown in FIG. 2, a pseudoternary signal pulse sequence Pi consisting of five bits is shown in the upper line. This signal pulse sequence Ρ can assume the amplitude values +1, 0 and -1. The pulse repetition frequency ί is equal to 1: T _1,. In the second line of FIG. 2, a clock pulse sequence P2 acting as a carrier is shown with the same period as the signal pulse sequence Pi; it is also a pseudoternary pulse sequence. With a pulse duration τι of the first signal pulse train Pi results in a pulse duty factor of τ ι to Ti), with a pulse duration T2 of the clock pulse train P2 results in a pulse duty factor of Γ2 to TJ ₁ .

In the third line is the resulting product of the pseudo-ternary coded digital signals (pulse train Pi) with the clock pulse sequence P2.

If the phase shift (φ) between the signal pulse train and the clock pulse train is equal to zero or n \ ■ Tt) (n \ = integer), the product of the signal pulse train and the clock pulse train results in a pulse train Pi · P2 with the same pulse period Tq and a pulse duration τι for each signaling input pulse. The following applies

for each signal input pulse has two output pulses of the same pulse duration (τ. \ - τ *) , it is

The two output pulses for a signal input pulse are always bipolar to one another. At the same time, the polarity of the first signal output pulse for a signal input pulse is always opposite to the second output pulse of the previous signal input pulse if the two successive input pulses are bipolar to one another and separated by an even number of zero steps. The two output pulses per signal input pulse have the same pulse duration, but generally a different period duration (Γι, T ₄ ).

The following applies:

T ₁ , = 7; + V ₄ .

7 "+

7> ⁷ «

For a random sequence of signal input pulses, the signal spectrum has an additional zero position the frequency zero, the energy maximum between the frequency zero and the spectral distribution shows this largest energy maximum for the frequency range

0.5 / ,, < f < 1.5 / ».

Further energy maxima occur in the frequency ranges

r> ■■
or τ; 3 *

■ Ti for Fi < T ₂

2 η, I I

2 h, + 3

I ₂ = - 2, 3

Ti

2 = TO

the output signal sequence arises in the known duobinary code.

In this code, the power density distribution as a function of the frequency of a random pulse sequence has its maximum at frequency zero and the main energy range below fall. For ψ Φ Ο there are significant energy ranges above W2 .

If there is a phase shift between the signal pulse train and the clock pulse train of odd

numerous multiples of, to:

do

(; i, I I)

('S

The frequency-dependent power density distribution is particularly favorable if Γι = τι is chosen. In this case it will

t, v ₄ (;.

2 ', Vi ₁ 2r, V ₁₁

The AiK.gungsimpulsc have ulk · the same pulse period duration. At the same time, the l-nergicmaxim.i for odd / .number /) .. much smaller.

The modulation was described in the 1 lauptanmcldiing for;

Γι = Ty = Ti,

in this way a pseudo-ternary output signal is obtained, i.e. for rectangles with the duty cycle I: I.

I. B JT-

The maximum of the spectral distribution for a simple frequency conversion was in the range

0.5 / c </ < 1.5 /; ,, at / = 0.95 A ,.

The maximum for the frequency-dependent power density distribution of the ideal received pulses according to the However, equalization is / "= 0.9 / Ό, so something below the bit rate, as can also be seen from FIG. 1.

For an optimal equalization function, the pulse duty factor for Γι and τ ₂ must be selected to be less than 1.

Because of the above consideration of symmetry, it is useful here '5

T | = V ₂

to choose.

The pulse duty factors listed in Table 2 are then obtained:

2: 3
1: 3
1: 6

3: 4
1: 2
1: 4

4: 5
3: 5
3:10

5: 6
2: 3
1: 3

1: 2

25th

In FIG. 3 shows the digital modulation of a signal with two clock sequences. The pseudoternary signal Pi present in the AMI code is shown in the top line. In the second line below, a binary clock signal P _{2 is} shown, the modulation product Fi · F ₂ shows the third line. It turns out that when a pseudo-ternary signal present in the AMI code is multiplied by a binary clock sequence with phase coincidence, a recoding takes place, in that the signal sequence Fi appears in duobinary code as the result. In the fourth line from the top in FIG. 3 shows the clock sequence P ₂ again, but with a phase shift φ = ^] / i T ₀ . In this case, the product Fi · F _{2 again} results in a recoded form of the signal sequence Fi, which in this case is present in a code which is referred to as the F-30-D code. In the following lines 6 and 7, a further clock pulse sequence F ₃ and the product Ρ, · P ₃ are shown.

If the product of the signal input pulse train Pi and the clock pulse train P _{2 is} multiplied by a further clock pulse train Fj, i.e. a further frequency conversion is carried out, then the following conditions must be observed:

I. Signal sequence F ₁ :

Duty cycle 1: 1, r, = 7 ,.

Balance sheet queries /

T _n

three amplitude ranges: +1: 0; - 1:
2. 1st pulse pulse

Takipcriode / ,,

two amplitudes I I: 1;

λ 2nd clock pulse P ₃ :

let the pulse duration of the second cycle pulse be the same; the desired pulse duration τ, the Ausyangs pulse train;

2
Clock period / _r , = ^. = -j \,

two amplitude levels: +1: 0:

4. Phasing

T _n

F ₂ versus F, (/ i, + I) ^ («, = 0, 1.2, 3

F, against F ₁ and F ₂ so that in the time in which F assumes the amplitude level + 1, neither F ₁ nor F _{1 have} a zero crossing.

The order in product formation

Px-P ₂ - Pz

is indifferent.

The modulator shown in FIG. 4 has already been described in detail in the description and in claim 7 with regard to its structure. With derr first input terminal pair £ 1 ', Ei "is irr this case supplied with the signal pulse train P \ shown in Fig.3. The signal sequence P \ must to equal pulse polarity can be converted previously into two unipolar pulse trains, the positive pulses of the signal sequence Fi by the first unipolar pulse train and the negative pulses are represented by the second unipolar pulse train. The second input terminal pair £ 2 ', £ 2 "is _{fed the clock pulse train F 2} , which is also converted into two unipolar pulse trains, and the third input terminal £ 3' is fed the clock pulse train F3. The duty cycle of the pulses of the clock pulse train Fj determines the cycle ratio of the output pulses, which is the product Fi · Pi · Pi corresponding to F i g. 3 represent.

In FIG. 5 shows a further double push-pull modulator which is used to save gates contains four NAND gates with three inputs each on the input side. The structure of this modulator is also already outlined in the description and also in claim 8. The inputs of this Modulators correspond completely to those of the modulator according to FIG. 5; same pulse train with the same duty cycle.

Finally, in FIG. 6, a third modulator is shown which, in terms of its complexity, is by the Use of only two AND gates with three inputs is further reduced. Building this Modulator is also already described in detail in the description and also in claim 9, so that a repetition is dispensed with at this point. The connections are the same except for the connection £ 3 'for the unipolar inverse clock sequence Fj the connections of the modulators according to the F i g. 4 and 5.

The possibility of further developing these modulators by replacing the push-pull transformer an electronic push-pull circuit has already been pointed out. From the explanations of the Γ i g. 3 there is also a possibility for the Use of these double push-pull modulators for recoding pseudo-ternary coded digital signals.

I Ik ¹ I / 11 I IiIaIl

Claims (9)

Patent claims: 1. Method for the additional transmission of pseudo-ternary coded digital signals over - '.' At least part of a plurality symmetris · or coaxial line pairs of a cable set up for the transmission of voice-frequency and carrier-frequency analog signals with a transmission range of the carrier-frequency signals that overlaps the ι ο baseband of the digital signals in terms of frequency and in which the pseudo-ternary coded digital signals in η (with π = 1, 2 , 3 ...) stages are converted by multiplication with one or more clock signals acting as carrier waves, one of which has a pulse repetition frequency equal to half the bit repetition frequency of the pseudo-ternary coded digital signals to be transmitted, and from the new pseudo-ternary coded digital signals resulting from the frequency conversion the main energy area. which is above the clock frequency, is screened out and transmitted, according to claims 1 or 2 of HauptipiUi.Mii 25 19 322, dad 11 rchgeke η η / eic h lid that the pulses of the new pseudo-ternary coded digital signal resulting from frequency conversion have a duty cycle less than 1: 1. 2, method according to claim 1, characterized in that a simple frequency conversion is made with a carrier oscillation and the power density distribution 5 of a new pseudo-ternary coded digital signals for random signals resulting from the frequency conversion Pulse sequences depending on the nominal frequency of the relationship S [L ') = cos (l - ■ A) η ■ U - cos Bn- U V D (1 + cos 2 .7 U) is sufficient and A is equal to the sum of the pulse gaps at the beginning and at the end of a bit transmitting a logical "one", ß the pulse gap between the two individual pulses of a bit transmitting a logical "one" and the normalized frequency Ω = ί: ί ₀ and thereby / | i is the bit rate of the original pseudo-ternary encoded digital signals and f is the frequency under consideration. 3. Process according to claims 1 or 2, characterized in that the costs incurred by frequency conversion new pseudoternär coded digital signals in each bit included in consecutive pulses of alternating polarity in In the same bit portions and each of the successive pulses around the center of the Bitabsch; itte symmetrically is arranged. 4. The method according to claims 2 or 3, characterized in that the resulting after a simple frequency conversion new pseudo-ternary coded digital signal per bit consists of mutually identical pulses of alternating polarity and the relationship for the frequency-dependent power density distribution Ss cos (1 - A ).- 1 U - cos A. -7 U) \ - Ss ₁ U) = (,, enough. 5. The method according to any one of the preceding claims, characterized in that the setting the duty cycle of the pulses of the new pseudo-ternary encoded digital signal by a further multiplication with an additional unipolar clock pulse with a pulse repetition frequency of 4s equal to 2n times the bit rate of the original pseudo-ternary encoded digital Signal takes place and that the duty cycle of the unipolar clock pulse is the pulse duration of the output signal definitely so 6. The method according to claim 5, characterized in that the phase of the additional unipolar Clock pulse is set so that during the occurrence of a single pulse of this clock pulse neither a change of state of the original ss pseudo-ternary encoded digital signal nor one the wearer occurs. 7. Modulator for performing a method according to claim 5, characterized in that a double-phase modulator consisting of a gate network and a transformer no (Ui) is provided which has a first pair of input terminals (/: 'l, Ei ") for the original pseudo-ternary encoded digital Signal, a second input cycle pair (/ '2', /: 2 ") for a first carrier, one (> ·, third input terminal (!" V) for ilen unipolar · ;; clock pulse, eight NAND gates (GI ί .. .G 18) with two inputs each and one as output over- (1 + cos 2:, U) Contains slower acting push-pull transformer (Cl) and in which the first input (111) of the first NAND gate (ClI) and the second input (132) of the third NAND gate (G 13 ), in which the second input (122) of the second NAND gate (C 12) and the second input (142) of the fourth NAND gate (C 14) are connected to the second input (Ei ") of the first input terminal pair , in which the second input (112) of the first NAND gate (GIl) and the first input (141) of the fourth NAND gate (C 14) is connected to the first input terminal (El ') of the second input terminal pair, in which with the second input terminal (E2 ") of the second input terminal pair, the first input (121) of the second NAND gate (C12) and the first input (131) of the third NAND gate (C 13) is connected, in which the outputs of the first and of the second NAND gate (GlI, C 12) with the inputs of a fifth NAND gate (C 15) and the outputs of the third and fourth NAND gates (C 13, G 14) are connected to the inputs of a sixth NAND gate (G 16 ', in which the output of the fifth NAND gate (G 15) is connected to the first input (171 of a seventh NAND gate (G 17) and the alisgang of the sixth NAND gate (C 16) is connected to the first input (181) of an eighth NAND gate (G 18), in which the /. Expands Inputs (172, 182) of the seventh and eighth NAND gates (C 17, G18) with a third input terminal (£ 3 ') for a unipolar clock pulse and the outputs of the seventh and eighth NAND gates with the external connections of the primary winding (L / 11, U 12) are connected via the output transformer (U 1), and in which the two connections (L / 21, U 22) of the secondary winding represent the output connections of the modulator and the center tap of the primary winding of the first transformer (t / 1 ) is connected to a supply voltage (Fig. 4). 8. modulator for performing a method according to claim 5, characterized in that a digital double push-pull modulator is provided which has a first pair of input terminals (EΓ, El ") for the pseudo-ternary encoded digital signal, a second pair of input terminals (£ 2 ', £ 2") for the Takisignai acting as a carrier and a third input terminal (£ 3 ') for the unipolar clock pulse, four NAND gates (G21 ... G24) with three inputs each, two AND gates (G 25, G 26) with two each Contains inputs and an output transformer (t / 2), in which the first input (211) of the first NAND gate (G21) and the first input (231) of the third NAND gate with the first input terminal (Ei ') of the first input terminal pair (G 23) is connected, in which the second input (£ 1 ") of the first input terminal pair with the third input (223) of the second NAND gate (G22) and with the third input (243) of the fourth NAND gate (G 24) is connected, where the first input terminal (£ 2 ') of the second input terminal pair is connected to the third input (213) of the first NAND gate (G 21) and to the first input (241) of the fourth NAND gate (G 24), where the second input terminal (£ 2 ") of the second input terminal pair is connected to the first input (221) of the second NAND gate (G22) and to the third input (233) of the third NAND gate (G 23) and in which the third input terminal (£ 3 ') is connected to the second inputs of the first, second, third and fourth NAND gates (G21 ... G24), in which the outputs of the first and second NAND gates (G 21, G 22) with the two inputs of a first NAND gate (G25) and the outputs of the third and fourth NAND gates are connected to the inputs of a second AND gate (G26), in which the outputs of the first and second AND gates (G25, G 26) with the two outer connections of the primary winding of the second output transformer (U 2) are connected, and in which the Mitt Elan tapping the primary winding with an operating voltage and the two connections of the secondary winding of the output transformer are connected to the output connections (Fi g. 5). 9. modulator for carrying out a method according to claim 5, characterized in that a digital double push-pull modulator is provided which has a first pair of input terminals (Ei ', E i ") for the original pseudo-ternary coded signals Signa! (Pi), a second pair of input terminals (1 : 2 ', £ 2 ") for clock signals that act as carriers! (P2) and a third input terminal (£ 3 ') for the inverted unipolar clock pulse (Pi) are provided at the four NAND gates (G 31 ... G34) each with two inputs and a first and a second AND gate (G 35, G 36) each with three inputs and a push-pull transformer as output transformer (L / 3) are included and in which the first input (311) of the first NAND gate (G31) and the first input (331) of the third NAND gate (G33) are connected to the first input terminal (Ei ') of the first input terminal pair, in which the second input terminal (£ 1 ") of the first input terminal pair is connected to the second input (322) of the second NAND gate (G32) and to the second input (342) of the fourth NAND gate (G 34), where the first input terminal (£ 2 ') of the second input terminal pair is connected to the second input (312) of the first NAND gate (G3t) and to the first input (341) of the fourth NAND gate (G34), where the second input terminal (£ 2 ") of the second input terminal pair with the first input (321) of the second NAND gate (G 32) and with the second input (332) of the third NAND gate (G33) is connected, in which the outputs of the first and second NAND gates (G31, G32) with two inputs of a first AND gate (G35) and the two outputs of the third and the fourth NAND gate (G 33, G 34) are connected to two inputs of a second AND gate (G 36), in which the third input terminal (£ 3 ') for the inverted unipolar clock pulse with the second inputs of the first and of the second AND gate (G35, G36) is connected and in which the outputs d- ~ s first and second AND gates (G35, G36) are each connected to an external connection of the primary winding of the output transformer (L / 3), while the center tap of the primary winding is connected to a connection for a supply voltage and the two connections of the secondary winding are connected to the outputs of the double push-pull modulator (Fi g. 6).