DE2517630A1 - COMPONENT INTEGRATED IN SEMI-CONDUCTOR TECHNOLOGY, WHICH IS PART OF A DATA PROCESSING SYSTEM - Google Patents

Description

• - ■ ί.Γ? lichen 2, April 21, 1975

Berlin and Munich Wittelsbacherolatz 2

^VPA 75 P 6 0 6 9 FRG

Module integrated in semiconductor technology that is part of a data processing system.

As is well known, it is advisable to use data processing systems from building blocks together, which are monolytically integrated Semiconductor components are involved, which are manufactured in particular using MOS technology (see "Electronics 1974", pages 379 to 395, in particular 3SS and 389; DOS 2 233 430, 2 336 333, 2 247 7C4). Each component is located in a so-called chip, which has a limited number of single-pole connections. During the operation of a data processing system from several Such chips are, among other things, to enter information into a chip. It therefore arises the task of such information to be able to enter using as few connections as possible. Ss can then impose an excessive limit on the number of different Functions that can be carried out by the component contained in the chip can be avoided. The more diverse Functions such a module can perform, the more connections it usually has.

The invention now shows a way in which this object can be achieved can. The invention therefore relates to a semiconductor technology integrated module that is part of a data processing

work system and which has at least one register that can be used for the operational sequence in the module, into which register information consisting of several bits is entered, which helps determine the operational sequence. This module is characterized in that the register information, which can be changed by a counting circuit belonging to the module, when the module cooperates with other modules of the data processing system, is supplied by another module of this type via a single-pole Z ¹ SUSteinanschluS with the help of a series of pulses that are sent from the counting circuit in the register information is implemented.

VPA 9/610/4307 Hlr / EK _ 2 -

609845/0409

In the course of this implementation, for example, one can be entered beforehand in the register The register information contained therein is deleted and replaced by a new B.egisterinforination be replaced or it can, for example, the original register information by an addition process or a subtraction process can be changed.

The invention enables the delivery of register information brought about via a single single-pole module connection. The number of connections required for the module is therefore kept within narrow limits. This also makes it possible that the chips for the various belonging to a data processing system Modules can have a uniform and a small number of connections. This also removes the wiring between these building blocks facilitated. By switching operations within a module, this can also be achieved with the help of Several different registers can be supplied with register contents from pulse series.

Appropriately, there is also a reset input in each module provided, via which the module can be set to the initial state for the operating sequence by an externally supplied RXackstellsignal. With this signal the implementation is then also an incoming series of impulses. During the absence of the reset signal, the single-pole module connection is for the supply of control pulses can be used, which trigger further processes in the block. The single-pole can thus advantageously travel Connection can be used multiple times for different purposes.

Examples of building blocks that are equipped according to the invention, are shown in Figures 1 and 2. Figure 1 shows a combination module, the input-output ports for peripheral units and contains a buffer memory. FIG. 2 shows a module which contains a program control unit of a data processing system. Both Blocks also contain at least one register and at least one counting circuit. An operating register can be used as a register be provided, the register information supplied by pulse series to switch the block to different modes of operation (see also DOS 2 245 284).

VPA 9/610/4307 - 3 -

609 845/0 40 9

251763Q

The Kcr.binatior.sbaustein shown in Fi £ ur 1: the operating register T- ¹ IR and the counting circuit ZK. Pulse series supplied via the single-pole module connection H are in each case converted into the register information by the counting circuit ZM. The register information recorded in each case affects one of the control terminals a, b, c, d of the operating register MR and the identically labeled control terminals of other sub-devices of the combination module B connected there. Of this combination module, only those partial devices are shown here to the extent that it is necessary for an understanding of the invention. These partial devices are interconnected in part via the busbar SS, which in turn is connected to the busbar DS1, which leads to other modules. Control information can be supplied via the address busbar AS. Reset signals can be supplied via the reset input R and from there passed on via the control terminal r to other sub-devices with the same name. The combination module has, among other things, the input / output ports K1 ... K4 as partial devices, to which the peripheral devices P1 ... P4 are connected. In addition, the input / output gate K-5 is also provided, via which the busbar SS can be connected to the busbar DS2, which leads to other modules. The directions of transmission for the busbars are indicated by arrows. The combination module also contains the buffer memory QS, which has several memory cells and which is equipped with the input counter EZ and the output counter AZ, each of which serves as an address generator for memory cells. Modules with input-output gates are known per se (see Rockwell International Corporation MOS / LSI Parallel Processing System, Rev. May 1937, pages 2-13 to 2-17 and Data Sheet Parallel Processing System (PPS-4) Rev. 1 , July 1974, pages 2-1, 8-1 to 8-3). It is also known to additionally equip such modules with a memory (see Electronics 1974, pages 379 to 395, in particular page 381). The input counter EZ belonging to the buffer memory determines in each case the memory cell that receives an information and the output counter AZ in each case determines the memory cell that emits information.

VPA 9/610 / 43.Ο7 - 4 -

609845/040 9

cell, as it is already known per se (see BOS 2 362 245, 2 002 369). The address decoders DE and DA are used to decode the memory cell addresses supplied by the counters. When switching over the module with the help of the operating register MR, the counting method of the counters EZ and AZ is set in such a way that that from the buffer store QS either during the cooperation of the module B with another device only useful data for one memory cell are received or released, or that a useful data block occupying several memory cells is accepted or released. To change their counting method, the counters EZ and AZ are via their control terminals c and d switchable. If a user data block is recorded, so is accordingly the input counter EZ over several counting positions to switch one after the other. The delivered memory cell address is to be decoded in each case, so that the associated Memory cell each pending information can be supplied. This repeats itself until all belonging to the user data block User data are received one after the other during the same interconnection of two modules in several memory cells. The output of the useful data belonging to this useful data block is handled in a corresponding manner, also during the same interconnection of, for example, two modules. The buffer store QS is on the input side and on the output side connected to the busbar SS. The user data can therefore, if required, for example, be sent to the busbar via the SS connected busbars DS1 and DS2 are supplied or delivered.

The presence of control terminals a and b in the operating register MR indicates that further switchovers of the operation not described in detail with the help of the operation register possible are. The module is reset to its initial state via the reset input R by means of an externally supplied reset signal offset for the operational process. This reset input leads to control terminal r, which is labeled identically with others Control terminals in other sub-devices, such as the input-output gates K1 ... K5 and the counters EZ, AZ and the counting

VPA 9/610/4307 - 5 -

609845/0409

circuit ZM is connected. A reset signal will therefore here the input-output gates K1 ... K5 in their idle state offset to ground. Furthermore, the counters EZ and AZ can be brought to their start S counting position. Because the reset signal here also acts on the counting circuit ZM can through this signal also causes the series of pulses arriving via the single-pole module connection H to be converted into the register information which is to be recorded by the operating register KR. To the busbar AS for incoming addresses, the decoder DC is connected, which has the control terminals 1, 2 ... r. It can therefore an address arriving there is also decoded into a reset signal will. In addition, other addresses can use the tax codes 1, 2 ... e.g. affect the input-output gates K1, K2 ... and these in a Yfeise required for operation adjust each time.

In the case of module C shown in FIG. 2 with a program control unit of a data processing system, the operating register SR is provided, for which the single-pole module connection H The counting circuit ZS converts the supplied series of pulses into the register information. The business register is owned by SR here to the sequence control device ALS of the program control unit. A switchover of module C can therefore either be done here, for example cause the program to be stopped after each program command or only after each jump command, as such functions can be brought about by a sequence control device in a manner known per se. The next command execution can then be initiated by a special control pulse who-i the one that is fed to the single-pole module connection H. This control pulse is there during the absence of the reset signal at the reset input R and therefore has a different effect than the pulse series to be converted into register information. These As already described, implementation is only initiated by the reset signal supplied to reset input R. In In this context, module C is operated in the same way as module B.

The block C has other sub-devices that for its way of working as a program control unit can be exploited. In addition

VpA 9/610/4307 609845/0409

belong the information processing plant INW and the Kellspeicher ICZR, to the: the read / write register LSR and the address r senausgäbe facility belong to ADR. Become the basement itself Addresses of memory locations supplied via the address decoder ADK. These addresses and the other information to be stored in the stack store meet there via the bus DB connected to the internal collecting line ZZ belonging to module C. Addresses returned by the stack become are output via the line AB and are e.g. fed to a read-only memory for calling up program commands. The sequencer ALS can still be supplied with control information from the outside via the collecting line SB and it can also be via this collecting line from the sequence control device ALS information to the outside. To the inner manifold At the moment there are more registers connected, namely the one in each case the program command to be executed first, the command counter register BFR of the sequence control device ALS, the general Register REG and the accumulator AKKU; The accumulator is still in connection with the information processing system INVi so that it can receive data processing results. The various manifolds and other lines are the directions in which information can be transmitted are indicated by arrows. Only from the program control unit are here the most important sub-devices shown, in particular those related to the invention.

The invention has an effect here in particular on the various registers. In this context, by switching " of block C with the help of the operating register SR also in each case the output of register information, in particular the contents of the accumulator, to an external device, e.g. a display device, be initiated. Such information then gets there via the inner collecting line ZZ and the one connected there collecting line leading to the outside DB.

It is already known per se to have registers belonging to a program control unit work together with counting circuits

VPA 9 / 6IO / 43O7 - 7 -

8 0 9 8 4 5/0409

(see Intel, MCS-4 Kikrocomputer-SET Users l'anual, March 1972, Rev. 2, page 10). The associated counting circuits are, however not used there to convert incoming pulse series into register information. A counting circuit can each individually assigned to a register, or it can also belong to several registers. At the program control unit according to 2, the general register REG and the accumulator AKKU each have their own counting circuit, namely the counting circuits ZR and ZA. The counting circuit ZS, on the other hand, is the operating register SR and the command counter register BFR of the sequence control device ALS jointly assigned. For all of these registers, incoming pulse series can be recorded with the help of one of these counting circuits can be converted into register information. To distribute incoming series of impulses to be implemented to the The distribution device serves the counting circuit in question M, which is controlled by the sequence control device ALS as a function of control information. The single-pole module H can be used to convert pulse series in the register information are also supplied from an external device, in particular from an operating device.

The technique described above, using a single unipolar Module connection Supplying information to a module with the help of a series of pulses can also be modified accordingly can be used to transfer information from the module to other modules via a single-pole module connection. In particular, this can also be register information to be delivered. In this case, the block has also a module connection provided for this purpose. The counting circuits that are present can also be used accordingly to convert register information, which consists of several bits, into pulse series.

11 claims
2 figures

VPA9 / 61O / WO7 _{M8tus / 0409}

Claims (2)

Pe.t- e nt claims Module integrated in Kalbleitertechnik, which is part of a data processing system, and which has at least one for.den Operating sequence in the module has a usable register into which register information consisting of several bits is entered which co-determines the operational sequence, characterized in that the by a counting circuit belonging to the module (e.g. ZM) changeable register information b ^ i of the cooperation of the module with other modules of the data processing system occasionally from such another module via a single-pole module connection (FI) with the help of a series of pulses is supplied by the counting circuit (ZM) in the Register information is implemented. 2. Module according to claim 1, characterized in that a reset input (R) is provided, via which the module (B, C) is returned to the initial state by an externally supplied reset signal can be displaced for the operating sequence, and that this reset signal also converts the incoming series of pulses can be caused. 3 · Module according to Claim 2, characterized in that, during the absence of the reset signal, the relevant single-pole module connection (H) can be used to supply control pulses that trigger further processes in module (B, C). 4. Building block according to one of the preceding claims, characterized in that that the component (B) includes an operating register (MR), the register information supplied by a series of pulses to switch the block to different modes of operation. 3 · Module according to claim 4, characterized in that, as a combination module (B), it contains input-output gates (K1 ... K4) for peripheral units and a buffer memory (GS) which has several memory cells and which is equipped with an input counter ( EZ) and an output counter (AZ), each of which VPA 9/610/4307 609845/0409 - 9 - O.2.S1 Ac..Tessen ~ en? Rator for memory cells, and that Lei the U:. '. :: Ehr. 1 tang of the "raise stone (3) the counting mode of the counter (Ξ-Ζ, AZ) is set in such a way that from the buffer memory (QS) during the cooperation of the module (B) with another device either only useful data for one memory cell is received or or that a useful data block that takes up a plurality of memory cells is received or released. 5. Module according to claim 4, which is a program guide of the data processing system contains, characterized in that by switching over the module (C) "either a stop of the program sequence s can be initiated after each program command or only after each jump command, and that the next command execution is caused by a special control pulse which is fed to the single-pole module connection (H). 7. Module according to terminal 6, characterized in that by a Switchover of the module (C) additionally in each case the output of register information, in particular the accumulator content another, in particular an external, device can be initiated. 8. Building block according to one of claims 1, 2, 3, 6 and 7, characterized in that that an instruction counter register (BFR) belongs to the module, in which register information is entered with the help of a series of pulses can be entered, which determines the program command to be executed first. 9. Building block according to one of claims 1 to 3 or 6 to 8, characterized characterized in that the module (C) includes an accumulator (AKKU) for receiving data processing results, which is also carried out by Register information supplied to the pulse series. 10. Building block according to one of the preceding claims, characterized in that that his relevant single-pole module connection (H) pulse series also from an external device, in particular a control unit, can be supplied. VPA 9/610/4307 - 10 - 609845/0409 Bs. ". IK tsi-Π rncli βΐπ.θ: Τ! Der vor'liorp'ehpnrien AnsOrv.chs. Thereby pro - k ^r ; if.seichr.e ^J ;, caß he has a single-pole block connection,., Via the Register information can be delivered to other modules in the form of a series of pulses. VPA 9/610/4307 609845/0409