DE2505842A1 - Microprogrammable data processor using integrated circuits - with data memory employing data cards - Google Patents

Abstract

The data procession has an input circuit, a data memory a logic circuit, a read-out circuit and control means, which are intercoupled for communication between them. The data memory employs data cards each of which has several data zones containing various data characters, with the input circuit having means for receiving further data cards, which similarly have several data zones, containing the data characters. One of the data zones on each of the latter data cards contains the memory address for a corresponding data cards contains the memory address for a corresponding data card contained in the data memory. Pref. the memory data cards contain the programme data and the input data cards contain the operand data.

Description

Data Stream Controlled Data Processing System The invention relates to generally refers to improvements in digital data processing equipment and particularly relate to new and improved digital data processor systems in which the data processor is a micro-programmed integrated circuit.

In the field of digital data processing, it corresponds more at present Practice to use system architectures and organizations that are under the influence the costs to be expended for the hardware or circuit technology were developed. This requirement led to the centralization of the system control in devices that are known as Central processor or main memory units are referred to.

Because of this extensive and complex centralized circuit technology (hardware) that had to be controlled became work systems (main control programs) designed to expand the range of uses of the circuits, by doing it was intended for a number of programs or tasks. The system structure, that results from these influences is highly generalized and consequent unnecessarily complex and uneconomical for a large number of special situations. This type of structure is divided up in an irregular manner and works in principle with a sequential circuit logic.

The use of micro-programming techniques also becomes functional The basic system of the system has not changed because of the microencrypted processors nevertheless a step control for the registers influenced by the machine cycle follow.

The new IC technology, i.e. technology of integrated circuits, such as such as NSI and LSI, which enable the essential parts of a data processor can be housed on a single chip or board, can only be used economically and effectively if the lines of development be redrawn for the construction of such processors. The LSI technology, for example requires a regularity of the circuit technology and does not allow that special or complicated algorithms can be assigned to the circuit chips. There further IC memories, i.e. memories made up of integrated circuits, The register-oriented processor structure can be interface-compatible with the IC logic be exited by distributing all of the system memory across the system will. This of course eliminates the need for a centralized main storage subsystem. Since it is now desirable and appropriate to have system memory through a system to distribute, it is now also desirable to have the previously required central control to eliminate workflow systems.

To make the most of the advantages of LSI technology can, A system architecture is required that is well-formed and regular divisible system leads. Although almost all micro-programming techniques used to date When it comes to addressing this issue, well-known programming techniques are incapable of a system to develop that can be programmed efficiently and that is an efficient & Execution of its algorithms. The well-known micro-programmed systems thus show the complete lack of continuity between what which represents machine language and what is used for user programming is needed and what the language requirements are. This is all the more true because the well-known Nikrocode machine languages are of a serial nature and moreover are binding, which is in direct contrast to the requirement for regularity of LSI technology and also runs counter to the non-binding of complex functions.

It is therefore a concern of the invention to provide a digital processor to create that as a basic building block in a data processing system, for example a multiprocessor data processing system, can be used, whereby the need to use a main control program is superfluous or where it continues no extensive interruption system is required, and the one improved Has the ability to emulate.

The problems encountered in centralized systems referred to above pointed out are overcome, by a binary data system in which a memory of data fields and data characters contains data files *, the circuitry of the system including circuitry to accommodate them. A data field contains the address of the data file in the memory. The system can be general as a data-driven or data stream * (English date files, below also "data group" called) controlled system are circumscribed, which designation is used throughout here.

The general purpose of the invention will be detailed through use a subscriber vocabulary in a character serial data processor, where two of the characters defining the beginning and the end of a special Data field can be used. Each character is represented by several binary bits. The data structures are organized in data files, which fields in a way that allows these fields to expand and contract. Every data field is preferably terminated by an end-of-field code, which is a comparison between the count from the start of the field character to the end of field character in the data structure and a reference count. The structure and organization of a card index becomes described by the content of the first field in the card index. A program or a method is carried out as a function of the coupling of pairs of data files, each pair contains a data file that contains a part of the program, and wherein the other data file contains the operands for that part of the program. Of the one or another data card type can be (static) in the memory area of the data processor be included, while the other type is supplied to the processor (dynamically) from the outside will.

The arrival of the dynamic data files causes the associated Data card in the memory is addressed. Thereupon the Mectorkartei can the Cause the operation to be carried out which is dictated by its content, whereby the operands supplied by the incoming operand lists are used will.

When all operands of the addressed data structure are available or arrived, the operation designated by the program data structure executed and that Transfer the result to a destination, which is specified by the program data structure. The two matching data files can be used in combination so that the program data index prescribed result.

Other features and many advantages of the invention are apparent from the following Description of the invention, reference being made to the accompanying drawings will.

The drawings, in which like reference characters refer to like parts, show in detail: FIG. 1 a block diagram of a single one with the features the invention equipped processor data processing system; Figure 2 is a block diagram the input queue in the processor of Figure 1; Figure 3 is a block diagram of the vector logic unit from the processor of Figure 1; Figure 4 is a block diagram of the control unit of the processor from Fig. 1; Figure 5 is a block diagram of the exit queue from the processor Fig. 1; Figure 6 is a logic circuit diagram of that in the input queue of Figure 6 Fig. 2 signal detection circuit used; 7 shows a representation of a four-two character vocabulary, which can be used in the processor of Figure 1; 8 shows an illustration the general structure of a data file used in the processor of FIG can be; 9 shows an illustration of a general data structure file with sub-directories; 10 shows a representation of a tree-like branch as an example of a program, which can be executed in the processor of Figure 1; Fig. 11 a representation of a simple algorithm in tree-like branching as well as the Data structure or card index that represents the algorithm, what is in the processor according to Fig.1 can be used to carry out the specified operations; and Figure 12 shows a specific example of the interaction of program and operand data structures in the various major parts of the processor of Fig. 1 to achieve a desired Get result.

Fig. 1 shows a processor of a data stream-controlled processor system, which communicates with several peripheral units ~ 15,17,19 via an I / O switch 13. The EA switch 13 can be an ordinary switching device such as, for example in telephone exchanges use, one of the peripheral units with the data stream controlled processor 11 via the input cable 31 or the output cable 33 can be connected. The peripheral units can be serial or parallel designed units. To adapt to the character serial nature of the processor 11 should be used when using peripheral units with parallel format work, the I / O switch 13 contain a nultiplexor, the several parallel Signal paths from the peripheral units 15, 17, 19 in relatively serial signal paths as input for the processor 11 converts. To adapt the character serial signal transmission from the processor 11 into the peripheral units 15 "19, which work with parallel format, the I / O switch 13 should contain an end multiplexor.

The peripheral units 15, 17, 19 can be known devices and as such, for example in question magnetic tape devices, card readers, card printer units, Control consoles, printers, disk or drum storage devices.

The data stream controlled digital computer or data processor 11 takes the data structures from the peripheral units on its input queue 21. These data structures, which will be discussed below, have a specialized one organization and have to obey certain syntax rules.

The input queue 21 is essentially a FIFO unit (i.e. buffer unit, the first input is also output first), the additional function the synchronization of the asynchronous data structures received on the input cable 31 to the system clock of the processor 11 makes. The ones received from the input queue 21 Data structures are received character serially.

These data structures can be viewed as if they were the supplied to other elements of the processor 11 in a character-serial manner. The data structures in the input queue 21 are for example serial characters to the processor memory 25 via cable 35, a control unit 23 and from the control unit 23 via cable 51 transferred to processor memory 25. The control communication between the input queue 21 and the control unit 22 via cable 37 and the control communication between the Control unit 23 and memory 25 via cable 49 are explained below.

In addition to the transmission of the data structures from the input queue 21 to memory 25, these can also be converted to a vector logic unit 27 by virtue of the Control unit 23 can be transmitted via cable 47. Similarly, the Data structures from the memory 25 of the vector logic unit 27 via cable 45 capacity the control unit 23 are supplied. The control communication between the vector logic unit 27 and the control unit 23 via cable 43 will be explained further below.

The vector logic unit 27 is basically a serial arithmetic unit, which for example such basic functions as addition, subtraction, comparison and Can carry out transfers to data structures of variable field lengths.

The vector logic unit can be connected directly to the memory 25 via the Data cable 53 and communicate with an output queue 29 via data cable 59. The control communication between the vector logic unit 27 and the memory 25 via control cable 55 and to output queue 29 via control cable 57 are described below still described.

The processor memory 25 of the data flow-controlled computer 11 can A random access memory in an integrated circuit made up of random access memory chips of preferred size, such as those available from Signetics Corporation be put on the market. In the catalog of this company from 1972 a 32 by 2 random access memory chip is offered on page 4-24, the can be used to build the memory 25. The construction of a bigger one Memory with such a memory chip is of course within the scope of the invention. A Another example of a memory chip that can be used to build the memory 25, St stated, for example, on pages 4-13 of the Signetics Corporation 1972 catalog, where a fast content addressable memory chip is discussed.

The output queue 29, the data structures from the vector logic unit 27, the memory 25 or the input queue 21, brings the from you received data structures in a form that is sent to the peripheral units 15-19 can be transmitted through the I / O switch 13. The exit queue is similar like the input queue, basically a FIFO buffer, * of the data structures in series receives and feeds these characters to the I / O switch.

Referring to Fig. 2, the input queue 21 is connected to the I / O switch connected via cable 31. Cable 31 exists * (FIFO = first in, first aut) the end lines 79,81,83 and 85 coming from interface logic 61 in the input queue 21 come forth or lead into them. Lines 85 are two parallel data lines, receiving the two bits in parallel from the I / O switch (Fig. 1). These two parallel Bits represent a character. The other three lines 79, 81 and 83 are control lines between the input queue and the I / O switch. Line 79 transmits a Binary signal instructing the I / O switch to retransmit the data structure, if an error was found in the previously received data structure.

Line 81 carries a binary signal that prepares the I / O switch or blocks with regard to the transfer of data structures. Line 83 leads a. Signal generated by the I / O switch indicating a request Data structures from one of the peripheral units or. the exit queue of the Data processor 11 to send. Depending on such a request signal the signal on line 81 enables the I / O switch when the input queue can hold additional data.

The character serial data structure obtained from the I / O switch 13 (Fig. 1) was received on lines 85, the interface logic 61 is supplied and next to it by the logic circuit, appropriately called error detection logic, and a binary up / down counter 65 checked for the presence of errors, the is responsive to the error detection logic 63. The count of the counter 65 becomes the Interface logic 61 is supplied via cable 93.

It is self-evident at the moment that if the Counting of the binary up / down counter 65 at the end of a data structure is not zero, the interface logic 61 requires a retransmission via line 79 because an error occurred in the data structure. The special logic of the error detection circuit 63 and their interaction with the up / down counter 65 and the Interface logic 61 is described in detail below.

As already mentioned, the input queue 21 basically works like a FIFO buffer and synchronizes the asynchronous incoming data characters the processor system clock, not shown, which is part of the interface logic 61 is. The buffer part of the input queue is the input queue memory 67, which can be a random-access memory made up of IC-RA memory chips which may be that of the Signetics Corporation in their 1972 annual catalog Page 4-20 are described and indicated.

The data characters received on lines 85 from the peripheral units are fed to the input queue memory 67 via lines 96, where they are in the next available space will be saved by what is written by the write pointer circuit 73 is specified. Between storing the data characters in the input queue memory data characters are read out of this memory and the other components of the Processor 11 (FIG. 1) via the control unit 23. The respective data character, which is to be read out from the memory 67 at a certain point in time determined by the read pointer circuit 71.

The data character read from the input queue memory becomes from the input queue memory via lines 98 to interface logic 61 and then transmitted to the control unit 23 via lines 35. The control lines 123, 121, which form the control cable 37, carry the read enable and read request signals from the control unit 23. The line 123 carries a read enable signal. The administration 121 carries a read request signal.

Generally speaking, the information is therefore stored in the input queue memory 67 is saved as quickly as it was received and is Storage 67 read out in a FIFO order as quickly as the control unit 23 afterwards demands. And the interface logic 61 receives data characters via lines 85 it generates a signal on line 97 and passes it to a memory cycle controller 69 to indicate that a write function is required.

The memory cycle controller responds to this write request signal a write enable signal on line 103 for the input queue memory 671 a write selection signal on line 105 for a selector 75 and an incremental signal on line 99 for a write pointer 73.

The selector 75 can be the one in the 1972 yearbook of Signetics Corporation on catalog page 2-136. Basically the selector selects in response to a write or read selection signal on line 105 Write or read pointer output signal fed to it on cables 109 and 111, respectively to it via cable 107 to the address register of the input queue memory 67 to transfer.

The write pointer 73 and the read pointer 71 can be binary counters, for example as stated in the 1972 catalog of the company mentioned on page 2-100. The increment inputs 99 and 101 for the write pointer and read pointer on the memory cycle controller 69 would connect to the non-illustrated A input of this Signetics counter be. Line 100 from interface logic 61 to read pointer 71 as well to write pointer 73 would be with the reset inputs (not shown) of these To be connected to the counter.

The outputs of both the write pointer and the read pointer are checked by a comparator 77 and apart from that go through the selector to the input queue memory 67 to be addressed. The comparator may take the form of a comparison circuit made by Signetics Corporation and is listed in their catalog 1971, TTL / MSI on page 101. This comparator has two output lines that indicate which of the two Entrances which is larger and if they are the same size. As the entrance queue 67 acts as a FIFO, i.e. is a buffer in which the first input is also first is output, the write pointer count will always be greater than the count of the read pointer if the input queue memory 67 contains data but not is full. Hence, a signal on line 119 is derived from comparator 77 of the interface logic 61 indicate that the count of the write pointer is greater than that of the Read pointer. This indicates to the interface logic that in the input queue memory data is still included.

When the count of the write counter is equal to the count of the read pointer is then a signal from the comparator via line 117 to the interface logic 61 transferred. This signal can mean that the input queue memory 67 either completely empty or completely full, depending on whether the interface logic 61 last memory request generated was a read or write request. the Interface logic 61 interprets the signal on line 117 to mean that the input queue memory 67 is full if the last store was a write. If the last memory operation was a read operation, then a signal is on line 117 is taken as an indication that the input queue memory is empty. the Interface logic 61 knows whether the last store operation was a write or a Read operation was because it was either a write or a read request over lines 97 or 95 to the memory cycle controller 69. If the Interface logic 61 determines that the input queue memory 67 is empty, it generates a reset signal on line 100, which both the write and is fed to the read counter.

The special circuitry of the memory cycle controller 69 and the interface logic 61 is not discussed here in detail because the implementation in terms of circuitry the functions are familiar to a person skilled in the art, provided that they have average knowledge is.

According to FIG. 3, there is a serial vector logic unit 27, which is shown in the processor of Fig. 1 can be used, basically from two read-only memories (Read-only memories ROMs) 125 and 129. Both read-only memories can for example, of the type listed on page 4-1 of the 1972 catalog of the above Company is listed. The address registers 124 and 128 for the read-only memories 125 and 129 are common address registers with parallel inputs and outputs. One and only the structural difference between the two read-only memories is the microcode, which is contained in them. The read-only memory 125 contains that Nikrocode that is needed to generate the results of dyadic operations, such as Addition, subtraction, comparison. The read-only memory 129 contains the microcode, the is required to produce the result of monadic operations, such as Complement, suppress the first bit, set the first bit to zero, etc.

Data structures, which are character serially from the memory 25 of the processor 11 reach the vector logic unit 27 by means of the control unit 23 via lines 45, are out by the de-multiplexor 135 in accordance with a control signal on line 43a the control unit 23 to the dyadic read-only memory 125 via line 139 or the monadic Read-only memory 129 via line 142, depending on what type of data structure is addressed was determined by the data structure of input queue 29. This will be seen from below become even clearer.

Similarly, the demultiplexor 137 receives data character serially via lines 47 from the input queue 29 by virtue of the control unit 23 and forwards it either to the dyadic read-only memory 125 via line 141 or to the monadic Read-only memory 129 via line 143. The output of either the dyadic read-only memory 125 or the monadic read-only memory 129 is the memory 25 of the processor or the output queue 29 of the processor, depending on the destination address, which is contained in the program data structure. This destination address will be the Demultiplexers T33 and 130 via lines 43d by the control unit 23 of the processor fed.

The demultiplexor 135,137,130 and 133 that are in the Vect6r logic unit may be of the type shown on page 2-132 of the catalog 1972 of the named company are recorded.

For example, suppose that a dyadic operation is performed should be, whereby an operand A should be summed with an operand B, then, an OP code designating the dyadic addition operation becomes the address register 124 either from memory 25 or input queue 21 of the processor for reasons that will become clear below. Along with this op code will be two operands are also supplied to the address register 124 character serially. As a result the exit on cable 126 of the reading-storage 125 becomes the serial L'rg Jnis be the summation ndtr both operands. What actually happened is this that the op code in addition to the operands as addresses for the special Fields in the read-only memory 125 acts, which are the results of the summation of two special Saves characters from the summed operands.

In this particular example, the output of the read only memory would be also contain a signal on line 43c which indicates to control unit 23 that special character information is completed. Further would be in the case of Edition of carry signals back to the input of read only memory 125 on lines 132 arrive to modify the addition of the next characters accordingly.

In the case of monadic operations performed by the read only memory 129 feedback lines 131 can easily be a step counter input to modify the content of the address register 128 of the monadic read-only memory so that the next memory address is addressed.

Overall, the control unit 23 leads data structures from the Memory 25 and the input queue 21 in the vector logic unit 27, which on addresses these two data structures in that a result and control signals which are sent back to memory 25 via lines 53 and 55, or to exit queue 29 via lines 57 and 59.

Referring now to Fig. 4, the control unit 23 of the Processor 11 represents as a micro-programmed unit, which consists of several read-only memories or read memories and multiplexers. The read-only memory 146 for field analysis receives data structures from the input queue over lines 35 or from memory via lines 51b. Either the data structure from the input queue 21 (Fig. 1) or the data structure addressed from the memory 25 (Fig.1) the read-only memory 146 for the field analysis via the address register 145, whereby the field analysis read-only memory 146 is responsive to the fact that it receives control signals to one of several demultiplexers 148, 150 and 152.

For example, if a data structure on line 35 is out of the incoming queue (Fig.1) arrives and happens to be an operand file, the field analyzer would cause the demultiplexor 148 to read the operand fields over one of three To transmit lines 47a, 39a or 51a, with line 47a to the vector logic unit, Lead 39a to the output queue and lead 51a to the memory. The field analyzer in this example would respond to the description field in the operand file. Similarly, if a data structure of line 51b from memory (Fig. 1) arrives and happens to be an operand file or a field, then the read only memory would 146 cause the demultiplexor 152 via line 162 for the field analysis, data via line 39b or line 45, with line 39b to the output queue and lead 45 to the vector logic unit.

Assume now that a program data structure is received, in place of the operand data structure, which is either via lines 35 or 51b was received.

This program data structure would read memory 146 for field analysis address and cause it to write an address to one of the read memories 154,156,158 to be transmitted using the demultiplexor 150.

The read memories 154,156,158 form a microprogram library, which contains special microprograms. These microprograms are made by the data structures which come in on either data lines 35 or 51. You take indicates that the memory 146 received for field analysis Data structure begins with a field indicating that a program index follows; the field analyzer would then give multiple signals to the demultiplexer 150, which forward the signals to the read-only memory 154 for the program file, for example would. In response to these signals, which address special areas in this read-only memory, control signals are generated which are transmitted via lines 43 to the vector logic unit (Fig. 3), via line 41b to the exit queue (FIG. 5) via line 121 to the interface logic the input queue (Fig. 2) and, if appropriate, via line 144 to the address register 145, indicating that the particular operation is complete is.

In addition to receiving data structures via lines 35 and 51b the address register 145 various control signals. For example via line 123 becomes a write control signal from the interface logic of the input queue (Fig.2) supplied. An operation end signal is sent from the vector logic unit via line 43c (Fig.3) supplied. The output queue (Fig. 5) delivers a stop signal via line 41a, that indicates to the controller that it is full. There is also a continuation signal the address register 145 from the read-only library on line 144 supplied.

The address register 145 is an ordinary parallel register with parallel inputs and parallel outputs. The read-only memory 146 for field analysis may be of the type described in the Signetics Corporation 1972 catalog on page 4-1 is specified. The microprogram library read-only memories 154, 156 and 158 can be accessed from be of the same kind. Demultiplexors 148 and 152 are on pages, for example 2-132 in the Signetics Corporation 1972 catalog. The demultiplexor 150 can consist of several demultiplexers in cascade - with neither separate Demultiplexor, for example, from the one on page 2-130 of the Signetics 1972 catalog Corporation specified type.

In Fig. 5, the output queue 29 is a dual memory FIFO circuit shown. Ingress control circuit 145 receives data from either the ingress queue or the memory via lines 39 based on the control unit 23 from FIG. 1. the Lines 41 carry control signals from the control unit 23. The input control circuit 145 also receives data from the vector logic unit 27 over lines 59 and similarly transmits and receives control signals from the vector logic unit 27 over lines 57. Those received from the input controller 145 over lines 39 Data is either stored in the operand memory 155, which is a Råndom-access memory is, or the destination address memory 157, which is also a random access memory is supplied, depending on whether the received data structure is a destination address, determined by the signals on the control line 41 from the control unit 23 or are an operand, determined by the signals on control line 41.

The data received by the input control on line 59 are fed to the operand memory or the destination address memory, respectively after what the signals on control lines 57 determine.

Both the operand memory and the destination address memory can consist of RAM memory chips (RAM = Ran domaccess memory), which are listed in the catalog 1972 on pages 4-20 of Signetics Corporation. Both stores will addressed by a read pointer or a write pointer, the operand memory 155 has a write pointer 147 and a read pointer 163 and the destination address memory 157 has a write pointer 149 and a read pointer 161. The way of working this the respective read and write memory is identical to the one in the Execute input queue if you address the input queue memory 67 (Fig. 2).

The input control circuit 145 operates like the interface logic 61 in the input queue when responding to signals from the comparators 151 and 153 to prevent the transmission of information to exit queue 29 from the entry queue, the memory or the vector logic unit to stop. The comparators 151 and 153 each show the input control circuit 145 in the same way as the KomparEåtor 77 of the input queue according to FIG. 2 indicates that the memories are either full or empty or contain some data.

The output control circuit 159 of the output queue 29 triggers one Read request from either operand memory 155 or destination address memory 157, depending on the receipt of a transmission command from the I / O switch 13 (Fig. 1) over line 167 of cable 33. The output controller 159 is also responsive to a retransmission signal over line 165. Dependent on of signals on one of these lines, the output control circuit 159 may send a Request to write data signals on line 169 to the I / O switch transfer. For example, when a transmission signal is received over line 167, the Data structure, part of which is contained in both memories, character serial transmitted over lines 171 to I / O switch 13 (Fig. 1). Remember that the I / O switch 13 of FIG. 1 is dependent on the receipt of data structures Via lines 171 from the output queue 29 such data structures accordingly the address field received from the destination address memory 157 became. Thus, the peripheral unit 1,2 or N (Fig.1) the Receive data, or the data structure can be put directly into the input queue of the Processor 11 are directed for further processing.

Figure 6 shows the specific logic of the error detection logic circuit 63 from Fig. 2. The error recognition logic circuit 63 ("Sparens" recognition circuit) has two input conductors 175,173, each of which connects to one of the input conductors in line 85 is connected.

The signals on each of conductors 173 and 175 become the input of one exclusive OR gate 177 and also an AND gate 179 via line 193 as well an AND gate 181 via line 195 is supplied. The output of the exclusive OR gate 177 on line 191 serves as a second input for the respective AND gates. Of the The output 89 of the AND gate 179 generates a signal that a further counting by one Unity means, while the AND gate 171 on line 91 generates a signal, which means counting down by one unit, with both signals an up-down binary counter 65 are fed.

The up-down binary counter 65 can be of the type described in the 1972 catalog on page 2-170 of the company that has already been mentioned several times. The up-down counter 65 provides a binary count over lines 197 to interface logic 61 of the inputs queue and receives a clock signal from the interface logic 61 over the line 199 of cable 93.

Fig. 7 illustrates the preferred two-bit representations of the four characters, which are used throughout the processor 11. The left data delimiter 174, also called the left limit, is indicated by a high signal on a first line and a low signal is shown on a second line, both signals are received essentially simultaneously. A right data limiter 176, too Called right limit, is through high signal on the second line and a low signal on the first line in direct contrast to the illustration the left border. A binary 1 sign 178 is indicated by two high signals while a binary O ~ sign 171 is represented by two low signals will.

Referring to Fig. 6, the determination operation will now be explained in which it is determined whether the signals transmitted via line 85 have a right limit, Left limit, a binary 1 or a binary O mean. First assume that Example that the binary signal on line 175 means a 1, i.e. is high, and that the binary signal on line 173 means a 0 or low. then the output of the exclusive OR gate 177 will be a binary 1 and the signal on line 193 will be a binary 1, causing AND gate 179 to generate a high signal level on line 89 is caused. This signal level leaves the up-down counter 65 will continue to count up one unit. One now suppose that the binary signal on line 75 signifies an O and the binary signal on 173 signifies a 1, whereby a legal limit is shown; then the exit of the exclusive OR gate 177 can be a binary 1 and cause the output of the AND gate 181 goes up on line 21. The high signal level on line 91 leaves the Up-down counter 65 to count down by one unit.

The count of the up-down counter 65 is passed on to the interface logic 61 the input queue (Fig. 2) fed. If both.

Input lines 173 and 175 for the error detection circuit 63 are high, no output is produced on either line 89 or 91 because exclusive OR gate 177 does not generate a preparation signal on line 191. The same situation arises if both lines 173 and 175 are binary O lead.

In Fig. 8, the field arrangement or general format is a Data group (English: Data file, also called data card index above) shown, the forms the basic unit of a data structure. The first field of a group is a Description field. The next fields are data fields. The last field is a graduation oath.

Determine the extreme left and right boundaries 201 and 219 a group. Assume that this group is acting as a simple data structure can be viewed, transmitted from left to right, is the opening Bracket or opening 201 and closing bracket or closure 219. The first field following the opening 201 is a description field 203, the itself is limited by a pair of limiters. The next on the description field The following field can be an operand field, such as the one explained by field 205, or can be an address field or an operator field.

The data in the description field 203 becomes type and order the occurrence of the various fields following it. The empty spaces 207,211 and 215 between the date fields 205,209 and 213 can be used for simplicity Spaces are mentioned that allow the data fields 205, 209 and 213 can be expanded. When these fields contract, they create more White space. This entire empty space can be used to expand this later Enable fields. The exact tool that makes this possible is provided in the each described below.

The last field of each data group is a closure field 217, which is common contains no data. In other words, it just consists of two characters, one Left border and a right border. The closing field 2t7 and the group closing 219 are three characters that define the terminating code for the data structure or group represent. This code is then as shown in Fig.7 100 meets convention 010 and is serialized or with two bits each transmit simultaneously in parallel from left to right.

This ending field and the group ending (ending file paren) will interpreted as a group termination code from i1 ^ interface logic 61 of the input queue '. When this code occurs, the output of counter 65 will be 0, if none Errors occurred in the data fields of the group For example, the count of the counter 65 at the output for the general group structure from FIG. 8 to this Expire way: 121212121210. Thus, a combination shows a zero count the counter 65 and the occurrence of the completion code indicate that the received data structure contains no errors. For example, if there is an error in a bracket would occur, the counter would stop counting up or down. If a mistake was present in a data character, the bracket counter would incorrectly increase or count. In both cases, a count other than O remains when the Completion code occurs. This would indicate an error, whereupon the interface logic address from Fig.2 and request a new transmission as described above would.

The structure of each group shown generally in Fig. 8 must be certain Obey syntax rules. These rules are: 1) No 1 or 0 characters can be between identical looking brackets occur. For example, between the group opening bracket 201 and-the field opening bracket of the description field 203 no character available be.

2) The first field of a group must be the description field 203.

3) The last field of the group is always the closing field 207. In In our example, this field does not contain any data.

A data field, such as, for example, the A data field 205 from FIG consist of several fields or even several groups. For example, shows 9 shows a field A, which consists of three subgroups a, b and c.

The field opening bracket 221, the field closing bracket 223 define a data field A. However, within these brackets, several "vector groups" appear. The groups a, b and c, namely 225, 229 and 233, each denote groups of six. These groups must of course obey the general syntax rules that apply to the general group from Fig.8. That means that each group has one Contains description field, data fields and a terminating field. In a group you can also spaces between the vector groups within a field, such as 227 and 231, and may allow the vector groups to be within the The field can expand if that is desired.

This networked structure of the fields within the groups and vector groups within the fields can be more easily understood if one imagines a tree-like structure with nodes that represent programs or operators. For example, suppose the operation defined below is to be performed on multiple literals represented in capital letters: This arithmetic combination of the 14 different literals can be represented by the tree structure shown in FIG.

The tree structure according to FIG. 10 receives at its inputs, namely at the upper level 225, the literals or other operands used by the in the various Node 227, etc.

programs described in the tree are to be processed.

For example, the literals A and B are assigned to the adder Program operator supplied at node 227; the literals C and D become the adder-program operator fed at node 229. The results of both operations are sent to a subtracter program operator at node 231.

While this is happening, the literals F and G can be a different one Adder-program-operator at node 235 are supplied, the result of this Summation of one subtract program operator at node 237 along with another Literals J is supplied. Maybe at the same time during this previous one Operations take place, the literals K and L become a subtracter program operator at node 239 and the literals N and M to another subtracting program operator at node 241, while the literals O and Q are fed to another subtraction program operator at node 247 are supplied.

The result of the operation on node 239 and the result of the operation at node 241 are fed to an adder operator at node 243.

The result of Subtract Operator Node 231 and the result of Subtract operator node 237 becomes another adder operator node 233 fed. The result of the adder-operator node 243 and the subtracter-operator node 247 are fed to another adder-operator node 245. The result of the adder-operator node 245 is fed to the subtracter-operator node 249, which also receives another literary R.

The results of the subtracter-operator node 249 as well as the adder-operator node 233 are fed to another subtracter-operator node 251. The result this node is sent to the send-to-X 253 operation.

From this description of the tree structure it is clear that the processing of operands in a tree-like structured flow the processing of the operands facilitated on a simultaneous basis. That means that the Operations, which exist at the same level, for example as on nodes 227,229,235,239,241 and 247, can occur substantially simultaneously if the appropriate operands be available. The same goes for any operation on another or second level, such as at nodes 231, 237 and 243, 'if that Result of the previous operations are all available at the same time.

The example of Fig.10 was taken into account for reasons of simplicity Description and for easier understanding only dyadic operations like adding and subtract.

However, it is clear that this type of tree-like structured process sequence can contain monadic as well as dyadic operations. Notice that in order to take advantage of the simultaneous processing a system of Data processors must be used.

In order to explain how the networked data group structures of Fig. 8 and 9 realize the tree-like structured processing concepts considers the following simple dyadic operations on four literals: CA + B) - CC + D).

These operations are shown in a tree-like structured form in FIG. 11 shown. The literals A, B, C and D at the top level become 255,257,259,261 the first level of the operator nodes, namely the summing nodes 263 and 265. The results from this node level or from this node level become the next Stage or the subtraction node 267 supplied. The result of this node at 269 can be assigned to another node or a program operator or a physical Determination are forwarded.

Each node of the tree structure of Figure 11 can be viewed as a group will. Therefore, looking at these two levels of node operators becomes the one Group that describes subtraction node 267 as a subtraction node group 271 can be shown. This group is limited by right and left boundaries (Right brackets and left brackets) and has a first field, which is a description field 277 is that describes the nature and sequence of the group. In this example P represents the program and means that this group - a program operator group is. Since this group is an operator group, this is displayed in the description field The following field can be a field 279 which contains the operator code OP. In our example the operator code describes a subtraction operation.

Since the operation is dyadic, the following describe the operator field Fields the two operands to be subtracted. These operands are the result of addition nodes 263 and 265.

Since the operands are the results of other operations, the operand fields are Vector groups. The operands are therefore described as vector groups 273 and 275. The field following the operand fields is a destination address field 287, the the determination indicates to which the result of the subtraction operation is sent must become.

The last field of the subtraction group is the closing field 289. Space can be anywhere between fields in a group. For example a blank field at 281, 283 and 285 is indicated within the subtraction program group. Recall that empty spaces also occur between the fields of the vector groups because the operand fields of the subtraction program group are vector groups.

Now consider the two vector groups within the subtraction program groups, namely the addition vector group 273 and the addition vector group 275. These groups are also structured according to the syntax rules given above. There is left delimiting brackets -and right-delimiting brackets. Within of these brackets, the first field is a description field, which in this case is the Describes the group as a vector group and the next following field for the Operator code reserved.

An addition operation is specified for our present example. The fields following the OP field are the operand fields, which in our example Literals are.

In addition to the operand fields, the dyadic vector groups contain such as groups 273 and 275 within a larger group, for example a program group 271, result fields denoted by the letter R in FIG are. These result fields (R) store the result of the dyadic operation which is described by that vector group, if the result is not in the time its generation can be used.

General operation is now shown for ease of understanding of the processor 11 from FIG. 1 in connection with the simple program flow according to FIG 11 using only dyadic operators. To the explanation and to further facilitate understanding, it is assumed that the program data structures or program groups are dynamic and received from the input queue 21 (Fig.1) will. Note, however, that the reverse is equally applicable and that the operand groups can be stored in the computer memory 25 and that the Program groups could be fed to the computer 11 via the input queue 21.

To execute the flow of functions according to FIG. 11, the memory of the computer contain a program group which is explained in FIG. 12B and below the heading "storage" is. The initial content of this group before the calculator receives any operand groups, is explained in the position ~ 1 ". The first field 291 of this group is a description field which indicates that the group a program group is. The first field 301 after the description field indicates the operation to be performed. In the present example this is a subtraction operation. The next field after the operator field 301 is an operand field that is assigned by a left bracket 305 and a right bracket 327 is limited. This operand field is a vector group that represents a dyadic operation. On this operand field a second operand field follows, which is also a vector group. That the closing field The immediately preceding field is the destination address field 343. Remember that space between the various fields of the subtraction program group may be present so that the voids 303,329 etc.

enable any expansion of the operand fields.

Now consider the first operand field, which is a vector group. In this particular example, an addition operation is defined. The operand fields 309 and 313 follow this particular group as it defines a dyadic operation, the field that describes the operator. This vector group also contains a Result field 321 instead of a destination address field. The operand fields 309, 313 and the result field 321 are all in the contracted state and leave a significant amount of white space 307,311,315,323 between them. In other words, the fields are simply followed by a left bracket These operand fields are defined in the right bracket and no characters between them remain contracted, as will be explained, until operands are stored in them will.

The second operand field for the subtraction program group is also a vector group that is structured in the same way as the one for the first one Operand field has been written. There are a pair of operand fields 333 and 335, a Result field 337 and a closure field 341.

If the fields are empty, they are in a contracted one State, leaving considerable white space 331,339, etc., between them.

The foregoing is the envisaged structure of a program group described in the computer memory, which remains statically in memory until a Operand data structure or group arrives at the input queue and this special Program group addressed. The structure of this program group provides a recursive one Mechanism that speeds up the execution of the algorithm.

An alternative data structure for executing the function flow from Figure 11 would be one that has three program groups rather than one program group which contains Vectro groups as shown. Thus represent two addition vector groups and the subtraction program group represents three independent program groups. The result field (R) of each vector group would be replaced with a destination address field (DA). The destination address field in both addition program groups would be the subtraction program address group in a manner to be discussed. The usage This type of data structure requires the result of each operation from the computer is led out and returned to its entrance to the next operator node to obtain. In contrast, the explained program group structure eliminates the need to get the result of a vector group operation out of the processor and send it back to its inbox for further processing.

To continue with the data structure discussed, consider now the data groups arriving at the input queue. Suppose the first The operand arriving in a data group is the operand A. The group that did this Contains operands is shown as group structure 1 in FIG. 12A under under the heading "input queue". The first field of this Data group is a description field 375 which indicates that this particular group is an operand group that contains a literary. This description field is analyzed by the field analyzer 146 (FIG. 4), the controller 23, which is dependent on to this end, sets up the appropriate paths to the computer memory 25 for the next field 377, which is a memory address field that contains the special vector group to which the literal A heard, addressed. The memory address 377 becomes the location in the computer memory address the ones with the left bracket 305 of the addition vector group in the subtraction program group 301 begins. The next field after the address field 377 is an operand digit field 379, which indicates whether the following operand field 383 is to the left or right operand field 309 or 313 belongs to the special vector group. The operand group attached to the Incoming queue is received, also has a termination field 387 and can the Space 381, 385 included between the fields of the group.

The controller 23 asks with the help of the field analyzer read memory 146 and its sub-routine library, consisting of the multitude of read-only memories 154,156,158 the addition vector group after being sent by the operand group The input queue was addressed to determine if operand B was previously has arrived and has been saved in its field 313. As this is in the present If this was not the case, what was controlled by the empty operand fields 309,313 is displayed, the controller stores operand A in the appropriate field 309. When the operand A is written character by character into the memory, the operand group 309 expanded to fit the exact size required. The details, namely in what way the operand is actually written into the memory is known to the person skilled in the art, as long as he is only average # n Intellect possesses.

As a result of the literal group shown in position 1, becomes therefore, when they arrive at the entrance, the subtraction program group queues the literals A in the appropriate operand field 347 of the vector group in the computer memory that has been addressed and begins with the left bracket 345, as can be seen in position 2 under the heading t'storage "(= memory) in FIG. 12B is. Since the literal A is now stored in the appropriate operand field, this field expanded and the space 349 between this operand field and its accompanying operand field can now be used up completely or considerably be reduced.

Assume now that the next group of operands, which are included in the Input queue 21 of the computer or processor 11 (Fig.1) comes, the operand D in its operand field 382, as in position 2 under the heading "input queue "(= input queue). In addition to the description field that the control unit the following fields are a memory address field 376 and an operand location field 389 exists in this operand group. The literal group instead of 2 of the input queue has a memory address field 376 that contains the addition vector group within of the subtraction program group, to be precise at the opening bracket 346 (Position 2 under the heading "storage"). If this vector group is addressed the control unit will, after seeing the operator field of the vector group, activate a suitable addition microprogram in the microprogram library leave, which consists of the read-only memories 154,156,158 (Fig. 4).

If this microprogram detects that all of the operands that necessary to perform the operation are not available, neither in the input queue still in the processor's memory, becomes a different microprogram to the Store the literary D in operand field 382 of the input queue group in the appropriate operand field 351 of the addition vector group activated, according to the determination by the operand location code in field 389 of the literary group at the input queue. As a result of processing the second literal group, the data structure in the storage as explained in position 3 under the heading "storage" appear. This means that a literal A is in its appropriate operand field in of the first addition vector group and a literal D is in its appropriate Operand field stored in the second addition vector group.

Now assume that the third group of operands is in the input queue arrives and carries an operand B in the operand field 384 that starts with the operand A is to be linked. The control determines, based on the description field L that this is a literal group and therefore the following field 378 is a memory address, which addresses the first vector group containing the operand A. The control advances and reads the addressed vector group; furthermore you put Associated field analyzer read-only memory 164 (Fig. 4) from the description field "V" states that this is a vector group that contains a program. The field that now must follow this description field, is then an operator code field. On the The field analyzer releases the appropriate microprogram from the operator code field Microprogram library of read memories 154, 156 or 158 and also causes reading the literal A from memory to the appropriate read-only memory 125 in the vector logic unit (Fig. 3), while at the same time the literal B is read from the input queue to the same read only memory 125 in to address the vector logic unit.

Remember to address the vector logic unit.

Recall that the vector logic unit operates in series Arithmetic is a unit that works on two characters at the same time, each one one character from the two operand fields. When the vector logic unit does its job of adding the operands A and B has been completed, the microprogram determines whether the result field in the second vector group is full. As in this example if it is empty, it will be the result of adding the literals A and B in the appropriate one Save the result field in the first vector group. As a result of the third Operand group appearing on the input queue becomes the subtraction program group be structured in the memory like position 4 under the heading "storage" (= Memory) shows, namely the operand fields in which the literals A and 3 are occupied are, namely the fields 355 and 359, are now empty because they contracted while reading became; the result field 359, which contains the result of adding A and B, is full. The literal D is also available as an operand of the second vector group.

The only missing operand at this point is the literal C. Now assume that an operand group arrives which contains the operand C in the field 386 contains. Control determines that this is a literal group and closes the appropriate paths so that the memory address field 380 is the second vector group can address. The control will then read this vector group, the vector logic unit set to perform the operation desired by the operator code field and the sum G and D in the same manner as described for operands A and 3 calculated.

However, when this operation is completed, the result field 369 of the first addition program subgroup is full, besides saving the result the sum of the literals C and D in the result field 367 a further microprogram selected, that the vector logic unit corresponding to the subtraction operator code field in the Subtraction program croup. This microprogram leaves the control unit supply the vector logic unit with the result in a character-serial manner the summation A + 3 from result field 369 in calculator memory if the result from C + D so that the two results can be subtracted.

During the execution of this operation, the content of the destination field 343 of the subtraction program group to the destination address memory 157 of the output queue 29 (Fig. 5) supplied. This destination address field 375, in Fig. 12B under the Heading t? Output queue "(= output queue) specified in position 1 is a Destination vector group, the first field of which is a description field 381 which is contained in the In the present example, the group is designated as a literal or operand group; it an address field 383 follows, followed by an operand location field 385. such as field 387 may follow the operand location field. As the syntax of a group structure Must be followed, the destination address group ends with an end field 391. Because of its vector group nature, the destination address field is also with provide optional space between the individual fields, such as the space 389. The operand field 387 contains nothing stored at this point and is therefore in a contracted form. If the vector logic unit receives the result subtracting the literals c + D from the literals A + B, it will be as in position 1 under the heading "toperand memory" (= operand memory) of FIG.

123 specified, to the operand memory 155 of the output queue (Fig. 5) sent.

The output control 159 of the output queue 29 transmits a Message in a form that is essentially identical to the one Form is obtained at the input queue and in Figure 123 under the heading "message transmitted" is specified. There in our example the result is a literal, the transferred group is an operand group, limited by a right bracket 377 and a left bracket 379.

The first field is a description field 381 which defines the group as an operand group Are defined. The second field is an address field 383. This address field can according to Fig. 123 can be a simple field containing a peripheral unit designation 384, or, in the case of a multi-processor system, component fields may contain, such as a field 386 defining a processor unit; and a memory address field 388, which designates a specific area in the memory of the addressed processor.

The field following the address field is an operand location field 385, if so this should be necessary. The field following the operand location field is the result field 393.

The operand group leaving the output queue ends with a Closing field 391 and a right bracket 379.

Overall, therefore, from the above functional description It is clear that the computer of FIG. 1 carries out an operation only after two data structures are connected, one of which is a program structure and the other is an operand structure. In the case of a specific example, is the program structure stored in the form of program groups in the computer memory and awaits the Arrival of operand structures or operand groups, the appropriate program groups address and the control of the computer for the execution of the designated program cause. This data stream driven operation therefore results in a digital data processor, who has superior emulation capabilities and as a basic building block for a multi-processor data processing system can be used, whereby each building block in its functions through the in program groups stored in the respective storage areas is defined. There the arrival of the operand groups at the input of a special data processor Activation of the addressed program causes when such a computer as Basic module is used in a multi-processor data processing system, is omitted the need for a main control program or elaborate interruption systems provide for the interaction of the processors in the multi-processor system have to regulate. The above description, as can be seen, makes it clear that the computer of FIG. 1 has improved emulation capabilities because the four character dictionaries in a character serial computer the scope with data structures variable field length facilitated. These data structures are created in a simple manner checked for errors by using simple logic circuits in the data flow path will.

Overall, it became a serial, electronic, with Describes a calculator that works with digits and uses a four-character vocabulary, where each character is represented by two binary bits and is structured in this way is that it can process character serial data that arrive at the computer, wherein the processing is specified and triggered by the incoming data Way done. The data structures that are sent to the data arriving at the computer Define the program or operations to be executed are in the memory area of the Computer in the form of networked data structures stored in tree-like Branch can be represented, each node being the tree-like branch structure represents an operation. The operands represent data structures are also fed to the computer in a networked organization. This operand data address a certain node or operation that is in the memory area of the computer. Linking the incoming operand data with their Program data triggers the execution of the operation. In one Case where more than one operand is required before an operation is performed the arrival of a first operand without the second operand to store the first operand until the arrival of the second.

The arrival of the second operand then triggers the start of the operation the end. This interaction of the program data and operand data, i.e. the connection dynamic data with static ~ data to trigger the operation, always exists, be it that the program data is stored and static or the operand data are stored and static.

When using a four-character vocabulary to represent the data, where two of the characters are used to indicate the beginning and the end of a data field facilitates the implementation of an error checking technique in which only Sensed characters that indicate the beginning and the end of a data field are counted will. The use of the beginning and ending mm data field characters in the data structures consisting of injured data fields allows any expansion and contraction of the fields in them.

Claims (62)

Expectations 1. Binary data processor with an input circuit (21), one Memory (25), a logic circuit (27), an output circuit (29) ~ and a connected to it controller (23), which the data traffic between the said Units allows, the memory (25) containing data groups consisting of data characters containing data fields exist, furthermore the input circuit (21) incoming Data groups can take up, and one of the data fields a memory address for contains a data group in the data memory (25). 2. Processor according to claim 1, characterized in that the data memory Contains binary information that is interposed between the data groups and the data fields and show the beginning and the end of the data groups and data fields. 3. Processor according to claim 1, characterized in that the data memory Contains data groups representing program data; and that the input circuit Can accommodate data groups that represent operand data. 4. Processor according to claim 3, characterized in that the one Fields in the program group that form the program group are separated by white space are separated in which the fields can expand. 5. Processor according to claim 3, characterized in that the in the Data memory residing program data group one or more program groups contains that a special program field and a destination address field assigned. 6. Processor according to claim 1, characterized in that an output Circuit for receiving a destination address field and operand fields as well is intended to be linked to an output data group. 7. Processor according to claim 1, characterized in that the groups are structured in a hierarchically networked order in the memory (25), and that the data groups in the input circuit (21) are networked in a hierarchical manner Are structured in an orderly manner. 8. Processor according to claim 7, characterized in that the data memory Contains binary information that is inserted between the data groups and the beginning and end of the data groups. 9. Processor according to claim 7, characterized in that an output circuit for receiving a destination address field and at least one operand field as well as for linking these to form an output data group is. 10. Processor according to claim 7, characterized in that the data memory Contains data groups which represent program data, and that the input circuit Receives data groups representing operand data. 11. Processor according to claim 10, characterized in that the one Program group fields in the program group are separated from each other by white space are separated in which the fields can expand. 12. Processor according to claim 10, characterized in that the in program data group residing in the data memory one or more Contains program groups, which have a special program field and a destination address field assigned. 13. Processor according to claim 10, characterized in that the one Operand group fields in the operand group are separated from each other by spaces are separated in which the fields can expand. 14. Processor according to claim 7, characterized in that the data groups, which are received by the input circuit, an operand field, an operand identifier tion field and no memory address field included. 15. Processor according to claim 1, characterized in that the data traffic Via serial data transmission channels (31,35,39,47,45,51,53,59,33) in character serial Way, where a character is two binary bits long. 16. Processor according to claim 15, characterized in that the data memory Contains binary data that is inserted between the data groups and the beginning and show end of data groups. 17. Processor according to claim 16, characterized in that four characters used to represent all data, two of which are high signals binary 1 sign, two low signals, a binary O sign and a combination from a high and a low signal either start data or end data characters represent. 18. Processor according to claim 15, characterized by an output circuit for receiving a destination address field and an operand field and for Linking these to form an initial message group. 19. Processor according to claim 15, characterized in that the data memory Contains data groups which represent program data, and that the input circuit Receives data groups representing operand data. 20. Processor according to claim 19, characterized in that the in the data memory resident program data contain operand fields to which a Program field for editing is assigned to a program group, and that the operand fields empty and contracted until they are suitable, inscribed by inclusion Operands are expanded. 21. Processor according to claim 20, characterized in that the fields which form a program group, from each other within the program group by white space are separated, in which the fields of the group can expand. 22. Processor according to claim 19, characterized in that the in the data memory residing program data groups one or more vector groups to which a special program field and a destination address field are assigned is. 23. Processor according to claim 15, characterized in that the of the input circuit received data groups operand fields, an operand identification field as well as a memory address field which form a group of operands. 24. Processor according to claim 23, characterized in that the one Operand group fields in the operand group are separated from each other by spaces are separated, in which the fields of the group can expand. 25. Processor according to claim 1, characterized in that the groups in the memory (25) are composed of data fields which contain data characters, where the data fields and the data groups are represented by data start and data end characters are limited; that each of the stored data fields is organized into a data group which has the following format: ((A) (B) (c) ..... (D) (E)), where the left brackets Data start character, the right brackets data end character, A a description field, that denotes the types of the following fields, B, c and D mean data fields that May contain operands or operators, and where E is a terminating field; that the data groups in the input circuit (21) are composed of data fields are that contain data, the data fields and data groups by data start and End of data characters are limited and the data fields are organized in a data group are with the following format: ((A) (3) (ä) CD) (E)), in which the left brackets denote the Data start characters, the right brackets the data end characters, A a description field, which designates the types of the following fields, B, c and D data fields, the operands or can contain operators and E signify a terminating field; and that one of the Data fields B, c or D a memory address for a data group in the memory (25) contains. 26. Processor according to claim 25, characterized in that the description fields and the data fields themselves consist of data structured in the group format are. 27. Processor according to claim 25, characterized in that the data groups follow the following syntax rules: 1. no binary information between in same Direction of opening brackets; 2. is the first field of a group always the description field; 3. the last field of a group is always the closing field. 28. Processor according to claim 25, characterized in that the data fields in the data groups are separated from one another by white space, which is used for expansion the data fields can be used. 29. Processor according to claim 25, characterized in that four characters can be used to represent all data, with two high signals one binary 1 sign, two low signals, a binary O sign and a combination of high signals and low signals represent either a start of data or an end of data character. 30. Processor according to claim 29, characterized in that the description fields and the data fields themselves are made up of data structured in the group format are. 31. Processor according to claim 29, characterized in that the data fields in the data groups are separated from one another by white space, which is separated by several Binary characters is represented and used to expand the data fields can. 32. Processor according to claim 25, characterized by an output circuit for receiving the destination address field and an operand field as well as for linking this to form an initial message. 33. Processor according to claim 32, characterized in that the operand field and the destination address field received from the output circuit, Contain data structured in the group format. 34. Processor according to claim 25, characterized in that the description field contains program-designating data in the data groups in the data memory, and that the description field in the data groups in the input circuit designating operands Contains data. 35. Processor according to claim 34, characterized in that the description fields and the data fields themselves are made up of data structured in the group format are. 36. Processor according to claim 34, characterized in that the data groups obey the following syntax rules: 1. no binary information between two in the same Directional brackets; 2. the first field of a group is always a description field; 3. the last field of a group is always an end field. 37. Processor according to claim 34, characterized in that the data fields in the data groups are separated from one another by white space, which is used for expansion the data fields can be used 38. Processor according to claim 34, characterized in that that four characters are used to represent all data, two of which are high Signals a binary 1 character, two low signals a binary O character and one Combination of a high and a low signal either a data start or Represent end of data characters. 39. Processor according to claim 34, characterized in that one of the operand fields in the data groups in the memory for storing a Destination address is provided and the operand fields are contracted when they are empty until they are expanded by suitable operands when they are filled. 40. Processor according to claim 1, characterized in that data transmission channels (31,35,39,47,45,51,53,59,33) are provided which have a transmission device (85) for essentially simultaneous transmission of two discrete signal levels and a sensing device (63) at the receiving ends of certain data transmission channels are provided that senses and interprets the two discrete signal levels, two high levels a binary 1 character, two low levels a binary 0 character and a high level and a low level a data start character or a data end character mean. 41. ~ Processor according to claim 40, characterized in that the between The transmission device switched on to the circuits has two electrical signal conductor paths and that the sensing device interprets the two discrete signal levels so that a high level and a low level are interpreted as data start characters, when the high level is on a first conductor path and the low level is on a second conductor path occur, and a high signal level and a low signal level interpreted as an end-of-data character when the high signal level is on the second Conductor path and the low signal level occur on the first conductor path. 42. Processor according to claim 40 or 41, characterized in that an up / down counter is connected to the sensing device and when it is detected of a data start character continues to count by one unit and when a End of data character counts down by one unit. 43. Processor according to claim 1, characterized by an error detection device (65) to determine errors that have occurred in data, only counting certain characters that are transmitted over the serial data transmission channels. 44. Processor according to claim 43, characterized in that for representation of all data four characters are used, with two high signal levels binary 1 character, two low signal levels, a binary O character and a combination from a high signal level and a low signal level either a data start or represent an end of data character. 45. Processor according to claim 44, characterized in that the error detection device the data start and data end characters count. 46. Processor according to claim 45, characterized in that the error detection device indicates an error that has occurred when an end-of-data character is detected and the count of the start and end data characters did not result in zero. 47. Processor according to claim 43, characterized in that the error detection device means for sensing the characters having first and second data input lines as well as an up / down counter which counts one unit further when a data start character has been established and counts down a unit, if an end-of-data character was established. 48. Processor according to claim 1, characterized in that a recursive Mechanism of data structures stored in the memory as well as from the input circuit has received data structures, the data structures stored in the memory Represent program data in a hierarchically networked order accordingly Program data groups are organized, which consist of operand fields and a result field exist, to which a special program description field is assigned; and that the data structures stored in the input circuit represent operand data, which are organized in a hierarchically networked order and addressing cause certain data structures in the memory. 49. Processor according to claim 48, characterized in that a program data group at least one operand field and one destination address field, which is a program description field is assigned, wherein the operand field is a vector group consisting of at least an operand field, a result field and a vector description field. 50. Processor according to claim 48 or 49, characterized in that the operand fields and the result field of the vector group are pulled together, if they are empty and are expanded when data is written. 51. Processor according to claim 1, characterized by a recursive one Mechanism in which data structures are stored in memory and program data represent that in a hierarchically networked order according to: ((P) (OP) xxx ((V) (OP) xx (A) xx (B) xx (R) ()) xx (C) xx (DA) ()), with all through Brackets limited Areas within the brackets are fields, P a program description field, OP an operator field, A, B and C operand fields, V a vector description field, R a result field and DA a destination address field mean. 52. Processor according to claim 51, characterized in that the operand field and the results field are contracted if they are empty, and if they are registered Data are expanded. 53. Processor according to claim l, characterized by a recursive one Mechanism in which data structures are stored in memory and program data represent that in a hierarchically networked order corresponding to a program data group with the format: ((P) (OP) xxx ((V) (OP) xxCA) xxC) xxCR) ()) xx (C) xx (DA) ()) are, with all areas delimited by brackets within the brackets fields P is a program description field, OP is an operator field, A and C are operand fields, V is a vector description field, R is a result field and DA is a destination address field meaning and data structures received from the input circuit and operands represent that in a hierarchically networked order according to the operand sets are organized that consist of at least one operand field and one memory address field are combined with the associated operand description field. 54. Processor according to claim 53, characterized in that the operand fields and the result field in the memory are contracted when empty and with the Writing data to be expanded. 55. Data stream driven information processing system marked by a storage unit that contains one or more control operators stored one a programmable unit containing a logic unit for Execution of operations on data segments, by an input device that is coupled to the logic unit and data segments for transmission to the logic unit receives, as well as by a control unit, which is connected to the input unit and the logic unit and the memory is connected and on the memory unit for a control operator accesses depending on the receipt of a data segment from the input unit, wherein the logic unit indicates the performance of an operation on the data segment will. 56. Information processing system according to claim 55, characterized in that that a source of data segments is provided, the data segments of the programmable Unit for performing operations supplies. 57. Information processing system according to claim 55, characterized in that that a programmable unit is connected to other programmable units and receives a data segment therefrom, an operation on the data segment executes after at least one other programmable unit has already performed an operation performed on the data segment. 58. Information processing system according to claim 55, characterized in that that connection means for serial data transmission to and from the units are provided. 59. Information processing system according to claim 55, characterized through a peripheral data source to which the programmable unit is connected and controls the data transfer. 60. Information processing system according to claim 55, characterized in that that the control unit of the programmable unit contains a memory in which Control signals are stored. 61. Processor according to claim 1, characterized in that the input circuit a FIFO buffer (67,75,69). for receiving the data groups. 62. Information processing system according to one of claims 55-60, characterized in that a data segment is received by the programmable unit that is on the memory unit that is connected to the programmable unit is accessed when the data segment is received and a control operator is selected the memory is fetched; and that of the logic unit of the programmable unit the execution of an operation on the received data segment is indicated. L e r s e i t e