DE2500320A1 - PROGRAMMABLE CONTROL UNIT - Google Patents

Description

TEXAS INSTRUMENTS INCORPORATED
13500 North Central Expressway
DALLAS, Texas / V. St. A.

Our reference: T 1708

Programmable control unit

Briefly summarized, the invention relates to a programmable control unit containing a memory device for storing commands and 1-bit data words, represent partial results, intermediate calculations or the like; the control unit also contains devices to retrieve such words for use in further calculations.

In a preferred embodiment, the control unit constructed with integrated semiconductor circuits contains a Memory for storing multi-bit commands and 1-bit data words, wherein a processor is selectively coupled to the memory for processing the data in accordance with the instructions is. A stack memory is attached to the processor for storing partial results of the processor calculations selectively connected with the width of a 1-bit word.

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The partial results are from the stack in the reverse Order of their entry depending on the completion of invoices of a further section of the Calculations read. The result of the other section of the calculations is taken from the stack with one Partial result combined.

According to a further feature that is useful alone or in connection with the embodiment described above, A programmable control unit contains input elements that are used to determine the state in each of several multi-wire Lines of a relay conductor circuit are scanned. According to a programmed group of commands, which are stored in a control unit memory, connect output elements of the relay conductor circuit supply voltage sources with energy consumption units and separate them from the supply voltage sources, thus from the Relay chain circuit required operating conditions are met. Scanners generate in a sequential manner a group of 1-bit words, one of which represents the state of each of the input elements. It will a group of 1-bit output control states is generated depending on the states of the input elements, with each generates an output control state for an output element will. A timing device operating once per half cycle of the supply voltage triggers the generation and storage of 1-bit input words and 1-bit output control states in a read / write semiconductor image register. Furthermore, the time control device contains a control device for sequentially creating a serial input / output operation, in which the input elements are scanned and the output control states are read from the register and switched on the output elements are applied, which is followed by a running mode in which a new group of control states is generated and stored in the registers.

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According to one feature, the invention relates to a programmable one Control unit that allows for practically an unlimited number of parallel paths in each line or rung a circuit corresponding to a relay conductor circuit. In terms of this particular characteristic relates the invention is based on an unaddressed, 1-bit stack and to circuits connected thereto for temporarily storing intermediate calculation results and for retrieving such intermediate results for combination with subsequent calculations. According to another Feature, the invention relates to a programmable control unit in which multi-core lines with Multiple branches in relay conductor circuits by scanning the states of input elements of these lines and by generating control state signals for output elements of the lines are controlled, in this course 1-bit flags in a read / write image register stored within the control unit, eliminating the need for the use of output devices for number plate storage exists.

Multiple relay systems have hitherto been used to power machines that are powered by alternating current sources were to control depending on conditions. Such systems have generally been implemented by controlling electrical circuitry in the form known as ladder circuits. .

Several attempts to overcome the difficulties in simplifying assembly procedures are described in Control Engineering ", September 1972, page 45 ff.

The invention relates generally to the field of programmable control units. Programmable control units have so far been used to control machines, processes, electromagnets, Engines etc. have been provided. Such control units

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has generally been a larger number of output storage devices assigned. In the course of the generation of control states from a machine with a control unit must Intermediate results of calculations are saved. In the past, such results have been in output storage devices has been stored, which is an expensive way of storing the capacity of a given System as it makes use of a large number of available output storage devices. if an output intermediate result in an output storage device has been saved then it is not available for further calculations, if not a substantial one Expenditure on electronics and wiring is provided, which enables these output variables to be read.

Existing programmable control units restrict the programmer on a few parallel paths in each line or rung of the relay ladder circuit logic. Because of the complexity normally encountered in such logic arrangements, those previously existed Overly restrictive boundaries. The suitability for an unlimited number of parallel paths in each line one Relay conductor circuit would therefore be desirable.

The invention eliminates the limitation of the previously known systems by using a non-addressable one Storage in the form of a basement with the width of a 1-bit words. This enables the temporary storage of intermediate results of calculations. The interim results can then be called back for combination with further calculations. The operations can also be performed with Boolean Equations are executed that are broken down into subgroups. Each group can be separated after the calculation and Storage in the stack retrieved and combined to produce the final result of the equation will. For the invention, the fact is important

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that the word length is only 1 bit. It is also important that the length of the stack, i.e. the number of bits that can be stored, is practically unlimited. According to the invention, this is achieved with the aid of a programmable control unit, which is constructed from integrated semiconductor circuit units, - "the memory devices for storing multi-bit commands and 1-bit data and processing devices selectively coupled to the memory devices for processing the data accordingly included with the commands. According to the invention, a stack is selective for words of one bit length connected to the processor for storing partial results of Boolean calculations. Facilities are provided with the help of which the partial results in the reverse order of their input depending on the completion of calculation steps in a further part of the Calculations can be read back from the stack. In addition, facilities are provided with their Help the result of the other part of the calculations can be combined with the partial result retrieved from the stack.

According to a further feature of the invention, a relatively inexpensive memory for intermediate results is provided in an in Random access memory accommodated in the electronics of the arrangement was created. The numerous interim results of Calculations can be stored in such a memory; they do not have to be in home storage devices saved as it would otherwise be necessary. By using the random access memory to store all output values in parallel with their storage in an output storage device, they can be made available for use in further calculations. According to this last-mentioned feature of the invention, a semiconductor read / write image register is created in a programmable control unit, which has input elements which are used to

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Mood of the state of each of multi-core lines can be scanned in a relay conductor circuit. The control unit also contains output elements in the conductor circuit, connect the supply voltage sources to energy consumers and these according to a programmed set of Separates commands that are stored in a memory of the control unit, so that required operating conditions the conductor circuit are met. The arrangement contains .Scanners which sequentially a group of 1-bit words generated, each of which represents the state of one of the input elements. The arrangement also includes Devices which, depending on the state of the input elements, generate a group of 1-bit output control states from each of which there is one for each of the output elements. A timing device operates every half cycle the supply voltage, the generation and storage of the 1-bit words and the output control states in the register. Devices are also provided for generating identifiers in the course of determining the output control states. Storage devices are also provided for storing the identifiers in the image register for reading out on retrieval.

The invention will now be explained by way of example with reference to the drawing. Show it:

Figure 1 shows a programmable time control system, Figure la and Ib the keyboard switch matrix of Fig. 1,

FIG. 2 shows a typical conductor circuit representing the installation of FIG. 1,

Figures 3 and 4 show the main section of the sequence control arrangement *

FIG. 5 shows the memory sections of the sequence control arrangement,

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FIG. 6 certain control units of the arrangement of FIG. 3 to 5,

Figure 7 to 10 details of a programming unit used here,

Figure 11a to He pulse diagrams, FIG. 12 shows the mutual position of the

3 and 4, FIGS. 7 to 10, FIGS. Ha to Hc and FIGS. 13 and 14, and

13 and 14 the input / output units used here.

The invention is described here in connection with an embodiment of a programmable control unit arrangement, in which there are three separate units. The first unit is a control unit, which consists of a programmable Sequence control arrangement consists with a set of instructions stored in a memory and contains devices that serially interrogate the input devices that are used to Display the status of input elements assigned to various controlled devices.

The second unit is a programming unit, which is responsible for this is applied, the desired command is initially in the. To store sequence control arrangement, so then a desired Group of operations is processed independently of a controller according to changing conditions. To the For initial programming of a given controller, a programming keypad can be used which is then used by the Arrangement can be separated and used elsewhere until the control unit requires another change in its mode of operation.

The third unit consists of a group of input and output devices which extend at various desired locations along one of the sequence control arrangements

Cables are connected. Generally, one or more of the output devices serve to provide an AC power source to connect to a consumer such as a motor, an indicator lamp, an electromagnet or the like. The arrangement works so that input devices along the cable to determine their condition in a ordered sequence can be queried at least once per half cycle of the supply voltage. The states of the input devices are stored in the flow control arrangement. After that, due to the activity of the Sequence control arrangement formed control states from serially read the memory of the sequencer, applied to the cable, and memory devices of the output devices supplied so that the state of the output devices if necessary, for example to switch on or switch off the Engine is changed.

Thereafter, the is stored in the memory of the flow control arrangement Command set is queried and used to process the input data received from the input devices have been obtained so that a new set of output states is generated. This way the conditions can of the output system can be changed selectively at intervals which are not greater than a period of the supply voltage are.

The arrangement described here relates to improvements in the implementation of the portion of the operation in which by the activity of the sequence control arrangement generates identifiers will. In particular, the arrangement described here relates to operations in which intermediate results of the activity the flow control arrangement in a read / write memory in Form of an image register can be stored so that they can be recalled at any time during the generation of the output states Are available.

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Figure 1

In Fig. 1, a programmable control unit IO is shown, that via a plug 39 8 and a multi-core cable 399 with an input / output base unit 400 and from there via a Cable 399a is connected to an input / output base unit 401, with a cable 399b pointing in the direction of arrow 402 further basic input / output units, which can be at any desired point. The programmable control unit 10 is a hardwired one in itself Completed process flow control unit, which is programmed by a plug-in input unit 6OO. The scraping unit 600 is connected to the control unit 10 with the aid of a cable 600a via a plug 600b.

The basic input / output unit 400 contains a plurality of input / output connections, for example connection 409, for various circuit elements. The basic input / output unit 401 is also provided with multiple input / output ports such as ports 411 and 414. The connections are for example used in the control of an X-Y coordinate drawing table 404. A motor 405 drives the Table 404 along an axis. The table 404 is driven by a motor 406 along the other axis. A Limit switch 407 is mounted so that it is operated when it is touched by table 404. The engine 406 is over Connection conductor 408 with the output terminal 409 at the Input / output base unit 400 connected. The switch 407 is via connection conductor 410 to the input terminal 411 connected to the input / output base unit 401, ftber Connecting conductor 413, a pressure switch 412 is connected to the input connection 414 on the base 401.

The programmable control unit 10 is used, for example, to switch on the motor 406 only when the both switches 407 and 412 are closed. Such an effect would occur depending on control states that

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are stored in a memory in the control unit 10. Via the memory in the control unit 10, the input unit 6OO loaded with the desired control states.

In the exemplary embodiment described here, the basic input / output unit 400 contains eight input connections 40Oa and 40Oa eight output terminals 400b. In the same way, the Basic input / output unit 401 has eight input terminals 401a and eight output terminals 401b.

Figure 2

The arrangement works depending on command voltage states, which are loaded in the terminology of conductor circuits, as they are normally used in wiring of power supply arrangements are applied. Fig. 2 For example, Figure 12 shows a typical ladder circuit with limit switches 407 and pressure switch 412 in series are connected to the motor 406 between power supply lines 415 and 416, which are connected to the base unit 4OO Supply cables 397 leading from Fig. 1 are included. In the same way, the engine 405 is in series with the same Control elements connected between lines 415 and 416, a third circuit between lines 415 and 416 can consist of three parallel switches leading to a timer 417 and a control relay 418 in which the Timer is effective when one of the switches connected to it is closed.

The embodiment of the invention described here is suitable for 256 output elements such as output port 409 and for 256 input elements such as the input terminals 411 and 414. The arrangement shown in Fig. 1 enables instructions to be stored for realizing many connection paths in a ladder circuit. The arrangement can be expanded to cover a much larger number of elements in one through a ladder circuit

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represented system. This is done by using an unaddressed stack for caching purposes from intermediate results of programmed processing operations that can be achieved just as well with Boolean equations function that are broken down into subgroups, each of which is stored separately in a stack and then combined to produce final results of the Boolean relationship. In Fig. 2 are only simple ladder circuit elements are shown, but the arrangement of FIG. 1 is versatile in that it lends itself to an almost unlimited number of rungs in the ladder circuit with an unlimited number of elements in a given Rung is suitable.

The following is a description of the structure of the control unit 10, the basic input / output units 400 and 401, and the input unit 600. It can be seen that the input unit 600 is only used for programming a control unit. In operation, the plug 600b is only plugged in while the desired conductor circuit is being input into the control unit 10 will. Then the plug 600b is removed, and the input unit 600 is then available for programming further, control units installed at other locations.

Programmable control unit 10 - Fig. 3 to 6

The programmable controller 10 shown in FIGS. 3 through 6 has the individual ones described below Functional sections.

Counter - Data Register - Figures 3 and 4

Units 12 to 15 serve as serial input / output counters, when operating in a serial input / output mode, and as a storage command register when operating in an execution mode. You are working with an image register 20 together, as will be explained below.

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Bit and command counter - Flg. 3 and 4:

The units 36 to 38 are interconnected so that they form a bit and command counter for synchronizing and controlling the sequence operations in the arrangement.

Sample cycle counter - Fig. 3:

A counter 35 is used to count sample cycles that have been performed to aid timing operations which may be required if timers such as timer 417 of FIG. 2 are to be used.

Processor - Figure 3;

Units 61, 62 and 63 serve as primary processing units. The unit 61 is a main decoder and a Processor read-only memory. The unit 62 is a time counter processor read-only memory. The unit 6 3 is a Time counter status memory.

Synchronization Hold Circuit - Figure 3;

A start pulse for initiating each cycle of the control unit is transmitted via a synchronization hold circuit 11. The control unit 10 normally works with devices together, which are supplied with energy by lines 415 and 416 of FIG. 2, across which a voltage of 110 volts is present. The control unit 10 operates over a complete cycle within the time limits of each half cycle of the supply voltage. An input sync pulse applied to the terminal He of the sync hold circuit 11 is caused at the apex of each half-wave Supply voltage to occur.

After each synchronization pulse has been generated, signals that indicate the states of all control elements in the conductor circuit, For example, the switches 407, 412 etc. from FIG. 2, are read into the control unit and stored in the image register 20 via an AND circuit 417 serving for data input

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saves. After the data has been read in, recently generated control states are transmitted from the control unit 10 via a cable 399 output, from which a conductor leads to a NAND circuit 18 serving for data output. After that, everyone will Instructions in memory 25-28 or 30-33 of Figure 5 are reviewed and new output data is generated. Of the The cycle is then ended and the control unit waits for the next peak of the supply voltage to be triggered another control cycle.

The data output from the NAND circuit 18 is shown in Shift register memories are stored in the basic units 400, 401, etc. of FIG. These memories, in the form of double output registers, store output data that Form control conditions for a given time interval, as explained in connection with FIGS. 13 and 14 will. In the course of this time interval, new output data are stored in the other part of the double output register. Control changes from data in one half of the output register to data in the other half of the output register shifted after each zero crossing of the supply voltage curve.

Stack - Fig. 3;

Unit 80 is a stack of words with a Length of one bit. Results of logical arithmetic operations carried out by other parts of the control unit, are stored in this stack. The results can be saved in the reverse order to be fetched back. The length of the basement can be practically unlimited, with appropriate units Cascade to allow any reasonable number of results to be saved. the Intermediate results of the process control operations can be used for Combine with other expiration calculation results the stack 80 can be retrieved.

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Memory section - Fig. 5;

The memory section contains a random access memory (RAM) composed of four RAM units 25 to 28 and one programmable Read-only memory (PROM) made up of PROM units 30 to 33. Each of the RAM units 25 to 28 has a storage capacity of 1,024 bits with 10 input control lines, so that one bit can be read out at a time. The PROM units 30 to 33 are provided with 8 input control lines, so that four bits are output in parallel at a time can be. The RAM units 25 to 28 thus enable 256 commands of 16 bits each to be stored. the Instructions can be entered into the RAM units 25 to 28 using the input unit 600 when the NAND circuit 2 4 is enabled. The line 2 3 is a memory data input line which is used for the supply of Data to the RAM units 25 to 28 must be released. As an alternative, 256 commands can be used in the PROM units 30 to 33 can be saved.

It can be seen that in Figure 5, both the RAM units 25-28 and the PROM units are shown in place are. The RAM unit 25 and the PROM unit 30 are connected for parallel operation so that they are in the Arrangement occupy the same position. Only one of these two units is ever used. The same applies the RAM unit 26 and the PROM unit 31, for the RAM unit 27 and the PROM unit 32 and for the RAM unit 28 and the PROM unit 33. While Figure 5 actually shows an arrangement with redundancy, only four memory units become in the embodiment described here with the desired combination of RAM units and PROM units.

The commands stored in the RAM units 25 to 28 can be accessed by using the input unit 600 in the usual way Operating sequence for entering new commands or for Change existing commands. In contrast

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for this purpose the PROM units 30 to 33 are fixed, and they cannot be changed using the input unit 6OO. If both RAM units 25 to 28 as PROM units 30 to 33 are also used, commands in the form of 16 1-bit control states are sent serially via a logic circuit 34 read out.

Before the arrangement is described in more detail, there is an overview description of the desired one Way of working.

The arrangement is switched by three operating modes:

(a) a wait state, (b) a serial input / output state and (c) an execution state.

The waiting state:

The arrangement waits for the next occurrence of a peak value of the 60 Hz AC supply voltage. When a If the peak value occurs, a sync pulse is generated that triggers operation, with each cycle preceding exits when the next peak occurs.

The serial input / output operation;

This operating mode is triggered by the occurrence of the synchronization pulse. There are three separate stages involved in this serial input / output operation. During the In the first stage, the status of all input units (407, 412) on the basic units 400, 401 of FIG. 1 is read and stored in image register 20. In the embodiment described here, the image register 20 has a capacity of 1,024 bits. The input section of the image register 20 is limited to 256 bits. Thus, up to 256 input units are possible, the states of which can be read into the image register 20.

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During the second stage, a serial output operation takes place in which the in the center of the image register 20 stored 512 bits are read out serially. The 512 middle memory locations are used to store license plates used internally in the arrangement and available to any external device that may need such labels. No special use is made of it here, but it is storing such labels is part of the operation and reading them out is part of the second stage of work. The corresponding operations are contained in the serial I / O operation as an intermediate group of steps.

During the third stage, the last 256 bits of the image register 20 are read out and via cable 399 from Fig. 1 for storage in the basic units 400, 401, etc. transferred.

The one stored in the last 256 bits of register 20 Information is one during the previous cycle of operation and particularly during the execution mode information generated in the previous cycle.

The execution company:

In this operating mode, the memories 25 to

28 and / or 30 to 33 stored commands in the arrangement

is performed on input data stored in the first 256 bits of image register 20.

It should be noted at this point that in each of the basic units 400, 401, etc., a parallel input serial output shift register is included that for each input port (411) of a given basic unit, for example the basic unit 401, assigned, contains a bit. It is also a serial input parallel output shift register provided that one bit for each output

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ansdiIuB (409) which is assigned to a given basic unit _t, for example the basic unit 400. The shift registers in the basic units 400, 401 etc. are connected in cascade so that the states of all input units 407, 412 can be read serially into the image register 20 via the cable 399 during the serial section of the serial input / output operation. Thus, the bits stored in the first 256 storage locations in image register 20 represent the states of control elements, such as switches 407 and 412 of Figure 2, at the instant the serial I / O portion of the scan cycle occurs. At the end of the serial input / output operation, the states which the output units, for example the motors 405 and 406 are to assume, are read into the serial input / parallel output register, and they are stored there so that they can be applied via control devices that can be connected to the output units can be.

On the basis of the knowledge obtained so far, a description of details of the arrangement shown in FIGS. 3 to 6 will now be made, followed by a description of the mode of operation.

Control Unit - Figs. 3 and 4

A NAND circuit 11a in the hold circuit 11 is over a line 91 is connected to the clear inputs of the counters 13 to 15 and to the input of a run-flip-flop 21. A pulse on line 81 is a cycle enable pulse that enables the device to operate at each peak of the Supply voltage triggers.

The output Q of the flip-flop 21 is via a line 82 connected to the loading input of each of the counters 12 to 15 and to the control input of the AND circuit 17. The exit Q of the flip-flop 21 is connected via a line 83 to the control input of an AND circuit 17a. The AND

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Circuits 17 and 17a are connected to the inputs of a NOP circuit 17b connected via an inverter 17c and an AND circuit 17d to the data input of the image register 20 is connected. The data output of the image register 20 is via a line 84 to the data input A des Main decoding and processing read-only memory 61 connected, the output signal on the line 85 to the data input of the AND circuit 17a and to the D input of one D flip-flops 86 is returned, which is subsequently called Active indicator AI is referred to. The Q output of the AI flip-flop 86 is via the line 87 with the data input of the stack memory 20 and with the input terminal B of the read-only memory 61 in connection.

The Q output of the running flip-flop 21 is via the line 83 with an enable input and with a clear input each of the counters 36, 37 and 38 are connected. The carry output of the counter 36 is available via an AND circuit 88 with a second release input of the counter 37 in connection, whose transfer output via a line 89 on second release input of the counter 38 is connected. The carry output line of the counter 39 is via a Line 52 with a second enable input of the counter 36 and with a NAND circuit 90 in connection. The carry output of the counter 36 is connected to a second input of the NAND circuit via a non-equivalence circuit 91 90 connected. The non-equivalence circuit 91 has a control line 92 which is fed by a flip-flop 93 of FIG. comes, via which a control voltage is supplied, which represents a time window with a duration during which a Word can be written into one of the four RAM units 25 to 2 8. The NAND circuit 90 includes a third input line 94, to the flip-flop 95 of FIG. 6, a control voltage to achieve a serial input switching pulse is created. The output of the NAND circuit is connected to the charging terminal of the counter 39. The clear input of the counter 39 and the flip-flop 21 are supplied by a NAND circuit 21a.

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The output lines K2, KQD, K3 to Κ14 are lines which are contained in a cable leading to the RAM units 25 to 28 and to the PROM units 30 to 33. The output line K14 of the counter 38 is via an inverter 96 connected to the clock input of the counter 35. The output of the inverter 96 is connected to the two inputs of the NAND circuit lld via an inverter 97 and a parallel connecting line 9 8. The NAND-S ch al do tr Hd there a "sampling completed" signal from the NAND circuit Hb is supplied so that the holding circuit 11 is in a state for receiving the next, the input terminal He supplied synchronization pulse is reset.

An oscillator 50 is connected to the clock input of the counter 39 via a line 51. The oscillator 50 operates at a frequency of about 8 MHz. It is shown in more detail in FIG.

The output lines of counters 12 to 15 are labeled BO to B15 denotes; there are 16 output bits. The lines BO to B7 are each via non-equivalence circuits 100 to 107 are connected to the inputs A0 to A7 of the image register 20. The second inputs of the non-equivalence circuits 100 to 107 are connected to a line 108. When the signal on this line 108 is high, the addresses to register 20 are negated. the Clock inputs of counters 12 to 15 are fed via a NANP circuit 109.

The signal states on lines B 8 to BH from the counter 13 are used as timing function signals, as will be described in connection with FIG.

The lines B12 to B15 are connected to four inputs E to H of the read-only memory 61, so that the desired OP code groups are applied to the processor fixed value memory 61 will. The read-only memory 61 is provided with two connections X, X, which represent release inputs. The upper

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Terminal X is connected to the output of a NAND circuit 120, which is also at the release connection S / L (move / load) a 4-bit counter 63 and connected via a line 121 to an inverter 122, which is connected via a NAND circuit 123 leads to the clock input of the storage bin 80. The second release terminal X of the read-only memory 61 is of the Bit 0 line 124 fed.

The data input A of the read-only memory 61 is via the Line 84 is connected to the output of the image register 20. The input line D is taken from the carry line 125 (CRY line), which originates from the counter 35. The input B is connected to that of the terminal Q of the active indicator flip-flop 86 outgoing line 87 connected. The input C is connected via the line 127 to the output of the storage cellar 80 in connection.

The processor read-only memory 61 has four outputs Yl to Ϊ4: (I) The output Yl is via a line 85 with the Input D of the active indicator flip-flop 86 and to the AND circuit 17a connected; (II) the output Y2 is connected to an input of the NAND circuits via a line 128 123 and 129 connected. The output of NAND circuit 129 is connected to the clock input of the active indicator flip-flop 86 via line 130. The NAND circuits 123 and 129 are each output from a NAND circuit

131, whose inputs are supplied via a write pulse line

132 and bit 0 line 124 are fed; (III) the Output Y3 is connected to the AIQ (MCR or JUMP) line 133; (IV) output Y4 is on the booster line 134 with the input terminal 6 of the 4-bit counter 6 3 in connection.

The read-only memory 62 has four outputs Y1 to Y4: (I) the output Y1 is connected to the line 85, see above that it is parallel to the output Yl of the read-only memory 61; (II) the output Y2 of the read-only memory 62 is present via line 135 to the data input of counter 12

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in connection; (III) output Y3 of the read-only memory is connected to the memory write data line 23; (IV) the output Y4 of the read-only memory 62 is connected to the D input of a flip-flop 13 7, which serves as a carry flip-flop for the processor read-only memory 62.

The output Q of the flip-flop 137 is connected to the input D of the read-only memory 62. The input A of the Read-only memory 62 is supplied by a line 138. The input B of the read-only memory 62 is from the output BO of the counter 15 is fed as described above. The input C of the read-only memory 62 is supplied via a WAF line 139. The inputs H, G and E of the read-only memory 62 are connected to the outputs A, B and C, respectively of the counter 63 in connection. The input F of the read-only memory 62 is supplied by the EF line 40, which from Output of the linking the counter outputs K4, K5 and K6 NAND circuit 136 is coming. The output D of the counter 6 3 leads to the D output line 141, which in turn leads to FIG. The enable connection P of the counter 63 is supplied via a NAND circuit 142 which is connected to a terminal via the ROM load line is fed. The other input of the NAND circuit 142 is fed from the external charging line 144, The external charging line 144 is also connected to the enable terminal CE of the image register 20.

It can be seen that the switched clock line 110 is on the clock inputs of the counters 12 to 15, to the clock input of the carry register 137 and to the clock inputs of the counter 36 to 38 is connected.

A write pulse line 132 is connected to one of three inputs of the NAND circuit 109, the application of clock pulses on line 110 controls.

Data read from memories 25-28 and / or 30-33 appear on memory read data line 146 which

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is connected to the AND circuit 147. The output of the AND circuit 147 is connected to the input of an AND circuit 150 via a NOR circuit 148 and a line 149. The second input of the AND switch 150 is supplied by a NAND circuit 151, which is fed at one input from the output B of the counter 63. The other input of the NAND circuit 151 is supplied from the output A of the counter 6 3 via an inverter 152. The output signal of the AND circuit 150 is fed to a NOR circuit 153, the output of which is connected via an inverter 154 to the line 138 which leads to the input A of the read-only memory 62.

The output of the NAND circuit 151 is available via an inverter 155 also connected to an input of an AND circuit 156. The second input of the AND circuit 156 receives a Signal from output line 127 coming from the stack 80 is coming. The output of the AND circuit 156 is then connected to the second input of the NOR circuit 15 3.

A bit zero delay line 157 is connected to terminal 2 of counter 63.

A low battery line 15 8 is at an input of the NAND circuit 18 connected, which is in the data output path of the Image register 20 is located. The third input of the NAND circuit 18 is supplied via the start line 159.

Lines A8 and A9 are at inputs 9 and IO of the image register 20 connected. A line 160 for supplying a switched screaming pulse to the image register (IRGWP line) is connected to the R / W input of the image register 20.

A serial data output line 165 is drawn from the output of the NAND circuit 18 through an inverter 166.

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The counter output lines K3 to K14 lead according to FIG. 5. The register output lines BO to BIl merge with the lines K2 and KQD according to Fig. 6. The lines KO and Kl are not used.

A NAND circuit 166 provides an on / off on a line 167 Output clock signal. The inputs of the NAND circuit 166 receive a signal from the output Q of the flip-flop 21 as well the switched clock signal on the line 110 coming from the NAND circuit 109.

The output Q of the flip-flop 21 is connected via an inverter 168 to the run line 169, which leads to the input unit 600 used for programming.

The output of the NAND circuit 11b is available through an inverter 170 with the cycle release line 171 in connection.

It has already been mentioned that the external charging line 144 is connected to the AND circuit 147. The line 144 is also connected to an input of an AND circuit 173 via an inverter 172. The output of AND gate 173 is connected to a NOR circuit 148. The second The input of the AND circuit 173 is fed by the data input line 174 coming from the input unit.

Figure 5

In Fig. 5, the main memory of the arrangement is shown. It contains the RAM units 25 to 28 already mentioned above and the PROM units 30 to 33. Let me repeat it should be noted that in this embodiment four Storage units are used. These four can be any combination of units 25 and 30, the units 26 and 31, the units 27 and 32 and the units 28 and 33 exist. A group of four could consist of the units 25 to 28 exist. Another group could include units 25-27 and unit 33. Another group

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could consist of units 25, 26, 32 and 33 etc.

The counter output lines K4 to K14 are at address inputs of storage units 25 to 28 and 30 to 33 are connected. The lines K3 to K12 are connected to the inputs A0 to A9 of the storage units 25 to 2 8 connected. The lines K5 to K12 are connected to the address inputs AO to A7 of the storage units 30 to 33 are connected. The lines Kl3 and Kl4 are connected to the inputs Λ and B of a data selector 175 connected. The data selector 175 is with output select lines 180 to 183, which release the PROM units 30 to 33, respectively. A data selector 177 is with Output enable lines 185 to 188 are provided, which enable the storage units 25 to 28, respectively. The data picker 175 and 177 form a unit known as a demultiplexer. A multiplexer 190 has inputs A and B that are connected to the Lines K3 and K4 are connected. Each of the memory units 30 to 33 is provided with four output lines Y1 to Y4 Mistake. The output lines Y1 through Y4 are one of four Collective line 191 comprising output lines connected in parallel, which leads to inputs ICO to IC3 of the multiplexer 190. An output line 192 leads to a flip-flop 19 3, whose clock input is fed via line K2. The output line 194 of the flip-flop 19 3 is on an output logic circuit 34 connected, whose Output to memory read data line 146 and via an inverter 196 to memory read data line 19 7 leads. the Data on line 146 are used in sequence control unit 10. The data on the line 19 7 are used in the input unit 600.

The data output line 19 8 emanating from the data outputs of all memory units 25 to 28 is at the second input the NAND circuit 34 is connected.

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Figure 6

FIG. 6 shows the logic modules which are used to generate control state signals and time control signals can be used for the operation of the previously described process control unit IO

A main control relay and jump unit 210 contains two 4-bit counters 211 and 212. The from Counter 15 of Fig. 4 coming lines BO to B3 connected. The lines B4 to B7 are connected to the inputs of the counter 212 is connected.

The counters 211 and 212 are up / down counters. Of the The output of the counter 211 is connected to the down-counting input of the Counter 212 connected. The output of the counter 212 is at the clear input of a flip-flop 213 and at the preset input of a flip-flop 214 connected. The output Q of flip-flop 213 is connected to the clock input of flip-flop 214 and connected to one input of a NAND circuit 215 and to the charging inputs of the counters 211 and 212. The exit Q of flip-flop 213 is connected to an input of a NAND circuit 216, the output of which is connected to input D of flip-flop 213. The Q output of flip-flop 213 is also connected to the count output line 217. the Line B14 is connected to input D of flip-flop 214. The cycle enable line 171 is at the clear inputs the counters 211 and 212 are connected. The sequence control output line 128 from output Y2 of the read-only memory 161 is connected to an input of the NAND circuit 215 and to an input of a NAIiD circuit 218. The second input the NAND circuit 218 is supplied from the Q output of a flip-flop. The output Q of the flip-flop 95 indicates a signal the serial input line 94 from. The reset input of the flip Flops 95 is supplied with the end-of-cycle signal on line 163, which is the output signal of NAND circuit 21a of Fig. 3 is.

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250G320

The main control relay and jump unit 210 is used to generate an output signal at the output Q of the flip-flop 213, this controls whether the system is in a JUMP mode or in a main control relay mode (MCR mode) is working. The flip-flop 213 shows the main control relay mode or the jump mode while the flip-flop 214 only indicates the jump mode. When the signal at the Q output of the flip-flop 214 is low, the system operates in a jump mode.

The output Q of flip-flop 214 is connected to an input of a NAND circuit 220 whose output signal on line 160 _it erscheint.D clock input of flip-flop 95 is supplied from the line ΒΘ. The main control relay and sprun

Unit 210 thus contains counters 211 as main components for generating the signals on lines 160 and 217, 212 and the flip-flops 213, 214, 95 and the NAND circuit 220.

The input line B8 is via an inverter 221 with a Input of a NAND circuit 222 connected. The output of the NAND circuit 222 is at an input of a NAND circuit 223 connected, which is the second input of a non-equivalence circuit 203 feeds. The second input of the NAND circuits 222 and 223 and the non-equivalence circuit 202 are each supplied via the line BIl. The third input of the NAND circuit 222 is supplied via the BIO line. The second input of the non-equivalence circuit 203 is via the line B9 supplied.

The run line 82 is connected to one input of the NAND circuit 200. The output of the NAND circuit 200 is available via an inverter 201 with the "negation at 1" line 108 in connection. The second input of the NAND circuit 200 is supplied via the line B8, which is connected to the NAND circuit 200 via a non-equivalence circuit 202.

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The output of the antivalence circuit 202 appears on line A8. The signal on line A9 is generated at the output of non-equivalence circuit 203, the output of which is also connected to the third input of the NAND circuit 200.

The circuit leading to the WAF line 139 contains an AND / OR negation circuit 224, an inverter 225, a flip-flop 226 and an inverter 227. This circuit is used to multiplex the AIQ signal on line 87 and the signal on line B15. Line B15 is at the entrance D of the flip-flop 226 connected. The pulse line 126 for bit 0 is connected to the clock input of flip-flop 226 tied together. The D line going out from the counter 6 3 is connected to the input of the inverter 227, the output of which is connected to the preset input of the flip-flop 226 is connected. Of the Output Q of flip-flop 226 is connected to an AND circuit in AND / OR negation circuit 224. Of the Output B of counter 63 is connected to inverter 225, the output of which is connected to the second AND circuit in negation circuit 224 and to the second input of the first AND circuit in negation circuit 224. The AIQ line 87 is connected to the second AND circuit in FIG Negation circuit 224 connected.

A write pulse on line 145 is generated with the aid of flip-flop 2 30, whose input D is connected to the KQD line from the counter 39 and whose clock input is connected to the line K2 from the counter 39. The output Q of the flip-flop 230 is connected to the write pulse line 145. Of the Output Q of flip-flop 230 is connected to a third input of NAND circuit 220 and to an input of a NAND circuit 231. The output of the NAND switch tuner 231 is the CPU3 line 232 included in the input unit 600 of FIG Fig. 1 is used. The line 233, which originates from the carry output of the counter 36, is with the input D one Flip-flops 2 37 connected. The clock input of the flip-flop

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the signal "switched clock" on the output line 110 supplied. The output Q of the flip-flop 237 is connected to the second input of the NAND circuit 231. The third The input of the NAND circuit 231 is supplied from the output KQD of the counter 39 via an inverter 238.

The outputs A and B of the counter 6 3, together with the external charging line 144, are used to generate a RITED signal on line 2 39 and a ROM LOAD signal on line 14 3 is used. Lines A and B are connected to an anti-valence circuit 240 and an inverter 241 with the line 143 in connection. The output of the inverter 241 is also connected to one input of a NAND circuit 242, to the second input of which the external charging line 144 is connected is. The output of NAND circuit 2 42 is with a Connected to the input of the NAND circuit 243, the output of which forms the RITED line 2 39.

The output of the NAND circuit 243 is connected to the input D of the flip-flop 9 3 via the line 239a. Of the The clock input of the flip-flop 9 3 is supplied from the output Q of the flip-flop 2 37. The output Q of the flip-flop 9 3 forms the RITEFF line 92, which is connected to the second input of the NAND circuit 2 43 is connected. The output Q of the flips-flop 9 supplies the complement of the signal on the line 9 2a.

The Q output of flip-flop 237 also appears as the BIT 0 output line 124. The BIT 0 signal on the line 124 is generated by using a flip-flop 244 as the "bit O delay" signal on line 157. The entrance D of the flip-flop 244 is connected to the output Q of the flip-flop 237. The clock input of flip-flop 244 is over the line K2 coming from the counter 39 is supplied. The output Q of the flip-flop 244 is then connected to the output line 157 and connected to the clock input of the flip-flop 213 via a line 157a.

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In the arrangement, provisions are made for an expected failure of the energy supply and of the staff members controlled by the control unit 10. This aspect concerns the battery 250 that powers the RAM memory power supply circuit 251. The RAM memory circuits are those shown in FIG. 5 as memory units 25-28. In the circuit shown in FIG. 6, the battery 250 is charged from a power supply which draws its energy from an alternating current network. The charge current received and supplied to terminal 252 is passed through a transistor 253 to the battery 250. The circuit operates in such a way that if the AC power fails and the voltage of the battery 250 falls below a certain value, the NAND circuit 18 of FIG. 4 is blocked against reading data from the basic units 400 _f 401 etc. and that all output elements in the basic units 400 and 401 are put into a state of recovery until the AC power is restored.

The voltage of the battery 250 is stored in an amplifier 254 compared with a reference voltage applied to line 255. If the supply energy fails, the Voltage on line 255 has the value 0. If the voltage on battery 250 does not exceed one of the voltage on the Line 255 represented by the default value is then the signal on the line 255a assumes a high value, which turns on the light-emitting diode 256 to indicate a low battery voltage. The line 255 is one input with one NAND circuit 257, which together with the NAND circuit 258 forms a hold circuit. The exit line 259 of the holding circuit 257, 258 is connected via a logic circuit 260 to the line 158 indicating a low battery voltage.

A power-on clear circuit 261 contains a Schmitt trigger NAND circuit 262, which via an inverter 263 with the second Input of the NAND circuit 258 is connected. The one

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The output of Schmitt trigger 262 is fed from terminal 264. A capacitor 265 slowly charges when the failed supply energy returns. The charging current flows through a resistor 266. The power-on-clear circuit 261 puts the signal at the output of the NAND circuit 25 8 a high value, which blocks the transistor 25 3, so that prevents is that the battery 250 briefly or at least so long that the comparison for determining the functionality of the battery 250 can be carried out. If the battery is inoperative, the assembly will not be allowed to operate after the power is re-applied starts operating automatically and without further ado.

A start switch 270 can, depending on its position, be the input of an inverter 271 or the input of an inverter Connect 272 to ground. When the input of the inverter 271 is grounded, the START line 159 is also on Dimensions. This prevents data from passing through the NAND circuit 18. When the switch 270 is in the other position in which the input of the inverter 272 is connected to ground is connected, the line 159 has a high level signal which enables the NAND circuit 18.

For the transmission of a switched clock signal PPGC to the input unit 600 of FIG. 1, an output line 273 is provided. The clock signal PPGC is output at the output of a NAND circuit 274, which is connected to the output Q of the flip-flop 9 3 connected input and a second, with the leading to an inverter 275 line 110 for the signal "Switched." The third input of the NAND circuit 274 is the RUN line 82.

In this embodiment, the processor 61 is a read only memory (ROM). The type H PROM 1-1024-5B read-only memory, which is included in the Table VII attached at the end of the description is given in more detail. The read only memory 61 was according to the at the end programmed in Table I appended to the description.

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The time control unit 62 is also a read-only memory (ROM). The type H PROM 1-1O24-5B was used for it, which is used in Table VII is identified in more detail. Read only memory 62 was programmed according to Table II at the end of the description.

In the preceding description, FIGS. 3 to 6 related to the content of the control unit IO of FIG Control unit IO can be designed to respond to input devices such as switches 407 and 412 of FIGS is responsive to control output devices such as motors 405 and 406. The special requirements that must be met by using the control unit are included With the aid of conventional devices, for example with the aid of the ladder circuit diagram of FIG. 2. Suitable Preset states are entered into the memory in the control unit IO from the input unit 600, if this is connected according to FIG.

Programmer - Fig. 1, la, Ib, 7 to IO

The unit 600 of FIG. 1 is a small portable keyboard input unit. It. four groups of buttons are included. the first group 600c consists of eleven keys with the digits O to 9 and a clear button (CLR button). The second group 60Od contains four keys, labeled as follows: INS (enter), WRT (write), INC (increase) and READ (read).

The third group 60Oe contains four buttons, three of which are used, namely the IN-X, OUT-Y and CR (control relays) buttons.

The fourth group 60Of contains eight keys which are designated as follows: ST (start or save printout), CTR (Counter), TMR (timer), MCR (main control relay), OUT (output), INV (invert or not), OR (or) and AND (and).

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The keypad is a field 60Og of 7-segment neon numeric indicators assigned, as they are usually provided for handheld computers.

A light-emitting diode 600h is provided for each key of the group 60Of. For each of the keys X, Y and CR as well as for the A light-emitting diode 60Oj is provided for position AI, which is not a key.

The input unit 600 of FIG. 1 used for programming enables one to work in one of five different operating modes selected operating mode. An operating mode is activated after depressing one of the four keys in group 600d or the delete key (CLR key) of group 600c is selected. Pressing the delete key in group 6OOc is used to do this, the registers and storage units specified later before carrying out one of the functions of group 60Od to delete.

In the read mode, any command in the memory of FIG. 5 can be read. This can be done by initially using the keyboard group 600c is inputted with the memory address of the command to be read, for example an address of O. to 255. The subsequent depressing of the read button has the consequence that the command appears in the display field 600g and that the corresponding light-emitting diodes in the diode groups 600h and 60Oj light up.

In the increment mode, each address entered into the input unit 600 via its keyboard is not deleted after pressing the INC key by the value One increments and the left part of the display and the OP code command are cleared. For example, if the CLR key in group 600c is depressed, and then the INC key of group 60Od is depressed, then is the address effective in the machine is address no. 1; if

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however, the address shown in the display field 600g is 250 then this is increased to 251.

The memory addresses that are effective at any point in time are shown in the four positions on the right-hand side of the display field 600g reproduced.

In write mode, any new command you want can be written to the Memory to be written. If a command was previously sent to one of the desired store list has been entered in the memory then the write operation results in the new command being written over the previous command.

In the input mode, a new command can be entered at any desired location in the memory, each in the Save the command that is subsequently saved is moved up one memory location after the INS key has been pressed will. Expressed in terms of the ladder circuit diagram of FIG. 2, this means, for example, the following: If the ladder rung with the motor 405 the memory locations 100, 101 and 102 occupied and desired in the memory

beginning with the memory location 100 to insert the rung containing the motor 406, then would be using the input unit 600 carries out the following operations:

Step 1: Depressing the CLR key. Step 2: Entering the address, i.e. pressing the

Keys 100. Step 3: Depressing the ST button (start / save)

and the X button. Step 4: As the switch 407 is the input / output address

No. 9 is occupied, the key for the number 9

of group 600c depressed. Step 5: Depressing the INS (Enter) key of the

Group 60Od.

As a result, the switch 407 is stored at the memory location 100.

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Step 6:

Step 7:

Step 8i

Step 9i

Step 10:

Depressing the INC key. Depression of the AND key of group 60Of. Depression of the X key of group 60Oe. Since switch 412 is the input / output address No. 16 occupied, the number keys 1 and 6 of group 60Oc are depressed. Depress the INS key of group 60Od.

This completes the entry of switch 412 into memory location 101 along with its relationship to switch 407.

Step 11: Depress the INC key of group 600d. Step 12: Depressing the OUT key of group 60Of. Step 13: Depressing the Y key of group 60Oe. Step 14: Since the motor 406 has the input / output address No. 8

occupied, the number key 8 of group 600c

pressed.
Step 15: Depress the INS key of group 6OOd.

This completes the entry of motor 406 into memory location 102 along with its relationship to switches 407 and 407 412.

The elements of the second rung previously occupied the memory addresses 100, 101 and 102. Entering switch 407 into memory shifts all items in memory by one Memory address up. The same applies after entering switch 412 and after entering motor 406. Thus the elements of the rung with the motor 405 now occupy the new memory locations 403, 404 and 405 Pushbuttons shown operate switches which are connected to one another in the arrangement shown in FIGS. la and Ib are. In Fig. La, eight lines m0 to m7 lead to the keyboard. Four lines KBD2, KBD3, KBD6 and KBD7 are off the keyboard. The push button switches are so switched into the resulting matrix that on the four output lines leading out of the keyboard

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coded output signals arise. All switches in the Group 60Oc (with the exception of the CLR switch), in the group 60Oe and group 60Of are in the x-y matrix of Fig. La as indicated by the labels inserted there. Depressing the zero switch of the Key group 600c of FIG. 1 establishes a connection between the line mO and the line KBD2 of FIG. It is to recognize that the switches MCR and INV have the same function, that is, when they close, each establish a connection between the input line m4 and the output line KBD7.

In Fig. 7, the input unit 600 includes lines MO to m7, which lead to the keyboard in the manner indicated in Fig. la. Lines KBD2 and KBD3 of Figure 6 and lines KBD6 and KBD7 of Fig. 9 are led out of the keyboard.

The circuit shown in Figures 7-10 includes two main loops of data that respond to commands sent via can be entered using the keyboard. The following is a general description of the two main data loops before the further application of the keyboard arrangement of Fig. 1, la and Ib will be discussed.

The first data loop emanates from the sequence control unit 10 of FIGS. 3 and 4 and leads via a Schmitt trigger 601 of Fig. 9; it contains in the Flg. 9 and 10 shown shift registers 602 to 606. With the shift registers 604 to 606 binary up / down counters 607 to 609 work together.

The output of the first data loop leads via an inverter 610 to the line 174, which feeds back to the output control unit 10. Signals or data information that are to be transmitted from the input unit 600 to the sequence control unit 10, must pass through shift registers 604 through 606 and then line 174.

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The second data loop is a binary coded decimal loop (BCD loop). It is suitable for 32 bits Numeric data loop. A first group of 16 bits is stored in shift registers 612 and 613 of FIG. The second group of 16 bits is stored in shift registers 614 through 617 of FIG. The bow, which the data traverses contains that connected to the A and B (NAND) inputs of shift register 612 Input line 618. The data bits are sequentially through the shift registers 612 to 617 are clocked, and they then reach the NAND circuit 620 via the output line 619 and NAND circuit 621 back on line 618.

numerical input via the keyboard in the input unit 600 Data is entered into the loop through units 612-621 via a shift register 622. Four Lines 623 lead to shift register 622. The signal states on line 623 are determined by counters 624 and 625 controlled by a slow clock oscillator 626 (LSC oscillator). The clock oscillator 626 is running with respect to the clock oscillator 50 of the sequence control unit IO free. A second oscillator is provided along with the clock oscillator 626. This second oscillator is a with high speed clock oscillator 626a (HSC oscillator). These oscillators operate at a frequency of 180 kHz or 1.8 MHz.

The LSC oscillator output line 627 leads to the clock input of the counter 624. The output QD of the counter 624 is connected to the clock input of the counter 625 via a line 628. Counters 624 and 625 operate with decoders 630 and 6 31 together so that the outputs of decoder 630 scan the switches on the keyboard. The ones on the lines 6 33 output status signals from the decoder 6 31 scan the display panel 600g and the keyboard outputs, i.e. the output lines W2, W3, W6 and W7. The lines designated in FIG. La with m0 to m7 correspond

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lines 632 of FIG. 7.

The line KBD2 from the keyboard leads to a NOR circuit 6 34, the second input of which is connected to the line W2 of the line group 633. In the same way, the Keyboard line KBD3 to a NOR circuit 635, the second input line of which is line W3. The line KBD6 leads to a NOR circuit 636, the second input line of which is line W6. The line KBD7 leads to a NOR circuit 6 37, the second input line of which is line W7. the NOR circuits 6 34 and 6 35 provide the input signals of a NOR circuit 638. The NOR circuits 6 36 and 637 provide the input signals for a NOR circuit 6 39. The output the NOR circuit 6 38 is routed via a monopulse circuit 6, which generates a digit clock pulse on the output line 6 41, which is fed to the clock input of the register 622 so that the code group is sent to the register in this register Lines 623 representing the numeric key depressed on the keyboard is loaded. The one from the counter Pulses supplied via decoder 630 from clock oscillator 626 form a keyboard scan sequence. First the signal on the line MO changes to the low signal value, whereupon the signals on the lines Ml ... M7 follow, and then the signal on the line MO goes back to the low signal value, the Cycle repeated. The switching through of the code group on lines 623 into register 622 is achieved by depressing controlled by a key on the keyboard. The special code group on lines 623 is the one that is present at the point in time at which a special pulse occurs in response to the depression of a given key. The keyboard operation described so far is in essentially the same as the computers sold by Texas Istruments Incorporated of Dallas, Texas under the Designation pocket calculator TI25OO manufactured and sold will.

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Pressing one of the keys O to 9 in the group 6OOc thus has the consequence that a binary code group representing the selected number 0 to 9 is entered in register 622 is loaded.

The selected number in register 622 can then enter the BCD loop and finally transferred to registers 604 to 606. Those entered in registers 604 through 606 Data is the input / output address of a given, except for a few cases discussed below Connection element which is attached along the cable 399. It should be remembered that in the one described here Embodiment 256 input addresses and 256 output addresses along the cable 39 9 are present. In the basic unit 400, the first eight ports 40Oa are input ports and the second eight ports 400b are output ports. As described above, the input / output address indicates the location of such a connection unit, as used to connect to motor 406, switch 4O7, switch 412, and so on.

The input unit 600, which is used for programming, is also used to encrypt certain OP code groups that are transmitted by Press the switch in the key group 6OOf. The input unit 600 also enables identification desired input / output address additions by pressing one of the keys in group 60Oe.

The circuit causes the OP code groups to be stored in register 602 and the I / O address extensions to be stored in register 603. The circuit arrangements assigned to registers 602 and 603 enable input a desired OP code group or multiple OP code groups as well as the removal of one or all OP code groups, that have been entered so that an operator can flexibly represent a conductor circuit Enter a data record or change a data record previously loaded into the system. In particular, the actuation causes

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a key energizing either line KBD6 or line KBD7 decodes the data on the lines

650 for loading into registers 602 and 603. The logic circuits indicated within the dashed line 651 are used to decode the data on lines 650 in a binary form for storage in registers 602 and 603, The code group stored in these registers represents those indicated in FIGS. 1, 1 a and 1 b and the lines OP code groups assigned to KBD6 and KBD7.

The ones at the outputs of the logic circuits of the unit

651 appearing status signals are given in Table III appended at the end of the description.

The initial state signals given in Table III are generated as follows: The line Wl of the line group 6 33 is at an input of the NAND circuit 651a and connected to one input of the AND circuit 651b. The line W6 of the line group 633 is connected to an input of the AND circuit 651c and connected to one input of AND circuit 65Ie. The lines of the line group 623 for the three least significant bits are then connected to circuit unit 651. In particular, the output is QA of the counter 625 via an inverter 651h to the second input of the NAND circuit 651a and to the second input of the AND circuit 651c connected. The output QD of the counter 624 is connected to the second input of the AND circuit 65Id and to one input of the AND circuit 651f. Of the The output of the NAND circuit 651a is at a second input the AND circuit 651d and connected via an inverter 651j to inputs of the AND circuits 651f and 651g.

The output QC of the counter 624 is connected to the second input of the AND circuit 651e and to the second input of the AND circuit 651g.

The outputs of the AND circuits 651b to 651g each have an input from antivalence circuits 65Im to 651s tied together. The outputs QA to QD of the shift register 602

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feed the second inputs of the antivalence circuits 651m to 65Iq. The outputs OA and QB of the shift register 603 feed the second inputs of the antivalence circuits 60Or and 60Os.

The data stored in shift register 602 is the OP code group (Operation code group). Sixteen OP code groups are used in this example. These OP code groups are given in Table IV at the end of the description.

The data stored in shift register 603 is the input / output address extension. There are three address additions here used, which are given in Table V also attached at the end of the description.

All OP code groups specified in Table IV can be activated by pressing keys in key group 6OOf from Fig. 1 can be selected. As can be seen, some of the OP code groups include entries by pressing down two of the keys in group 60Of, and some include entries by depressing three of the keys.

From an examination of the circuit comprising the antivallence circuits 651m to 651q it can be seen that each of the The OP code group appearing at the output of the circuit unit 651 is input to the register 602 when this register is deleted. However, if the same OP code key is pressed a second time, then the return via the Channel 602a results in the previously entered into register 602 OP code groups are deleted. The circuit thus enables a selected entry into register 602 Bit for bit, as well as a deletion of this register bit for bit without affecting the rest of the operation of the input unit 600 is changed somehow. Assuming Fin. 1 is for example, assume that an operator tries to enter switch 412 and accidentally im 8step 7 of that described above in the previous example

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Sequence of pressing the OR key and not the AND key, If the operator then recognizes the error and wants it to be corrected, then this correction can simply be carried out pressing the OR key again following the pressing of the AND key. The sequence of operations in this case becomes the code group in register 602 change from 1010 to 1000. Thus, the selective entry and removal of a single bit for changing the code group is achieved. The use of the antivallence circuits 651m to 651q enable this special sequence of operations, i.e. the alternating entry and deletion of a given code group in register 602 after repeated entries of the same input commands.

The same applies to the three of the OND statements 651f and 651g of the circuit unit 651 leading lines. she cause the antivallence circuits 65lr and 651s Control of the light emitting diode display devices 600j. At the same time, lines 603a are for the selected controller of the data in register 603 is fed back to anti-valuation circuits 651t and 651s.

The output signals of the shift register 602 are in addition to being fed back to the anti-valence circuits 651m up to 65Iq are also used to control the light-emitting diode display device 600h. From the circuit shown it can be seen that when a given key is pressed in group 60Of, the corresponding light-emitting diode in the display device 600h lights up. The light-emitting diodes in the display device 60Oh from FIG. 9 have the same labels as the keys in the group 60Of from FIG 1. In the same way, the light-emitting diodes labeled X, Y and CR of the display device 60Oj of 10 controlled by the outputs QA and QB of the shift register 603.

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The logic circuit 652 functions in the same way as the logic circuit 640 for a controlled loading of the registers 602 and 603.

It can be seen that the digit clock line is one of the output lines of logic circuit 640. This indicates that a digit code group has been stored in register 622 and is to be entered into the data loop clocked by registers 612 through 617. This process will by applying the digit clock signal to the charging terminal ■ of a status counter 653 and via an AND circuit 654 triggered at the clock input of the status counter 653. Of the Counter 653 is pre-wired so that it is forcibly set to count five. The output lines QA to QD of counter 653 are connected to terminals A, B, C and STRB of a data selector 655 and to input lines of a decoder 656. Since the output of the counter 65 is preset to the value five, the data selector 655 selects the signal on the line 657 which originates from a NOR circuit 658 via an inverter 659.

A 32-bit word circulates in the second data loop with the shift registers 612 to 617. It is constantly shifted by sampling clock pulses SCAN. Are sampling clock pulses are fed to the clock inputs of the shift registers 612 and 613, and they are applied to the clock inputs of the shift registers 614 to 617 via a NOR circuit 660.

If a 4-bit word is stored in shift register 622, then that word must be placed in the appropriate location in the Circulating 32-bit words are already inserted in the shift registers 612 to 617. The operation of the bit counter 653 and the data selector 655 together with the decoder 656 causes a delay until the correct time for the insertion is reached. This is achieved by a delay interval during state 5 of the data selector 655. After the occurrence of state 6 of the data selector 655, the NAND circuit 661 is enabled, so that

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the output line OD des leading to the NAND circuit 662 Shift register 622 causes the word stored in this shift register 622 to be entered into the input of storage register 612. Data on line 619 pass through then shift register 622 and drag the word entered into the data loop from register 622. Thus, the sixteen bit register 622 is inserted into the second data loop. During state 6 off a NOR circuit 663 is enabled in the decoder 656. As a result, the MOW4 signal is present. this generates a state of charge on line 665 via a NOR circuit 664, which is binary-coded to the charge inputs of Up / down decimal counters 666 to 669 is kept. Counters 666 to 669 are connected to shift registers 617 to 614, respectively. Line 665 also leads to the Clear inputs of the binary counters 607 to 609 via an inverter 655a. . ,

Thus, the 16-bit data word is in shift register 666 "Has been loaded to 669, and it's supposed to be in one in the counters 609 to 607 generated binary form can be implemented. At state 7 of decoder 656, there is a via a NAND circuit fast clock signal HSC applied together with state 7 from decoder 656 releases an AND circuit 671 which is operated in an OR operation, so that pulses of the fast clock signal HSC then appear on clock line 672. The clock line 672 is connected to the down counting input of the counter 666 and to the up counting input of the Counter 609 connected. The counters 666 to 669 then count down to the count 0. During the same time counters 609 to 607 count up. At the point in time at which the counter 669 reaches the counter reading 0, appears a borrow signal on line 673 which is applied to NOR circuit 674, where it effectively goes to state 7 is combined in an AND operation, so that the Line 675 to each of the load inputs of registers 604 through

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a charging pulse is applied. At the time the borrow pulse occurs, the contents of the counters 607 to 609 detected directly in the storage registers 604 to 606, so that they can be read out over the line in this way 611 are available for the output control unit.

During operation, the sequence control unit shown in FIGS. 3 to 6 repeats the waiting, series input / output and execution modes after each billet value of the AC power supply.

When the input unit 600 is connected to the system and is to be used, then the sequence control unit works usually continuously. However, if the input unit of Figs. 7-10 is put into the reading mode, then the operator specified memory address is entered into counters 666-669. The counters then count down to the counter reading zero. After the count has reached zero, the channels are switched off by the NAND circuit

601 and in particular the enable terminals of registers 602, 603, 604, 605 and 606 are energized so that the in memory words stored in the memory locations with the address initially specified in counters 666 to 669 are output and stored in shift registers 602-606. The light-emitting diode display fields are also immediately visible 600h and 60Oj energized so that the contents of the registers

602 and 603 are displayed. The contents of registers up to 606 are the input / output addresses that are in main memory is stored in the location specified by the user. The input / output address, which is thus in the registers 604 to 606 is then loaded into counters 6O7 to 609. The counters 607 to 609 then count up to Count zero down when counters 666 through 669 are counting up. When the counters 607 to 609 show the count When it reaches zero, counters 666-669 stop counting. The output signals from the counters are then sent to the Shift registers 614 to 617 applied. Their initial values

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are shown to em. In particular, the input / output address comprises -16 bits of the 32 bits circulating in the BCD data loop. Each group of four of the 16 bits is held in a hold circuit 690, the output signals of which are sent to a decoder 691 are fed. The decoder 691 is connected to selectively energize the segment drivers. One of these segment drivers is represented by circuit 692. The 16 Bits are used in this way to light up the four digits on the left-hand side of the display 60Og allow. The four digits on the right are decoded so that the four digits of the memory address on the right are displayed.

In the input mode, an operator inputs the desired data as described above. The OP code group is stored in register 602. The supplementary data are stored in shift register 603. The input / output address is entered into the BCD data loop. The data will be then transferred to shift registers 604-606. in the Execution mode starts the transfer of the data from the memory when the selected address is reached Register 602, if the data starts from register 606, to flow into memory. The data in the memory is then passed through registers 602 to 606 in a serial sequence until all memory addresses have been read and written back into memory offset by one memory address.

The input of numerical data, the input of the OP code groups and the input of the input / output address extensions has now been described. Operations will now be described which include entering the five programming mode commands, clear (CLEAR} _# read (READ) * write (WRITE), enter (INSERT), and increment (INCREfEHT). The clear key CLR of FIG 9. State the clearing line CLEAR PB of Fig. 9 with cash register. This line is connected to an AND circuit 900, whose output signal is the clearing signal CLEAR. The output is also with

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an AND circuit 901 and connected to the clear inputs of the registers 612 and 613. The output of the AND circuit 601 is connected to the clear inputs of registers 602 to 606 and to the clear inputs of registers 614 to 617.

When the READ button is depressed, line 902 is connected to ground. Line 902 leads to one NAND circuit 903, the output of which with a multivibrator

904, which is used to prevent multiple entries of an intended single entry. Depressing a pushbutton can in particular lead to its switch being closed several times. The circuit arrangement with the flip-flop 904 is a debounce circuit, which has a NOR circuit 905 as output. Line 906 is used to delay the signal so that it does not pass through NOR circuit 905 until the multivibrator 904 cycle is complete. The output of the NOR circuit

905 is then fed to an input of a NAND circuit 907, whose output is connected to input 0 of the multiplexer 655. The second input of the NAND circuit 907 is from a AND circuit 908, the inputs of which are supplied with the signal on the MIWO line of FIG. 7 and the OEN signal.

The input key INS and the write key WRT are also connected to the NAND circuit 903 and thus lead over the NAND circuit 907 to input 0 of the multiplexer 655. The write key WRT is in addition to the connection with the NAND circuit 903 also to a NAND circuit 909 and on the clear input of a D flip-flop 910 is connected via a line 911. The write key WRT is connected to the NAND circuit 903 and the NAND circuit 909.

Three lines RUN »PPGC and CPU3 are connected to the input unit 600 connected by the sequence control unit according to FIGS. 3 to 6. The RUN line is connected to the clock input of the D flip-flop 910 and to a NAND circuit 914 via an inverter 913 tied together. The output Q of the flip-flop 9IO is via a Inverter 915 with the clock input of a B flip-flop 916 in

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Link. The output of the NAND circuit 909 is connected to the Clear input of flip-flop 916 and connected to an input of a NAND circuit 917. The output of the NAND circuit

917 is connected to an external charging line 918 leading to the sequence control unit. It's also about NAND circuits 919 and 920.

The PPGC line from the AbIaufsteuerwerk 10 is via a Inverter 921 is connected to one input of NAND circuit 920. The line CPÜ3 is, as described above, connected via line 232 to input 3 of multiplexer 655. It is also connected to a NAND circuit 922 and a NOR circuit 923 connected. The output Q of the flip-flop 916 is connected to the second input of the NAND circuit 917. The Q output of flip-flop 910 is with the third Input of the NAND circuit 917 connected.

The output signal of the NAND circuit 917 is a key signal in the transmission between the sequence control unit 10 and the input unit 600. In particular, the signal monitor controls on the line 918 whether the AbI on the control unit 10 data from the input unit 600, which may appear on line 174, receives or not. The signal remains in read mode on line 918 is always at a high signal level.

In write mode, the signal on line 918 is only active during of the time interval has a low value, in the course of which a word of 16 bits is read from registers 602 to 606 via line 174 to sequence control unit 10.

In the input mode, a signal with a is on line 918 high value until the counters 666 to 669 reach a count after a start signal that corresponds to that address in the Corresponds to the memory at which a new command is to be entered. At this point the signal goes on the line

918 goes low and the data from registers 602 through 607 is passed on line 174 to sequence controller 10 until the end of the cycle is reached, i.e.

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until all remaining commands are read from memory and over registers 602 and 606 have been returned to memory.

When the write key WRT is pressed, the clear line of the flip-flop 910 has a low signal value and the clear line of the flip-flop 916 has a high signal value. Every time the sequential control unit goes into execution mode begins, the clock input of the flip-flop 910 is operated so that the signal at the output Q has the same value as the Signal at input D is clocked, i.e. to the low Signal value passes over. Thus, the output of flip-flop 910 remains on when the WRT key is depressed a low signal level until the signal at output 2Y3 of demultiplexer 656 goes low. This resets the flip-flop 910, which means that the signal at its output Q assumes a high value. When the preset pulse is terminated, the signal decreases a low value again at output Q. At this point in time, the flip-flop 916 is clocked via the inverter 915 so that a signal with the value "Zero" appears. The signal at the output of the NAND circuit 917 goes low only when all of its input signals are high. Thus, the output of the NAND circuit 917 in the write mode only during the time interval a low value, in the course of which the preset input signal of the flip-flop 910, i.e. the signal at output 2Y3 of demultiplexer 656 is low.

The circuit with the flip-flops 910 and 916, the NAND circuit 909 and the demultiplexer 656 works in the input mode so that the signal on the line 918 in the time interval after the transition of the signal at the output 2Y3 of the Demultiplexer 656 to a low value up to

Maintained low at the end of the execution cycle will. The line 918 is via a NOR switch 9 30 and

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a NOR circuit 931 with the clear input of the ZShIers 653 in connection. The second input of the NOR-ScSi al device 930 is connected to the output 2Y3 of the demultiplexer 656. The second input of the NOR circuit 931 is supplied by a NAND circuit 932. An input of the NAND circuit 932 is connected to the output, IY3 of the demultiplexer 656. The other input is connected to output IYO of the demultiplexer 656. The circuit containing the NAND circuit 931 resets the counter 653 in the input mode at the end of the status signal 2Y3 and in the read or write mode at the end of the status signal IYO. It resets the counter 653 depending on the status signal 1Y3 at the l & xitöto of the numerical input mode.

When the INC increase key is pressed, the input becomes a Schmitt trigger 940 associated with hate «· This solves the process of incrementing everyone in the BCD data loop the registers 612 to 61? circulating address off * The output of the Schmitt trigger 940 is connected to a NAND circuit 941 and a second NAND circuit 942 and connected to the clear inputs of the D flip-flops 943 and 944. The exit the NAND circuit 941 is connected to the clock input of the flip flop

943 connected. The output Q of the flip-flop 943 protrudes a NAND-S chal device 945 with the clock input of the flip-flop

944 in connection. The output of the NAND circuit 941 is connected to the input of an AND circuit 948 via an inverter 946 and a NAND circuit 947. The output Q of the flip-flop 943 is connected to one input of the ODEP circuit 949 and to the second input of the NAND circuit 947. The output Q of the flip-flop 944 is connected to the second input of the NOR circuit 949. The output Q is connected to the second input of the NAND circuit 942. The output of the NOR circuit 949 is connected to an "input of a NOR circuit 950, the voä at the second input of a NAND circuit is supplied 951" which is driven through an inverter 952 from the output of the demultiplexer 2yo 656th The second input of the NAND circuits 945 and 951 is connected to the

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Output line for the timing signal MOWO of FIG. 7 tied together.

It should be remembered that in the operating state in the over BCD data loop carrying registers 612 through 617 wraps around a given address. If desired, this To increase the address by the value one, then the INC key is pressed. This will give the clear signal terminated at flip-flops 943 and 944. The zero enable signal is switched off via the NAND circuit 942, so that it is no longer effective at the AND circuit 9O8. The NAND circuit 941 is also enabled. The NAND circuit 941 is supplied through the NOR circuit 955, the the status signal 2YO of the demultiplexer 656 and the status signal MOW4 of FIG. 7 via the inverter 956 are supplied will.

When the operation involving multiplexer 655, counter 653 and demultiplexer 656 is in the NuIl state and the M0W4 state is generated, then the output of NAND circuit 9 41 goes low and then high depending on and corresponding to the state signal MZOW4 at _j This signal clocks the flip-flop 9 43, with the result that the signal at output Q assumes a high value and the signal at output Q assumes a low value. The NAND circuit 945 is enabled and the NAND circuit 9 47 is disabled. The output signal of the NAND circuit 945 then clocks the flip-flop 944 when the state signal MOWO of FIG. 7 is generated. At the first output pulse of the NAND circuit 941, the output signal of the NAND circuit 947 is switched to the low value and applied to the up counting input of the counter 666 via the AND circuit, so that at this point in time the address stored in the counting registers 666 to 669 was, is increased. At the same time, the signal through the AND circuit 901 becomes clear

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of registers 614 to 617 are created.

Before the increment key IUC was depressed, the output of the NAND circuit 942 was enabled so that the counter arrangement could run through its cycle via the AND circuit 908. The XNC increase key is then pressed, and the output signal of the NAND circuit 942- is switched off, so that the counter arrangement can no longer run until the increment process has ended. When the signal MOWO is applied to the flip-flop 944, the output of the NAND circuit 942 is enabled again, so that the counter 653 can continue with its workflow.

Time control - Flg. lla to lic

In Fig. 11a certain timing functions used in the arrangement described above are shown. The in Fig. Lla The functions shown are provided with the same numerical designations as are given in FIGS. 2 to 6.

It should be remembered that the sequence control unit 10 described above goes through three operating states, namely (a) a waiting operation, (b) a series I / O operation, and (c) an execution operation. In Fig. Lla there is the curve 800 the synchronization pulse supplied to the line He of FIG. The sync pulse curve 800 1st characterized by a jump 800a at a peak value of the alternating voltage.

Simultaneously with the jump 800a, the series input / output operation of the control unit 10 is triggered Cycle enable curve 801 is generated at the output of the NAND circuit Ha; it appears on line 81 of FIG. 3.

The signal K2 is one of the output signals of the counter 39; this output signal is a pulse train with a Repetition rate of 1 MHz. The oscillator 50 of FIG. 4 operates in the embodiment described here with a

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Frequency of 8 MHz. The output signal KO of the counter 39 has a frequency of 4 MHz, and the output signal K1 has a frequency of 2 MHz, but the outputs marked Ko and K1 in the drawings are used for Operation of the arrangement is not used, but they are only used in the counter 39. So there is the curve 802 a main control pulse train K2 with a repetition frequency of 1 MHz.

The curve 803 shows the KQD signal at the last output of the Counter 39. It has half the repetition frequency of signal K2 or the repetition frequency of 0.5 MHz during the serial input / output operation of the sequence control unit. After that, it only has output pulses for every sixteenth pulse of the K2 signal 803a, 803b, etc. The signal indicated by curve 803 thus has a repetition frequency of 0.5 MHz during the input / output operation and a repetition frequency value corresponding to the sixteenth part of the repetition frequency of 0.5 MHz during the first part of the execution mode, followed by the main memory write portion of the Execute operation again to the repetition rate of 0.5 MHz returns.

In Fig. 11a, the serial I / O operation begins when the curve 801 becomes high. The serial input / output mode ends with the end of time interval 804.

Execution operation begins at the end of time interval 804 and extends to the end of the time interval 805

The curve 806 indicates the image register write pulse train which is applied to the input R / W of the image register 20 of FIG will.

The curve 807 shows the switching output signal at the output of the NAND circuit 109 of FIG. 4. The data registers 13 to 15 thus count during the serial input / output operation.

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continuously. During the time it took that bend 806 is effective, the states of the 256 input connections on cable 399 are entered in the image register 2O in the order O, 1, 2 ... 254, 255 read «At the end of the serial input section of the I / O operation read from the image register 2O 512 identifier states. They are with the higher clock rate of the through the Signal K2 indicated curve 802 is read out. You will be in in the order 0, 1, 2, ... 510, 53.1.

Then the signal state on line 108 is reversed Fig. 3 um, so that the order in which the in the image register 20 stored output data can be read, reversed. During the last part of the series I / O operation the 256 output connections on cable 399 The signal states to be applied are read out in the reverse order. That means that the state of the furthest remote output connector on cable 399 is read out first. These states are with the high clock frequency of the signal K2 indicated by curve 802 in the order 255, 254 ... 1, 0 read out.

At this point, it is the end of the I / O operation reached, and the arrangement then works in execution mode. The first section of execution operation, viz the time interval 810 is used to read commands from the Memory used in the data registers 12 to 15 with the main clock frequency of the signal K2 of the curve 802. At the same time, a repetition frequency of the signal K2 having corresponding pulse train PPGC generated by the curve 811 is indicated and which is the clock pulse sequence switched by the input unit. The input unit of Flg. 1 1st thus the only element in the arrangement that is controlled by the Makes use of curve 811.

During time interval 810, a 16-digit memory word is transferred from main memory to the data register had read.

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During the time interval 812, the command is executed by the sequence control unit IO. The curve 813 gives the signal AIQ (MCR + JMP) which appears at connection Y3 of the processor fixed value memory 61.

The curve 814 specifies the signal OUT + OUT C, which appears at the connection Y2 of the processor fixed value memory 61. During the During time interval 815 a second word is read from memory and during time interval 816 the second is read Word executed. Thus, words O and 1 are read from memory and executed. Usually it would Sequence control unit with reading and executing all commands continue in memory.

In the example given in FIG. 11, an interruption in the memory is shown rather from the sequence. After running the Word 2 a jump sequence 820 is generated, which has the consequence that the data registers 12 to 15 from the external memory, i.e. loaded from the memory in the input unit 600. Jump history 820 appears on line 144 of FIG. If present, the next word read into data registers 12-15 is derived from the input unit and read during time interval 821. At the end of the time interval 821, the signal indicated by the curve 822 becomes RITE FF switched to a low signal value. This prevents the signal PPGC, indicated by curve 811 continues to be effective at the input unit 600, and it is caused that the run fs expensive plant then writes the contents of the data registers 12 to 15 at the memory location of the word 3 in the memory, i.e. at the same memory location that was used during of the time interval 821 was read from the memory. Thus, the memory write time interval becomes 823 for this purpose used. At the end of time interval 823, the signal indicated by curve 822 goes high so that the application of the pulse train PPGC of the curve 811 to the input unit 600 is triggered and with the reading of the word 4 from the memory is continued in the time interval 824.

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The above operations will then continue until the last of the instruction words has been read from memory and executed as desired. At this point the signal indicated by curve 825 is sampling ended generated. This signal appears at the output of the NAND circuit 11 of Fig. 3. The signal sampling ^ terminated of curve 825 has the consequence that the cycle enable signal curve 801 assumes a low value and that the process controller 10, beginning at the end of the time interval 805, waits for the next peak value of the supply voltage so that the same cycle is repeated « The end-of-cycle signal of curve 826 causes operations to be halted. The process control unit IO remains until The next peak occurs in this state.

It can be seen that the signal stops the scanning Curve 825 is fed to the clear input of the flip-flop 93 and that the end of cycle signal of the curve 826 is fed to the preset input of the flip-flop 93, so that the from the Curve 822a indicated negative pulse is generated. The pulse 822a ensures that the last word from the Memory will be read and fully executed before the execution operation time interval 805 ends. In each of the Time intervals 821, 823 and 824 command words are read from the memory or into the memory, which means that a control pulse group 830 is generated at the beginning of each of these intervals. This impulse group contains:

a negative KQD pulse of one microsecond duration, which upon its return to the true signal value marks the beginning of a memory cycle as in time interval 821;

a clock pulse GATED CK, i.e. a positive one Level with a duration of 1.5 microseconds, that is a duration one microsecond longer than that KQD pulse;

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an AID pulse with either AID = 1 or AID = 0. The active indicator AID is formed by the flip-flop 86 of FIG. The AID signal is the signal applied to the D input of flip-flop 86.

When the signal at the Q output of the active indicator flip-flop 86 as a result of a previous memory cycle has a has true signal value, then the signal fed to input D has the form AID = 1, which is expressed by a negative pulse which assumes a true signal value around half a microsecond before the end of the pulse KQD. If that The signal at the output Q of the active indicator flip-flop 86 is supposed to have an incorrect signal value, then that has the input D signal supplied to flip-flop 86 is in the form AID = 0, and it is a pulse of 2 microsecond duration which is around half a microsecond after the dashed line 831 assumes a true signal value. The dashed line 831 coincides with the trailing edge of a negative pulse AICK and PDS CK, i.e. the one fed to the flip-flop 86 Clock pulses and the clock pulses supplied to the stack 80 together.

The active indicator flip-flop 86 changes its state at the dashed line 831. Active indicator flip-flop 86 includes Instruction execution results and serves as a one-bit wide accumulator. Load all memory dumps new data into the active indicator flip-flop. The stack causes data to be shifted down to two OP code groups, an upward shift on four OP code groups and no shift on ten OP code groups.

In particular, the basement has that in the at the end of the Description of the appended table VI specified behavior in response to the 16 OP code groups involved.

In Table VI the OP code groups are given as they appear on lines Bl5 to B12 emanating from register 12 of FIG. For the OP code group ST, the lines

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B15 to B12 assign the 4-bit word 0001 to the processor read-only memory 61.

Time control - Fig. Lld

Curves 800, 841 and 842 are shown in FIG. The cycle enable signal is the signal appearing on the line 81 at the output of the NAND circuit Ha. The peak value of the half cycle of the AC supply voltage occurs at point 80Oa of curve 800. The output signal Kl4 of the counter 38 contains a positive pulse, once per Half cycle of the AC supply voltage occurs. The output signal Kl4 indicated by curve 841 is above the inverter 96 is fed to the clock input of the timer counter 35. The timer enable signal indicated by curve 842 thus has one for every 12 pulses of curve 841 Output pulse on. This means that the pulses of the timer enable signal indicated by curve 842 occur at time intervals of 0.1 seconds. The output of the timer counter 35 emits the output signal CRY. This output signal is fed to input D of the line 125 Processor read-only memory 61 supplied, and it is used for timing the application of the sequence control unit 10. Such a timer is shown in FIG. 1 as a timer 417 specified. The timing commands are loaded into main memory and can be read from memory so that they take effect to control the operation of the sequence control unit. The controls for such timing operations are as shown in Tables I and II for the processor read-only memories 61 and 63 contain specified programming.

Timing - Fig. He

Fig.He shows the relationship between (1) the curve 803 of the Signals KQD, (2) the signal AIQ (MCR + JMP) indicated by curve 813 at the output of the processor read-only memory 61, (3) the count output signal indicated by curve 843 of the flip-flop 213 of FIG. 6 and (4) that indicated by the Curve 814 indicated signal OUT + OUT C.

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The signal KQD indicated by curve 803 represents negative pulses with a duration of one microsecond, which occur every seventeenth microsecond. The flip-flops 211, 212, 213 and 214 generate depending on the signals BO to B7 and from signal AIQ (MCR + JMP) the count output signal indicated by curve 843. Three output pulses of the signal OUT + OUT C are generated within the time period in which the count output signal of curve 843 is positive is. The curve 843 can have 256 OUT + OUT C pulses extend. The length of the count output signal of the curve 84 depends on the value of the input signals B0 to B7 of FIG Moment of occurrence of the AIQ (MCR + JMP) pulse.

Input / output units - Figs. 13 and 14

As shown in Fig. 1, the sequence control unit is IO connected to input / output ports via cable 399, which are attached to the base units 400 and 401. The output unit 409 is attached to the base unit 400. The input unit 411 is attached to the base unit 401. The base units 400 and 401 are over the cable 399a connected. The base unit 401 is via the cable 399b connected to further basic units, so that, as described above, a total of 256 output units like the Unit 409 can be used together with a total of 256 input units like input unit 411.

13 and 14 show how the basic units 400 and 401 via the supply cables 39 7 and 39 8 supplied energy is used. In the case of the motor 406, the output unit 409 is used to initiate the application of power from cable 397 via lines 408 to motor 406. The one used to achieve this purpose Interface unit is shown in FIGS. 13 and 14.

The cable 397 contains a conductor which is connected to one terminal of a triac 701. The other connection of the triac 701 is via the line 408a with a terminal of the

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Motoxs 406 in connection. The other terminal of the motor 4Ο6 is connected to the second conductor in cable 397 via conductor 408b. The circuit, which works depending on the sequence control unit IO, causes the triac 701 to be switched on afterwards a given initial state from the sequence control unit 10.

The control arrangement for the triac 701 contains an output logic line 702, which leads via a light-emitting diode 703 in the line 704 to a positive voltage source. If that Signal on line 7Ο2 has an incorrect signal state, triac 701 is switched on. This is done by scanning light from the LED 703 in a photo sensor SCR 705. The photo sensor SCR 705 is connected to an RC filter 706 connected. It is also connected to triac 701 via a full-wave rectifier diode bridge 707. More accurate said line 708 leads to * control electrode of the triac 701, and it leads through a capacitor 709 to the line 408a. The upper connection of the diode bridge 707 protrudes the line 710 with the connection point between the filter capacitor 711 and the filter resistor 712 in connection. The upper connection of the resistor 712 is connected to the upper connection of the triac 701, and it is connected to the power supply cable 397 via the line 713. the Swing limiter circuit 714 is parallel to filter capacitor 711 and to filter resistor 712.

In Fig. 14 the only output circuit is shown, as used to drive or otherwise control the motor 406. Similar circuits are used for Controlling the application of AC power to the other seven output channels 720 is used. Since the control circuits are constructed in the same way as the control circuit described for channel 702, they are not described further here.

According to FIG. 1, the switch 407 is opened or closed depending on the position of the XY coordinate drawing table 404. The switch 407 is connected to the input input via the cable 410

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unit 411 is connected to the base unit 401. The state of switch 407 is used to remove power from the cable 39 8 to be used in the base unit 401 to display the switch status via the cable 399a. 14 shows the input circuits in a basic unit. In this circuit is the energy source is connected to the system via the cable 39 8. The switch 407 is via the line 410a one of the energy conductors in the cable 39 8 connected. The other terminal of switch 407 is across line 410b a voltage divider with resistors 730 and 731 is fed back to the other conductor of the cable 39 8. For education In a filter circuit, a capacitor 732 is connected in parallel with the resistor 731.

Resistors 730 and 731 lower the voltage applied to full wave rectifier diode bridge 733 to about 12V away. The diode bridge is connected to a trigger element 735 via a line 734 and then via a resistor 736 a light emitting diode 737 connected. The second connection of the diode 737 is via a line 738 with the other terminal the diode bridge 733 in connection. The light-emitting diode 737 is switched on when the switch 407 is closed. if the light emitting diode 737 is switched on, the light emitted by it is detected by a phototransistor 739. The phototransistor 739 in the conductive state causes the signal on the output line 740 to be in the wrong state Has. The other line 741 starting from the phototransistor 739 is connected to ground. The one indicated in FIG Circuitry thus serves to control the state of the signal on line 740 so that it is a low signal level when switch 407 is closed.

There are seven more input lines 750 in the circuit of Fig. 14, the same circuits

how to control the circuit described for controlling the signal state on the output line 740.

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It can be seen that the base unit 400 serves as a fastening device for the output unit 409. The base unit 401 serves as a fastening device for the input unit 411.

The circuit shown in Figs. 13 and 14 includes an arrangement in which the logic in a single basic unit both for receiving output units as the Output unit 409 as well as for receiving input units such as the unit 411 on the same base unit is available. In the arrangement of FIG. 13, a multiple plug 399c connects the cable 399 to the base unit 400. The plug 399d terminates the cable 399a in the base unit 400. An identical plug 399e is plugged into the base unit 401 and the plug 394f connects them Cable 399d with the base unit 401.

In Fig. 13, line 702 and associated lines 721 are connected to the eight inputs of two 4-bit parallel input / Parallel output shift registers 760 and 761 connected. Shift registers 760 and 761 are on lines 762 with the outputs of an 8-bit serial input / parallel output shift register 76 3 in connection. The output data line of the control unit 10 is connected via the plug 399c to the line 764, which is connected to the data inputs of the shift register 763 via the inverter 765. the

Q output line 766 is connected to the for η

Plug 399d connected leading data output line. Consequently an output data sequence emanates from control unit 10 during each half cycle of the supply voltage. This output data sequence arrives at the basic unit 400 and passes through the The shift register 763 is controlled by a sequence of clock pulses, a new bit being entered for each clock pulse. The I / O clock signals on line 768 reach the clock input of the shift register 763 via a negating gate circuit 769. The input / output clock line 768 is also connected to an I / O clock port in connector 399d

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connected. It should be remembered that when data is read by the control unit IO during each half cycle of the Supply voltage 256 bits can be read to cable 399. The first bit read is in a register with the register 76 3 is stored in the last of a series of base units attached along the cable to section 399d is. The last of the 256 output bits is stored in the first bit location in register 763.

If the input / output clock signal is blocked, the output data are then stored in the register as in the register 76 3 stored. During the zero crossing of the alternating voltage in the control unit 10, the input / output storage line 770, a signal state to the clock inputs of the Shift registers 760 and 761 applied. This shifts the data in register 76 3 into shift registers 760 and 761, see above that in this way the output signal states on lines 702 and 721 are controlled, whereby depending on the case Lines 408a and lines 720 are energized or de-energized.

The input logic line 740 and associated lines 750 are connected to an 8-bit parallel input / serial output shift register 775 connected. The store I / O state on line 770 changes after each sequence of Input data to the control unit 10 from the input state to the Output status, serial reading is carried out via negator 87 the voltage states on lines 740 and 750 to line 776 and then through inverter 777 to the input data port at connector 399c.

It can be seen that the input data connection is on the plug 399d through inverter 778 and line 779 to the serial input terminal of register 775 is connected. If the arrangement is in the input mode, will be on this way all signal states on lines 740 and

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as well as the signal states on a further 248 similar lines in further basic units, all of which can be handled by the arrangement, via the line 779 through the shift register 775.

The cable leading to connector 399c includes an input data line, an input / output storage line, a I / O clock line, an output data line, a +7.5 V line, a light emitting diode supply line, a Group of logic ground lines and a thermal fault line.

In the embodiment described above, various integrated components are used as described. Logic units are with the conventional symbols specified. Other components used are given in Tables VII to IX attached at the end of the description.

The invention has been described here in connection with a specific exemplary embodiment, but those skilled in the art can readily recognize that within the scope of the invention further modifications are also possible.

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Table I. Programmable read-only memory

ο oo cn cn

Hex. NOP Outputs ^Y 3 ^Y 2 ^Y i Hex. Γίτττ Outputs ^T 3 ^Y 2 ^Y l Addr. JMP ^Y 4 0 1 0 Addr. VJUJ. ^Y 4 1 0 0 0 1 0 1 0 30th 1 1 0 0 1 1 1 1 1 31 1 1 0 1 2 1 1 1 1 32 1 1 0 1 3 1 0 1 0 33 1 1 O 0 4th 1 0 1 0 34 1 1 0 0 5 1 1 1 1 35 1 1 0 1 6th 1 1 1 1 36 1 1 0 1 7th 1 0 1 0 37 1 1 0 0 8th 1 0 1 0 38 1 1 0 0 9 1 1 1 1 39 1 1 0 1 A. 1 1 1 1 3A 1 1 0 1 B. 1 0 1 0 3B 1 1 0 O C. 1 0 1 0 3C 1 1 0 0 D. 1 1 1 1 3D INV 1 1 0 1 E. LOAD 1 1 1 1 3E & 1 1 0 1 F. (ST) 1 1 1 0 3F MCR 1 O 1 0 10 1 1 1 1 40 1 0 1 0 11 1 1 1 0 41 1 1 1 1 12th 1 1 1 1 42 1 1 1 1 13th 1 1 1 0 43 1 0 1 0 14th 1 1 1 1 44 1 0 1 0 15th 1 1 1 0 45 1 1 1 1 16 1 1 1 1 46 1 1 1 1 17th 1 1 1 0 47 1 0 1 0 18th 1 1 1 1 48 1 0 1 0 19th 1 1 1 0 49 1 1 1 1 IA 1 1 1 1 4A 1 1 1 1 IB 1 1 1 0 4B 1 0 1 0 IC 1 1 1 1 4C 1 0 1 0 ID 1 1 1 0 4D 1 1 1 1 IE CTR 1 1 1 1 4E LOAD
(ST) 1 1 1 1 IF 1 1 1 0 4P 1 1 1 1 20th 1 1 1 0 50 1 1 1 0 21 1 1 1 1 51 1 1 1 1 22nd 1 1 1 1 52 1 1 1 0 23 1 1 1 0 53 1 1 1 1 24 1 1 1 0 54 1 1 1 0 25th 1 1 1 1 55 1 1 1 1 26th 0 1
1 1
1 1
0 56 1 1
1 1
1 0
1 27
28 0
1 1 1 0 57
58 1
1 1 1 0 29 1 1 1 1 59 1 1 1 1 2A 1 1 1 1 5A 1 1 1 O 2 B 1 1 1 0 5B 1 1 1 1 2C 1 1 1 0 5C 1 1 1 0 2D 1 1 1 1 5D 1 1 1 1 2E 0 1 1 1 5E 1 1 1 0 2F 0 5F 1

Table I (continued) Programmable read-only memory 61

Hex. TMR Exits ^Y 3 ^Υ 2 ^γ ι Hex. Outputs ^Y 3 1 Y Addr. ^Y 4 1 1 0 Addr. ^Y 4 1 1 0 60 1 1 1 0 90 1 1 1 0 61 1 1 1 1 91 1 1 1 0 62 1 1 1 1 92 1 1 1 0 63 1 1 1 0 93 1 1 1 0 64 1 1 1 0 94 1 1 1 0 65 1 1 1 1 95 1 1 1
1 1 66 1 1
1 1
1 1
0 96 1 1
1 1 1
0 67
68 1
1 1 1 1 Il - 1
1 1 1 0 69 1 1 1 1 99 1 1 1 0 6A 1 1 1 1 9Α 1 1 1 0 6B 1 1 1 0 9Β 1 1 1 0 6C 1 1 1 0 9C 1 1 1 0 6D 1 1 1 1 9D 1 1 1 1 6E OUTC 0 1. 1 1 9Ε 1 1 1 1 6F 0 1 0 1 9F 1 1 1 0 70 1 1 0 1 AO 1 1 1 1 71 1 1 0 0 . Al 1 1 1 1 72 1 1 0 0 A2 1 1 1 1 73 1 1 0 1 A3 1 1 1 0 74 1 1 0 1 A4 1 1 1 1 75 1 1 0 0 A5 1 1 1 1 76 1 1 0 0 A6 1 1 1 1 77 1 1 O 1 ^A7 Often 1 1 1 0 78 1 1 0 1 A8 ^OT 1 1 1 1 79 1 1 0 0 A9 1 1 1 1 7A 1 1 0 0 AA 1 1 1 1 7B 1 1 0 1 AWAY 1 1 1 0 7C 1 1 0 1 AC 1 1 1 1 7D ID 1 1 0 0 AD 1 1 1 1 7E AD 1 1 0 0 AE 1 1 1 1 7F 1 1 1 0 AF 1 1 1 0 80 1 1 1 0 BO 1 1 1 0 81 1 1 1 0 Bl 1 1 1 1 82 1 1 1 1 B2 1 1 1 1 83 1 1 1 0 B3 1 1 1 1 84 1 1 1 0 B4 1 1 1 1 85 1 1 1 0 B5 1 1 1 1 86 1 1 1 1 B6 1 1 1 1 87 1 1 1 0 ir » 1 1 1 0 88 1 1 1 0 B9 1 1 1 0 89 1 1 1 0 BA 1 1 1 1 8A 1 1 1 1 BB 1 1 1 1 8B 1 1 1 0 BC 1 1 1 1 8C 1 1 1 0 BD 1 1 1 1 8D 1 1 1 O BE T 1 1 1 1 8E 1 1 1 1 BF 1 1 1 8F 1 1

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Table I (continued)

Programmable read-only memory 61

Hex. Outputs ^Υ 3 ^Υ 2 ^Υ 1 Hex. Outputs . ^Y 3 ; ^Y 2 ! ^Y l Addr. ^Y 4 1 1 O Addr. ^Y 4 1 1 1 CO 1 1 1 O EO 1 1 1 O Cl 1 1 1 1 El 1 1 1 1 C2 1 1 1 O Ε2 1 1 1 1 C3. 1 1 1 O Ε3 1 1 1 1 C4 ^N 1 1 1 O Ε4 1 1 1 O C5 1 1 1 1 Ε5 1 1 1 1 C6 1 1 1 O Ε6 1 1 1 1 ^C7 ARC 1 1 1 O ^Ε7 cmc 1 1 1 1 C8 " ⁰ ^ 1 1 1 O FR "SC 1 1 1 O C9 1 1 1 1 E9 1 1 1 1 CA 1 1 1 O EA 1 1 1 1 CB 1 1 1 O EB 1 1 1 1 CC 1 1 1 O EC 1 1 1 O CD 1 1 1 1 ED 1 1 1 1 CE 1 1 1 O EE 1 1 1 1 CF 1 1 1 O EF 1 1 1 1 DO 1 1 1 O FO 1 1 1 1 Dl 1 1 1 1 Fl 1 1 1 1 D2 1 1 1 1 F2 1 1 1 1 D3 1 1 1 O F3 1 1 1 O D4 rH 1 1 O F4 r-t 1 1 O D5 1 1 1 O F5 1 1 1 1 D6 1 1
1 1
1 O
O F6 1 1
1 1
1 1
1 ⁰⁷ ATC
• D8 ^ATC 1
1 1 1 O F7
F8 ^0TC 1
1 1 1 1 D9 1 1 1 1 F9 1 1 1 1 THERE 1 1 1 ι-Η FA 1 1 1 1 DB 1 1 1 O FB 1 1 1 O DC 1 1 1 O FC 1 1 1 O DD 1 1 1 O FD 1 1 1 1 DE 1 1 1 O FE 1 1 1 1 DF 1 FF 1

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Table II Programmable Test Value Memory 62

Hex. Outputs Hex. Outputs Addr. V ^Y 3 ^Y 2. ^Y 1- ^Y 4 ^Y 3 ^Y 2 ^Y l

0 10 0 0 20 10 0 0

1 10 10 21 1 O 1 0

2 110 0 22 110 0

3 1110 23 1110

4 10 0 1 24 10 0 1

5 10 11 25 1,011

6 110 1 26 1 10 1

7 1111 27 1111

8 10 0 0 28 1 O 0 O

9 10 1 O 29 10 10 A 110 0 2A 110 0 B 1110 2B: 1110

c looi 2c ■■■■■ '. ■'. ι ο ο ι

D 10 11 2D 10 11

E 110 1 2E 1 1 O 1

.F 1111 2P 1111

ίο looo 3ö. ■ ';' .. looo

11 10 10 31 10.10,

12 110 0 32 110 0

13 1110 33 11 I 0

14 1 Ö 0 1 34 10 0 1

15 10 11 35 10 11

16 110 1 36 Il 0 1

17 11.11 37 1111

18 10 0 0 38 10 0 0

19 10 10 39 10 10 IA 110 0 3A 110 0 IB 1110 3B 1110 IC 10 0 1 3C 10 0 1 ID 10 11 3D 10 11 IE 1 1 O 1 3E 110 1 IP 1111 3P 1111

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Table IJ (continued) Programmable read-only memory 62

Hex.
Addr. Outputs
Y. Y, Y ₀ Y ₁ 0 0 0 Hex.
Addr. 1 Ai
^Y 4 as ge
^Y 3 ing «
^Y 2 a 0 40 0 0 0 0 60 0 0 0 0 41 0 1 0 0 61 0 0 0 0 42 0 1 0 0 62 0 1 0 0 43 0 0 0 1 63 0 1 0 1 44 0 0 1 1 64 0 0 0 1 45 0 1 0 1 65 1 0 1 1 46 0 1 1 1 66 0 1 0 1 47 0 0 0 0 67 0 1 1 0 48 1 0 0 0 68 0 0 0 0 49 1 1 0 0 69 0 0 0 0 4A 1 1 0 0 6A 0 1 0 0 4B 1 0 0 r-t 6B 0 1 0 1 4C 1 0 1 1 6C 1 0 0 1 4D 1 1 0 1 6D 1 0 1 1 4E 1 1 1 1 6E 0 1 O 1 4F 1 0 0 0 6F 1 1 0 50 0 0 0 0 70 0 0 0 0 51 0 1 1 0 71 0 0 0 0 52 0 1 1 0 72 O 1 1 0 53 0 0 0 1 73 0 1 1 1 54 0 0 1 1 74 0 0 0 1 55 0 1 0 1 75 0 0 1 1 56 0 1 1 1 76 0 1 0 1 57 O 0 0 0 77 0 1 1 0 58 1 0 0 0 78 0 0 0 0 59 1 1 1 0 79 0 0 0 0 5A 1 1 1 0 7A 0 1 1 0 5B 1 0 0 1 7B 0 1 1 1 5C 1 0 1 1 7C 1 0 0 1 5D 1 1 0 1 7D 0 0 1 1 5E . 1 1 1 1 7E 1 1 0 1 5P 1 State 7F 0 1 1

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Table II (continued) Programmable Read Only Memory 62

Hex.
Addr. Outputs
^Y 4 ^Y 3 ^Y 2 ^Y l 1 O Hex.
Addr. 2 Outputs
^Y 4 ^Y 3 ^Y 2 ^Y l O 1 O 80 1 O 1 O AO 1 0 1 O 81 1 1 1 O Al 1 1 1 0 82 1 O 1 0 A2 1 1 1 0 83 1 1 1 O A3 1 1 1 0 84 1 0 1 O A4 1 1 1 O 85 1 1 1 O A5 1 0 1 O 86 1 O 1 0 A6 O O 1 O 87 1 1 1 1 A7 O O 1 1 88 1 O 1 1 A8 1 0 1 1 89 1 1 1 1 A9 1 1 1 1 8A 1 0 1 1 AA 1 1 1 1 8B 1 1 1 1 AWAY 1 0 1 1 8C 1 O 1 1 AC 1 0 1 1 8D 1 1 1 1 AD 1 1 1 1 8E 1 O 1 1 AE 1 1 1 1 8F 1 1 1 O AF 1 0 1 0 90 1 0 1 0 BO 1 O 1 O 91 1 O 1 O Bl 1 1 1 O 92 1 O 1 O B2 1 1 1 O 93 1 O 1 O B3 1 1 1 0 94 1 O 1 O B4 O 1 1 O 95 1 0 1 O B5 0 O 1 O 96 1 0 1 O B6 1 0 1 0 97 1 0 1 1 B7 1 O 1 1 98 1 O 1 1 B8 1 0 1 1 99 1 O 1 1 B9 1 1 1 1 9A 1 O 1 1 BA 1 1 1 1 9B 1 0 •1 1 BB 1 0 1 1 9C 1 0 1 1 BC 1 O 1 1 9D 1 0 1 1 BD 1 1 1 1 9E 1 0 1 1 BE 1 1 1 1 9F 1 0 State BF 1

509829/0855

Table II (continued) Programmable Read Only Memory

Hex. Outputs Hex. Outputs

Outputs
YYYY
^Y 4 ^Y 3 ^Υ 2 ^Υ 1 O O 1 Hex.
Addr. 3 1 O 1 1 EO / 0855 1 1 O 1 El 1 1 1 1 E2 1 O O 1 E3 1 O 1 1 E4 1 1 O 1 E5 1 1 1 1 E6 1 O O 1 E7 1 O 1 1 E8 1 1 O 1 E9 1 1 1 1 EA 1 O O 1 EB 1 O 1 1 EC 1 1 O 1 ED 1 1 1 1 EE 1 O O 1 EF 1 O 1 1 FO 1 1 O 1 Fl 1 1 1 1 F2 1 O O 1 F3 1 O 1 1 F4 1 1 O 1 F5 1 1 1 1 F6 1 O O 1 F7 1 O 1 1 F8 1 1 O 1 F9 1 1 1 1 FA 1 O O 1 FB 1 O 1 1 FC 1 1 O 1 FD 1 1 1 1 FE 1 State FF 509829

^Y 4 ^Y 3 ^Y 2 ^Y l 1 O O 1 1 O 1 1 1 1 O 1 1 1 1 1 1 O O 1 1 O 1 1 1 1 O 1 1 1 1 1 1 O 0 1 1 O 1 1 1 1 O 1 1 1 1 1 1 O O 1 1 0 1 1 1 1 O 1 1 1 1 1 1 O O 1 1 O 1 1 1 1 O 1 1 1 1 1 1 O ' O 1 1 O 1 1 1 1 O 1 1 1 1 1 1 O O 1 1 O 1 1 1 1 O 1 1 1 1 1 1 0 O 1 1 O 1 1 1 1 0 1 1 1 1 1

Table III

651b 651c 651d 651e 651f 651g

OP code group

ST (LOAD)

MCR / INVERT

ST INVERT (LOAD)

OUT INVERT

AND ST

AND INVERT

AND ST INVERT

OR INVERT

OR ST INVERT

O O O O 651m 651n 651p O 651q 1 O O O O O O 1 O O O O O O O 1 1 1 O O O O O O O 1 O 1 O O O O O O O O 1 O 1 O O O O 1 O O 1 O O O O 1 1 O 1 O O O 1 O O O 1 O O O 1 O O 1 O O O O 1 1 O 1 O O O Tabel IV 1 O 1 O 1 1 1 1 1 1 1 1 O O O 1 1 O 1 1 O O O 1 1 O Auseanjresional 1 1 O O O 1 1 O 1 1 O O O 1 1 O 1 1

509829/0855

Table V 651 button 651r 1 X O O Y 1 1 CR 1 Table VI Basement PP code group

ST (storage term) (load) ST-INV (storage term, negated)

(Load)

AND-ST (AND storage term) AND-INV-ST (AND, negated,

Storage term)

OR-ST (OR, storage term) OR-INV ST (OR, negated,

Storage term) AND

ANDC (AND comp lernent) OR (OR)

ORC (learn OR comp t) OUT (output) OUTC (output complement) MCR (main control relay)

or negates JMP (jump) or none

Operation TMR (timer) CTR (counter)

Down Shift OOOl Down Shift 0101

Up Shift 1001 Up Shift HOl

Up Shift 1011 Up Shift 1111

No shift lOOO No shift 1100 No shift lOlO No shift 1110 No shift 0Ol 1 No shift Olli No shift 0100

No shift 0000

No shift 0110 No shift 0010

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Table VII

units

Read / write memory 20, 25, 26, 27 and 28 1024-bit read / write Speieher the company MIL of Canada, Ottawa, Canada, Cat. No. 2102

Counters 12-15, 35-39, Texas Instruments counters

and 63

Read-only memories 30 to 33, 61 and 62

Shift register 80

Flip-flops 21, 86, 193, 213, 214

Counters 93, 95, 211, 212, 226, 230 and 237

Demultiplexer 175, 177

Multiplexer 190 Incorporated, Dallas, Texas, Catalog No. SN 74163-N

Programmable processor read-only memory from Harris Semiconductor, Inc., Melbourne, Florida, Catalog No. H. PROM

Texas Instruments Incorporated Shift Registers, Catalog No. SN 74194 N

Texas Instruments Incorporated Flip-Flops, Catalog No. SN 7474 H.

Texas Instruments Incorporated Counters, Catalog No. SN 74193 N

Double demultiplexer from two to four lines from the company Texas Instruments Incorporated, Catalog No. SN 74155 N

One half of a double multiplexer made up of four lines a lead from Texas Instruments Incorporated, catalog no. SN 74153 N

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Table VIII

units

Decoders 630, 631 and Shift register 612 and

Counter 624,

Shift registers 602 to 606, 614 to 617 and

Up / Down counter 607 to

Up / Down Counters 666 to

Hold circuit Decoder

Counter 653 Counter 655 Decoder from three to eight Texas Instruments Incorporated leads, Catalog No. SN 74155N

8-bit shift register from Texas Instruments Incorporated, Catalog no. SN 74164N

Texas Instruments Incorporated Counters, Catalog No. SN 74177N

Texas Instruments Incorporated Shift Registers, Catalog No. SN 74195N

Up / Down binary counter from Texas Instruments Incorporated, Catalog No. SN 74193N

Up / down decoding counter from Texas Instruments Incorporated, Catalog No. SN 74192N

The company's 4-bit hold circuit Texas Instruments Incorporated, Catalog No. SN 7475N

Decoder from BCD representation to 7-segment representation of the Texas Instruments Incorporated, Catalog No. SN 7448N

The company's 4-bit binary counter Texas Instruments Incorporated, Catalog No. SN 74163N

Demultiplexer from eight lines to one line from Texas Instruments Incorporated, Catalog No. SN 74151N

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Table IX

Units shift register 775

Shift register 763 Shift register 760, Coupler 737 to 739

SCR 703 to 705 .8-bit parallel input / serial output shift register of the Texas Instruments Incorporated Company, Catalog No. SN 74165N

8-bit serial input / parallel output shift register of the Texas Instruments Incorporated, Catalog No. SN 74164N

4-bit parallel input / parallel output sluggish register (hold Circuit) from Texas Instruments Incorporated, Catalog No. SN 74195N

Optocoupler from Texas Instruments Incorporated, Type designation TILlIl

Opto-SCR units from Monsanto Semiconductor, Inc., Cupertino, California, type designation MCS 240

509829/0855

Claims (31)

Claims 1. Programmable logic control unit, marked by a storage device for storing multi-bit instructions, a temporary storage device mounted in the control unit for the temporary storage of input / output or partial result data as 1-bit data words and devices installed in the control unit for retrieving and processing this data. 2. Programmable logic control unit with integrated semiconductor circuit units, the memory devices for storing multi-bit instructions and 1-bit data words to which a processor device for processing of the data is selectively coupled in accordance with the commands / identified by (a) a 1-bit word wide stack, for storing partial results of Boolean calculations selectively with the processor device connected is, (b) a reading device for reading the partial results from the stack in the reverse order of theirs Input depending on the completion of calculations of another part of the calculations and (c) a device for combining the result of the other part of the bills with one of the "stack" stores retrieved partial result. 3. Control unit according to claim 2, characterized in that the output of the processor device via an active display flip-flop is connected to the stack and that the input of the processor device is directly connected to the Stack is connected. 509829/0855 4. Control unit according to claim 3, characterized in that a clock device blocks data transmission from the activity indicator flip-flop to the stack or to a picture register. 5. Programmable sequence control unit, characterized by (a) a processor receiving multi-bit opcode groups for processing 1-bit data words, (b) connected to the processor via input lines Data sources with (I) an active indicator memory flip-flop, (II) an image register data store and (III) a cellar, (c) a device for applying a group of opcodes to the processor for the selective detection of Data from less than all lines and for processing the data, (d) a data output line leading to the active indicator memory flip-flop, (e) a device that, depending on the operation code group, the output signal of the processor in the Active indicator memory flip-flop stores and (f) means for selectively transferring the contents of the active indicator memory flip-flop to the image register data store or to the stack memory. 6. Computer with a memory, the capacity of which can be changed without changing the associated computer components is indicated by (a) a group of m memory modules for the respective storage of η memory words, 509829/0855 (B) m receiving devices for receiving the memory modules and for connecting the memory modules to a common serial memory output line / (c) a memory read controller for sequentially addressing words in a given module and for sequentially addressing modules in the group during each storage cycle and (d) means for putting the signal on this output line in a predetermined state when during a section of the Speieher cycle of m χ η Words did not read any data on the output line will. 7. Computer according to claim 6, characterized in that the memory modules are read / write memory modules and that the memory read control device contains an addressable sequence control arrangement for cyclically enabling the m memory modules. 8. Memory arrangement, the capacity of which can be changed without changing associated computer components, marked by (a) several storage units from which data words are to be read out during a sequence of storage cycles, (b) Means for connecting the memory to a common output channel, (c) a control device for reading the storage units in a single serial sequence of all the words stored therein, (d) means for enabling the reading of the units in a sequential manner and 509829/0855 (e) means for placing the output channel in a predetermined state if during the sequence no data is read from one of the memory locations by storage cycles. 9. Arrangement according to claim 8, characterized in that the storage units are multi-word read / write serial / serial units. 10. Arrangement according to claim 8, characterized in that the storage units detachably with the output channel and with the control device via a multiple connection socket are connected. 11. The arrangement according to claim 8, characterized in that no operation code groups can be stored in the memory if a memory word only contains bits with the value "1" contains, and that a lifting resistor connects the output channel with a voltage source, so that the channel on the state "1" is set if none from the memory Data are read. 12. A method for operating a computer memory with a plurality of multi-word memory modules, characterized in that (a) that successively each memory address in each memory module and each memory module for reading all Data in the memory modules are addressed during each sequence of memory cycles and (b) that the memory output is set to the state ^{N tt} if no data is read from one of the addressed memory locations during the sequence of memory cycles. 13. Data processing arrangement, characterized by, (a) a processor read-only memory, 509829/0855 - ÖC - (b) a memory for storing data on the processor read-only memory commands to be created, (c) a device for serially reading the commands the memory and for application to the processor read-only memory, (d) an image register for storing from the processor read-only memory input data to be supplied and for storing output data resulting from the actuation of the processor read-only memory, (e) an active indicator for receiving and temporarily storing output signals from the processor read-only memory, and (f) a stack connected to the output of the active indicator, the output of which is for receiving partial results of operations in the processor read-only memory indicated by the instructions from the Active indicator and for feeding these partial results to the processor read-only memory with an input of the processor read-only memory is connected. 14. Arrangement according to claim 13, characterized in that input devices supply the input data in the form of 1-bit words, so that the output data in the form of 1-bit words are generated that indicate the state of a group of controlled devices or that of a group of controlled devices Devices to represent states to be applied. 15. The arrangement according to claim 14, characterized in that the devices from an alternating current source with energy and that a storage cycle is carried out every half cycle of the AC power. 509829/0855 16. The arrangement according to claim 14, characterized in that the output of the processor read-only memory for storing each 1-bit result to the image register or is switched through to the active indicator. 17. The arrangement according to claim 13, characterized in that the memory contains detachably attached multi-word modules, that devices for the serial reading of commands from all modules of the memory are provided and that Circuit devices operate after removing one of the memory modules from its fastening device so that a no-op command is generated from each memory address of each remote module. 18. Processor for generating a solution to a Boolean relationship, characterized by (a) a one-bit-wide shift register, (b) means for loading partial results of the relationship into the shift register and > (c) a device for extracting and combining the partial result with at least one further partial result of the relationship. 19. Programmable logic control unit in which input elements are scanned to determine the state of each of the multi-component lines of a relay conductor circuit are, with output elements of the relay conductor circuit Connect supply voltage sources with energy consumers and disconnect them from the supply voltage sources according to a programmed group of commands that are required to meet operating conditions, which are required by the relay conductor circuit, in are stored in a memory of the control unit, characterized by 509829/0855 (a) a read / write solid state image register, (b) a scanner for sequentially generating a group of 1-bit words, each of which one represents the state of one of the input lines, (c) a device for generating a group of 1-bit output control states depending on the States of the input elements, with an output control state for one of the output elements exists, and (d) a timing device that runs once every half cycle the supply voltage is so effective that the generation and storage of the 1-bit words and the output control states in the register are triggered will. 20. Control unit according to claim 19, characterized in that the time control device reads out the output control states triggers to the output elements. 21. Control unit according to claim 19, characterized in that the time control device has a control device for sequentially establishing a serial input / output operation in which the input elements are scanned and the Output states are read from the register and sent to the output elements are created, whereupon an execution company follows, in which a new group of control states is formed and stored in the register. 22. Control unit according to claim 19, characterized in that the time control device has a means for generating a synchronization pulse at the peak value of the supply voltages. 509829/0855 23. Control unit according to claim 21, characterized in that Instructions stored in the memory in a cycle starting with the log value of the supply voltage addressed serially. 24. It programmed a logic control unit in which input elements are scanned to determine the state of each of the multi-component lines of a relay conductor circuit output elements of the relay conductor circuit connecting supply voltage sources with energy consumers and disconnecting them from the supply voltage sources according to a programmed group of commands that are required to meet operating conditions, which are required by the relay conductor circuit are stored in a memory of the control unit, characterized by (a) a read / write solid state image register, (b) a scanning device for sequential generation a group of 1-bit words, each of which one represents the state of one of the input elements, (c) a device for generating a group of 1-bit output control states depending on the States of the input elements, with an output control state for one of the output elements, (d) means for generating a set of 1-bit tag states in the course of generating the output expensive states, and (e) a timing device that generates and Storage of the 1-bit words, storage of the Output control states and the storage of the identifier in the register triggers. 50 9829/0855 25. Control unit according to claim 24, characterized in that the memory contains an identifier register section and that an output device for outputting data from the identification register section on demand upon completion the solution calculations is provided. 26. A programmable logic control unit implemented with integrated semiconductor circuits, in which input elements are used to determine the state of each of the multi-component lines a relay conductor circuit are scanned, with output elements of the relay conductor circuit Connect supply voltage sources with energy consumers and these from the supply voltage sources accordingly should separate the operating conditions required by the relay conductor circuit, characterized by (a) a keyboard input device for inputting commands in the control unit, (b) an image register for storing multiple 1-bit words encoded information, the register containing addressable storage devices, (c) an addressable memory device for storing multi-bit program instructions for controlling the Generation of output states by the control unit, (d) a control device for receiving the program commands and for generating control connections accordingly the program commands, (e) a scanner for loading 1-bit words according to the states of the input elements in a section of the image register, (f) a processor device connected to the control device and to the image register for performing logical operations with the 1-bit code words, if 509829/0855 - it - they word for word under the. Control can be pushed outwards by the control device, and for generating output states in a further section of the image register and (g) a timing device which, depending on each peak value of the supply voltage, generates timing signals which the scanning device and the Control the processor device so that the image register is sequentially addressed bit by bit. 27. Control unit according to claim 26, characterized in that the image register contains an identifier register section and that a identifier output device for transmitting the content of the identifier register section is provided for the rest of the arrangement. 8. Control unit according to claim 27, characterized in that transmit the license plates in accordance with a first condition at a first speed via the license plate output device to the output elements to the outside and that the identifiers are transmitted on demand during the generation of the output states. 29. Procedure for the selective, condition-dependent change of Output devices in multi-component lines of a relay ladder circuit in a programmable logic Control unit, characterized (a) that peak values of an AC supply voltage are sampled to generate a sequence of synchronization pulses, (b) that depending on each synchronization pulse (I) in an image register, an I-bit image of the State of each conditional input element of the lines generated and stored will, 50 982 9/0855 (II) that for each output device a control state is output during the one immediately preceding each sync pulse Half cycle of the supply voltage has been generated and stored and (III) sequentially to the stored 1-bit images Control generation commands are created that are required by the relay conductor circuit, so that new initial states are generated, processing the 1-bit images represent the commands, and (c) that as a function of the zero crossing of the supply voltage after a given peak value to the output devices S expensive conditions created v / ground that have been stored during the half cycle of the supply voltage, which is one full cycle before the given synchronization pulse has started. 30. Programmable logic control unit in which a read / write semiconductor image register states the states of controlled circuits and stores control states of elements in each of multi-component lines of a relay ladder circuit, marked by (a) Devices for outputting the control states the relay conductor circuit with a data gate circuit, (b) Means for connecting the control unit to a main power source, (c) a standby energy source normally kept operational by the main energy source; (d) a device for blocking the data gate circuit, if the main power source fails and the standby power source is below one to maintain 509829/0855 "if f; the value necessary for storage in the registers drops, and. (e) a device for enabling the data gate circuit after the input of the state of the components in the relay conductor circuit representing new Command into the register. 31. A method for operating a programmable control unit for a system of devices which each display states and are to be controlled, the control unit has an operating cycle within each half cycle of an AC supply voltage, characterized in that (a) that in a first section of a register a Sequence of 1-bit states is stored, each bit representing the state of one of the devices during each half-period, (b) that a 1-bit control state is stored in a second section of the register during each half cycle, to be applied to each of the devices, (c) that in a further section of the register a Sequence of 1-bit identifiers is stored with are related to the control states during each half cycle, and (d) that a control device in each half cycle the Reads license plates and control states from the register. 509829/0855