DE2459476C3 - - Google Patents

Description

60

The invention relates to a circuit arrangement for non-cyclical data permutations between the memory cells of a dynamic memory with an encouragement network for transferring the content in a predetermined memory cell to the read-write> opf and an access control unit for generating permutation sequences, with 2 * memory cells as a permutation network in the form are arranged in a tree structure in k levels numbered from 0 to A-1.

Disk and drum memories are mainly used to store large amounts of data in computer systems used. In these memories, the data is recorded on a magnetic medium, the opposite a fixed read / write head a continuous rotating movement with constant speed of rotation executes. A disadvantage of this cyclical data movement relative to the read head is that that the access time to any date from its respective position in relation to the read head in Moment of addressing depends, so that a statistical mean half a revolution of the recording medium must be carried out before the desired date is read or written can. The time required for this is in the range of milliseconds, so that direct access to the around Central unit operating three to four orders of magnitude faster is not economically justifiable. Therefore These dynamic memories are used as background memory, of which there are contiguous Data blocks via independently working sewer systems initially in the main memory of the central unit transmitted before the computer core is given access. The central unit can access this The access time gap resulting from the fetching of a data block from the background memory bridge through other activity. However, this procedure involves a significant administrative burden , e.g. B. for the release of a working memory area, the creation of a channel program and the Handling of interrupts connected. In addition, there is often the transfer of a coherent block of data not necessary at all if z. B. only individual data have to be inspected. From these For reasons it is advisable to give the central unit quick direct access to individual data as well as also to procure contiguous blocks of data in very large capacities in background storage kept turning.

Only technologies that can be used for the implementation of background storage are characterized by low costs per bit and extremely high data packet density. From this point of view »Charge-Transfer-Devices« appear instead of drum storage systems and »Magnetic-Domain-Devices« especially suitable instead of disk storage. These technologies, unlike disk and Drum storage is a continual movement of data both relative to the storage medium itself and relative to a read / write head permanently attached to the storage medium. Because of the movement relative to the storage medium, it is possible to implement switching functions so that the Data movement does not have to be restricted to a cyclical movement. Rather, the content of a Memory cell by activating one of two outputs on one of two or more successor cells can be transmitted while the cell itself is at the same time via one of two inputs takes over the content of one of two or more predecessor cells, with the respective input and Output is activated by an external binary control signal. There are several ways of doing this or exactly a very short way available on which the contents of any selected cell to the

Read / write head can be transported.

A permutation network is known (IEEE Transactions on Computers Vol. C 21, No. 4 [1972], pp. 359-366) which is based on a tree-like connection structure in which each memory cell has exactly two successor cells and two predecessor cells. All connections within the network are assigned to two permutations, of which the connections of one permutation are activated simultaneously. The two permutations, called "perfect shuffle" and "exchange shuffle", are designed so that in a memory with 2 * cells the content of each cell can be brought to the read / write head in a maximum of k steps via a connection network between the cells . The connection paths assigned to the “perfect shuffle” and the “exchange shuffle” each form closed cycles of different lengths, for example consisting of 2, 3, 4, ... intercellular connections, depending on the size of k.

In another known permutation network (IEEE Transactions on Computers Vol. C-23, No. 3 [1974], pp. 272-276), the connections between the cells are set up in such a way that with a total capacity of 2 ^k − 1 cells with also two permutations, the content of a cell in the order of magnitude of k steps, but the content of all consecutively numbered cells can be transported to the read / write head with a further step delay.

A major disadvantage of both networks is that there are no connections between them neighboring storage cells have to be produced which, with reasonable storage capacities, create a complex, require a non-planar interconnection network with a significant number of line crossings, that takes up a considerable amount of the space available on the memory chip. These networks are completely unsuitable for "magnetic domain devices", since data is transported via larger distances cannot be carried out in a permutation cycle.

The invention is therefore based on the object of structuring the permutation network in such a way that data exchange only takes place between immediately adjacent memory cells, that the connection network remains free of intersections and that access to a memory cell is in the order of k cycles, access to 2 * consecutive cells in the order of magnitude of 2 « cycles with a total storage capacity of 2 * -1 {k> g) cells.

This object is achieved according to the invention in that the level i is formed from 2 'memory cells, that each memory cell of the level / is connected to two adjacent memory cells of the level / + 1 connected to it in such a way that these three memory cells form a triangle in which the contents of the memory cells are cyclically interchangeable clockwise that each of the memory cells of the levels

two triangles and the one memory cell of level O serving as read / write head and each of the memory cells of level k- \ only belongs to one triangle, that an access control unit for the simultaneous transfer of the contents of the memory cells arranged in even-numbered levels into assigned memory cells of the next higher Odd-numbered levels (permutation A) and for the simultaneous transfer of the contents in the odd-numbered levels arranged memory cells in assigned memory cells of the next higher even-numbered level (permutation B) is provided, which either the permutation A or the permutation B causes the access control unit in essentially of a permutation status register for identifying the current permutation status of a first memory cell with the aid of the binary code of the cell address, the content of which is in the read / write head and a memory address register for receiving the binary code of the cell address ei ner second memory cell, the content of which is then to be read or written, and that these registers are followed by a logical comparison network for generating the shortest permutation sequence for transferring the cell contents of a predetermined memory cell to the read / write head.

In an advantageous development of the circuit arrangement according to the invention, the permutation network is formed from a storage capacity of 2 (2 * -1) cells evenly on two tree-like Storage networks are distributed so that the first network contains all cell addresses in their binary code the bit with the value 2 has an O and the second network contains all cell addresses whose binary code is attached this point has a 1, and that a selection circuit operated by the access control unit automatically the Establishes a connection to one of the two read heads of the storage networks.

In another advantageous embodiment of the invention, the memory address register of the access control unit is designed as a forward-backward shift register with k binary digits for loading the address code consisting of k + 1 bits, with the exception of the bit with the valency 2, which is stored in a first single-digit register that A first single-digit overflow register is interconnected with the memory address register to form a ring shift register, so that the permutation status register of the access control unit is designed as a forward-backward shift register with k binary digits for storing the binary code of the cell address, the content of which is to be transferred next to the read / write head , with the exception of the bit of significance 2, that a second single-digit overflow register takes over its bit of significance 0 when the permutation register is shifted to the right, whereby the content existing before the takeover is deleted in the second overflow register and that with the left shift of the Permutation status register transfers its content to the bit with the value 0 in the permutation status register and takes over the content of the first overflow register that a pointer register with k binary digits triggered as a forward-backward shift register contains a pointer in the form that only one binary digit has the value 1 and all the others Binary digits lead to the value O, that a second single-digit register identifies the last ¹ executed permutation A with 1 and the permutation / with O, that a third single-digit register identifies the first permutation A at the address required for access to the address contained in the memory address register with 1 or B with (indicates that a fourth single-digit register is provided for displaying the first permutation A with 1 or ß with I the permutation sequence necessary for the content of the permutation status register, since a single-digit control register contains the content of the two-line

Overflow register duplicates that a / 77-digit counting register determines the right shifts carried out with the memory address register by counting up and the left shifts by counting down, that a fourth shift register with three binary parts shifts its contents to the right with each permutation and in its left binary place a permutation A with 1 and a permutation ß is marked with 0 and from the right binary digit of which the control signal for the permutations in the network can be tapped after two permutation cycles, and that a fifth shift register with three binary digits shifts its content to the right with each permutation and its left binary digit is set to 1, if the first register has a 1, the contents of the memory address register and the permutation status register are congruent and if the right binary digit is 1, the read head of the network is activated.

The advantages that can be achieved with the permutation network according to the invention for dynamic memories are that, compared with memories of the same capacity of 2 * or 2 * -l cells with cyclic data permutation, the access time to any date has drastically increased from an average of 2 * - 'permutation cycles to a maximum of 3k permutation cycles What is shortened is that the transfer of a memory page with 2 £ consecutive cell contents takes exactly / 77 + 3 (2 * -'- 1) permutation clocks, where m <2 (k ~ g) , and that compared to known permutation networks with which Access times of the same order of magnitude can be achieved, the network according to the invention is technologically considerably easier to implement due to its planar, intersection-free structure in which only connections between directly adjacent cells are required.

An embodiment of the invention is shown in the drawing and will be described in more detail below described. It shows

F i g. 1 schematic representation of a memory cell, FIG. 2 structure of a storage network, Fig. 3 permutation network consisting of two simultaneously operated storage networks,

F i g. 4 block diagram of the access control unit, FIG. 5 circuit diagram of the comparison logic of the access control unit.

In the case of a cyclically permuting memory, i.e. a dynamic shift register memory, 2 * memory cells numbered from 0 to 2 * -1 are connected to one another in such a way that the output of the cell / to the input of the cell / + 1 and the output of the cell 2 ^k - 1 is led to the input of cell 0, which serves as a read / write head. When executing a permutation, all characters simultaneously transfer their content to the subsequent cells in the connection structure. In order to transfer the content of the cell to the read / write head, 2 * -i cyclic permutations are required. It follows from this that the average access time to a cell corresponds to 2 * - 'permutal ions, i.e. half a turn of the ring-shaped closed shift register, i.e. h "the average access time is directly proportional to the storage capacity.

In principle, this mean access time can be shortened by using the cyclical Connection structure is replaced by a much more complex network in which some or all cells by means of external control signals, optionally with one of several predecessor cells, whose content is taken over is, as well as with one of several successor cells, to which the current content is delivered at the same time can be connected. This makes it possible to travel much shorter distances between one predetermined cell and the read / write head than with a purely cyclic permutation and thus reducing the number of permutations to be executed accordingly. For information preservation reasons Every cell that takes up the contents of a first other cell must also be hers at the same time Deliver content to a second other cell and vice versa. It follows inevitably that every cell must be part of a cycle during each data permutation, but in contrast to the above. a cyclic pen mutation, to which all cells belong at the same time, one cell alternatively several small ones May belong to permutation cycles, the number of which is determined by the larger number of input resp. Output compounds of the cell, of which, however, at most one permutation per cell is carried out may be.

With a view to a technological implementation with justifiable effort, memory cells with a maximum of two and two outputs are to be considered sensible. Such a memory cell is shown in FIG. 1 shown schematically. The actual data storage takes place in the memory cell FF . The input switch ES and the output switch AS are switched via a control line SL simultaneously by a binary control signal Cso that in the deactivated case (ie == C = O) the cell FF takes over the content of the memory cell upstream of the input £ 1 and its current content to the memory cell connected downstream of output A 1, while in the case of the activated switch (ie C = I) information is taken from input E 2 and output via output A 2 .

Such a storage cell forms the basic building block of a tree-like branching storage network, the structure of which is shown schematically in FIG. 2 is shown. The memory cells are numbered consecutively Arranged levels, with level 0 a memory cell that is used as a read / write head, and each Level 2 contains storage cells. The connecting structure between the cells is structured in such a way that each cell has a level / area

where k- 1 is the index of the highest level of the tree, has one input-side and one output-side neighboring cell in level i + 1. Corresponding to the cell numbering shown in FIG. 2, every even-numbered cell in the level / an input-side neighboring cell in the level / and an output-side neighboring cellc in the level / -1, (and thus every odd-numbered cell in the level / an output-side neighboring cellc in i), as well as a neighboring cell on the input side in / -1. The inputs and outputs of the memory cells are connected in such a way that each cell has a level / in the area

either with the two in level / + 1 Neighboring cells or with those in the levels / or. / -1 located neighboring cells to a clockwise running permulation cycle can be connected, which comprises a total of three cells. Since the Read / write head no neighboring cells in a subsequent

709 637/377

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lower level and the cells of level Ar-1 have no neighboring cells in a next higher level, these cells only take part in one permutation cycle, ie when the other permutation cycle is carried out, the contents of these cells are retained. In order to keep the overall permutation states possible in the storage network and the associated complexity of the access control system low, the triple permutations, which exchange all cell contents in levels with even numbering with the contents of the respectively assigned cells in the next higher, odd-numbered levels, are simultaneously as a first permutation A carried out, and the triple permutations, which exchange all cell contents in levels with odd numbering with the contents of the assigned cells in the next higher even numbered levels, carried out simultaneously as a second permutation B. With a corresponding orientation of the permutation strategy required for the restoration of the initial state after access to a certain cell content: The permutation sequence necessary for the transport to the read head is gradually broken down again that - starting with the last performed permutation - all applied permutations in reverse order of three successive permutations of the same type can be added. From this it follows at the same time that the access to a cell content in the level / and the immediately following restoration of the initial state requires exactly 3 / permutations, ie in the worst case for A: levels exactly 3 (Ar-I) permutations.

In many cases, however, it is not necessary to restore the original permutation state, namely if two successive accesses are made to cells, for the first of which a permutation sequence PQs and for the second a permutation sequence.

and outputs of the memory cells, this 20 sequence PQ _{2 is} required, where Qi and Q2 are different ~ '~ ^: '"''" ^: "', and just like P any order of

Represent permutations A and B. In such a case, after access to the first memory cell, the permutation state only needs to be reduced to P by complementing the partial sequence Qi and then supplemented by Q ₂ .

Should z. If, for example, the content of cell 22 'is accessed first and then the content of cell 26', the sequence BAABBA is executed first. Since the

Permutations through a single control line S, which is connected to the control inputs of all cells - in FIG. 2 represented by the broken line - to be manipulated in such a way that with deactivated control line S CC = O) the permutation B, and with activated control line 5 (C = 1) the permutation A is executed in the entire network.

An important property of this permutation network, which is of decisive importance for it

Control is that - starting from 30 access to cell 26 ' requires the sequence BAABAA , a current permutation state P, which is indicated by an »n ^ the« c »^ ,,, = ^,. ,,:» j » ": -: - c.-._ 7ji" 1 * u _Q - ,; _{1 (} riifh

any sequence of permutations A and B has come about - a triple execution of one and the same permutation, ie a sequence PAAA or PBBB returns to the original permutation state P. This property, which can be derived directly from the network built up in three-cycle cycles, can be used in a simple manner to define any desired permutation state and this sequence corresponds to that for cell 22 'with regard to the first four permutations BAAB, is permuted as follows:

BAABBAAABBAA

(the compensating permutations are underlined). This brings the sequence to a total

to the initial state Φ, in which each cell shortens its twelve permutations compared to twenty-four

. ιι.ΐ-ι-Μ'Μη * γ1ί /> ΐΛ TiKTQArrlnotnn Contents ViirMflZisrhalt -ittrl'inh τίη DA ».» t..4 _n «: I '\\ t> ,, ,, J Auf.

originally assigned content gets back.

Is that in the fig. 2 storage network shown in the initial position Φ and should z. If, for example, the contents of the memory cell 22 'are brought into the read / write head, the first permutation β, then the permutation A twice, then the permutation B twice and the permutation A once must be carried out, i.e. the sequence BAABBA in total. How dozens of permutations when restoring the initial state after accessing cell 22 '.

Successive access to two cells can only then take place with such a shortened sequence if at least the first permutation of both sequences zen is the same, i.e. if both cells are on either even-numbered or odd-numbered levels Index lie. in the

If the first permutation is inequality, the first ZcIIf

from Fig. 2, on the other hand, the overpass 50 requires the initial state to be restored, bcvo the contents of the read / write head in cell 22 ', which can be used to access the second cell. Since in

complementary permutation sequence AABABB. A concatenation of the mutation sequence leading from cell 22 'to cell t' and the permutation sequence leading from cell 1 'to cell 22' leads to

BAABBAAABABB the permutation A changes the content of the Lcsekopfcs! this is always the last permutation of an access sequence. Permutation sequences for access M cells of the same level are characterized by this; that they begin with the same permutation and di 'have the same number of changes between A and', with each change between A and <or B and A, the desired cell content changes to a level with a lower index, ie closer to de

Read / write head is moved.

Consistent application of the rule that at least three must be used to bridge a Fbcnc

Successive permutations of the same type compensate for one, but at most two permutations of the same type, and are therefore carried out from the permutation sequence. The shortest access sequence can be crossed out (which is represented by the <, _{5 is} a cell of a given Fbcnc dcmnac connection symbols), shows that the above characterized in that both Λ and
specified sequence on the initial state Φ of the alternately executed exactly once wcrdci network. This immediately follows the during the longest 'access sequence to a line

the same level is characterized in that both A and B are alternately carried out exactly twice in succession. In Fig. 2 is z. B. with the shortest sequence for level 4, namely BABA, access to cell 16 ', while with the longest sequence, namely BBAABBAA, the content of cell 31' is transported to the read / write head.

To simplify the access control system, the permutation memory is operated in such a way that the respectively effective permutation state results from a permutation sequence which, after deleting all sub-sequences AAA or BBB, contains at most as many changes between A and B as are necessary to access cells of the highest level of the network. This means that for the network of FIG. 2, which has only five levels, although a sequence BBABAA that refers to the. Cell 25 'accesses, allowed, but a sequence BBABAABA that accesses cell 9' is forbidden, since cell 9 'can be accessed with the much shorter sequence AABA.

If, under this restriction, all 2 'cells of a level / are to be accessed with the shortest possible permutation sequence, then a strategy must be used in which the entire tree between the reading head and the level / is traversed in such a way that the total number to be executed of the permutations corresponds exactly to the number of connection edges in this tree. This strategy is based on FIG. 2 for access to all memory cells of level 3. The shortest sequence with which e.g. B. the memory cell 8 'of this level can be reached is ABA. Starting from this sequence, the memory cell 12 ′ of this level can be reached directly by executing a further permutation A, that is to say by means of the sequence ABAA as a whole. Continuing this sequence with both A and ß leads to a sequence ending with B , ie in neither of the two cases does the content of a further memory cell of level 3 appear in the read head. In the first case, however, the sequence is effectively shortened to AB , after which a single application of the permutations BA produces a resulting sequence ABBA which again feeds a memory cell content of level 3 to the read head. The next storage cell 14 'can now be accessed again directly by a further permutation A, which extends the sequence to ABBAA. After the sequence is shortened to ABB again with a third permutation A , a further memory content of level 3, which has not yet been accessed, can now only be brought into the header using the permutations BABA. The consequent continuation of this scheme generally results in access to the memory cells of a level i that the shortest possible incremental sequence is applied first, that the first permutation A, which brings a memory content of the bcne / into the read head, leads to three permissions AAA is supplemented, and that then the sequence of two BA is used so often until a cell content of the level / appears in the Lenckopf again. Thereafter, the procedure is continued as above until the entire Pcrmutalionsscsequen is brought back to the initial state Φ . The complete permutation sequence for accessing the cell contents of level 3 in the tree structure Fig. is shown in the table below, which lists the addresses of the cells whose contents are in the read head after the corresponding permutation sequences have been executed.

Sequence addr.

sequence

Addr.

A. T AWAY 2 ' ABA 8th' ABAA 12th ¹⁰ ABAAA 2 ' FIG 2 ' ABBA 10 ' ABBAA 14 ' ^15th ABBAAA 2 ' FIG 2 '

AA 3 ' AAB 3 ' AABA 9 ' AABAA 13 ' AABAAA 3 ' AABB 3 ' AABBA 11 ' AABBAA 15 ' AABBAAA 3 ' AABBB 3 ' AAA 1'

The + symbol indicates all those sequences that either contain the content of the read head do not change or where the content of the read head does not match one of the memory cells of the Level 3 corresponds.

The table shows that with this permutation sequence at most two cell contents of the desired Level can be brought into the read head by consecutive permutations, and that this both permutations are followed by at least two more,

■>, o in which the read head content does not match that of one of the level 3 cells. This applies, as can be seen from FIG. 2 results for all levels. The total number of permutations performed for level 3 is 21, which corresponds exactly to the number of permutations in the tree between deirr. Read head and the level 3 existing edges, which are traversed by the specified permutation sequence from the original content of the read head exactly once each clockwise. In general, therefore, the shortest possible permutation sequence requires access to all 2 'cells of the level / exactly 3 (2' - 1) permutations.

The permutation properties of the memory structure shown in FIG. 2 can be used particularly advantageously in a so-called "paging" system in which the virtual memory space is implemented by a dynamic memory. During paging, data blocks corresponding to the content of 2> continuously addressed memory cells, the ersu of which must have an address η 2s , are transported between the (virtual) dynamic memory and the (real) main memory of the system. Such a data block, also called page or "page", can be stored in the 2 * cells of level g of the specified memory structure. Since each Zeil · g of the plane part, each root cines / t -g Ebcnei deep sub-tree of a capacity of 2 ^k ~ n I Zelići is, can in the entire memory 2 ^k -t ~ complete pages are stored in such a way as to the same side relevant data is de

do the same cells of these subtrees if the memory is in the starting country Φ . An incomplete page of 2 * '- 1 is accommodated between levels 0 and g-1. ) The complete page can therefore be represented by a so-called prefix sequence, which ii

(15 conventional sense of the Scitenudressc in the virtual Memory, permuted into level ^, and vo can be read or written there according to the specified minimum algorithm. Dn this access sc

If the sequence is usually based on consecutive cell addresses, it is advisable to compare the cell addresses the in F i g. 2 should be changed accordingly.

The property of the permutation sequence required for access to a page of length 2 * ¹ positioned in plane g that two consecutive permutations that transport a cell content of this page into the read head are immediately followed by at least two permutations that the read head does not Feeding in the required data is used to double the total available storage capacity and the data access area for paging without significantly expanding the access control unit. This is done in that two permutation networks of the same capacity are operated simultaneously in such a way that the permutation sequence fed to the first network is also applied to the second network with exactly two permutation clocks delay. The execution of the permutation sequence required for sequential access to the cells of level g then leads to the fact that during the gap created immediately after access to two cell contents of level g of the first network, at least two permutation clocks in the read head of the second network are exactly two cell contents g appear on its level. With appropriate numbering of the cells in the two networks, therefore, can be accessed exactly eight sequentially numbered cells in immediate succession before an access gap occurs This increases access rate is doubled., ie over the simple network be on to access the 2 ^ cells of a page, which are now each housed in half in the planes g- \ of the two simultaneously operated networks, exactly 3 (2s -'- 1) Permutationstakte needed.

The F i g. 3 shows schematically such a permutation network in a tandem tree structure, the cells of which are consecutively numbered so that when a shortest permutation sequence is used for a level / 'the cell contents appear alternately in the order of monotonically increasing addresses in the respective read head. The law of development for this numbering is given by the fact that in the network I, starting with the level / = 1, every cell in a level / with an address x / each has a neighbor in the level / + 1 m ^: t the addresses x, · + 2 '+' and *, + 2 '+ ² .

In the network II, the corresponding cell addresses are each 2 higher. This results in immediately that - apart from the address of the respective read head - the binary codes of the addresses in network I in the bit with the value 2 a zero and in network II all addresses at this point a 1 to have. From this assignment of the cell addresses and those necessary for access to the respective cells Permutation sequences can be the structure and the function of the necessary for the operation of the memory Derive access work.

The functionally essential components of such an access control unit are shown as a block diagram in FIG. A permutation status register SAR represents the current permutation status of the network in binary-coded form. The respectively desired address of the cell, the content of which is to be transported next to the read head, is loaded into a memory address register MAR. A logical network, supported by a few auxiliary registers, generates the permuuiiion sequence necessary for the transport and the corresponding control signal sequence from a comparison of the contents of MAR and SAR.

From the distribution of the addresses over the two simultaneously operated networks it is immediately clear that the address bil with the valence 2 occupies a special position insofar as it is not necessary for the derivation of the permutation sequence. since addresses that differ only in this bit each require the same permutation sequence. This bit is only necessary in order to select which read head is to be used when the required cell content appears in the read head of the respective network. According to the definition, in the case of a 0 this is the read head of network I, and in the case of a 1 the read head of network II. The address bit of significance 2 is therefore not loaded into the MAR register, but into a single-digit register MFF.

The coding suitable for describing the permutation state of the network is derived from the fact. that due to the above restriction of the 7 permutation sequences, each cell content can get into the reading head with only one permutation sequence. To specify the permutation status of a tree network comprising 2 * -1 cells, an fc-digit register is sufficient, which contains the address of the cell in binary-coded form, the content of which is currently in the read head. In the case of the permutation network in tandem structure, the total capacity of which comprises 2 (2 * -1) cells, a Jt-digit register is also sufficient, since here - as in the case of the address register - the bit of significance 2 is irrelevant . The control problem of the network is then reduced to bringing the content of the register SAR to coincide with that of the register MAR by means of suitable permutations.

The algorithm required for this and its circuit implementation results from the relationship between the binary codes of the cell addresses and the permutation sequences necessary for access to the cells. This relationship will be explained using two examples. Access to cell 56 located in network 1 of ir F i g. 3 is located tandem memory, success - as can easily be seen from the structure - with the sequence BBAABA. If, as agreed, the permutation A is coded with a 1 and the permutation B with a C, the following relationship results between the address code and the permutation code:

Address code 1 1 1 0 I. I. T
1 Permutation code 00 11th 0

The most significant bit 1 in the address code, also referred to below as the pilot bit, identifies the level on which the addressed cell is located, and thus the permutation to be carried out first. In this case the cell belongs to level 4. the first permutation is then B, represented by 0 in the permutation code. The number of bits to the right of the pilot bit, with the exception of the framed bits with significance 2, increases by 1! Number of required changes between permutations A and B. since each bit represents a level in the tree. In the example, starting with the permutation B, three changes, namely BABA, are required. This also separates the correspondence between

Address code: 1 0 0 1 I. I. ι Permutation code: 0 1 00

Those bits in the address code and those in the permutation code are obvious. If the address bit is 1. then the associated permutation is carried out twice, but if the address bit is 0, then only once. This is also shown by the example for the access to the cell 39, which lies in the network II, with the aid of the sequence BABuAA.

11th

The pilot bit in the address code again points to the fourth level, i.e. that is, the first permutation must be B. Since the first bit to the right of the pilot bit contains a 0, this permutation is only carried out once. The same applies to the following permutation A. while the following permutations B and A each have to be executed twice. From this assignment of the address code to the permutations necessary for access to the respective cells, the result is shown in FIG. 4 schematically represented access control unit.

It contains

a memory address register MAR, designed as a forward / backward shift register, consisting of Jt binary digits corresponding to a storage capacity of 2 (2 ^k - 1) cells in the tandem network), into which the address code consisting of k + 1 bits - except for the bit of significance 2 - is loaded in such a way that the / -th bit of the address is in the / -th binary digit of the register, whereby the binary digits are numbered from right to left in the order 0,2,3,4, ... k— 1, Jt [this is briefly represented in the form MAR (k : 2.0)];

an overflow flip-flop HM, which together with the register MAR forms a ring shift register in such a way that with the right shift the content of the binary digit MAR (0) is transferred to HAi, and the content from HM to MAR (k) , while vice versa with the left shift the upper reaches from MAR (k) to HM, and its content is shifted to AMÄ (O);

a one-digit register MFF into which the bit of significance 2 of the address code is loaded; a permutation status register SAR (k: 2.0), also designed as a forward / backward shift register, which contains the binary code of the address of the cell in each permutation state (except for the Bk of the valency 2), the content of which is currently in the read head of network I. ; a single-digit overflow register HS, which takes over the content of SAR [O) when the register SAR is shifted to the right, while its own content is lost, and which transfers its content to SAR (0) when shifting to the left, while itself the content of the overflow flip-flop HM takes over; a pointer register (forward / backward shift register) SPR (k: 2,0), which contains a pointer of the form that only one binary digit SPR (i) always has the value 1 while all other binary digits have the value 0; a one-digit register 5FF which represents the type of the most recent permutation such that SFF-X corresponds to permutation A and SFF = O corresponds to permutation B;

a one-digit register MHF. in which it is recorded whether the position of the pilot bit immediately after loading MAR corresponds to a first permutation A (MHF = 1) or B (MHF = O) to be carried out for accessing the corresponding cell; a single-digit control register HH, in which the content of HSdupüzier; can be; a single-digit register SHF. in which the first permutation of the permutation sequence contained in SAR is recorded;

a / »- digit binary counter CNT (m-1: 0). in which the number of right shifts and left shifts performed with the MAR register can be counted;

a ^ -digit binary counter ADCT (g- \ : 0). which is used for the continuous addressing of cells on a page in such a way that the counter reading - starting with the value 0 - is incremented in steps of 1 until the value 0 is reached again and that after each increment the content of this counter reaches the last g Binary digits of the memory address register MAR is transferred; a shift register DEL (0: 2) consisting of three binary digits , in whose bit DEL (O) a 1 is entered if a permutation A is executed, and a 0 if B is executed, the content of which is one binary digit after each permutation is shifted to the right, and from whose bit DEL (2) the control signals for the network Ii can be derived after exactly two permutation clocks;

a shift register READ (O: 2), which is also shifted to the right with each permutation, and in whose bit READ (O) then a 1 is written if the flip-flop MFF is set to 1 and at the same time the contents of MAR and SAR have been brought into congruence, and whose READ (2) bit controls the read head of network II if it contains a 1; a logical network COMP, which evaluates the contents of the registers MAR, SAR and SPR and generates various control signals, as well as a in FIG. 4 control unit, not explicitly shown, which executes the microprograms necessary for controlling the registers and the memory network. The data exchange with the control unit is shown in the block diagram of FIG. 4 represented by arrows S.

The current permutation status of the storage network is given by the content of the permutation status register SAR, which specifies the address of the content currently in the read head, and by the content of the single-digit register SHF. the first permutation of the time necessary to achieve this state Permutationssequenz indicates Moreover, the register SFFdie last Permutatiori executed stored When loading a new address in the Speieneradreßregister MAR is with the procedure described below, the contents brought this cell in the read head of the respective storage network with the help of logical network COMP wire, the pointer in SPR is initially set to the binary digit that corresponds to the higher value of the two pilot bits in MAR and SAR. At the same time, a signal IMAX determines whether the pointer position coincides with the pilot bit in MAR , and a signal KMAX whether the pointer position coincides with the Püötbit in SAF. coincides. If IMAX = 1 and KMAX = the higher-order Piiotbit belongs to the register MAR

Il

It is now determined on the basis of the pointer position set in SPR whether this pilot bit is in a position. which corresponds to a permutation A or ö, and fixed by setting Λ / W accordingly. Then the pointer in SPR is shifted step by step to the right or circulated in the specified form, simultaneously with the contents of the MAR register, until both IMAX = 1 and KMAX = I. The pilot bits in MAR and SAR are now in the same position . ^{| 0}

If, on the other hand, IMAX = 0 and KMAX = 1 in the initial state, the content of SAR is first shifted step-by-step to the right together with SPR. In each step, the SAR bit transferred to the single-digit overflow register HS is evaluated as follows. Since an I means that the permutation specified in SFF has been carried out twice, the same permutation must be carried out exactly again to compensate for these permutations in order to verify the right shift of the register SAR by a corresponding shortening of the permutation sequence. If, on the other hand, SFF contains a 0, which means that the relevant permutation has only been carried out once, then in order to compensate for this one permutation it must be carried out exactly once again. This is done with the help of the single-digit register HH, in which the content of HS is duplicated and interpreted there. If W // contains a 1, the permutation is aborted after a single execution, if HH, on the other hand , contains a 0, HH jo is set to 1 after executing a first permutation and the same permutation is added to three and the effective permutation sequence has been shortened accordingly, the content of SFF is inverted. SFF now contains the permutation which corresponds to the bit transmitted by the next right shift from SAR to HS. This right shift is first repeated step by step until both IMAX = 1 and KMAX = 1. At the moment when IMAX assumes the value 1, MHF is set because the pointer position set in SPR now also coincides with the pilot bit in MAR . If the pilot bits already coincide in the starting position, there is no need to shift MAR and SAR separately.

Now both MAR and SAR are shifted to the right together with the pointer in SPR, which now points to the pilot bits in both registers. As before, the bits flowing out of MAR to the right are rewritten into MAR from the left, while the bits flowing out of SAR to the right are lost in HS and HH according to the interpretation already described.

If the contents of the single-digit registers MHF and SHF, which indicate the first permutation of the permutation sequence required for the address stored in MAR or the first permutation sequence required to implement the current permutation state, are the same, parts of the two permutation sequences may under certain circumstances be identical . The network COMP therefore compares the contents of SAR and MAR after each right shift between the pointer position and the binary digit 0. If the contents are not identical, a further right shift is carried out; in the case of identity, the shift to the right is aborted.

In the event that the contents of MHF and SHF are not the same, there are no identical partial sequences and the right shift of MAR. SAR and SPR have to wait repeatedly until the pointer position and the respective pilot bits have reached binary position Q. In this way the network is in its starting / usiand Φ /backvcrse.zl.

With every right shif. in which the MAR register is involved. the binary counter is respectively incremented CNTum one so that contains CNT at the end of right shifts, the number of ünksshifts that must be performed on MAR to the initial situation in MAR restore simultaneously.

In the case of MHF equal to SHF , the content of SFF is retained after the right shift has been completed, while in the case of Λ / W not equal to SW, the content of MHF is transferred to SHF.

There is now a common step-by-step left shift of the MAR registers. SAR and SPR carried out. I _n each step the appearing in the overflow register of the register MAR HM bit is transmitted in HS and HH simultaneously. A 1 in HH is converted into a double execution of the permutation specified in SFF , a 0 is converted into a single execution of the permutation. After completion of this action, the content of SFF is inverted, the counter CA / ⁷ "is counted down by one, and the registers are shifted to the left. The procedure is then stopped when the content of the counter C / vT has counted down to 0, ie the in MAR charged cell address to its original position is again reached. Since the bit contained in HM in HS was duplicated in each step and the corresponding permutations are carried out is at CNT = O, the content of MAR and SAR are identical, and in the reading head of the network I appears the cell content identified by the address contained in MAR If a cell content of the network II is addressed, which is indicated by the status of the single-digit register MFF , then when CN1 is reset to the value 0, a 1 is loaded into the delay register READ , which enables access to the read head of network II after two further permutation cycles.

This procedure implements a minimal permutation sequence for accessing any two successively addressed cell contents according to the example for accessing cells 22 and 26 of the FIG. 2 shown network. Since the cells of the network of FIG. 3 are numbered so that access to 2 ^ consecutively numbered cells is minimal, after all cell contents have been transported to levels g- \ of the tandem network, this access sequence can be generated in the specified access structure by using the ^ -digit binary counter ADCT - starting with counter position 0 - counting up by 1 until counter reading C is reached again. The respective counter setting is transferred to the last g binary digits of the MAR register, whereupon the required permutation sequence for the shortest possible transport of the content of the addressed cell to the read head is carried out. Special measures for addressing the cells of network II are not required if the control bit MFF remains set to 1 throughout this process.

An essential part of the access control unit is the logical network COMP, which contains the contents of the MAR. SAR and SPR correlated with one another. Corresponding to the k- 1 binary digits of these registers, the network contains k- 1 cells, which are connected to one another in a cascade, that logic signals are present

left to right, d. H. from the higher genes to the low-order binary digits. One solci-e cell corresponding to the binary digit / is in FIG. 5 shown,

The logical network COMPscm immediately after loading the register MAR with an η ^ uen address the pointer position in SPR in such a way that it coincides with the higher value of the two pilot bits in MAR and SAR . Furthermore, this network generates a signal IMAX, the coincidence of the pointer position in SPR _with the pilot bit in MAR, and a signal KMAX, the Ko ^; Indicates the incidence of the pointer position in SPR with the pilot hit in SAR . In addition, this circuit is used to determine the identity of MAR and SAR between the pointer position and the binary digit 0. ,

For this purpose, the contents of the binary digits MAR (O via a line 60 and SAR (i) via a line 61 are each fed to one input of the AND gate 62 and the antivalence gate 63. At the same time, there is a third input of the AND gate 62 a control line 64 common to all cells, which carries a signal SET . Another AND gate 65 receives a signal 0UT (i + \\ via line 66 from the left neighboring cell / + 1 and at the same time via line 67 the inverted content of the binary digit SPR (i) the pointer register. the outputs of the gates 62,63,65 are led to the inputs of an OR gate 68 whose output line 69 a the signal received from the left cell / + 1 via the line 66 signal oUT (i + \) corresponding Signal OUT (O is sent to the right neighboring cell / -1. At the same time, line 69 is connected to a first input of AND gate 70, control line 64 to its second and third input and, in inverted form, the output of AND gate 65 are switched. The output line 71 of the gate 70 is led to the input of the binary position SPR (i) of the pointer register SPR . The signal present on the output line 69 is formed by the logic operation

40 OUTd) = MAR (i) ®SAR (i) + MARd) SAR (O SET

The entire signal pattern SPR (i) is inserted into the pointer register SPR and the pointer position is thereby fixed.

SPR * is now 0, if StT = 0 is applied to line 64, then output 69 of each cell carries the signal according to equation (1)

+ 0UT (i + 1) SPR (O) (1)

The signal formed on the output line 71 is produced by the logic combination OOTd) = MAR (i) ® SAR (i) + 0UT (i + \) SPR (O).

Accordingly, a signal 0 appears at each output of cell 0 only if between the current pointer position SPR (i) = 1 and position 0 for all binary digits / and

MAR (i) @ SAR (O = O

is, ie if the cell contents of the two register segments MAR (i ·. 2.0) and SARfi: 2.0) are identical.

The AND gate 72 combines the lines 67 and 60, ie the pointer position SPR (i) with the content of MAR (i) in such a way that a 1 is always present at the output of the AND gate 72 if both MAR (i) = 1 as well as SPR (O = 1, whereby the latter can be the case for exactly one binary digit by definition. This signal becomes an OR function via a protective diode 73 with the corresponding gate outputs of all other cells

IMAX = Σ MARd) SPRd)

(3)

hardwired on bus 74.

The same function is carried out with the aid of the AND gate 75 and the protective diode 76 on the bus 77 for the contents of the registers SAR and SPR in the form

KMAX = XSAR (OSPRd)

(4)

SPR (I) = OUT (i + I) OUTd) SET (2)

This part of the network can be used to set the initial pointer position as follows: -:

Before the set zen v on SPR applies to all positions SPR (O = 0, ie SPR (i) = 1. When setting the pointer position signal S £ Tauf is placed logic 1, thereby on the line 69 in accordance with equation (1) the signal

OUT (O = MAR (O + SAR (i) + OUT (i + I)

is applied. According to the definition, the pointer must be set exactly in the binary position /, for which OUT (IV I) = O but OUT (O = 1, ie both the MAR register and the SAR register only contain logic 0 to the left of / ', but it does is MAR (0 = \ or SAR (i) = \. This state is determined by the AND gate 70, at whose output under the condition SET = 1 the signal

SPR (O = OUTp + \) OUT (i) ⁶ ^

according to equation (2), which can only assume the value 1 for exactly one binary digit. The realized.

Since the contents of MAR and SAR are, as agreed, shifted synchronously with the pointer position in SPR as soon as the pointer comes from the left and encounters the pilot bits of MAR or SAR , / MAX = O only as long as the pointer is to the left of the pilot bit in MAR otherwise IMAX = 1.

By definition, this defines the conditions for controlling the shifts in the MAR and SAR registers.

To determine whether the position of the pilot bit in MAR requires a first permutation A or B , the even-numbered binary digits of the pointer register SPR are hard-wired to an OR function via protective diodes on a further bus SMF, not shown in FIG a signal 1 leads if the pointer coincides with an even-numbered position, and a signal 0 if the pointer is in an odd-numbered position at the moment when the pointer coming from the left encounters the pilot bit in MAR , ie when IMAX from 0 switches to 1, the signal indicating the pointer position to SA / flying will be transferred to the single-digit register MHF .

Another variant of the permutation network consists in the tandem network according to FIG. 3 to change the control of the second network in such a way that the permutations B and A are interchanged with respect to the levels of the network. As a result, with synchronous operation of both subnetworks, the first always delivers a new cell content to the read head when permutation A is carried out while the

second network always changes the read head content when permutation B is executed. The execution of the algorithm specified for the »paging« in such a tandem network then leads to the fact that with the appropriate cell numbering, tree-like organized data structures, which are stored in a suitable manner, can be traversed according to the so-called »pre-order« or »end-order«. Principle.

It is also conceivable to have such a dynamic background memory with fast direct access arbitrarily addressed data as well as fast sequential

len access to data blocks that are stored in 2f continuously addressable cells, upstream of a peripheral processor that frees the central unit from part of its workload by ei various activities, such as. B. List processing and other management activities are handled directly with the background memory. In addition, such a processor would have to be able to function as a channel; to be assumed if a data transport between the background memory and the main memory of the central processing unit is required.

For this purpose 4 sheets of drawings

Claims (6)

24 claims: 1. Circuit arrangement for non-cyclical data permutations between the memory cells of a dynamic memory with a permutation network for transferring the content of a predetermined memory cell to the read / write head and an access control unit for generating permutation sequences, with 2 ^A -1 memory cells in the form of a tree structure as a permutation network k planes numbered from 0 to k- 1 are arranged, characterized in that the plane / is formed from 2 'memory cells that each memory cell of the plane / is connected to two adjacent memory cells of the plane / -1-1 connected to it, that these three memory cells form a triangle in which the contents of the memory cells are cyclically interchangeable clockwise; that each of the memory cells of the levels two triangles and the one memory cell of level 0 serving as read / write head and each of the memory cells of level k- 1 belongs to only one triangle, so that an access control unit for simultaneous transfer of the contents of the memory cells arranged in even-numbered levels into assigned memory cells of the next higher Odd-numbered levels (permutation A) and for the simultaneous transfer of the contents of the memory lines arranged in odd-numbered levels into assigned memory cells of the next higher even-numbered level (permutation B) , which either the permutation A or the permutation B causes the access control unit in essentially from a permutation status register (SAR) for identifying the current permutation status of a first memory cell with the aid of the binary code of the cell address, the content of which is in the read / write head and a memory address register (MAR) for receiving the binary code d he cell address of a second memory cell, the content of which is then to be read or written, and that these registers (MAR, SAR) have a logical comparison network (COMP) for generating the shortest permutation sequence for transferring the cell content of a predetermined memory cell to read / write -Head is downstream. 2. Circuit arrangement according to claim 1, characterized in that the permutation network is formed from a storage capacity of 2 (2 * -1) cells, which are evenly divided between two tree-like Storage networks are distributed in such a way that the first network contains all cell aciresses in which Binary code the bit with the valence 2 has a 0, and the second network contains all cell addresses, whose binary code has a 1 at this point, and that a selection circuit operated by the access control unit automatically establishes the connection to one of the two read heads of the storage network. 3. Circuit arrangement according to claim 1 and 2, characterized in that the memory address register (MAR) of the access control unit is designed as a forward-backward shift register 476 k binary digits for loading the address code consisting of k + \ bits, with the exception of the bit with the valence 2, which is stored in a first single-digit register (MFF) , that a first single-digit overflow register (HM) with the memory address register (MAR) z \ i ein Ring shift register is interconnected that the permutation status register (SAR) of the access control unit is designed as a forward-backward shift register with k binary digits for storing the binary code of the cell address, the content of which is to be transferred next to the read / write head, with the exception of the bits of the valence 2, that a second, single-digit overflow register (HS) at the right shift of the Permutationsstatusregisters (SAR) takes over the bit of weight 0, the existing prior to the acquisition content is deleted in the second overflow register (HS) and at the shift left of the Permutationsstatusregisters (SAR) transfers its content to the bit with the value 0 in the memory address register (SAR) and the In halt of the first overflow register (HM) assumes that a pointer register (SPR) designed as a forward-backward shift register with k binary digits contains a pointer of the form that only one binary digit has the value 1 and all other binary digits have the value 0, that a second single-digit register (SFF) the last executed permutations A with 1 and the permutations ß with 0 indicates that a third single-digit register (MHF) for the permutation sequence required for access to the address contained in the memory address register, the first permutation A with 1 or B with 0 indicates that a fourth single-digit register (SHF) is provided for displaying the first permutation A with 1 or B with 0 of the permutation sequence necessary for the content of the first permutation status register (SAR) , and that a single-digit control register (HH) contains the content of the second overflow register (HS) duplicates that a / 77-digit counter register (CNT) with the memory address reg ister (MAR) executed right shifts by counting up and the left shifts by counting down; that a fourth shift register (DEL) with three binary digits shifts its content to the right with each permutation and marks a permutation A with 1 and a permutation B with 0 in its left binary digit and from its right binary digit the control signal for the permutations in the network can be tapped after two permutation cycles, and that a fifth shift register (READ) with three binary digits shifts its content to the right with each permutation and its left binary digit is set to 1, if the first register (MFF) has a 1, the contents of the memory address register (MAR) and the permutation register (SAR) are congruent and with a 1 in the right binary digit the read head of the network is activated. 4. Circuit arrangement according to one or more of claims 1 to 3, characterized in that each binary digit of the memory address register (MAR), the permutation status register (SAR) and the pointer register (SPR) in the logical network (COMP) is assigned a cell that each Cell / four inputs (60, 61,67,66) has that the first input (60) with the output of the / -th binary digit of the memory address register (MARX of the second input (61) with the output of the / th binary digit of the permutation status register (SAR), the third input (67) with the output of the / th binary digit of the pointer register (SPR) and the fourth input (66) with the output of the ( 7+ l) -th cell of the comparison network (COMP) is connected, that each cell has two outputs (69, 71), that the first output (69) with the corresponding fourth input (66) of the C / -l) -th Cell of the comparison network (COMP) and the second output (71) is connected to the input of the / th binary digit of the pointer register (SPR) and that all cells of the logical network (COMP) are connected to a first and a second signal bus (74, 77) and a control line (64) are connected. , ₅ 5, circuit arrangement according to claim 1 to 4, characterized in that the first input (60) of each cell of the logic network (COMP) with a first input of a first AND gate (62) and a first input of an antivalence gate (63) connected is that the second input (61) to the second inputs of the first AND gate (62) and the antivalence gate (63) is connected that a third input of the first AND gate (62) is routed to the control line (64) that a first input of a second AND gate (65) with the fourth input (66) of the cell and a second inverted input of the second AND gate (65) is connected to the third input (67) of the cell that the outputs of the first and second AND gates (62,65) and the output of the antivalence gate (63) to the inputs of an OR gate (68) are placed that the output (69) of the OR gate (68) to a first input of a third AND gate (70) is connected so that a second inverted input of the third AND gate (70) to the output of the second AND gate (65) and a third input of the third AND gate (70) is connected to the control line (64) that the output of the third AND gate (70) with the second output (71) of the cell is identical that the first and third input (60, 67) of the cell to the Inputs of a fourth AND gate (72) are connected, the output of which via a first protective diode (73) is connected to the first collecting line (74) and that the second and third cell input (61, 67) to the inputs of a fifth AND gate (75), the output of which is via a protective diode (70) is connected to the second collecting line (77). 6. Circuit arrangement according to claim 1 to 5, characterized in that for sequential access to 2s consecutive addressable cell contents, the first address of which must be an integer multiple of 2ε , a # -digit binary counter (ADCT) is integrated into the access mechanism, the content of which is according to is transferred to the last g binary digits of the memory address register (MAR) in each counting step.