DE2456534A1 - DATA PROCESSING SYSTEM - Google Patents

Description

COMPAGNIE HONEWELL BULL
94 · ι Avenue Gambe ti? A
PARI 'S (20) / France

Our sign; H 1025

DATA PROCESSING / iOMGSSYSTEM

This invention relates generally to computer systems and, more particularly, to a system and method of control of computer processes in a multi-program / multi-processor operation.

The fourth generation systems will be able to to meet the following requirements:

1, "The system is called a communication and control system

classified and able to cater for wide and diverse processor applications ".

2. "The system is mainly through data and not through

Programs, as was the case with earlier Fal3 machines, controlled: i.e. the system control is mainly controlled by entered information and not by stored Commands carried out ".

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3. "The hardware will do the communication and control procedures carry out; the use of system control programs is significantly restricted or abolished » .

4. "Most of the processing is done in real time; the operations are carried out as data is entered carried out at a speed that an output of information within the required response time guaranteed ".

5. "The system will be prepared for expansion.

Hardware and software are designed to be functionally modular "'.

Processing in the first generation hardware / software computer systems was relatively "straight forward" with the "job" or program considered to be the basic unit of processing. For each user-drawn "job" or operation, the program generally ran with little or no interruption until the "job" or operation was completed. Many ^H straight ahead "jobs, such as compiling and executing programs in a high-performance language such as FORTRAN, could run as a single process. However, more difficult" jobs "would require multitasking operations and produce processes other than those being performed represents a concept that involves performing a particular activity and should not be confused with the concept of a program, which is an activity description and can be used by one or more processes speaking who is running a program (see explanation of definitions).

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The concept of a processor as a basic processing unit was designed to be a. Claim of the multi-program / multi-processor structures to correspond to the third generation of computers. In such a structure where many users access services at the same time, it is normal to use multiple processes with the Institutions within the computer system compete. Each process consists of a program (i.e. an ordered Collection of commands and others related to the commands Data), which is carried out by the computer and processed data in order to perform the "job" of the user or a 'specific Phase of this "job" to carry out. Wherever many such processes require the use of the system at the same time, become the task of communication with and between such processes as well as the tasks of controlling and assigning the auxiliary equipment for such processes, especially with regard to the requirements of the fourth Computer generation extremely difficult.

In a document entitled "Process Control and Communication" by A.J. Bernstein, G.D. Detlefsen and R.H. Kerr, published in the ACM Symposium of Operating Systems, becomes “the structure of processes and those used in a general purpose surgical system Inter-Process Communication Devices "is described.

In this system, a procedure can consist of up to 4 parts called logical segments. the Segments can be in spatially separated memory locations if the process is in memory. That Find and protect these segments carried out with the help of four registers.

In general, processes are controlled by an operating system which uses primitive instructions (i.e. pseudo instructions) which are generated by the process and use a mechanism that enables communication between enables the processes. A communication consists mainly of events that have the same AIT input (Active Items Table), which contains a single entry for each file that has just been opened. With the help of this Structure, a process can get a "notification" (by issuing a "Notify" primitive ~ command) when the Incident occurs. As a result, the operating system generates input to the event queue assigned to the Event is assigned, which identifies the waiting notification of the retrieval process. At this point you can the calling process can continue the execution or do its own thing by issuing a block primitive command Interrupt execution. The incident is said to have occurred when some other process a "CAUSE" primitive command for this event generated; the incident can be cataloged and processed in the lead structure, the same. Primitive commands used. Information can be transferred from one process to another or the processes work together in a different way to carry out a specific task. Other primitive commands in the Operating system create and develop processes or cancel them.

This process and communication control technology does not generate an orderly dynamic process history of the running Program; however, it does bring some conceptions of software multiplexing from processes and event control to application.

In a multi-program / multi-processor structure, it is from

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it is of the utmost importance that the interaction between two or more sequential processes is efficient and rapid is carried out. Many solutions to this problem have been proposed in the past; the technology of however, process communication control required for the fourth generation computers is still up to now has not been fully realized. Developing the concepts required for fourth generation computers however, is partly from E.W. Dijkstra in a document entitled "Cooperative Sequential Processes from Programming Languages "of the NATO Institute for Advanced Studies edited by F. Genuys in Paris and published by the Academic Press in 1968. In In this document, Dijkstra calls for a "basic semaphore concept" which is used for process synchronization can be, and after P and V commands that affect the "semaphore". Unfortunately, Dijkstra hits only one for process communication and synchronization Software process and thereby not only slows down the Operating time of the system, but also determines the effectiveness and the overall utilization required for such a system down. More importantly, Dijkstra is not one of the fourth for the effective operation of a computer Generation necessary concepts developed, since he formulates only a basic proposal for process synchronization. For example, the transfer of messages from one process to another is not implied in Dijkstra's document still described. For the fourth generation, a system is required that automatically handles process communication and control integrated and thus not only increases the operating performance of the system, but also increases it sufficient flexibility to cope with the numerous situations that result from the transfer of information surrender from one process to another.

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The concept of the P and V commands has been previously discussed by Edsger W Dijkstra in the aforementioned article been. However, these concepts are given only in general terms and do not make a statement for a fourth generation computer required configuration. Furthermore, Dijkstra hardly develops a software basis for decryption and using the P and V commands. It therefore does not describe the necessary storage organization for the fast Access to processes in connection with the creation of a systematic reallocation of the data processor.

Purpose of the invention

A primary purpose of the invention is to provide an improved system and method for process synchronization in a multi-program / multi-processor structure.

Another purpose of the invention is to develop a system and method for process synchronization with the help of a family of commands designed to reduce operational congestion.

Another purpose of the invention is development a system and a method for process synchronization of events outside the central processing subsystem expire in order to overcome the previous functional limits.

Another purpose of the invention is to develop a system and method for integrating the input / Output interruption in the function of the central processing subsystem, to reduce circuit and time expenditure.

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Another purpose of the. The invention consists in the development of a system and a method for initializing the "Semaphore", in this way both the execution time and the total size of the required memory space to reduce.

The above objects are achieved in accordance with one embodiment the invention and its mode of operation achieved in that in a data processing system an instruction family that generates data for further processes. The command family primarily generates information by two operations, i.e. by the P operation, which Information (data) needed and the V operation that Information (data) generated.

A process executing a P instruction needs data to continue the operation. The P command addresses a "Semaphore ¹¹ data structure and decrements its number field by the numerical value 1. If the result value of the" Semaphore "count field is not negative, the process executing the P command continues its execution next command in its segment procedure; if the result value is negative, however, - the process which carries out the P command is interrupted and placed in a waiting status on the "semaphore" addressed by the P command furthermore (ie a V operation on this same "semaphore") a dynamic continuation of the process which is executing the P instruction is logically not permitted and no processor is assigned to this process.

A process performing a V instruction generates data. The V command addresses a "semaphore" and increments the Value of the "semaphore" counter field by 1. If the result value of the "semaphore" count field: is positive, the V command in the data transfer is complete; but if the result value

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of the "semaphore" count field is not positive, the V command issues one of the processes which are in the waiting state and which are assigned to the same addressed "semaphore" free for the change to the ready status, i.e. the dynamic continuation of the waiting status The called process is again logically permissible and at the intended time, i.e. when it is a processor has been assigned, it changes to the operating status.

Variations of the P and V commands include individual ones Commands for both "semaphore" structures without messages and for "semaphore" structures with messages; each variant also has test commands, the test commands give the Continuation of the procedure in the operating status free if the P or V commands cannot be carried out. External events, i.e. pending input-output interruptions and certain pending exception conditions processed. This is done by the system event retrieval unit (System Event Poller), which is normally entered by the central unit at the end of each command. If the central processing unit is not in a critical transition mode, all input-output interrupts will be and retrieved certain exceptions. With every external incident, the "system Event Poller "on behalf of the input-output subsystem or the central exception mechanism a simulated V operation to transfer the relevant information. In the meantime, the selective retrieval is continued until all external events have been processed. After all pending input-output interrupts and exceptions have been processed, an Input to the dispatcher unit to determine the next process that will control the central unit takes over.

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The "semaphore" initialization command finds a "semaphore" with the help of the address development of its address syllable. If the "semaphore" does not contain a message, the "semaphore" count field receives an N number which is stored in a general register of the process in progress. If the "semaphore" contains a message, the "semaphore" counter field is cleared to zero. In the case of a message "semaphore", if its previous counting field was greater than zero, all message chaining in Q / M / S are returned to the free message chaining ¹¹ semaphore "FLS and chained with Q / ML / FLS. If the previous counting field of the "semaphore" is equal to zero, no transmission of the message chains is required and the command is complete.

The novel facilities characteristic of this invention, are particularly described in more detail in the attached claims. The invention itself can however, by inspection of the following description in conjunction with the drawings, both by the organization and by the can be best understood from the operational point of view as well as with regard to other goals and advantages:

Fig.1 shows the block diagram of a multi-program system represents in which the invention is used,

Fig. 2 is a schematic representation of the various hardware structures used for the invention,

Fig.3 contains an explanation of the reserved for the Memory areas of the expressions used in the registers shown in Fig. 2,

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Fig. 4 is a schematic diagram of a process control block,

Figure 5 is a schematic diagram of a system for Addressing a process control block,

FIG. 6 is a schematic diagram of the system base of FIG Invention,

7A and 7B are each systematic representations of a stack segment and a stack element,

Figure 8 is a schematic diagram of a system for Addressing the G segments and especially the process queue in the GO segment,

Figure 9 is an exploded schematic diagram of a GO segment and represents the process queue and process chain,

Figs. 10a to 101 are block diagrams of structures within of the PCB,

Figures 11a through 11r are block diagrams of structures within the system base,

FIG. 12 is a schematic diagram of the addressing of FIG S-Schemas for user and system segments using the system base and PCB structures,

Figures 13a, 13b and 13c are schematic diagrams of the Control unit,

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Fig. 14a to I4i are flow charts of the firmware dispatcher unit,

Figure 15 is an exploded view of a "semaphore" descriptor segment and its structure,

Figs. I6a through I6d are block diagrams of ¹¹ semaphore "structures used in the system;

Fig.17 is a schematic diagram of the "semaphore" address development,

Fig.18 is a schematic diagram showing the relationship

of the "semaphore" descriptor segment to a GO-. 'Segment is shown,

19a and 19b are schematic exploded diagrams of the "Scratch Pad" memory of the one shown in Fig.13 logical storage unit and explains the overall organization of its word structure,

Figures 20a and 20b are flow charts for all of the P and V commands used "semaphore" descriptor acquisition subroutines,

Fig. 21 is a flow chart of the P command for "Semaphore" without reports,

Fig. 22a to 22e are flow charts of the P commands for "semaphore" with messages,

Figures 23a through 23h are flow charts of both the P and the also called by the V commands EVP subroutines for transferring the current process in the waiting status.

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Figures 24a through 24d are flow charts of the PMZ subroutine for Transmission of a message without entering a queue in a "semaphore".,

Figures 25a through 25i are flow charts of the V command used for a "semaphore" is used if the SCT field of the "semaphore" is negative,

Figures 26a through 26j are flow charts of the V command used for a "semaphore" is used if the SCT field of the "semaphore" is positive,

Fig. 27 is a flow chart of the instruction at the end of the current instruction called "System Event Poller",

Fig. 28 is a flow diagram of the input / output event handler; which is entered by the System Event Poller,

Figure 29 is a schematic diagram of a logical channel table entry and the queues in which the logical channel table entries are used,

Fig. 30 is a flow diagram of the simulated V command shown in FIG is used for a message "semaphore" if the SCT field of the message "semaphore" is positive and no free message chains are available,.

Fig. 31 is a flow chart of the simulated V command shown in the is used for a message "semaphore" if a free message chain has been made available,

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• and a queue of logical channels on one free concatenation "semaphore" (Q / LC / FLS) has been created is, .

Fig. 32 is a flow chart of the simulated V command used for a message "semaphore ¹¹ when the SCT field of the message" semaphore "is zero and a Q / LC / FLS is present.

Description of the Preferred Construction General Discussion

The invention is typically described in one of the following Hardware system structure used that is coordinated by a hardware / firmware / software operating system will. The subsystems according to FIG. 1 are the processor subsystem 101, the memory subsystem 102 and one or more several - up to 32 - peripheral subsystems 103. Das Processor subsystem includes a central processing unit (CPU) 104 and up to four input / output control units (IOC) 105. Each peripheral subsystem consists of a peripheral control unit (PCU) 106, a number of device adapters (DA) 107 and up to 256 peripheral input / output devices 108. The memory subsystem 1o2 consists of., One to four semiconductor memory modules of 32 to 512 kilobytes each.

I. The processor subsystem

In the processor subsystem 101, the CPU 104 performs the basic processing operations of the system and the interface functions with the memory 102. The IOC 105 controls the entire exchange of information between the storage subsystem and the peripheral devices 106.

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A. The central processing unit CPU

The CPU includes a main memory synchronizer 109, a buffer memory 110, various elements constituting the arithmetic unit 111, and additional emulation devices 112. Main memory synchronizer 109 resolves conflicts over main memory usage by the arithmetic unit 111, the buffer memory 110 and the IOC 109. The conflicts are resolved on a priority basis: the IOC has the highest priority level, this is followed by the write memory (from the arithmetic unit) and then the read memory (in the buffer memory), Die The main CPU also contains the address control unit ACU 131, which handles the addressing of the main memory and the associative memory AS 132 controls the one for storing the most recent, currently used addresses in the main memory is used. The buffer memory 110 is a small, high-speed buffer memory that has a selected one Area of the main memory reproduced and via interface functions is connected to the computing unit in order to reduce the average memory access time. During each memory read operation, both the buffer memory and the main memory are accessed. if if the information to be fetched is already in the buffer memory, the main memory read operation comes to an end brought and tapped the information from the buffer memory. Otherwise the main memory 102 is read. Each time this happens, the CPU 104 captures 32 bytes which contain the required information. This information remains in the buffer memory as future memory references. Since the buffer memory is software-transparent, the program that connects the -.- computer to any controls any point in time, does not determine whether the information which it has just processed, taken from the buffer memory or the main memory.

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The arithmetic unit 111 performs the entire data processing and Address generation within the CPU. A typical control store 130 within the processing unit (see brochure entitled "Microprogramming: Principles and Practices" by Samir S. Husson, Prentice KaIl Inc.) contains firmware for initializing the system, for controlling the CPU 104 and IOC 105 and for decryption an instruction set (not shown) Optionally, the control memory can contain scientific instructions, test routines, Have emulation packages or special purpose features that extend the capabilities of the processor subsystem.

Optionally, the CPU emulates other systems that differ from the present system. The emulators 112 are firmware, software, and in some cases hardware components.

B. Input / output control unit

The IOC 105, as part of the processor subsystem, creates a data path between each peripheral subsystem 103 and the Memory subsystem 102. This path enables peripheral commands to be initialized and the resulting data transfers. One IQC can typically control up to 32 channel controllers (not illustrated).

C.Periphe'rie Subsystems

The PCU is in a peripheral subsystem 103 (FIG. 1) a free-standing microprogram processor that powers the CPU 104 by controlling the input-output devices 108 during the input / output operations are relieved. The PCU performs this function by executing commands that are specified in a channel program are included .. For this program

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arithmetic, logical, transfer, shift and branch operations result, which are in the PCU to be carried out. Depending on the type of controlled device, there can be several types of PCUs: Data carriers, bulk (disks) - memory, magnetic tape, communications, etc ..

, The device adapter 107 mediate between each PCU and the devices it controls. Each adapter contains the · to carry out communication with a given Device type required firmware and logic. Depending on the type a DA 107 can control one or more devices.

The major functions performed by a peripheral subsystem 103 are:

1. Conversion of the CPU commands into a series of commands that are accepted by the corresponding peripheral device can.

2. Stacking and destacking of data in the form required for the CPU or the corresponding peripheral device.

3. 'Constant information of the CPU about the status of the subsystem and the devices under its control.

4. Independent initialization and execution of errors and Restart procedure;

5. Performing an on-line diagnosis of a device without doing it to impair the device division capabilities of the connected peripheral processor.

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A PCU resolves conflicts in the main memory with regard to the devices connected to it; however, the IOC resolves conflicts between '' ^:

II. Basic structure of the machine ■.

In this hardware, types tend to have three basic data structures used; Data formats, spftwarez / accessible Registers and command formats.

A. Data formats

The information is transferred between the memory and the CPU in multiples of 8 parallel bits. Any 8-bit information unit is called a byte. Parity Q of the error correction data is also included with the data transfer> are not accessible to the software. Therefore, the term "data" is included in the present Description of the corresponding parity or error correction data the end.

B. Bytes

The bits within a byte are from left to right denoted by 0 to 7. The bytes are processed separately or in groups. Two bytes form a half word, four

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Bytes a wait _? eight bytes a double word and 16 bytes a quadruple word. These are the basic formats for all data including commands.

C. Data structure

All data is "binary" but can be in binary-decimal or alphanumeric data are translated. The data bits are in groups of 4 bits as binary-coded decimal data, in Groups of 8 bits translated as alphanumeric or in groups of 16 to 64 bits as binary digits. the the latter are marked as digits with "sign ■ translated as fixed point numbers or as floating point numbers in binary notation. Any number of people next to each other Bits up to a double word can be processed as a chain. The alphanumeric character set is in EBCDIC shown / ASCII serves as an alternative alternating code.

D. Byte address n

The byte positions in the main memory are starting with 0, consecutively numbered; each number is the address of the byte. A group of consecutive bytes is called a halfword, ' Word, double word or quadruple word structure is considered if the address of the left byte of a group is a multiple of 2, 4, 8 or 16. Whenever a half word, word, double word or quadruple word is structured in this way this unit can be tapped from this address. The position of data in main memory is determined by the data "descriptor" specified to which indirectly during the address development is accessed.

E. Readable registers

The CPU 104 'contains' 33 registers that can be read by the user (Fir :. 1), the contents of which together indicate the status of the CPU. The CPU

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contains four types of registers: (see Fig. 2).

i.General registers

2. Basic register

3. Scientific. Register (optional) 4. Various registers.

F. General registers "■.

The general registers (GR) 201 are used for handling used by binary fixed point digits and bit strings. The CPU 104 typically contains 16 general 32-bit registers, GR O to GR 15. The general registers GR 8 to GR 15 can also be used as an index register. When used as index registers, they are designated with XO to X7: the indexing is carried out using the 32 contained in a register and represented in two's complement 3.2 "whole bit number.

G. Base Register

The base registers (BR) have the same format as the instruction counters, IC and the stack registers 202-203. The base registers are used during the calculation of the address to define part of the memory. There are typically 8 32-bit base registers BRo to BR7.

H. Scientific Registers

The Scientific Registers (SR) are optional equipment for processing floating coefficient binary numbers. There are typically four 8-byte scientific registers, labeled SRO through SR3 are. The scientific registers have the format up to 205 of Fig. 2. ■.

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I. Various registers

The CPU contains five further registers:

. Command counter with format 202 to 203

. Status register with format 207

.. Stack Registers (referred to as T Registers), 202-203

. Address delimitation register with format 206

. Hardware control mask register with format 108.

The instruction counter (IC) - is a 32-bit register that stores the Contains address of the command just executed. The status register (STR) 207 is an 8-bit register that Stores information related to the current procedure, e.g. whether the operation being performed has a Created underflow. Also known as the T register, the stack register is a 32-bit register that contains the index at the top of the stack that relates to the procedure in progress. The one below described stacks create a work zone and a mechanism for storing local variables for Maintenance of the procedure inputs and for information return. The Address Limit Register (BAR) 206 is a 28-bit register which is the lowest absolute main memory address specified that is accessible to the software.

This register is loaded during system initialization and can only be read by the software. That Hardware control mask register 208 is an 8-bit register that stores machine status information.

I. Command formats

There are around 200 commands, although more or less can be used. Each command has one of the four

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different lengths, which always correspond to an even number of bytes. The commands are in sequential Storage locations saved. The leftmost byte address is a multiple of 2 and is the address of the command.

The. eight most significant bits (and in some cases the Bits 8 to 11 or 12 to 15) of a command represent the Opcode, while the remaining bits represent one or more operands. An operand can be a Register identifier, a relocation identifier, an address syllable (logical address), a literal ¥ ert, or a be an immediate literal value. The types and numbers the operands are specified using the command format.

III. System organization A. Job step and task

The work to be performed by a computer system is carried out externally through a series of job steps with the help of an Job control language defined.

A job step is a unit of work that includes hardware facilities assigned. A job step typically consists of several tasks. A task is the smallest unit of custom work, which consists of an instruction flow executed without parallelism.

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B. Processing method

The user-accessible concepts of task and job step are hardware-wise each by a process or a Process group shown. A process is defined as an ordered sequence of instructions that are performed asynchronously by the CPU can be (i.e. several processes can be active and divide the facilities among themselves, at one point in time however, only one process is running at a time). A process group is a set of similar processes that lead to Execution of a job step are required.

C. Process Control Block and System Base

Since the processes can run at different times during their execution without being controlled by the CPU, a memory zone is available in main memory for a process with which the status of the CPU is retained. This status information is used for preconditioning; the CPU used before a process regains control of the CPU takes over.

The memory area allocated to a process is shown in FIG referred to as process control block (PCB) 400. The data contained in a PCB contain the addresses of Memory areas (address space) assigned to the process, the content of all associated registers and the status of the process. Therefore, a PCB serves as a buffer area for starting or restarting a process required information. Each PCB is accessible to hardware and firmware and can be configured with the help of a group of Hardware firmware tables created during system initialization developed and changed during the operation of the system (Fig. 5), addressed by the operating system will.

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There is an absolute main memory zone, which is available as a System base (Fig. 5 and 6) is used. This zone is developed by the firmware and is via the base address register (BAR) 501 accessible, read that, but not can be described. The system base 502 contains a number of system criteria that have the designation (J, P) of the current process. Another criterion in the system base is an index 505 for a Hardware-defined I & en structure, which is stored as J table 503 is known. This table contains one entry for all Job steps available in the system. Each entry in the J table 503 identifies a P table associated with it 504, which is also a hardware-defined data structure. This table defines a process group and contains an entry for all processes in the process group. Each entry in the P table 507 identifies a PCB 400.,

According to FIG. 5, the J table index 505, which over the arithmetic part 506 of the arithmetic unit 111 (Fig.i) was indexed with the J number, access to a J table entry 503. This entry contains a P table index, which, if it has been indexed with the P number via the arithmetic unit 506, provides access to the P table entry 504 allows. The P table entry contains an index 507 for the PCB 400 of the currently running Process. Therefore, the operating system can be used of the contents of BAR 501 can access the active PCB and any other PCB, if the appropriate logical designation (J, P) is given.

D. Memory segmentation

As described here, a multiprocess structure contains many processes in memory at a given time,

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These processes can vary in size and space request. This leads to a memory allocation problem, In conjunction with the operating system (not shown here), the hardv / are solves the problem through dynamic allocation of storage space.

Because of the random access nature of the memory requirements, memory space is allocated in segments of various sizes and memory allocation can be restructured during the course of the process. Therefore, a Process a number of non-contiguous memories Segments are assigned. This memory allocation method is known as segmentation.

The segmentation leads to an additional problem in that the memory addresses are always changed must if part or all of the process is addressed again. To alleviate this problem the system described here uses a technique in which the addresses used by a process are logical and not are absolute main memory addresses. These logical addresses are used to develop the absolute addresses.

Segmentation also enables any process to be based on a system of segment "descriptors" access its own or allocated memory segments. By accessing a segment descriptor, a Process get the address of a segment. The segment descriptors are located in the main memory and are called with Using the operating system.

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The segmentation marks more than 200 million bytes of address space as available to the process. This number exceeds the capacity of the main memory; therefore, a secondary memory (magnetic disk or drum) is used in conjunction with the main memory. The operating system creates the illusion that the actually available memory space is much larger than the main memory. This system is known as virtual memory. IV. Process control and synchronization

The system described here performs multiprocessing operations that are controlled by an operating system, that uses a combination of software, hardware and firmware. The software creates and cancels processes within the system, whereas the hardware and firmware multiplex the processes of the CPU. Additionally guaranteed a combination of software, hardware and firmware die Synchronization between the processes.

Processes are usually, but not always, during the start and end of input / output operations the execution of similar "jobs" and started at other times due to concerns of the operating system and finished. Therefore, it is essential to start and stop similar processes and that between them effectively. the exchange of information taking place a communication system necessary. The hardware system generates internal messages called "semaphores" and which are used as communication links between processes.

A. Process functional states

A process can occur at any point in time of the four possible function states are: Process, Ready, Waiting or Interrupt state. The hardware detects these four possible process states and carries out various firmware procedures in order to carry out a process division.

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to determine changes and those on a process functional status based data structures. The PCB contains a status field which shows the indicates the current status of the process assigned to it.

A process is in the flow state when it is under Control of the CPU is located. This status brings the assignment of an address space (segment table) and a start address for the CPU with it. The CPU then executes commands in the procedure segments of the process. The. Process name J, P (logical address) of the PCB of the currently running process is in the current process word (BAR + 56) stored within the system base (Fig. 6). (Note: the system base shown in Fig. 5 is with identical to that shown in Figure 6; however, some details have been left out).

The ready status is the same as the run status with the exception that the process is not under control the CPU is because it was not recognized by the CPU. A process that is in the ready state is for the CPU on a par with the other ready processes and the ongoing process.

A process is in the waiting status if it only starts after a specific event, e.g. a message can be continued via a "semaphore". A waiting process is not in competition with the CPU, but it can compared to other waiting processes with regard to the necessary incident are in a competitive situation.

An interrupted process is a process that works for one was interrupted by the software for a certain period of time,

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and can be continued later. The decision to have one Interrupting and resuming the process is done outside of the process.

As a result, an interrupted process is inactive and therefore has no information regarding the occurrence of events and do not use the CPU.

A process is interrupted under the following conditions:

1. By executing a "Terminate" command (as a result performing all of its functions).

2. By executing a "Suspend" command through the Operating system.

3. By the occurrence of an exception * condition in which the Control is transferred to the operating system.

B. Process Allocation

Processes can be consciously carried out by one Passing status to another, or, "unconsciously" by the effects of other processes. The one as CPU firmware well-known "dispatcher" controls the transfer of processes from one status to another. The "dispatcher" uses a group of (described later ) Queues to influence the processes that are in the ready or waiting status. Interrupted Processes are controlled by the software.

In FIGS. 6, 8 and 9, a is in the ready or waiting status The process in progress is represented by a PCB and a special queue entry, which is called a process chain referred to as.

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. - 28 -

Fig. 9 contains an exploded view of the contents of the GO segment 802, the process chains 803a-803b and 803c-803g active process and the free process functions 805a-805c. Each process link specifies the process designation (J, P), the process priority and contains an index for the next process chain in the queue. There are different types of queues, such as B. the waiting queue 8O3.a to b, 803e - g and the Ready queue 803c - d.

A hardware device similar to the J-table, known as a G table is known (Fig. 6 and 8) contains the (on the System-level known) indexes for all common segments 802 to 802n. The first element GO, the G table 801, points to the 802 segment which the dispatchers ^ queues contains. A G table index for the G table 801 is located in the system base 502 of Figure 5. According to Figures 8 and The system base also includes an input referred to as the internal process queue word (IPQW) 905 and the "head" 803 identifying the GO segment 802 ready queue 803c-803d.

Therefore, the dispatcher can check all processes that are in the ready state by checking the ready queue 803c-803d check. If the current process changes its status, the dispatcher removes the am Process chain located "head" of the ready queue and uses the J and P designations to access it its PCB. The process defined by PCB will now be the new one active process.

Since more than one process can wait for the same event, there is a queue of processes 803a-803b for all.happenings.The waiting processes are also over

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2A5.653A. '

Process chains 804 (Fig. 8) connected to one another, that are in the GO segment. "Semaphore" 903 (will be later described), contains an index that is the "head" of the queue indicates. A process can wait for a multitude of occurrences; hence there are a number of queues available; a "semaphore" 903, 904 is assigned to each of these queues. The number of in the ready or Waiting status fluctuates dynamically. Therefore, the number of ready and Queues required process chains. This fact poses a memory management problem for the dispatcher on. -

This problem is solved by another queue, referred to as free process chaining queue 805a-c will. This queue concatenates all process chains in the GO segment that are not from the ready or Queues and to expand a special queue can be used by ready or waiting processes. An index 901 for the "head" 902 the free process chaining queue 805 is near the beginning of the GO segment 802 (Figures 8 and 9).

To mark the occurrence of an incident, a process uses two "semaphore" operations. Sends an operation one signal to a "semaphore", the other picks up a signal from a "semaphore". (The send operation will also be executed V operation denotes; the receive operation is called a P operation designated). The send operation enables a process to send data or a signal to the Display the ready status of the data. The "semaphore" stores the signal until another process is ready to tap it. Therefore, the send operation can proceed because it sent the data. Check the receive operation

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_ 30.

a specified "semaphore" and picks up the signal. If a signal is present, the receive operation continues. However, if the "semaphore" no signal is detected, the process proceeds in the ^T & rtestatus. The "semaphore" then serves as an index for the "head" of a queue.

The process remains in the waiting status queue connected to the "semaphore" until another process gives a signal this "semaphore" sends. Therefore a "semaphore" can be a signal hold until this is tapped by a process or. a semaphore can hold a process until a signal is received this is sent.

It is also possible to send messages from a process to pass on to another. A message has the same existing or nonexistent properties like a signal and contains additional information. Part of the information is provided by the hardware and part of the procedure of the process that sent the message. A message contains the process name of the process to be sent. Hence a lot of process information send via a single "semaphore" labeled with the sender's name.

A message ^J ßemaphor "can have a queue of messages awaiting collection by one of the processes. As with signal semaphores rise and fall with the requirements for space and thus provide a Speieher ~ administrative problem. Once again this Problemmit is a queue of These chaining are in a known position in a segment that is easy to find if required and which creates or accepts message chaining.

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Because the "semaphores" and the queues built on them are used by different processes, the entire "semaphore" structure is protected. This is done with hardware and software devices that have access to all Restrict segments that contain "semaphores". Therefore the "semaphores" must be in "semaphore" descriptor segments, some of which may be G-segments (if system communications required are). All G segments (with the exception of GO) are "semaphore" descriptor segments.

Each "semaphore" descriptor contains an index for one "Semaphore". The "semaphore" addresses are developed via a "semaphore" descriptor and thus guarantee one additional protection for the "semaphore". A "semaphore" can logically using a segment number and a relative Position within the segment or directly using the G and D numbers.

Structures of the process - »control block

In Fig. 4 the format of the process control block (PCB) is shown. The process control block 400 is a memory area of main memory in which the process has the CPU status kept. A PCB is addressed as above in connection with Fig.5 "was described. The PCB index 507 (FIG. 5) indexes a byte "0" of the process control block PCB (Fig. 4). It should be noted that the memory positions when operating in a downward direction Direction increase by 4 bytes, whereas they do when proceeding in an upward direction from byte position "0" off, increasing by 8 bytes each time. The memory positions facing down are from 0 as viewed positively, while the upward positions from 0 are viewed as negative. the upward positions behind the PCB byte

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addresses -16 are optionally available and may or may not be integrated into the process control block; positions 148 to 176 are also optional. (Note that the numbers under the memory positions indicate the shift from the reference position Print out "0" of the process control block PCB in bytes and do not confuse it with the reference numbering commonly used to identify parts in a patent drawing). Starting with byte "0" up to, but not including *. Byte 16, are four process nouns PMV / 0 to PMl '/ 3 stored; the length of each process noun PM is 4 bytes. The process noun 0 occupies bytes 0 to 3 and consists of four parts: a capability byte, a priority byte, a status byte and a "Decor" extension byte DEXT. FIGS. 10a to 10d show details of the process noun PM with further ones Details of the capability byte 1001 shown in FIG. 10b are shown. According to FIG. 10b, the first bit corresponds to 1005 the accounting mode bit which indicates whether (or not) time accounting functions for the process be performed.

If the set-off mode bit 1005 is positioned on binary 0 no time-accounting function is performed for the process; however, if the set-off mode bit 1005 is on is positioned binary 1, a time calculation is carried out. Science mode bit 1006 shows when it is at 0 is positioned on that the scientific register of the machine is not saved and that the saving area of the scientific register that is based on bytes 148 to 176 of Figure 4 are not in the process control block PCB is present. When the science mode bit 1006 is a binary 1, it is scientific Optional equipment available and used in the process; the savings area of the scientific registers becomes,

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if necessary, to keep the contents of the scientific Register used. Bit 1007 is NFS (not functional).

The remaining bits of the capability byte are set to zero.

Details of the priority byte 1002 are shown in Figure 10c According to "Fig. 10c, the first 4 bits 1008 . of the priority byte 1002 for determining the priority level of the process control block, PCB assigned to this given Process used. Each process is assigned one of the 17 priority levels that are used to order competing processes can be used, i.e. (a) to select the one to be performed Process from the prepared processes, (b) for classification of processes in queues. Take the priority levels from 0 to 15 and for a certain priority level the FIFO rule (first in first out, first in, first out) used. The next four bits 1009 of priority byte 1002 are zeros. .

Details of the status byte 1003 are shown in FIG. A status byte is used to generate information regarding the process associated with the process control block PCB 400 used.

The active field bit A 1010 is positioned on binary 1 if the process is activated. The interrupt field S 1011 "is positioned at binary 1 when the process is interrupted is. The sub-status field SS 1012 is a two-bit field and defines the following sub-states of the process: (a) with binary 00 the process is inactive; (b) with binary 01 the process waits in the ready process queue (Q / PR / RDY), (c) at binary 10 the process is waiting on one "Semaphore" in a "Semaphore" queue (Q / PR / S or Q / PR / FLS); (d) at binary 11, the process is run by the processor

• 5Q8834 / 083G-

carried out. The Central Operating Field (MOI) 1013 becomes positioned on binary 1 when an "interrupt" occurs and is monitored while a command is being carried out, i.e. before the end of the process. The bit "extended decor mode" EXTD 1014 is positioned at 1 if the Process operates in an extended decor mode which is an emulation mode of the machine. Bits 1015 and 1016 are set to 0. The fourth byte of the process main word PMW 0 contains the decor extension number and is used when the system is in emulation mode. (If equal to Eigen mode).

The process noun PMV / 1 is stored in bytes 4 through 7 of the process control block PCB. Details of PMW 1 are shown in Fig. The status byte 1016 is the first byte in PMW 1 and stores the content of the status register. The multiprocessor byte MP 1018 is in a Multiprocessor architecture matters, otherwise this is Field is zero. The second and fourth bytes of the process noun 1 represents the MBZ fields 1017 and 1019, which must be logic zero in normal operation.

The main process word PMW 2 occupies bytes 8 to 11 of the Process control blocks and is shown in more detail in Fig.10f. 10f, the field contains from bit 4 to bit the local designations SEG, SRA 1021 of the "semaphore" to which the PCB is chained when the process is in the wait state or to which the PCB was chained while waiting. The exception class and type field 1023 contains the class and type when a process interrupt exception occurs occurs and the field with bits 0 to 15 is (NFS) 1022 (no function). When one process another Has status than that mentioned above, bits 0 to 31 are meaningless.

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The process noun PMW 3 occupies bytes 3 to 15 in PCB 400 and denotes a Decor extension table. In Fig.10g is PMW 3 described in detail? the DETSZ field 1024 is there the number of the entries in the table, and if this field Is zero, the process cannot do a decor expansion.

The DETE field 1025 is the absolute address of the decor extension table in Units of 16 bytes; it only has meaning if DETSZ is not zero. The Decor extension table consists of DETSZ entries. Each input is the size of one byte. The DEXT-Singabe the table indicates the ability of the process to DEXT in Decor expansion mode to work. If the DEXT byte is zero, the decor extension number is DEXT not allowed; on the other hand, if the DEXT byte is "1", the decor extension number is DEXT permissible. DEXT values other than zero and 1 are not permissible (see Fig. OK, DEXT number 1004).

Bytes 16 to 23 of PGB 400 contain 2 address space words, ASV / 0 and ASW 1, and each ASW contains an index for one Matrix of segment table words. Both ASW 0 and ASV / have the same format shown in Figure 10h. The size the matrix of the segment table words is defined by the number of the segment table words in a matrix and typically contains 7 for ASW 0 and 8 for ASW 1. The STWSZ field 1026 indicates the size of the matrix of the segment table words. The segment table word matrix field STWA 1027 contains the absolute address STWA of the matrix in units of 16 "bytes, i.e. the absolute address of the matrix is 16 times STWA in bytes. -

Bytes 24 to 27 of the PCB contain an exception word EXIi, which is described in more detail in FIG. The exception word contains -an index (SEG, SRA) 1029 for an exception-

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class table, which indicates the activity, which accordingly a process exception according to its class, 'the one in the process noun PMW 2 is stored, must be carried out (see Fig. 10f). The 14BZ field 1028 of the exception word EXV / must Be zero.

The stack word contained in bytes 28 "through 3T of the PCB SKV / contains the value of the top of the T-register of the stack of the procedure if the procedure does not run (detailed Description see Fig. 10j). According to Fig.10j define the bits 0 and 1 the TAG field 1030. TAG identifies by its content the "Descriptor" type and must be zero for SKW. Bits 2 and 3 of the SKW word contain the ring field 1031, which is the segmented address of the stack for protection purposes assigned ring number, which must be zero in this case. Bits 4 to 31 contain the segment number SEG and the relative segment address SRA 1032 and form a field for identifying the in a segment table and the relative segment address within the segment described segment. The stack word SKW becomes every time then complete when the process has reached the functional status leaves. It is used to refresh the contents of register "T" whenever the processing of the process begins. In this last case it is checked that TAG 1030 and RING 1031 are at zero; otherwise, an illegal PCB exception occurs.

Bytes 32 through 35 of PCB 400 contain the instruction counter content word ICW, which is sometimes referred to as ICC. Refer to Figure 10k for details of the command counter word ICW shown; the TAG field 1033 must be 00 (i.e. values other than zero in the command counter are illegal). The current ring field 1034 occupies bits 2 and 3 and provides the sequential ring number of the process to be carried out in order to

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define the access rights to the main memory. Bits to 31 indicate the segment number and the relative segment address (SEG, SRA) '1035 which define the address of the next instruction to be executed.

The MBZ field in bytes 36 to 39 must be zero (it is closed note that the MBZ field always shows a field that is zero have to be). The MBZ word is tested every time, starting with the designation J, P, an additional operation to the PCB is carried out. If the word is not zero, an illegal PCB exception occurs.

The stack base words SBW 0-2 occupy bytes 40 to in process control block 400. These words are the same Format which is shown in more detail in Fig. 101. They are used during batch operations and every time You must use your TAG field 1036 and your RING field 1037 zero otherwise an illegal PCB exception will occur. Bits 4 to 31 contain the segmented address (SEG, SRA) 1038 of the first bytes of the stack segment, each for ring 0, 1 and 2.

Bytes 52 through 83 of process control block 400 are set represents a space reserved for the base register buffer area (8 words). Bytes 84 to 147 represent represents the buffer area which is used for buffering the values of all general registers (16 words). Bytes 148 to 179 represent the buffer area which is used to buffer the contents of the scientific Register (8 words) is used.

In PCB 400 there are 5 double words above the PCB zero address generated for offsetting purposes. These words are located in PCB addresses -8 through -40. Every word includes in his

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first 52 bits one expressed in microsecond units Time or time interval; bits 52 to 63 are padded with zeros. The remaining deceleration double word RTO (the first 8 bytes above zero in the PCB) contains an indication of the time currently used by the processor for a process is expended before a timeout exception occurs. The RTO word is completed as follows: each time the process leaves the functional state, the value of the process timer is stored in the RTO word. Every time the process goes into function status, the value of the process timer is loaded from RTO.

The runtime offset word RUA (byte address -16) is a time counter that indicates the total amount of processor time that a process is in the functional status used. The accumulated time is the time currently being used by the processor for the process only Time. The RUA word is updated as follows: every time the process leaves the functional state, the Read the value of the process timer PT. The difference in the contents of RTO and PT is added to RUA (then the PT value stored in RTO). It should be added that the time during which the trial is suspended does not is counted. The RTO and RUA words are only completed when the offset mode bit is at zero. the CET, RTA and WTA words (described later) are only used then supplied to the process control block when the accounting mode bit of the process main word PMW 0 is 1. The words will only completed in this case.

The waiting time accrual word WTA, located at byte address in the PCB, is a real-time counter that indicates the total amount of real-time that the process is in the V / arte state has spent. The WTA word is completed as follows: every time the process leaves the wait status, from

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a time of day clock (not shown) the time of day value TOD read, and the value TOD minus the value of the CET word is added to the WTÄ word.

The ready-time offset word in PCB byte address -32 is a double word designed as a real-time counter that indicates the total amount of real-time that the process has spent in the ready status. The RTA is completed as follows: every time the process exits the ready status, the time of day value TOD is read and the contents of TOD minus the contents of CET are added to the RTA. ,

The current input time double word CET is located in the PCB byte address and contains the time of day at which the process went into one of the following states: Ready, Waiting, functional and interruption status.

Structures of the system base:.

The format of the system base 600 is shown in FIG. The system base is located in the absolute main memory, it is developed by the firmware and is via the address limit register (BAR) that can be read but not written to. The address delimitation register BAR is located under a main storage zone, the. is reserved for hardware and separates it in memory for the hardware reserved zone of the system base 600. Referring to Figure 6, the system base 600 contains a number of System criteria that contain the process designation (J, P) of the currently running process. From the logical Name of the process, J, P becomes the absolute address of the corresponding process control block PCB. The size and address of the J table are determined by the content of the

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Table word J (JTW). This word is in the address specified by the BAR register. The format of the JTW is shown in Figure 11a. The Great (JTSZ) 1101 of the J table 1204 in Fig. 12 specifies the number of entries in the J table 1204, which can have up to 255 entries. the Size JTSZ 1101 is an 8-bit positive whole number; an exception "Outside the J table" occurs when J is equal to or greater than JTSZ. The absolute address of the J table 1204 is obtained by multiplying the J table index 1102 by 16 The J table 1204 contains the J table entries the format of which is shown in more detail in FIG. 11b. Every J table entry defines the absolute address of a P table 1205, which results from the multiplication of the P table index 1104 with 16 results. The size (PTSZ) 1103 of the P table indicates the number of entries in the P table. The size PTSZ is a positive 8-bit integer, which can typically vary between 0 and 255, and the number of entries in the P-table indicates. An "outside of the P table" exception occurs when P is equal to or greater than PTSZ. Every input of P table 1205 defines the absolute address of a process control block (PCB) 1206 by multiplying the Process control block index 110.7 with 16. A presence indicator P 1105 indicates when it is positioned on binary 0 is, the absence of a PCB 1206 and the presence of a PCB if it is positioned on binary 1. (If the presence indicator P 1105 is at zero, an exception "free P-table entry ".) Bits 1 to 7 of the P-table indicator (Fig.11c) must be zero (MBZ 1106, otherwise an exception "illegal P-table entry" occurs.

This is located on the BAR address plus 4 of the system base 600 Format byte of a G table word (GTV /) that is detailed in Fig. 11d is shown. The size and address of a G segment table 1212 (Fig.12) is based on the content of the G table word

& Ö.983W083Q

The size (GTSZ) .1108 of the G table 1212 defines the number of entries ii the G table, which is typically up to 255; Inputs can be. The size GTSZ is a positive whole 8-bit number; an exception "outside the G table" occurs if the G number is the same ._. or greater than GTSZ. The absolute address of the G table 1212 is obtained by multiplying the G table index 1109 by 16. The format of the _: G table entry corresponds to a double word (8 bytes) and, as a G segment ■. "Descriptor" referred to. The format of the G-segment "descriptor" is shown in detail in FIGS. 11c and 11f. All G-segment "descriptors" are direct and so must be indirect. Bit I, 1111 must be zero, otherwise an "illegal segment descriptor" exception occurs. The presence indicator P 1110 is a one-bit field which / when positioned at binary 1 indicates that a segment has been defined in main memory for the segment number to which this "descriptor"corresponds; if, on the other hand, the indicator is cleared to zero, no segment is defiled and a reference of the segment "descriptor" triggers an exception "missing segment". The available bit A 1112 is a one-bit field which indicates whether the segment is available or not; it is only checked if this segment is defined (ie P equals binary 1) and is ignored otherwise. The flag U 1113 used indicates whether or not an access operation to the segment has been performed. If the U-bit is positioned to binary, no access operation to the segment has occurred; if, on the other hand, the U field is positioned on binary 1, an access operation to the segment has taken place. The loading. Written marking field W 1114 indicates whether the data in the segment has been changed. When W is binary zero, there has been no change to the segment data; on the other hand, if W is binary 1, the segment data has been changed. Of the

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Gate indicator GS 1115 of a G segment "descriptor" must must be positioned on binary 01, otherwise an "illegal segment descriptor" exception occurs. The reason for this consists in the fact that a G-segment, with the exception of the GO-Seg, ments, always contains semaphores (although not the opposite applies, i.e. it is not necessary that all "semaphores" are in a G segment) and that the commands require the binary value QI of the GS code for "semaphores". the absolute base address of a segment 1214 is in the G-segment "descriptor" defined by the 24-bit base field 1116 of Figure 11e; the content of this field is used to achieve the absolute address multiplied by 16. The second word of the G-segment "descriptor" of FIG. 11f occupies the bit positions 32 to 63 in G table 1212.

The RS.U TeId 1117 (bits 32 to 39 ^> is reserved for software use and is generally ignored when used as a G-segment "descriptor" is used, as is the case here is. The MBZ field 1118 must be zero, there on the other hand a Exception "illegal segment" occurs. Since the MBZ field 1118 occupies bit positions 40 to 51, it sets the SIZS field 1119, which is the field for a small segment SIZE; therefore all G-segments must now belong to the "small segments" type.

The segment SIZE 1119 is a positive whole 12-bit number. The number of bytes in the segment is equal to i6x (SIZE + i). if If the 12-bit field is zero, the segment size is 16 bytes. Therefore, the segment size of a G segment 1114 cannot exceed 2 bytes (small segments).

In Figure 6, the system base 600 is with 9 system exception cell words shown, which are located between BAR plus 8 and BAR plus. That. The format of the system exception cell words is EXC shown in Fig.11g. Because "semaphores" are used to transmit messages related to certain procedures the indexes for these "semaphores" are in nine memory positions,

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if a Svstem * exception occurs. Any of these positions is referred to as a system exception cell, one for each system exception class. The MBZ field 1120 must be "binary zero, otherwise a system check (check) occurs. Each Exception cell (EXC) always contains the system designations G, D 1121 and 1122.

The channel exception cell located in BAR plus 44 of the system base 600 has a format that is similar to the system exception cell already mentioned, and the system designation GD a "semaphore" that is used to transmit messages used for certain processes when a channel exception occurs.

An internal processor queue word IPQW begins at BAR plus 48; Details of its format are shown in Eg.11h. As in Eg.9, the IPQW word identifies with the reference numbers 905 and 803C show the "head" of the queue of ready processes (Q / PR / RDY). The queue. of the ready-to-call processes (Q / PR / RDY) links all processes, that are in the ready state. On this queue refers to the "head" of the Q / PD / RDY field 1124 (Fig.Hh) of the IPQW word by marking the top of the queue of the ready-to-call processes. The "head" of Q / PR / RDY field 1124 contains a 16-bit positive integer, which represents the shift from the base of G segment number 0, called the GO segment, to the first byte of Q / PR / RDY. When this Q / PR / RDY bit field is zero, the ready queue becomes Considered empty. "The MBZ field 1123 must be zero otherwise a system check will occur.

With BAR plus 52 of the system base 600, the storage is the Initial and current retry counts shown, the format of which are shown in detail in Fig.11i. The NFS field 1125 is a non-functional one Memory field that is not used by the system base. The initial retry count field 1126 and the

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Current attempt-retry count fields 1127 are used to control the number of automatic command repetitions that occur before a machine error occurs Machine Fault Exception Throws. They are set by a reset count command (not shown) loaded with the same number.

The current process word (RPW) shown in Fig. 11j is stored in BAR plus 56 of the system base 600 and is used to store the designation of the current process, and in the case of a monoprocessor architecture, used to store the priority. The NFS fields 1128 and 1131 are non-functional memory fields and can be used by any facility for any purpose will; however, they are generally not used by the system base. The priority level of a running process is saved in the PRI field 1129. In the AB field 1130 is an asynchronous trap bit is stored; on the other hand, the asynchronous jump ring is stored in the ARN field 1132.

The logical designation (J, P) of the current process in the case of a monoprocessor architecture is in the J, P field 1133 saved.

An absolute table index word shown in FIG. 11k is in the system base with BAR plus 60 and is used for initialization during the initial system loading process of the absolute addresses in the initial system loader (ISL) by adding the contents of BAR with all absolute addresses used in the ISL program. The absolute table index 1135 defines the position of an absolute table (not shown). The size of the absolute table is shown in ATSZ field 1134.

The CPU serial number word shown in Fig. 111 is an in BAR plus 64 located 4-byte word that contains the serial number of the CPU in the CPU serial number field 1136.

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An upper one shown in FIG. 11m. The main memory delimitation word is in BAR plus 68 and. indicates the upper limit of the main memory by automatically generating the absolute address of the first unavailable quadruple word. It also expresses (in bytes) the size of the available main memory.

At BAR plus 72 there is one shown in Figure 11m Word with which the channel number of the initial system charger ISL (CN). 1140 and the channel number of the hardware device (CN) 1141 can be generated. .

The type and sub-type of the device used in the computer system are identified by the hardware device type word (Eig.11o). described in fields 1143 and 1144; the RSU-field 1142 is hereby ftwarezwecke for S _o reserviert.Dieses word is in the system based at BAR plus 7 &. A similar word shown in FIG. 11p with a similar type format contains the type and sub-type of the device used during the initial system loading process. This word can be found at BAR plus 80.

When the restart button on a computer is pressed, a simulated V operation is performed on a "semaphore" and the ready status is entered. A script for this "Semaphore" is located at BAR plus 84 of the system base 600 and is referred to as the restart cell word; its format is shown in Fig. 1Iq. Its format is that already described System exception cell similar and contains the system designation G, D of a "semaphore" in each case in G fields 1149 and D field 1150. The "MBZ field 1148 must be zero."

If the computer system has more than one processor, in the system base at BAR plus 88 a word for the multi-

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processing extension generated. Details of this word are shown in Fig. 11r.

Usage examples of the system base and the process control block

Figure 12 shows an example of how the system base is used in conjunction with the process control block can to do an addressing and an access operation to one User segment, a system segment or a V / art queue of process ready segments (Q / PR / RDY). The main memory 1200 has a part 1203 for hardware purposes is reserved. An address limit register BAR 1202 disconnects. the system base 1215 from the one reserved for hardware purposes Part of the memory 1203. The address delimitation register BAR 1202 is used for addressing fields in the system base 1215 by adding the contents of the address delimitation register with the shift in 4-byte units of that in the system base required field is used. This address now marks the first byte of the field in the desired system base. " In Figure 12, BAR 1202 identifies the J table word (JTT, '/). The J table word already mentioned has an index that identifies the J table 1204. By indexing The J number shown in Fig. 5 becomes a J table entry 1216 achieved.Bsi the J table entry indicates a P-TabaLenindex the absolute address of the P-Table 1205. Through Indexing of the P number (see Fig. 5) within the P table 1205 the absolute address of the process control block 1206 is obtained.

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As already shown in process control block PCB 1206, there are two address space words ASW 0 and ASW 1. The more significant Bits of the segment table number field STN in the base register 1201 become one of these for access Address space words used; in this case ASVi 1, whose Segment-TabellerL · Word matrix STA-Index the segment table word matrix STWA 1208 identifies. Together with the segment table number STN of the base register 1201 one of the 8 segment table words in STViA is accessed, which is one of the 8 segment tables Mark 1210.

The segment table entry STE is then taken from the base register 1201 carried out to one of 256 entries in the segment table 1210, in which there is a segment descriptor is to be carried out. The segment descriptor is now used to access a user segment 1211.

To access a system segment 1214 that is used for Storage of "semaphores" is used, a G table word is used GTW used in the basic system 1215. The address of the G table word is obtained by adding the shift of the G table word in the system base to the address delimitation register BAR 1202 is achieved. (See Fig. 6). The G table word GW contains a G table index that contains the G table 1212 indicates. Using one available for the system G number and indexing in the G table is based on a G segment descriptor which is used to address a system segment 1214.

Similarly, the system base 1215 becomes the access point used for the queue of the ready processes (Q / PR / RDY) 1213, in.dem addresses an internal processor queue word IPQW

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which indicates the Q / PR / RDY segment T213. Control unit

13a to 13c show details of the control unit The control unit is shown, although it is shown separately from the central processing unit CPU is actually part of the CPU and consists of a control storage unit CSU 1301, a control storage interface adapter CIA 1302 and the associated sub-units, the control store loader CSL 1302 and the Control and charging unit CLU 1304.

The control storage unit CSU 1301 "receives microinstructions, from the control store loader CSL 1303 via the control and charging unit CLU 1304 and the control store interface adapter CIA 1302. Under normal operating conditions, the Microprograms are loaded from an external source during system initialization and become a permanent one Control function of the machine. The control store unit CSU 1302 can, however, be reloaded and initialized in a manner that a multiplicity of operating modes of the central processing unit CPU 1306 arise. The following Operating modes of the CPU are available under the control of the CSU 1301: (a) self mode; (b) Emulation mode f (c) simultaneous intrinsic and emulation modes; (d) Diagnostic mode. The ability is due to in the CSU existing microinstructions possible; these are the source of the micro-operations that control the functions of all the others functional CPU units, such as the emulation unit 1316, the arithmetic logic unit ALU 1317, the command acquisition unit IFU 1318, the address control unit ACU 1319

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and the data flow control unit DMU 1321 can be used. Together with the central processing unit CPU 1J5O6 are the general registers 1307 already described, the basic registers 1308, the scientific registers 1309, the T registers 1310, the status registers 1311, the command counter IC 1312 and the hardware control mask register 1313 pictured. -

Typically, the control store unit CSU 1301 is a programmable one made up of bipolar integrated circuits gK read-only memory (PROM) with read / write random access memory (RAM) is connected. It has a typical read cycle of 150 nanoseconds and one write cycle of 450 nanoseconds. Each position of the control store stores an 84-bit microinstruction word (which will later be completed described) and each microinstruction word controls a CPU cycle. When a position of the control memory of the control memory unit CSU 1301 "is read, the content of which is decrypted by micro-operation decoders, which in turn Generate micro-operation control signals that each trigger a ^ specific operation within the CPU (will described in detail later).

By combining positions within each microinstruction word (will be described in detail later), control store sequences are generated that perform a specific CPU operation or perform a command. When a command is triggered by the CPU, certain bits used within the operation code to define the start sequence of the control memory. Checking certain Flip-flops (not shown) that are activated by the command decryption functions be positioned or deleted, allows branching of the control memory, if necessary to a more specific sequence.

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The control store interface adapter CIA 1302 carries out an information exchange with the control store unit 1301, the data flow control unit CMU 1321, the address control unit ACU 1319 and the arithmetic logic unit ALU 1317 in order to enable the function of the control store 1333 from FIG. to control 13 "b. the CIA 1302 includes the logic for control store address changes, checks, error checks and the hardware address generation the hardware address generation is generally used rler to develop start address of error sequences or for the initialization S _e frequency. .

The data flow control unit DMU 1321 forms the interface. between the CPU 1306 and the main memory and / or the buffer memory shown in FIG has the task of determining which unit contains the information required by other units and to send this information to the CPU registers at the right time. The data flow control unit leads also perform masking functions during partial write operations.

The command acquisition unit IFU 1318 has interface functions with the DMU1321, the ACU 1319, the .4LU 1317 and the CSU 1301 connected; it is responsible for the constant supply of the CPU with commands. The command acquisition unit holds the next instruction in its registers before the current instruction completes. To enable this capability ^ is the command acquisition unit IFU 1318 has a 12-byte command register (not shown), which is normally the Contains more than one command. In addition, the IFU, under the control of the CSU, calls information (commands) from main memory before the instructions are actually needed

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will; therefore, its 12-byte command register is always up The commands are usually grounded with help unused memory cycles are pre-tapped. The command acquisition unit continues to decode all commands and informs the other units of the length and format of the command.

The address control unit AGU 1319 performs with the IFU, ALU, DMU and the CSU exchange information via the CIA by. The ACU 1319 is responsible for all address developments in the CPU. All ACU operations, including Transfers to, from and within the unit are controlled by the CSU micro-operation and logic in the unit, The normal functioning of the ACU depends on the address types in the commands and not the command types. Depending on the address type, the ACU can perform different operations for all Carry out addresses in the commands. The ACU still contains an associative memory 1319a, which is typically the base address of the eight memory segments currently in use together with their segment numbers. Every time when a memory recall is made, the segment number is checked against the content of the Associative memory to determine if the base address of the segment has already been developed and saved is. If the base address is in the associative memory 1319a is located, this address is used in the absolute address expansion and takes a considerable amount of time saved. The base address is not in the associative memory 1319a, it is accessed by accessing the main memory tables developed. However, after the segment's base address has been developed, it is stored in the associative memory along with. the segment number is saved for future reference. .

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The arithmetic and logic unit ALU 1317 has interface functions connected to the ACU, IPU, DMU and the CSU. Their main function is to carry out the CPU required arithmetic operations and data processing operations. The operations of the arithmetic logic unit are entirely of micro-operation control signals which are supplied by the control storage unit CSU 1301.

With the ALU 1317 and the CSU 1301, the "scratch pad" is a storage unit LSU 1315 (sometimes referred to as the local storage unit). It typically exists from a solid-state memory with 256 storage locations (32 bits per memory location) and the selection and read / write logic for this memory. The "Scratch Pad "memory 1315 is used to store CPU control and maintenance information. Additionally included the "scratch pad" memory 1315 working positions, which are mainly used for the temporary storage of operands and partial results are used during data manipulation. Furthermore, an auxiliary memory 1317a is connected to the ALU 1317, which are typically made up of 64 flip-flops for storing various operating states of the computer system.

The CPU also includes a clock unit 1320 which mainly consists of two clock systems in one: the first clock system generates the timing for the control interface adapter CIA 1302 and the second clock system generate the timing pulses for the operations of the functional Unit within the central processing unit.

In Figure 13c, the format of the control store word is 1325 shown. The control memory word is typically 84 bits and is divided into six main fields:

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a. Sequence Type Field 1325 (3 bits);

b. branch and / or micro-operations 1327 (23 bits); c. constants generation and designation 1328 (14 bits); d. data on bus 1329 (8 bits);

e.MicroOperations 1330 (32 bits); and a.

for check 1331 (4 bits).

The 3-bit · E field of the control memory word 1325 is used as a Sequence control field used. There are typically 7 different ones Sequence types and one for the present computer system reserved type. Referring to block 1335 of Figure 19b, the branch field becomes A, B, C, D and L of microinstruction 1335 used to generate the next address if the E field is binary zero, 1, or 2. The first 6 bits of the KS register 1337 are used in conjunction with the B field; this results in a C-test, the D-test results and the L field generate the next address of the next Microinstruction, which is now in the address register KS 1337 is transmitted. If the E field is positioned at binary 4 (see block 1335), the next selected address will be tapped from interrupt return register KA 1339. The address stored in the ΚΑ register is the one generated by the next address generation logic when the hardware interrupt occurs. If the E « Field is positioned at binary 5, a branch is made to initialize a partial return from a microprogram subroutine used. The contents of the return register KR 1346 will be next, if this is used Control store address used. The return register 1346 is loaded by issuing a control store instruction which is the current one in KS register 1337 plus 1 Control store address from incrementor 1338 into KR register 1346 loads. A Uin level nesting subroutine is via the KT return branch register 1347 available.

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Every time the KR register 1346 is loaded, the old contents of the KR register transferred to KT register 1347; every time a microprogram return is called, the contents of the KT register are transferred to the KR register. The Nesting Subroutine Facility the third level is generated by KU register 1340; and the fourth level nesting subroutine means is generated from KV return branch register 1349. Y / if the E field of the control store word is positioned on binary 6 istj is the next addressed control store word equal to the current address contained in KS register 1337 plus 1 in incrementor 1338. If the e-field is positioned on binary 7, the CSU 1301 goes into diagnostic mode and the next address is that current address plus 1.

In addition to the sequence control of the branch to the next continuous memory address, which has already been described above and has been shown in block 1335, a hardware-generated sequence control is carried out in block 1336 of FIG. (Note: Blocks 1335 and 1336 are actually Hardware registers designed to take the various forms that microinstruction words take can, can capture). The hardware-generated branches are skip conditions (such as errors, initialize, control memory scanning, etc ....), which suppress the E field and a fixed address in the address register KS 1337 of the control memory. The branch is made by setting an interrupt line to logical 1 (not shown) during a clock period and storage of the address generated under the control of the E-Field would be, in the KA interrupt return register 1339. In the The control memory address register is a hardware-generated one

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Hies; =! -

Transfer address. Certain hardware and firmware generated Interrupts take priority when the interrupt block flip-flop (not shown) prevents additional interrupts in their class until the interrupt condition is satisfied. A firmware micro-operation is for the controller of clearing the interrupt block flip-eFlop for those Sequences available that are under firmware control. Generate those sequences that are under hardware control automatic deletion of the block flip-flop at the end the sequence. In this category, listed according to priorities, the following conditions exist: (a) load control memory; (b) scanning the control memory; (c) hardware failure; (d) software failure. The remaining Hardware conditions do not set the interrupt block flip-flop, however, cause immediate action to occur when they are generated. In this category are, according to Priorities listed, the following conditions exist:

(a) initialization; -

(b) soft clear;

(c) Entry of maintenance desk;

(d) Enter maintenance channel;
(e.) Hardware issue.

An initialization signal forces the CSU 1301 to branch to binary address 0, to delete errors that can be reset by hardware and to carry out a Control store load operation followed by a hardware controlled control store scan sequence. The initialization signal also carries out the system initialization. A soft clear signal forces the CSU 1301 to branch to the binary address 0 to delete 'hardware resettable errors and resetting of the interrupt block flip-flop. A maintenance desk input signal is forced the CSU for branching to the CSU set (not shown on the address switches of the maintenance desk) Address. ~ "

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A maintenance channel input signal forces the CSU to branch to an address that has the (not shown) Maintenance channel is generated. The address is loaded from the QMB 1344 maintenance bus, which is part of the of the maintenance channel and is right-aligned. A hardware output signal causes the CSU to branch to the. Binary address 2. This sequence is used as a communication facility used. At the end of the sequence, an E-Field ^ branch is output with the E-Field a return initiated.

A control store load signal forces the CSU to branch to binary address 0. It also switches the CSU read cycle flip-flop (not shown) and the system clock 1320 and it positions the CSU in the loading state. In the loading status, the CSU can from the control store loader CSL 1303, IOC 1305, main memory 102 or maintenance desk 1355 are loaded from v / ground. At the Load from the CSL, an automatic scan is generated at the end of the load operation. When the load operation is done from some other medium, scanning can either be done by generating a micro-operation signal or by setting the sampling switch on the maintenance desk. Forced a control store scan signal the CSU for branching to a binary address 0. A control memory rather- scanning is in progress for the duration of the Sequence under hardware control. During the scan, the system clock 1320 is turned off and therefore no commands or tests are executed. At the end of the scan sequence, the hardware transfers the contents of the interrupt return register KA to the address register KS, the system clock is switched on and the control is sent to the Firmware returned.

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A hardware error signal triggers a branch in the CSU to a binary address 4. In normal processing mode, an activates the in any functional unit CPU detected hardware error a hardware error line (not illustrated). The generated control store sequence checks the system status in order to carry out the Determine action. In diagnostic mode, error conditions that can be detected by hardware are for the microdiagnostics accessible. The microdiagnostics monitor the activity to be carried out. A software error signal on the other hand, causes the control memory to branch to binary address 1. This address is the starting point of the software error reporting sequence that is under microprogram control.

In Fig. 13c the E field 1326 is shown: A 3-bit field, which, as already described, is used for the branching code. The branch and / or micro-operation field 1327 consists of the fields A, B, C, D. and L (also shown at block 1335 of Figure 13b), of which the A field contains the six upper bits of the next address, the B field the middle 4 bits of the next Address of the masking field of the 64-tfeg branch, the C-field is a 6-bit test field for one of 64 tests, the D-field is another 6-bit test field for one of the 64 tests and the L field is the least significant bit. The K field 1328 is a 14-bit field, 6 bits of which are for the constant field can be used, 4 bits are used for a constant or control field and 4 bits are used for a control field for a constant. The data-to-bus field 1329 exists from the QA field, which has 4 bits for controlling information from the QA part of the QMB bus 1344 and the QB-Field has 4 bits for controlling information

50983A / 083G

in the QB part of the QMB bus 1344. The F field 1330 is a 32-bit field encoded to generate micro-operation sub-instructions. The P field 1331 consists of four, bits reserved for test purposes.

During operation, the microinstruction words are stored in the control store array 1333. While the control store matrix is addressed by the content of the KS address register 1337 during a function cycle. this causes the content of the position specified by the address to be transferred to the group of read memories circuits 1357. Parts of the word contents of the read memory circuits are distributed or transferred to memory registers located within all functional units of the CPU. Each functional unit includes Decoding logic to generate the required sub-commands, the sram control store word under Control specified by the system clock. Generally, the decoding occurs within each Functional unit of the CPU and not centrally. This is done in order to reduce the decoding time to a minimum and the number of cables that would normally be required to carry command signals when decoding would be carried out centrally to decrease. Additionally · the decoding is done within each unit to avoid timing problems which would result from the difference in cable delays. Continue to need through the Decryption of sub-commands in each unit, those signals that are specific, within the functional unit represent existing conditions and are required to generate certain sub-command signals, not to the CIA unit 1302 returned to ground.

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In Fig. 13t) a typical decoding unit 1359 is shown, which takes up various fields of microcommand words and generates the micro-operation signals a, c, c, d, ... q, r. A typical 1359 micro-operation decoder receives commands from a micro-iJort. The field of the microinstruction word is decrypted and s, sets one of the different lines s, t, u, ... y, ζ to logical 1. Through an impedance-related coupling of predetermined control lines with lines s to ζ at points c ^ ß, γ ..ψ, ω formed a matrix. When the field of a microinstruction is decrypted, one of the lines s set to logical 1 up to ζ. According to the black ones marked in the matrix with the Greek letters α to ω Points that represent the impedance coupling between two groups of lines are all electrical signals that any of the horizontal lines are coupled through to one of the vertical lines a through r in which an impedance coupling (black point) is indicated. Each of the vertical lines a to r can now be fed to one of the AND gates 1360 to 1365 as an input. Other input signals can also the AND gates I36O to 1365 with inclusion of the timing signal t_ at the central timing unit are fed. Whenever a timing signal t_ becomes logical 1, those gates for which all other input signals are logical 1, enabled and generate microinstruction signals for defined functional units within the CPIi-. For example, if a command 1341 is decrypted by a read memory circuit 1357 and a horizontal line is "1", the vertical Control lines a, b, c and q are set to logical 1 and AND gates 1360, 1361, 1362 and 1364 are enabled, when the timing signal t_ is sequentially fed to these gates. The combination in which the vertical control lines

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are coupled to the horizontal control line at different points marked with the Greek letters abisojgekzeichen, now represents a permanent switching matrix for the generation of micro-operation signals for the central processing unit CPU, which thus the functional units within the central processing unit with the help of the control memory matrix Controls microinstructions supplied in 1333 _; Therefore, permanent firmware with a changeable structure can be built into the machine of this invention by merely specifying the micro-operation sequence that is to be available as the capability of the computer system.

Under normal conditions, data is grounded via the CPU write data register, this is also known as the local register YO 1343 is known, written into the control store matrix 1333. The CIR / CSU Data is supplied via the maintenance bus QMB 1344, which is provided by the local Storage register YO 1343 are temporarily stored before they are written into the control store matrix 1333 will. The local storage register 1343 will allow time division operation as both a local read and a local write register used. The multiplexer KQM 1345 can either from the 1355 maintenance desk or through the micro diagnostics and generates a read path from the registers connected to it. A comparison register KP 1350 is available for non-functional purposes And is mainly used for maintenance purposes in connection with the comparison logic 1352 and the decoding logic 1351 used.

Dispatcher firmware to control processes

The dispatcher is a firmware / hardware unit whose main task is to manage the various process

509834/0830

Queues and switching between processes. It carries out the completion of the process queues, the process control blocks PCB, of the current process word in the system base and the register of a new process. It continues to broadcast messages about processes that are currently underway on a "semaphore" are in the waiting status (after a V operation, a simulated V operation for the IOC or the exception processing unit). The dispatcher also transmits a message to a "semaphore" after a P operation that has released a message chaining when a process has a free "chaining" semaphore Acceptance of its message is waiting.

The dispatcher continues to obtain the self-mode command firmware after a self-mode process is saved has been or after a "dispute" situation has occurred when the current process is still in its own mode. The dispatcher also calls the Decor extension firmware for the following purposes away:

(a) a short-term retrieval while a the process going on in this decor extension;

(b) a short-term retrieval while a the process going on in this decor extension;

(c) a final retrieval at the end of the saving of a process running in this decor extension and

(d) a final poll for a "streak" situation if the current process continues in that decor extension expires. .

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Furthermore, the dispatcher puts the system in an idle loop, when no process is in progress.

Entering or exiting the dispatcher is possible in different ways:

(1) The initialization procedure (SIP) causes an entry as the last step.

(2) The start and interrupt command causes the dispatcher to be entered. The start command triggers a process off, and the interrupt command terminates it.

(3) The P and V operations cause the dispatcher to be entered. The P operation picks up a message from a "semaphore" and if there is no message is, the process goes into the Fete status.

In short, the dispatcher is the main mechanism for managing processes and consequently the process control blocks PCB decide which process is to be carried out and they effect the appropriate action, such as saving a currently running process (i.e. all information relating to the currently running process current process and are located in the hardware registers, the "scratch pad" memory, etc., are written to the PCB) and the storage of a new process (ie all information required to carry out the new process is transferred from the PCB to the various hardware registers, the ⁿ scratch pad memory, etc.).

The functions performed by the dispatcher are shown in the flow charts in FIGS. For example Block 1402 of Fig. 14a provides the function of the dispatcher in which the control storage unit is a microprogram

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- 63-;

Word is generated and, through the decryption with the aid of the decoder 1359, controls the parts of the CPU to be used via a corresponding series of micro-operation signals 1360, I36I, etc. in order to locate the IPQW in the system base of the memory subsystem 102 and store it in the "scratch pad" memory 1315 to transfer. At the same time, the dispatcher (1404) calls up the GO segment descriptor (see Fig. 12) from the G table, to which the G table word GTV / in the system base refers. Bits 16 to 31 of the IPQW word contain a positive whole 16-bit number, which indicates the shift of the G segment number 0, which is regarded as a GO segment, from the base to the "head" (first byte) of the Q / Represents PR / RDY queue of ready processes. If bits 1.6 through 31 of the IPQW word are 0, then queue 1403 is considered empty. If the ready queue is empty, it means that there is currently no process waiting in Q / PR / RDY and the ready queue is empty.

The next to be decided in decision block 1405 The question is whether a process is currently running in the machine or not. This is done by checking whether the blank indicator is set or not. If the empty indicator is set (i.e., no process is currently in progress), go the machine into the idle status 14O6, since before it had been determined that no process in the ready queue was waiting to use the processor. if at this point, however, a process is running in the machine, but no other process is in use the machine is waiting, the process currently running takes effect his next command. 1407 from.

Referring again to decision block 1403 of the flow chart of Figure 14a; if in the Notice zone of the IPQW word (i.e. bits 16-31) one

509834/0830

positive integer is included, then the header the ready queue to which the IPQW word in the GO segment indicates, retrieved into the "scratch pad" memory. (To avoid repetition and ambiguity, the intermediate functions of the dispatcher connected to the control unit and the CPU are omitted; it understands however, it goes without saying that intermediate functions, such as the functions already described, typically exist are). Up to this point it has been determined that there is a process waiting in the ready queue is located. Before carrying out any further actions, it must be determined whether there is currently a process in the central processing unit expires. This determination is made in decision block 1410 of the flowchart, if not a process is running in the central processing unit (i.e. not a CJP) the header of the ready queue is processed (1412). if However, a process is running in the central unit, the dispatcher must determine which process has priority, which process is currently running, or the header of the ready queue. As a result, the priority byte located in the current process word of the system base PCB 400 becomes of the running process (CJP) retrieved (1413). A decision is now made (1414) whether the just running process CJP has a lower priority than the new process waiting in the header of the ready queue NJP owns or doesn't. (See decision block 1414). If CJP has no lower priority than NJP, keep CJP takes control of the central unit and the "streak indicator 1415 is deleted. (The" streak indicator is always zero, except when one or more new processes are added to the ready queue have been since the beginning of the last-for CJP the executed command creates a conflict possibility; under these conditions the "streak" indicator is positioned on binary 1. Before the current process CJP die

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Continuation and execution of further commands permitted a determination is made as to whether or not CJP is running in Decor expand mode 1415. When CJP is in Decor expand mode expires, the next command is executed in emulation mode (i.e. decor extension) and if CJP is not in decor extension mode expires-, the next command will be in Eigen mode executed. In decision block 1414, if NJP has a higher priority at the head of the ready queue than CJP (i.e., its priority number is lower than that of CJP) becomes the currently running process CJP is stored out of the machine and the new process NJP is stored in the machine. Accordingly controls a firmware priority subroutine PRIQ 1418 the inclusion of the current process CJP in the ready queue with the aid of the priority LIFO and the priority number by first saving the CJP under control through the firmware subroutine RLLO 1419. The RLLO subroutine controls the retransmission of the information from the CJP that is stored in the general registers, the basic registers, the scientific registers, the T-registers, the status registers and the command counter are stored to the corresponding memory areas of the process control block PCB in the main memory. RLLO still controls the update from RUA. In addition, the DEXT number of the process noun 0 (PMWO) in PCB 400 is updated (1420).

The new process NJP can now be saved. The border address register BAR is captured (i422) and the current process word is derived from address BAR plus 56 of the system base tapped. See block 1423. Next, the name of the new process is NJP in the current process word RPW written, and since the name of the new process NJP is written into the process link PL of Q / PR / RDY the designation from the process link PL is now transferred to RPW (block 1424).

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Therefore, the NJP is now CJP from the ready queue and can now control the central unit. Expected therefore no longer in the Q / PR / RDY; he must by reading his designation from the process chain PL of Q / PR / RDY (block 1425) can be dequeued. When this is done, the queue becomes of the ready processes Q / PR / RDY updated from firmware subroutine UQLK, 1425a. Accordingly becomes the JP number of the process just saved from the machine in a process chain of Q / PR / RDY because the process no longer has control of the machine and has to wait for the machine (1426). At this point, the process of handing over these stevedores to the new process and the placement of the old one is on Process completed in a ready queue; since a process (the new CJP) controls the central unit, is the empty indicator positioned on 0 (1427)? however, if no CJP is in control of the central processing unit, the empty indicator is positioned at 1. To this At this point, the assignment of the processor is complete and a new process is located in the central unit, whereas the old process has been placed in the ready queue; however, the new process can still not expire because of the hardware of the central processing unit 1306 of Figure 13a, such as the general registers

1307, the basic registers, 1308, the scientific registers 1309, the T register 1310, the status registers 1311 and the instruction counter 1312 is supplied with control information from process control blocks of the new process have to. Accordingly, the firmware subroutine 1430 controls the CPU and first transfers PMW 3 from the PCB (Fig. 4) to the "Scratch Pad" memory 1315 and then PMW 0. The MBZ field PIW 0 is checked (1433) and if it is not binary is, an "illegal PCB" exception occurs. However, if the MBZ field of PMW 0 is zero, PMW 1 is tapped (1434). The MBZ field is checked again by PMW 1 in order to

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-.67-

• 245653A

determine whether it is binary 0 or not. If this If the field is not binary 0, an "illegal PCB" exception occurs; if, on the other hand, it is 0, the dispatcher goes to C above.

Correspondingly, the address space word 0 ASW 0 is derived from the corresponding PCB field and the size of the segment table word SWSZ is checked (1437) to determine whether it is less than 7 or not. If it is less than 7 is, an "illegal PCB" occurs, if it is equal to or less than 7, ASW 1 is tapped from the PCB (Block 1438) and its SWSZ field is checked (1439), to see if it is equal to or less than 8 or not. If its field is greater than 8, occurs. »Illegal PCB"; however, if his STWSZ field is the same or is less than 8, the exception word EXW is tapped (1440) and its IiBZ field is checked to determine whether it is equal to 0 or not. If his MBZ field is not 0, an "illegal PCB" occurs, but if its field is 0, the stack word becomes SKW. tapped (1442) and its MBZ field is checked (1443) to determine whether it is equal to 0 or not. if the MBZ field is not the same as an "illegal" one PCB "; on the other hand, if it is 0, the instruction counter word ICW is transferred from the PCB to the command counter IC and its TAG field is checked to determine whether it is equal to 0 or not (1445). If that

TAG field is not 0, an "illegal PCB" occurs. If, on the other hand, the TAG field is equal to 0, the MBZ word is tapped (1446) and its MBZ field (bits 0 to 31) are checked to see if it is equal to 0 or not (1447). If it is not 0, an "illegal PCB" occurs; On the other hand, if it is equal to 0, the stacking

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Base words 0, 1 and 2 SBW 0, 1 and 2 tapped (1148). The contents of the eight base registers in the staging area the base register of the PCB is then tapped (1449) and stored in the base registers of the machine 1308. The contents of the 16 general registers are then removed from the general register buffer area of the PCB tapped (1450) and stored in the general registers of machine 1307. Before tapping the content the scientific register is however using of the capability byte of a process main word 0 (PMW 0) A review is done to see if the scientific Mode to be used or not (1451). If scientific mode is to be used, the contents of the scientific registers are tapped from the memory area of the PCB and stored (1452). The firmware will now check the capability byte of PMW 0 to see if the netting mode should be used (1453) or not. When the set-off mode is to be used (i.e. if the offset bit of the capability byte is binary 1), the offset words are present in the PCB and the ready time offset word RTA is updated. Now the firmware checks whether the DEXT number is 0 (1454) or not. If this number is not 0 this indicates that the machine can be in Emulatirms mode (i.e. the Decor extender is used), and accordingly the DEXT number of PMW 0 is checked (1454) to see if it is greater or is smaller than the DETSZ field of the process noun 3 or not; if it is larger than the DETSZ field, kick raises an illegal PCB exception 1456 because the DEXT number is smaller than the DETSZ field but not equal to 0 and the machine is in a legal emulation mode and goes to F. If at decision block 1454 the DEXT Field is binary 0, the Eigen mode is carried out and the

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Machine picks up the STWs (1457). The remaining term word RTO from PCB is tapped (1458) and the process timer is loaded with the maximum time that the CPJ can spend in functional status.

Up to this point, either (a) has been a new process NJP saved to take control of the CPU if there was an old CJP process in the machine and the new process NJP had a higher priority than the old process CJP, or (b) no CJP existed that supported the CPU controls, and then the "head" of the ready queue has been processed. In short, under condition (a), the CJP became the RPW removed and incorporated into the process chain PL of Q / PR / RDY, and that in a process chain PL NJP located by Q / PR / RDY was transferred to RPW; in this way, the actual position of the both processes, with control being given to the NJP, which has now become the CJP, while the old CJP has control has been removed. An access operation to the PCB of the NJP has now been carried out, and that to operate the NJP (now CJP) required information was stored in the "scratch pad" memory or in the register matrix of the ACU.

If no CJP had control of the CPU (condition (b)), the "head" of the ready queue was processed, i.e. NJP became CJP because the dispatcher removed the process NJP from the process chain PL of the "head" of the ready queue and translated it into the RPW word. This operation left a process chain PL of Q / PR / RDY empty and had to be pulled out.

Beginning with decision block 1461, check the Firmware now, whether a CJP had control over the CPU or not and if a free process chain (FPLS) was in place, an access operation was performed on it

$ 09834/0830

conducted and it was enlisted, followed by a CJP enrollment. When no CJP is in control via the CPU, the status byte of PMW 0 of the NJP is updated (1460) and it is checked again whether a CJP was or was not in the machine (1463). If not If CJP had control of the processor, the process chaining of the NJP (which was in Q / PR / RDY and now the Control of the machine) is pulled out (1466) (i.e. separated from Q / PR / RDY) from Q / PR / RDY and becomes a free one Process-chaining "semaphore" FLSP and is now used with the free Process 'concatenation queue (semaphore PLS) concatenated' (805 in Figure 9) and becomes part of the free process chaining queue (i466a). The contents of the address delimiting register BAR is tapped (1464) and the current process word RPW from NJP (now CJP), which is in BAR plus 56 of the system base is updated by storing the NJP identifier in the RPW (block 1465). The empty indicator is positioned at 0 if there was no CJP. Next up is the "dispute" indicator positioned on 0 (1467) and the segment associate (AS 132 in Fig. 1), which is a typical content addressable Memory is cleared (1471)} now the process mode is entered (1470). (A process mode indicates that there are exceptions to the process running in the processor and not to the operating system are processed). The firmware now goes to the CAB block 1480, and the asynchronous trap bit AB is checked, to determine whether or not it is at binary 1 (1481). When the AB bit is at binary 1, will a check is made (1482) to see if the process ring number PRN is equal to or greater than that asynchronous trap bit field ARN is (AB and ARN are in the priority byte of the PCB of each process; they are important when the process is functional

509834/0830

Status is located; AB and ARN are developed from the RPVi, which is the system base at BAR plus). Under the Assuming that PRN is equal to or greater than ARN, AB and ARN are deleted in BAR plus 56 of the RPW, there the next step 1484 is an asynchronous trapping routine which sets the conditions that a positioning of the asynchronous trap bit or the asynchronous ring number in the first position AB and ARN would not be deleted by the firmware until the next step, a display would appear after which a condition would be wrong even though there are no error conditions at this point, and the step for asynchronous trap routine 1484 would occur again and again, but the routine would not be performed. if in decision blocks 1481 and 1482, the AB bit does not set. or the AB bit set uirLPRN smaller than ARN the firmware would check in which operating mode the.Processor is working, in normal mode or in Emulation mode. As a result, the. Checks DEXT number to see if it is 0 or not; if it is at 0, the normal mode of the machine is performed (1487). If the DEXT number does not match " Is 0, however, the emulation mode is performed (i486).

'fSsmaphor "

It has already been explained that processes are program segments and can also share data segments. Because of this interlocking structure, processes be able to cooperate with one another and for this purpose the system described above includes one Number of process synchronization functions. These functions use data structures called "semaphores".

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245653A

The "semaphore" is a shared data structure used by the address base of all collaborative processes is indexed. As a shared data structure, a "semaphore" is used to connect a process and an event, which do not occur at the same time. As already explained, an incident is any observation which was made by one process and may be relevant to any other process. The incident for example, the completion of an asynchronous operation or the availability of a resource. An incident can occur either because another process reaches a certain execution state or because ' that a message arrives. A "semaphore" must therefore be able to detect the presence of events or resources to save pending proceedings. On the other hand, a process can have a certain point in its implementation reach before the incident occurs.

In this situation the "semaphore" must be able to store the process waiting for this event. Therefore, a "semaphore" must have the double ability of both the earlier occurrence of both a process that is based on a Incident is waiting to proceed, as is the occurrence of an incident awaiting trial, to be associated with it.

In order to fully represent the "semaphore", its relationships and existence are described first explained in the mechanism of the system and then its various data formats are checked in detail; then its use and operation within the system is explained.

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2A56534

In Fig.8 is the spatial configuration of the main memory as a logical summary of segment tables presentedM.lt. These tables, known as G segments, are used to store "semaphores" and related information used. In particular, these G tables are divided into two conceptually different segments divided, one of which is the GO segment and the other is a plurality of SD segments.

The GO segment is used to accommodate a variety of process? Chaining (PL) and a process chaining - '^ emaphor " (PLS.) Of the system is used. Each process chain contains four fields, one of which is the name of its' Process includes. The second field identifies the Priority of the process and also contains AB and ARN, the third field is a connection chain to the next Input and the fourth field contains a relative segment address. The designation field is a JP designation that corresponds to the JP designation of the process control block (PCB). Hence, each process chain creates the GO segment a two-word value for the PCB, since each process chain identifies the PCB it represents. That Priority field is a full copy of the PCB's priority field. The concatenation field becomes a queuing Used by process chaining in a queue so that the dispatcher puts them in a sequential order finds. Therefore, the GO segment is a simple mechanism with which the dispatcher can monitor all currently active processes, since each process has a two-word process chain that connects it to its PCB.

It has already been mentioned that a process can be in one of the four operating states, i.e. functional,

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Ready, waiting or interrupted status (currently not active). All processes with the exception of the process in the functional status that are currently active will be by the process designation and by a queue in which the process chain is located, which is the process designation is transferred to the GO segment. Therefore, these functional states are not only derived from the PCB displayed, but the process chains of the GO segment allow a queue organization so that the Dispatcher can easily perform access and change operations. Every currently active process has one other designation and its designation in the process chain; each chain of processes belongs to a multitude of queues in the GO segment. A process designation can therefore only appear in a process chain and a process chain can only refer to one queue at a time. To change the process status the dispatcher only needs to transfer the process chain to another queue that corresponds to the The status of the process. In this way, by changing the internal assignment of the process chain enables easy implementation of status changes in the GO segment.

Since only one process can be in the functional status, there is no queue organization for this process required; however, multiple processes can occur are either ready or waiting.

Furthermore, a process can go into many different wait states, since a process is capable of one to be seen of many different happenings. This means that there is a ready queue for the processes involved in taking over the resources of the

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Machine ready i.e. Q / PR / RDY, and a multitude of queues for those processes that respond to an incident or wait for an auxiliary source to continue, i.e. Q / PR / S or Q / PR / FLS. As already explains wuiu ·., an interrupted process is no current active process and therefore there are no queues for it interrupted processes.

Fig. 9 contains the exploded view of a GO segment. The system contains only one GO segment. The GO segment is generated all process links, i.e. two-word functions ("standins") for all processes that can be carried out by the system.

Every process that is in the ready state is' over shared Concatenation fields in the queue called the ready queue Q / PR / RDY 803c and d with the connected to other procedures. The ready queue must have a "head" and a "tail", i.e. a certain delimitation of the first and the last Process chaining in the queue. This is done as already described, using a "next process" link field. The "tail" of the queue, i.e. 803d, is characterized by having a next concatenation field with a null value. The "head" of Q / PR / RDY becomes designated by a field in the system base zone, dji. by a word retrieved from the internal process queue word (IPQW), which contains a note for the process * chaining, which corresponds to the "head" of the ready queue. The dispatcher therefore has an overview of all ready processes by having the "head" of the ready queue above it IPQW localizes and then all process links in Q / PR / RDY according to their "next link fields" sequentially

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lines up. If the currently running process in another Status, e.g. ignores the V / arte status, the dispatcher selects the process chain in the "head" of Q / PR / RDY, takes effect picks it up from the queue and uses the JP designation to find its own process control block. This process becomes the new running process and changes from the ready status to the functional status under the control of the dispatcher.

The process in the functional status is not represented by a process chain in the GO segment. Instead of there is another word in the system base zone called the current process word or RPW and includes two fields. One field is the JP designation of a process that is currently running, the other is a copy of the priority field of this process located in the PCB. If a situation arises in which the dispatcher has the "head" compares the ready queue with the process in progress to determine which process take control of the central processing unit should, it would compare the RPW with the process chain and then move on to another operation.

Processes in the waiting state wait for a signal or a message that a certain event has occurred more than one process can wait for the same signal or message, a queue of such processes can be to be required. Accordingly, all processes in the waiting status in the GO segment are linked by a two-word process chain and these process links are combined in a queue. Since more than a "semaphore" process can be on hold, 03 it is possible that numerous Q / PR / S by aggregations of Process chains are shown in the GO segment. To illustrate, two process queues are shown in FIGS

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803a and b and 'figures. 803e through g. The head" such a Q / PR / S is, as will be described, from marked with its own semaphore. This is in contrast to the one ready queue created by the internal Processor queue word is marked in the system base. Both Q / PR / RDY and Q / PR / S are queues of process chains created by the dispatcher hardware and, in the event of a process status change, by the P and V commands are processed. The dispatcher or the P or V command can select a process from one of these 'queues pull it out and put it on another queue and the dispatcher can put a process on the Move function status or lead him out of this status.

The format of the process chains for the waiting processes Q / PR / S is the same as the process chains of Q / PR / RDY identical; the "tail" of the queue is identified by the process chaining in the field "next chaining" contains the value 0. An indication of the "head" of the queue of waiting processes is located in a special data structure called a "semaphore" that is used to display events will. This "semaphore" will be described in more detail later contains a process queue header note PHQP, of the head process chaining in the queue of the indicates prazesas waiting at the "semaphore", i.e. Q / PR / S.

When a process goes from the ready or waiting state to the functional or interrupted state, it leaves its own Process chaining back in the GO segment. This room is now available for other purposes. If on the other hand a interrupted or running process in standby or

50983A / 0830

* - 78 -

Waiting status passes, it must call up a process chain from the GO segment. Hence occurs in the GO segment a memory management problem. The dispatcher must be able to quickly create two-word process chains retrieve and share. To solve this problem, the GO segment already contains another queue, which is automatically processed by the hardware. This queue contains all free process chains, which can be used when a new one. Process is started. Whenever a process chain of use is released, i.e. the interruption of a process in the ready or waiting status, becomes the queue A released process chain has been added to the free process chain. Whenever there is a new process chain , is required to identify a process movement in the ready or waiting status, this is turned off tapped from the queue of the free process chains. These activities are mainly carried out by the dispatcher, but p and V commands or Start and interrupt commands are used. The GO segment must have enough process links at all times to save the names of all processes that are currently active are.

The free process chains are combined in the same way as with Q / PR / RDY and Q / PR / S, and the "tail" the queue is identified by a link that contains the value 0 in the "next link" field. Of the "Head" of the free process chaining queue is identified by a field in a special data structure, which is referred to as the Process Chaining "Semaphore" (PLS) 901 and is located in the front part of the GO segment is located.

509834 / 083Q

The process chaining semaphore is in a known position of the GO segment and therefore the dispatcher locate it easily. Therefore, all process chains within the GO segment are different Assign either with the ready queue, any other queue, or the free one Process chaining queue connected.

It should be noted, however, that in the process chaining there is no element itself that identifies the queue in which it is located. if a process chain is considered in the GO segment you can only see a process name, a priority and a link field, which is one of the next links is taken over, i.e. no backward chaining or other identification information is available. At the Looking at process chains, it is not possible to determine the current status of the system.

It has already been made clear that a semaphore should be added has the ability to store an incident waiting for a process to be incorporated into it to become. The remaining majority of the G-segments are used to perform this function. The remaining G segments are called "semaphore descriptor" segments (SD) and consist of Gn segments 802n. An SD segment is a segment that can contain "semaphores" and queues of message chains sent by "Semaphore" and "Semaphore Descriptor" are controlled. Reference is made to the "semaphore descriptor" segments, if the normal segment residing in the local address base of a · JP process is a "semaphore descriptor" segment whose GS bits are 01. These GS bits

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will be described later in connection with the "semaphore descriptor" segment. Furthermore, two G segments cannot start the same absolute address. Therefore the GO segment in the first segment and the remaining SD segment, ie G1 to Gn, each have their own absolute start addresses. The construction of a "semaphore Descriptor" segment (SD) is shown in _FIG: shown 15th Accordingly, the first word of the "semaphore descriptor" segment must have the following 32-bit format. The first two bits are the TAG field, which shows the so-called TAG error as 11-bit coding. This error display is just a hardware mechanism for limiting access to a word of an SD segment. The next two bits, i.e. bits 2 and 3, represent the VR ring number.

The ring number VR identifies the highest processing ring in which a V operation on "Semaphores" via "Semaphore-De scriptor "is permitted in the segment. The next two bits, i.e. bits 4 and 5 represent the PR ring number, which mark the highest ring in which a P operation to "semaphores" via the semaphore descriptors in the segment. Bits 6 and 7 form the IR ring number, which identify the highest ring in which an initialized "semaphore" counting operation is performed on "semaphores" via the im The "semaphore descriptors" contained in the segment is permitted. The values VR, PR and IR of a "semaphore descriptor" segment do not necessarily refer to "semaphores" within this segment, but only to the "semaphore descriptors" 502 (these will be described later), which are located in this segment, i.e. those via these "descriptors" tapped "semaphores". Therefore the "semaphores" can be in a different segment than this "semaphore

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Descriptor "segment. Bits 8 to 15 must begin with MBZ marked and 0. Bits 16 through 31 are a free concatenation "semaphore" hint, FLSP, which is a relative address shift in the "Semaphore Descriptor Notice performs two functions in the system. This notice is first used as the top Address limitation of the "semaphore" descriptors considered in the "semaphore descriptor segment".

In other words, the relative segment address of any "semaphore descriptor" in the segment must be lower to be as FLSP. If the relative address of any "Semaphore Descriptors" in this segment is not lower than FLSP, the "Semaphore Descriptor" does not designate ' the "semaphore" located in this segment. Second the note identifies the free concatenation "semaphore" (FLS), which will be described later. According to Fig. 15 the number 1500 refers to the first word of the "semaphore" descriptor segment and the number 502 to one of the many "semaphore" descriptors.

The FLSP of the first word of the "Semaphore ^ descriptor segment supplies the relative address of the free concatenation "semaphore" 1504 following the "semaphore descriptors" 5.02. The free Concatenation »semaphore" FLS controls the queue of the free message chains Q / ML / FLS in this segment, if FLS is available. The free concatenation "semaphore" must be present if the SD segment "Semaphores" with Contains messages. In addition, FLS can be used to hold processes, i.e. Q / PR / FLS if all are free Message chains are currently in use.

If there were no "semaphore descriptors", 1502 would be empty. If there were no free message chains, the "semaphore" FLS represented as 1504 would not be required.

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In FIG. 15, 1506 identifies the position of the "semaphore". The "semaphores" located in this part of the memory "are described in FIGS. 16a and 16b. Block 1508 contains the message chains and the free message chains. Each of these concatenations is contained in the SD segment in the same way as the process chains in the GO segment. This message zone may contain different data than any other segment; however, the zone would normally contain messages which refer to the various "semaphores" in the segment.

Each message chain 1508 consists of four words that make up a message (see 1508a). Make up the first 48 bits the message header zone and the last 84 bits the actual message zone. The message prefix contains one and a half Words, i.e. bits 0 to 47; the actual message claimed the remaining space of the concatenation, i.e. two and a half words or bits 4 to 127.

The format of the message header has bits 0 to 15 as the "next concatenation" field. He contains in this In the case of the relative address of the next message chain of the queue in the "semaphore descriptor" segment, with the exception of if the concatenation is the last one in a queue, in this case a 0 indicates in the "next concatenation" field the end of this queue. Bits 16 to 23 represent the reason field, which is the reason indicating for the message. It is only used in situations where input-output messages occur and is otherwise irrelevant. Bits 24 to 27 identify the message priority level (MPL). This field is in Connection with message "semaphores" used, the lowest Fourth of the message priority level corresponds to the highest priority. Bits 28 to 31 represent the message TAG

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This field contains basic information about the species the message. A TAG message 0000 indicates that the Message generated by P or V commands. At a Message TAG of 1000 is known to the IOC to receive the message has pzeugt. Bits 32 to 48 identify the sender at. Depending on the message, this field contains the JP designation of the process that sends the message or the Channel number for IOC messages or O in all other cases.

Messages are in the "semaphore descriptor" segments, but not included in the GO segment. In Fig.17 the internal relationships of the message chains to the "Semaphores" and the free concatenation "Semaphore" are shown. Messages are generated in the general registers 0 to 3 of a PCB. Hence a process that would performs a V operation, stores the actual message in general registers 1 to 3, and the System hardware would generate the message prefix in the general registers 0 through. The use of general registers instead of the space of a data segment makes it easier for the hardware to send the message. If a process is in a wait state, will its registers in the process control block are easily addressed and the message fields in the registers are large Ease of checking when the process is in the functional status returns.

The message chains and free message chains are also organized in queues. If the message concatenations are connected to a "semaphore", a queue of messages is generated on the "semaphore" (Q / M / S). If the message chains are not currently being used, they are connected to the FLS "semaphore" 1504 and a Message chaining queue at the free chaining

SG983 £ / fi83G

"Semaphore" O / ML / FLS is generated. The structure of the Q / ML / FLS is if no messages are generated, analogous to the Q / PR / PLS structure; however, there are significant differences, as explained above.

The above creates the basic memory allocation, in which the "semaphore" is present. Before describing the operations of the structures of Figs. 9 and 15 as shown in Figs Referring to Figures 17 and 18, an examination of all "semaphore" data structures is performed.

In Fig. 16 are the data structures that make the connection of Enable processes and events. In particular, five "semaphore" types are shown in FIG can be used in the system already described. These "semaphores" are: a "semaphore" 1600 with no message that is shown in Fig.16a, a "semaphore" 1602 with message, which is shown in Fig.16b and of which two types are used , a free process chaining "semaphore" 901, which is used in the GO- ^ segment (Fig.i6c) and a free concatenation "semaphore" 1504, which is used in the SD segments (Fig.i6d).

It has already been mentioned that a "semaphore" is the connection between a process and an incident or an auxiliary source. In those cases where a "semaphore" is only used to indicate the occurrence of an incident to be marked and not to mark a transmission of special information regarding the occurrence When an incident is used, a "semaphore" message data structure (Fig.i6a) is used. "Semaphore" 1600 for example, it may be associated with input / output devices such as disk units. All information related to availability of disk units, e.g. a retrieval of the disk or

509834/0830

an indication that the disk operation is complete have been reported to a special "semaphore" 16OO. Other "semaphores" 1600 can be used to identify other input / output units or other units which have the property "present" or "not present". Each of these units can have its own "semaphore" 160. The "semaphore" I6OO consists of a double word, ie 64 bits. Its format is structured as follows: the first 4 bits, ie bits 0 to 3, represent the "semaphore" -TAG field (STAG) and are used in all semaphores to identify the particular "semaphore" type. In the case of a "semaphore" without a message, the STAG field has the code 0000. Bits 4 to 15 of "semaphore" I6OO are used to display the "semaphore" maximum count (SMC). The SMC field indicates the maximum number of auxiliary sources that can be built up on a "semaphore" or connected to it. Bits 16 to 31 contain a "semaphore" counter field (SCT) which is used to display the number of processes currently waiting on the "semaphore" or the number of resources waiting at the "semaphore" at that time. The relationship between the fields SMC and SCT is designed so that the value of the SCT field can never be greater than the value of the SMC field for reasons that will be clarified later.

Bits 32-47 are the head of a process queue (PQHP). The header of a process queue is a 16-bit relative shift that is the head of the in the GO Segment with the "semaphore" linked to the process chain. The head index of the process chain is 0 if the counter reading of SCT is 0 or positive, since there are no processes waiting at the "semaphore" and no process chaining to be carried out is to mark. If the SCT count is negative, the PQHP field shows the first one in the "semaphore"

50 9834/083 0 ORIGINAL INSPECTED

Process on. Bits 48 to 62 form the process designation TEP. This field contains the JP designation of the last Process that performed a successful P operation on the "semaphore". This means that the TEP field is the designation of the last process that successfully received a resource from the "semaphore". There is only one Indication of the occurrence of an incident is indicated, i.e. a signal, the TEP designation indicates the last one Process as the one who received the signal.

To · determine whether a "semaphore" indicates the presence of Events or resources or the presence of processes stores or not, is the count of the SCT field determining the "semaphore". If the SCT field is positive, the SCT value shows the number of processes waiting resources. On the other hand, when SCT is negative, the absolute value of SCT shows the number of times Resources waiting processes. If the SCT field is 0, no process is waiting at this time or no source of help on the "semaphore".

The SCT field is used in conjunction with the P and V operations at the "semaphore" used to increment the count value either or to decrement. Therefore, a P operation through which a process decrements an auxiliary source from a specified "Semaphore" retrieves the SCT field by 1 when executed. On the other hand, a V operation increments which the availability of a resource to the "semaphore" reports, the SCT field of the "semaphore" at 1. Although no messages are associated with "semaphores" without messages, become the respective base incrementation and decrementation by V or P operations of the SCT fields both applied to "semaphores" without messages as to "semaphores" with messages.

509834/0830

When the transmission of specific information relating to the occurrence of an event, is required, a "semaphore" 1602 ¹ used with a message. As in the situation of the "semaphore" without messages, all "semaphores" with a message are assigned to a specific event, for example the deduction of the social security amount or the tax on an advance wage payment. Therefore, each "semaphore" is fixed and the operating system generates the address syllable to locate the particular "semaphore" when the particular occurrence occurs.

The TAG field of the message "semaphore" (STAG) is represented as bits 0 to 3. Depending on the coding, the STAG field indicates whether the "semaphore" belongs to one of two types, ie a message management "Semaphore" or a message "semaphore". In the case of the "semaphore" with a message, the STAG field identifies the chaining type of the message. If the STAG field is 0001, the messages are chained according to a FIFO procedure (first in first out). If the STAG field has a TAG of 0010, only LIFO messages (last in first out) are chained to the "semaphore". If the STAG field is 0011, 'F ¹ FO or LIFO message chaining is permitted.

The message management "semaphore" has a STAG field from 0101, which indicates that the message chaining is done by the priority of the process and for each Priority level, the rules of the FlFo procedure are applied. The message management "semaphore" differs from the message "semaphore" in the use of Priority levels that allow important messages to be transmitted more quickly.

509834/0830

In word 1602, bits 4-15 identify the maximum "semaphore count" SMC, and bits 16-31 identify the SCT count and are identical to word 1600. Therefore a message that represents a different form of data than the signals has the same property of being present or nonexistence, such as the signal used in "Semaphores" without messages. Therefore, the SCT field in the. the same way of messages in the message "semaphore" is used as the signals in the semaphores without messages.

Bits 32 through 47 contain either a message header indication (MQHP) or a process queue notice (PQHP). When the SCT count is positive, there are SCT shows the number of messages linked to the "semaphore".

In this case 'would be the message header hint indicate the first message in the message queue. Bits 48 through 63 contain a message queue tail pointer (MQTP), which indicates the last message in the message queue if the SCT count is positive. If the SCT count is negative, the absolute value of the SCT count gives the number of chained on the "semaphore" Processes. In this situation, PQHP points to the head of the process chaining queue and the message Queue Tail Hint is 0 as obvious there are no messages. In the situation in which the "Semaphore" count is 0, PQHP, MWQHP, and MQTP to 0 because no messages or processes are identified.

The "semaphores" in FIGS. 16a and 16b represent the signaling mechanism for carrying out the process synchronization These are in the SD segments at 1506

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_ 89 -

saved. However, they also pose a problem with regard to the need for memory space that is used either for storing processes or for messages. In order to alleviate this memory management problem, the free chaining ¹¹ "semaphores" shown in FIG. 16d and the process chaining "semaphores" shown in FIG. 16c are generated. Each of these "semaphores" controls the available number of free message chaining, or free process chains, as described below.

Fig. 16c shows the data structure of a process chaining "semaphore" PLS 901. The process chain "semaphore" connects all unused process chains with one another, i.e. the process links without a process name. When the status of a process is changed to the ready status, the first unused process chaining results from the process chaining "semaphore". This process chaining takes then, among other fields, the name of the newly activated process.

On the other hand, if a process is interrupted, terminated, or in the function status is changed, the process name contained in the queue chain is tapped and the link field is now changed so that the link between all unused process links is maintained. Therefore, the organization enables control of the process chaining queue, without changing the location of a link in the GO segment, since it is easy enough to change the content of the "next link field" of a link. It follows from this that the process chaining from queue to queue be transmitted. Since all process names in the GO segment

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- .90-

are saved, the process chaining "semaphore" of essential importance as reserve memory for the process links that are newly entered into the system Processes are required. In addition, the process chaining "semaphore" contains a process chaining queue head indication (PLQP) in bit positions 48 to 63, which indicates the relative address of the first process chain of the queue with respect to the GO segment base. Each process chain contains a "next chain" field, that indexes the next process chain associated with the process chain "semaphore". Hence be the process links in the GO segment are rebuilt when processes are entered and terminated; only the first Process linkage must, however, be known, since all other process links can be localized from it.

The free concatenation "semaphore" shown in Fig.i6d In this respect, FLS is analogous to the process chaining "semaphore", that it connects all unused free message chains of the segment with one another. The free message chains are not included in the GO segment but in the SD segments already described. The FLS owns a data structure three words in length; it has the following format,

Bits 0 to 3 represent the STAG field, which is the "semaphore" type indicates. In the case of a free message concatenation "semaphore", this STAG field is 0000. Bits 4 to 15 must be 0 as indicated by the MBZ. Bits 16 to 31 are the count value of a free concatenation "semaphore" (FLSCT) and this field indicates the number of processes waiting for a free message chain Q / PR / FLS. This negative number is decremented when processes start with the free concatenation "semaphore". If the

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FLSCT number is O, no processes are waiting for a free message chaining. Bits 32 to 47 are the process queue head indications PQHP and bits 48 to 63 are the free message chaining queue indication FLQP * The process queue head indication has already been described; the "semaphore ¹¹ with messages and the free message chain queue header hint is an indication of the first message chain associated with the free chain" semaphore ". The free message chains are grouped in LIFO order using their next chain field Bits 64 through 71 must be 0 and bits 72 through 79 are the general designation (G designation) of the free concatenation "semaphore." Bits 81 through 95 represent the count of the logic channel (CCT), which is the number of logic channels This occurs in input / output operations in which a unit waits on its logical channels for a free message chain in order to communicate with a process via a "semaphore", and no free message chains are available.

When a V operation is performed by a process on a "semaphore" is carried out by FLS with a message in the SD segment, the first message chain displayed by FLQP becomes Used to store the message. FLQP is then changed to the next available free message chain to display. If, on the other hand, a "semaphore" with a message in the SD segment of FLS is performed a P operation the message chain that previously contained the information is released and returned to the queue associated with FLS. Only if no message chains are available and a chain is required the PQHP is used by FLS because it indicates that

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a process attempted to transmit a message without success. Therefore, FLS is a storage management solution for the Storage space restrictions of an SD segment by finding it all free message chains available in the segment.

According to the description of the system configuration in which the "semaphore" works and the description the "semaphore" itself, an analysis of the operations and functions of the "semaphore" is carried out. For support 17 of the description, the addressing of the "semaphore" is shown, and FIGS. 17 and 18 represent represents the various "semaphores" and the queues to be connected to them. FIGS. 17 and 18 show the relationship of the "semaphore" and the queue structure to the design of the overall system.

FIG. 17 shows the development of the "semaphore" position with the aid of the segmented mechanism described above (FIG. 5). In particular, the "semaphores" are made possible by process synchronization and! -Multiplexing commands addressed, e.g. P or V commands that have a 20-bit address syllable (AS), the resolution of which requires a search through the structure of the addressing tables 503 and 504 and a selection of the process control block 400 by the JP Numbers of the running process causes. The "values STN 1700 and STE 1702" are then used to find the segment "descriptor" which defines the relative address of the SD segment. The SRA (relative segment address) results from the addition of the shift ( _{specified in the address x} ilbe) , with the "OFFSET" within the base register 202 of FIG. 2 (also indicated in AS).

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The absolute address is then calculated in order to determine the position of the "semaphore" descriptor in the memory. The "semaphore" descriptor (Res.Fig.15, point 1505a) contains the segmented address (ie STN, STE and SRA) of the "semaphore" on which the PORV command is to be carried out. For the other processes within the system, no process should transmit a "semaphore" address and which are expecting a response via such a "semaphore", & h. an input / output process, the address of the "semaphore" is specified via its GD address, since the GD address can be used on a system-wide basis and not on a narrow JP process basis. This results in two "semaphore" addressing methods, since the "semaphore" and the structures built on them are necessarily located in the divided part of the address base of different processes and must therefore be ^{accessible for every W 1} drive.

As has already been explained in connection with FIG there are two basic semaphores which are addressed via P or V commands be, ie. "Semaphore" 16OO without messages and "Semaphore" 1602 with messages. First the "semaphore" Checked without a message and then the "semaphore" is accepted with the message. The survey submitted is carried out Taken over some time after system initialization. The "semaphore" structures already have a specific one Reached development status, which is shown in Figs. 18 and 17 " is shown.

When a new process is entered by the system, i.e. when If there is a change from the interrupt status to a function status, the process designation is included in the process chain 805a to c of the GO segment 802.

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This process chain results from the "semaphore" PLS 901 connected queue; i.e. the free process chaining queue. Hence the first concatenation, to which the PLS semaphore refers, used for the new process designation, and the PLQP of the PLS "semaphore" would be changed to indicate the next free link in its queue. The displacement field PLQP in Fig. 18 would be changed so that it no longer refers to 805a, but pointed to 805b. On the other hand, the concatenation 805a would be placed in the ready queue Q / PR / RDY, because the process has started and is ready to take over the machine's resource. When the process chaining 805a is queued in the ready queue, however, it would be assigned to the dispatcher according to its priority be included in the LIFO sequence. Therefore can this process chaining either in the "head" of Q / PR / RDY or at most in the sixth position within the given Configuration of the queue.

Once the process is in the ready queue, he would read his call until he got control of the central processing subsystem. After execution With this operation he would be able to set the central processing unit to process his procedure sequence including ναι communication signals about the P or V commands to cause. When a P command is performed on a "semaphore" without notification, i.e. a process that has a Signal from another process before it can run, the system mechanism would use the address syllable to determine a certain "semaphore" 1600 without a message that is to be used. During localization this "semaphore" is checked whether the STAG field is 0000 and the SCT field would be checked to see if the Count amount was greater than 0, less than 0 or equal to 0.

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If the SCT field was greater than 0, the corresponding "Semaphore" without notification that a particular auxiliary resource associated with it is available for the calling process is. The process would then take over the requested resource and enable the following operations. He would first decrement the payment amount of the SCT field by 1, to indicate that it is executing a P command and next to transfer its designation to the TEP field, which now contains the "semaphore" without a message and indicates that a successful operation was performed on a "semaphore".

If the SCT field of the "Semaphore" 1600 is lower without a message or equal to 0, this would mean that the auxiliary source associated with the "semaphore" is not available. Therefore the process which performs a P command on a "semaphore" without a message would be put into the queue Q / PR / S, i.e. because he could not carry out the P commands, because none If resources were available, he would himself the functional status leave and concatenate itself with the "semaphore" without a message. This "semaphore" would start the process report when the resource they require becomes available. In this way the process goes on on its own Activity when executing the P command from function to wait status. This is in Fig.17 (1600), in which this situation has occurred twice and two processes on the "semaphore" without Message waiting. At 1602, note that the process header pointer PQHP points to the first Process 1720, which is set up by the "semaphore" 1600, whose next ■ concatenation field again points to the second process 1722 constructed by the "semaphore"; contains the "next chain" field of the second process "0" and indicates that no further processes are on

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the "semaphore" 16OO are built up without a message. if the process itself has carried out its transfer to Q / PR / S, it would decrement the SCT field, but not its designation transferred to the TEP field, since no successful operation was carried out on a "semaphore" I6OO has been.

When the process sends a V command to a "semaphore" I6OO would perform without a message, i.e. the process has stopped and created the use of the auxiliary source a signal indicating this, which he wants to give to the semaphore, then the SCT field would be checked again, to determine the status of the "semaphore". If the SCT count of the "semaphore" were greater than 0, i.e. that two Resources are available or equal to 0, the count would be incremented by 1 to indicate that the resources used by the process are available for use by another process. The den The process executing the V command would then continue to run in the function status.

However, if the SCT count value were less than 0 (see Fig. 17) and would thereby indicate that another process in Q / PR / S is waiting for an auxiliary source, this would be through the Release to the first process 1720 by means of the V command which is connected to the "semaphore" in the queue Q / PR / RDY; Additionally the SCT count would be incremented by 1. The dispatcher would pick up the signal from the "semaphore" and the PCB the process 1720 waiting at the "semaphore" is put into the ready state. When a process is in the ready status has passed over, it is in a · queue Q / PR / RDY. This queue concatenates all processes that

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are in the ready status, ie waiting for the CPU to be available. Processes are lined up in the order of priority in Q / PR / RDY and the rules FIFO or LIFO are applied at each priority level. The FIFO rules are used when the process was in the wait state prior to the enqueue and the LIFO rules are used when the process was in the functional state prior to the enqueuing. The current process in the function status would now be checked for priority compared to the process in the "head" of the ready queue. Note that the "head" process of the ready queue may or may not be the same as the process that previously ^{waited 1} on the "semaphore" that just got ready. A test would is carried out to determine which process, ie the current process or the process located in the "head" of the queue, has the higher priority and the process with the higher priority becomes the new process in the functional status V operation performed on "semaphore" 1600, the header hint pointing to process chain 1720 would indicate that this process should receive the signal. Process chain 1720 would now be placed in the ready queue and the SCT count of "Semaphore" 1600 would be incremented to minus 1 (-1). Furthermore, the PQHP indication from "Semaphore" 1600 would indicate that the process chain 1722 will be the next process to receive the signal when an auxiliary source becomes available.

The "semaphores" 1602 of the type with messages are at 1706 shown in Fig.17 and at 1806 in Fig.18. if a P command is carried out on a "semaphore" with a message the SCT field is checked to determine the status of the "semaphore" itself. When the count is greater than zero, this indicates a V / art queue

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of messages on the "semaphore" Q / M / S. This results from the fact that a process previously carried out a V operation on the "semaphore" and thereby passed a message to the "semaphore" and, in the meantime, an increment of its count value of 0 to a positive number.

Since with the "semaphore" 1706 the messages 1708 and 1710 are connected, a copy of message 1708 is made in the general registers of the current process, who carries out this P command, in addition to the transmission of the content of the message, the message chaining 1708 is placed in the message queue of the free chaining "semaphore" Q / ML / FLS queued because the information that was in the message chain 1708 has been released have been. The count of semaphore 1706 would be decremented by 1 to plus 1. (+1); the message queue header would be changed to indicate that the message chain 1706 would do the next with the "semaphore" 1706 is message to be chained and the message queue tail hint would not change because 1710 is the last message in the message chain. if However, if a message was attached to Q / M / S from I706, the SCT field would be incremented by 1, the Message queue header would remain unchanged and the message queue tail would be the Display the message associated with the message chain that is performing a FIFO enqueuing. When displayed by LIFO or classification. with precedence, the resulting queue would express the appropriate order.

When a message chain is in the Q / ML / SLS is incorporated, tests are performed on the FLS "semaphore," which is the SD segment shown generally as 802n these tests determine whether a process

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waited for a free message chaining. There one Message chaining has been released by the currently running process if another process is on a free message chain was waiting, the message that this other process contains is now in the free one Message chain can be copied.

In this example it has been shown that free message chains have been available, i.e. 1712, 1714 and 1716 are free message chains, and therefore none Process is waiting for free message chains. However, this step is not carried out.

If the SCT count were less than 0 when the P command was performed on a "semaphore" with a message, this would indicate that a Q / PR / S has already been created has been. Therefore, the process performing the P operation would become another one of the "semaphore." waiting processes and enqueue themselves. The process according to FIGS. 18 and "Semaphore" 1800 with message that a free process chain has been received from GO segment 802 and itself with the process chain 1802 integrate that with "semaphore" 1800. connected and in the Q / PR / S queue at "Semaphore" Listed in 1800. (SCT would also be decremented to minus 5.)

When the · SCT count, as indicated by "Semaphore" 1704 in Fig. 17 If 0 were shown, there would be a queue at the "semaphore" formed by processes Q / PR / S, as the P operation decrements the SCT count to minus one (-1) and would change the PQHP of "Semaphore" 1704 so that this this "semaphore" indicates. It should be noted that there may be fluctuations in this procedure which depend on

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whether or not process chains are available; this however, need not be described for the invention.

In the situation where a process is performing a V operation on a Message "semaphore" executes, the process waits for its Continuation in functional status, but it has to get rid of the message it contains. This message contains the Process name of the process that transferred this message to other fields.

Therefore, many processes can send information through a single "semaphore" when labeled with the sender are provided and do not simply transmit signals, but messages. These messages differ from one another, and SD segment storage space 1508 can be used to store them.

To be more precise, a waits when executing a V command If the SCT field is less than 0, process 802b is the situation at "semaphore" 1800 of Fig.18 to which Release of the message. Therefore, the message of the process executing the V command would be written to the PCB, pointed to by the process chain 1802b connected to "semaphore" 1800 at which the V-instruction was carried out. The process containing the message would then go to the ready queue Q / PR / RDY 803 and the current process that performed the V command would would continue if it had a higher priority than the process in the "head" of the ready queue. The count from "semaphore" 1800 would be incremented by one to minus three (-3), and the PQHP would be changed to point to process chaining 1802a.

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If the SCT count was equal to or greater than 0, this is the case with the message "semaphores" 1704 and 1706 in Figure 17, it would indicate that there are no processes waiting for messages. In other words, there are messages that point to Processes wait to be associated with them. Therefore the message * would be generated by the current process ■ will set up a Q / M / S when fed to the "semaphore" 1704 was added, or in "Semaphore" 1706 the already developed Q / M / S was added.

In both situations the firmware would test whether a free message chaining is available from Q / ML / FLS is or not. Because at this point in time three free message chains, i.e. 1712, 1714 and 1716 are available the process can route its messages about the operation. Therefore it would be the first free process chain, i.e. 1712 and take over his message in this free Save the message chain. This message chaining would then be placed in the Q / M / S queue of the addressed "Semaphore" and the process that performed the V-operation executes and generates the message, would continue to run. The SCT field of the addressed "semaphore" would now be one incremented.

However, if no free message chains were available (according to Fig. 18: FLQP = 0.1504), the process could which executes the V command do not generate the message. It is possible that processes in Q / P .. C / FLS are on hold even if free message chains are queued in the Q / ML / FLS queue. Therefore, this process must be in skip the wait status ^: until a free message chain is available. In this situation, a process chain would be tapped from GO segment 802 and with it the free concatenation semaphore 1504 in Q / PR / FLS (18O4) Concatenating with FLS indicates that

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no free message chains were available when the process tried to send its message. If a free message chain then becomes available, the process in the "head" of Q / PR / FLS is set to the ready status. He will then have to perform his V operation again later. 17 and 18 should therefore be considered at the same time, since processes are connected to the free chaining "semaphore" because no free message chaining are available, whereas in Fig. 17 there are free message chaining available which are connected to the FLS - "Semaphore" are connected. In this way, the FLQP field in FIG. 17 identifies the first available free message chain, whereas in FIG. 18 no free chains are available and FLQP is equal to zero. The PQHP field identifies the first process connected to the FLS- ¹¹ semaphore ".

Several message semaphores are shown in FIGS. Since any "semaphore" can have processes waiting, there can be numerous Q / PR / S queues each of which is represented by queues of process links in the GO segment. this is shown graphically as 1802, 1804 and 1808 in Fig. 18, with process chaining in the GO segment the "semaphores" are connected. In addition, other SD segments (not shown) can use "semaphores" that are also able to include the process chains in the GO segment.

It has already been explained that a "semaphore" must have the dual capability of being either a process to save waiting for an event to continue or otherwise to save an event, waiting for a process to be associated with it. These concepts are respectively through Q / PR / S and

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Q / M / S has been shown. When looking at the relationship of this Queues to the "semaphore" can be seen that the message waiting queue at a "semaphore" and the process queue at a "semaphore" diametrically opposite Concepts are. The data structure, i.e. the "semaphore" contains one or the other. If a process has performed a P instruction and has no incident or no resource to complete of the call made in the P operation is available, the "semaphore" creates a process queue at the "semaphore" Q / PR / S. If on the other hand an incident or a resource becomes available and not a process waiting for this event or this resource, the "semaphore" creates a message queue on "Semaphore" Q / M / S. These are indicated by the SCT field in the "semaphore". So if the SCT count of the "semaphore" is positive, this indicates that messages are waiting for processes and a message queue ^ has been set up on the "semaphore". If the SCT count of the • Eemaphor ”is negative, it means that processes are on a Message or event waiting and a process queue has been set up on the "semaphore". When the "semaphore" count is zero, it means that there are neither waiting processes nor waiting messages nor a queue.

The Q / ML / FLS and Q / PR / FLS are generally just simple Execution on FLS semaphore 1504 available. If there are message chains that are not 'from the "Semaphores" are used in the SD segment, the free concatenation "semaphore" contains a queue with free message chains. This would be indicated by the fact that in the FLS "semaphore" a FLQP field is not at zero. If the free concatenation "semaphore" is a FLQP field with "0"

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which indicates that no free message chains are available, FLS builds a process queue Q / PR / FLS on when a free message chaining is requested by a V-operation.

With regard to the limited message concatenations in a "semaphore" descriptor segment, a facility must be in place which prevents a message * semaphore "from accepting all free message chains. This is done by that each message "semaphore", as shown in Figure 16b, contains a maximum count field. This field, i.e. bits 4 to 15, limits the length of the message queue. if So for messages that are attached to the "semaphore", the value of the SCT field exceeds the SMC value, an exception occurs. This facility not only helps in managing the storage space, but also ensures that a "semaphore" does not contain all or a significant number of free message chains contained in the SD segment are available. (Note: In the "semaphore" without a message (Fig. 16a) the same bits limit 4 to 15 the number of events (VOPS) that can be stored using this "semaphore").

General description of the P and V commands

It has already been explained how processes are represented in the hardware (PCB) and which functional states they can assume; Furthermore, the dispatcher unit has been described, which is used to control the functional states and movements of the processes. In addition, the process synchronization function with the data structure of a "semaphore ^{11" has been} shown and explained.

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With the dispatcher unit and the "semaphores" for controlling the process synchronization, the operations on the "semaphore" integrated. Two basic operations on the "semaphore" are required when processes that use the "semaphore" as a signaling mechanism want to use. An operation, the V-Operation or V-Instruction, sends a signal ^ to this semaphore. The other Operation, the P operation or the B command, captures a signal from the "semaphore".

The V command can be viewed as a send operation that can be used by the process who has some data and this to another process or any group of processes want to send. The V instruction enables the process to do that Sending this data (i.e. a signal or a message) to an intermediate point. The "semaphore" saves the data until another process is ready to access it. In the meantime, the will do the V command The executing process is released because the data has been sent.

The P instruction can be viewed as a receive operation used by the process that requires data from either a particular process or from one of many processes. The P instruction enables the process to receive data (i.e. a signal or a message) from the ^Ά · Semaphore ¹ J.

If there is data, the process executing the P instruction continues. However, if the data is not in the "semaphore" are stored, the process which executes the P instruction goes into the waiting status. The "semaphore" holds the In this case, process instead of the data. The process is held in wait status by the "semaphore" until another process the reason for staying this one

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Process in the waiting status, i.e. the sending of data for the process via the same "semaphore". These· The function is carried out by a V command.

Therefore, a process waiting for data (ie a signal or a message) from another process to continue on its own will attempt to obtain the signal by executing a P instruction on a predetermined "semaphore". On the other hand, a process that sends data (ie a signal or a message) to another process before it can continue to run tries to transfer this data by executing a V command on a "semaphore". The reason for being in the waiting status is canceled if the process receiving the data is in the waiting status. Therefore, the V command also enables the process that requested the message to be transferred to the ready state. In this way, the data generated by the V command are stored in the PCB of the process that is calling up the data, and they are then checked when the process is put into the functional status by the dispatcher mechanism.

Since there are two different types of "semaphores", i.e. "semaphores" with messages and "semaphores" without messages, there are also two types of P and V commands. Each type of a P and V command can only be carried out on a "semaphore" of the same type. Therefore every command must a "semaphore" with its own TAG bits, i.e. P and V commands with messages can only be "semaphores" which are sent by their TAG bits as message "semaphores" and P and V commands intended for "semaphores" without messages can only be routed to non-message "semaphores" which are characterized as such by their TAG bits. Additionally

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to the rules of application mentioned above, both Message as well as non-message P commands also as P test commands are executed. A test command enables the continuation of an ongoing process, even if the action intended by the command has not been carried out. Therefore there are four P commands. V commands with messages can Retrieve an LlFO or FIFO queue and also as V-Test commands be performed. This results in four types of V commands with messages, plus a V command without messages, so a total of five V commands.

The following mnemonics are in the flowcharts and are used to describe the following Commands used:

SEP A P command for a no message semaphore. This command either picks up a signal from the "semaphore" or causes the ongoing process in the waiting status and a queuing in Q / PR / S.

SEPM A P command for a message semaphore. This command either picks up a message from the "head" of Q / M / S of the "semaphore" or causes it a transfer of the running process to the waiting status and its inclusion in Q / PR / S. When a Message has been fetched from Q / M / S, the message chain is returned to Q / ML / SLS and the Counting fields in the FLS "semaphore" are checked.

If an input / output process (logical channel) is in the wait state, the system will immediately a free chaining made available for performing a V operation. If not,

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A check is made to see if there is a waiting process in Q / PR / FLS.

If a process in Q / PR / FLS is waiting for a free message chain, that process will is set back to the ready status and can execute its V command on the FLS "semaphore".

SEPT A P-test on a no-message "semaphore". This is the same command as SEP, except that if a semaphore does not receive a signal, no transfer of the process in progress to the Waiting status takes place.

SEPTM A P-test on a message semaphore. Identical to SEPM, with the exception that the current process is not placed in the waiting status if the "semaphore" does not receive a message.

SEV A V instruction on a non-message semaphore. This command generates a signal that is stored in the semaphore. If there is a process queue on the "semaphore" waiting for the signal, Q / PR / S, the first process in the queue receives the signal and changes from the waiting status to the ready status.

SEVF V commands for a message semaphore.

SEVL Every command generates a message to the semaphore. If there is a queue of processes at the "semaphore", Q / PR / S, the first process in the queue receives the message and changes from the waiting status to the ready status. If there is no Q / PR / S, the message is stored in Q / M / S in either FIFO (SEVF) or LIFI (SEVL) order. If there is no Q / PR / S,

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and no message chain can be found in which the message could be included, the current process goes into the waiting status and is chained with Q / PR / FLS. The B. command counter of the Process which executes the V instruction remains at its current count value, so that a repeated Execution of the V command can be attempted when the process is back in the function status.

SEVTF V test commands for message "semaphores".

, SEVTL These commands are identical to SEVE and SEVL, with the exception that if a free one is not found Message chaining in the free message chaining "semaphore" queue the process which is executing the V instruction is not placed in the waiting state he follows.

Each of the commands described above, when executed, enables the control store unit 130 to execute a defined group of functions. The various functions are shown in the flow charts 20 to 26. The implementation of these functions corresponds to that in connection with the dispatcher unit (Fig. 14) and accesses the the same operational elements shown in FIG return. In order to explain the general information transfer precisely, only the main blocks of the operation units are presented described. To avoid repetition and in the interests of clarity of description, the intermediate functions omitted the control store unit in connection with the P and V instructions and the central processing unit; it goes without saying, however, that such intermediate functions, as they are with regard to Fig. 14 are typically also present.

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In addition, there is a more detailed diagram in FIG of a portion of the ALU unit 1315 contained in the CPU 104 of FIG. So are in Fig. 19a the 256 words are shown which are stored in the "scratch pad memory" in the LSU 1315, and in Fig. 19b some of the shown in Fig. 19a Working positions shown that specifically relate to the function of the P and V commands to be discussed. Each of these detailed representations can be clearly understood in conjunction with FIGS. 20 to 26, these figures contain Explanations of their tasks in the overall function of the CPU system.

Development of "semaphores" for P and V commands

Figure 20 specifically illustrates the "semaphore" descriptor tap operation functions that are performed by all of the P and V commands, and in Figures 21 to 26 the various P and V commands and the functions they perform are shown.

In Figure 20, block 2000, the device is more specific of the "Semaphore Descriptor" tap routine used by all of the aforementioned P and V instructions is made possible. Each command contains an operation code (OP) in bits 0 to 7, a complementary code in bits 8 through 11 and a 20-bit address in bits through 31. The operation code identifies the system the command type, i.e. P or V and their variations. The complementary code identifies specific information regarding the command; E.g. whether a LIFO or FIFO queue takes place, whether a test command occurs etc ... the

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Address syllable is used to identify the "semaphore" descriptor. The resolution of the address syllable requires a Searching the structure of the address tables with the JP numbers of the ongoing process to select the PCB (see Fig. 4 and 17) and the values STN and STE, thus the segment table and possibly the indirect Addressing to which ultimately, if necessary, the Indexing follows, the relative segment end address SRA can be found within the segment. Last will an absolute address calculation is carried out which determines the position of the "semaphore" descriptor in memory. This is how the address syllable of a P- or V command to the address of the "semaphore" descriptor.

In addition to tapping and testing the "semaphore" descriptor subroutine 2000 continues to access the addressed "semaphore" and enables a branch to either to the P or V command carried out on the "semaphore" shall be. Therefore, prior to executing such an SF subroutine 2000, the operation and complement codes are made parsed so that it is known to be a "semaphore" descriptor is tapped. In step 2001 the question is whether the hardware gate is locked. The hardware gate belongs to hardware control mark 1313 and identifies a critical system status if it is locked. The operating system must be in a critical state Status when firmware processing of processes and queues occurs because of any interruptions can cause an irreversible loss of information within the system. Therefore, if the hardware gate has the value one and indicates that the flow of processes and queues continues,

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Certain commands, including the P and V commands, cannot be carried out because they are in the process of being carried out of these operations would intervene. If the answer to question 2001 is yes, then the hardware gate will locked and step 2002 performed. This triggers a "system check", which is essentially a has detected another critical operation, such as any exception (which is usually an interrupt the current operation and triggering the central exception mechanism) and starts a Model-dependent diagnostic sequence that the system continues to operate in a functional status which is referred to as "sick". In addition (IFHG = 1), any attempt to carry out a synchronization or process control command that requires an exchange the running process could cause a "system check" in step 2002. Both the check of the hardware gate in step 2001 as well as the "system check" in step 2002 are carried out by the hardware that is located within the command acquisition unit 1318.

Steps 2003 and 2004 are hardware tests that are also carried out by the command acquisition unit 1318. In step 2003 the question is whether (or not) the execution of a SECIN command (see description below) is requested. This SECIN command must have a process ring number which is equal to zero in order to be able to be carried out. Therefore, step 2004 checks if the answer is "yes", the process ring number of the command. If the ring number is not zero, a privilege command exception occurs 2004 on. However, for P and V operations, the answer to question 2003 will be "No" and therefore will Step 2005 carried out, in which the question is whether an indexing of the address syllable of the, P or V command is necessary is.

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245 ^ 534

At this point normal development of the address syllable has occurred. That way are the relative segment addresses SRA and a segment number SEG (described above) have been set. The question asked in step 2005 is whether a bit in the address syllable indicates indexing. If the answer is yes, step 2006 adds that Contents of a general register identified by the address syllable for SRA. In step 2007 becomes the transmission of the actual word 1500 of the SD segment from the main memory to the position WCO of the "scratch pad" memory (Fig.19b). That first word contains the TAG and ring fields for the P and V commands and determines whether these are executed may or may not. It should be noted that a tap operation from main memory 102 via the data flow control unit DMJ 1321 is carried out to the arithmetic and logic unit (ALU) 1317 and vice versa a main memory write operation is performed from the ALU 1317 to the main memory "102 via the DMU 1321 will.

In step 2008, some preliminary checks are carried out by the ALU 1317 in order to check whether an access operation to a valid "semaphore" segment has been performed. More specifically still, in step 2008 the GS bit in the segment descriptor itself must be 01. The "G" means gate segment and the "S" means "semaphore" segment, therefore the "semaphore" must Segment bits must be positioned to enable access to the "semaphore" segment. Will continue performed a check to see if STN is equal to or greater than 8 as the "semaphore" segments There are "small" segments for which this restriction applies

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is. In step 2008, a third check is made to see if the SRA is a multiple of four there SRA indicates a four-byte word-organized "descriptor". If the GS bit is not set to 01 and STN is equal to or greater than 8, an illegal segment "descriptor" exit subroutine 2008a triggered. If SRA is not a multiple of 4, as shown in step 2008b, it becomes an illegal system object address subroutine triggered. Unless otherwise stated, as in steps 2001 to 2004, ALU 1317 performs all test operations.

In step 2009 the first word of the "semaphore" segment (SD) i.e. word 1500 in Figure 15 is checked. This Word has been identified by the segment "descriptor" just examined. More precisely, bits 0 and 1 of the TAG field are then checked whether they contain the code 11, it is checked whether all bits 8 to of the MBZ field are at 0 and whether bits 16 to 31 of the FLSP field are a multiple of 8 (i.e. the last three bits are 0). If this data structure status does not occur, an illegal SD segment is displayed in step 2009; otherwise the data structure is correct and the next step 2010 is carried out.

After locating the SD segment and determining that the first word is correct, the next will be the The position and the content of the "semaphore" descriptor in the main memory are checked. Therefore, in step 2010 the in Step 2006 developed SRA checks to ensure that it is lower than FLSP, i.e. bits 16 to 31 of word 1500. The structure of the SD segment shown in FIG. 15 makes this step necessary. As indicated there, the "semaphore" descriptors that have been addressed by the relative displacement of SRA

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are generated in block 1502. FLSP points to block 1504, which is sequentially located at a higher address in main memory than the "semaphore" descriptors in block 1502 is located. Therefore, the SRA, which was developed from the address syllable of the P or V instruction, must point to one of the Obtain "semaphore" descriptors in block 1502, which is by design, lower than the relative address FLSP which points to block 1504 must be. Therefore, FLSP serves two purposes; one is the localization of the free concatenation "semaphore and the other in the definition the upper limits for the "semaphore" descriptors 1502. If these conditions are not met, it will Performed step 2010a. This step is an exception subroutine, indicating that an illegal system object address has been developed. The step 2010 also effects Ring protection reviews. In this way, the EAR field is checked to see whether it is equal or smaller as is the XR field, XR identifies the first word 1500 and is either VR, PR, or IR, depending on whether a V command, a P ^ command or a SECIN command is. If the EAR ring number, which is the ring number for the segment, is greater than the individual ring protection field is, an exception is made in step 2010b.

In step 2011 the "semaphore" descriptor 1502 is made the SD segment 802n of the main memory tapped and in the position WC1 of the "scratch pad" memory 1900 transfer. Step 2012 will be a series of tests performed on "semaphore" descriptor 1502. These tests are similar to those performed on the segment descriptor in step 2008. These tests are performed on bits 0 and 1 of the TAG field, which must be on o1; at

bits 2 and 5 of the ring field, which must be set to 00; at the STN bits 4 to 7, which must be equal to or greater than 8; and at bits 16 to 31 of the SRA field which are a

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Must contain multiples of 8. The SRA field of the "3emaphor" descriptor "1502 currently indexes this addressed "semaphore". Because the "semaphore" is double word size it must contain a double word limit and therefore be a multiple of 8 for addressing purposes. If one of these tests gives a negative result, an exception subroutine 2012a is carried out, which indicates that an illegal segment "descriptor" format has been detected. Since the exception subroutines refer to a test with a negative result that must be corrected by the system, these Situations not further explained.

After defining a suitable segment ~ "Descriptor", the next operations are to develop the current "semaphore" yourself. In step 2015 is the question of whether the "semaphore" segment number is in the Association "/ - memory 1319a of the address control unit 1319 is located or not. The reason for this question is that the "semaphore" location is tapped from main memory will; however, if it is within associative memory 1319a, main memory is not accessed. if so the answer to question 2013 is "no" · step 2014 triggers an SDF subroutine that loads the segment descriptor into the associator.

In step 2015 a test is carried out again to determine whether the GS bit of the new segment is 01 is ^. In general, the "semaphore" descriptor refers to to a "semaphore" within its own SD segment. However, this condition may not be present and the "Semaphore" descriptor may have indexed a new SD segment and a test is now carried out to determine whether the GS bits are equal to 01.

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In step 2016, the already described write permission bit WF checks to see if it equals 1, indicating that it is in memory may be. In step 2017 the written bit (W bit) in the segment descriptor is tested to see if it is equal to is. If the answer to this question is "yes", then step 2020 is performed; if the answer is no, step calls 2018 executes a WUP subroutine that writes and completes the W bit is performed because a write operation is taking place in memory and the W bit must therefore be updated, if this has not already been done. All of these operations are performed on the "semaphore descriptor 1502" already described.

It has already been explained that two possible methods can be used to address "semaphores", one method uses the P and V commands. The other © method for addressing "semaphores" is shown in step 2019 and, at this point, activates the Development process, i.e. the flowchart. The other method is to use the input-output unit or system addressing of the "semaphore", which generates an absolute GD address.

In both steps, step 2020 detects both words of the "semaphore", regardless of the addressing method used for the "semaphore" "Semaphore". These words would be tapped from the associator 1319a and placed in positions WC4 and WC5 of the "scratch pad" memory transfer. The ALU 1317 carries out various tests on the "semaphore" for these positions.

However, before these tests are performed, the Step 2021, the operation code and the complementary code of the instruction to determine whether it is a SECIN instruction 'acts ("semaphore ^ -count initialization) or not. If

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a SECIN instruction branches to the subroutine carried out, which enables the SECIN command. If it is not a SECIN command, but a P or V operation, the STAG field is displayed in step 2023 of the "semaphore" checked. This STAG field is shown in Fig. 16, in which various "semaphores" are mapped on which P and V commands are carried out.

In step 2024 the SCT field in position WC4 of the "Semaphore" is incremented by 1 and saved in position WC7.-This one Step is an anticipation resulting from the fact that the execution at a V instruction is necessary for operation of the system is more critical. By performing the incrementing step in 2024 the timing used in a V-operation is supported. If the anticipation step is wrong correct the subroutines which process the P commands, this situation. In step 2025 the SMC field is positioned in the ALU 1317; this will make the implementation a V-operation and therefore the verification of SCT against SMC anticipated. In addition, the arithmetic Logic unit 1317a positions a flip-flop labeled PMO. This flip-flop indicates that either a P operation or SCT equals "0. If this condition is not is available, a change will be made later.

At this point in time, the functions for starting a P or V command must have been carried out. In step 2026, the Checked command in IFU unit 1318 to determine whether its operational code and its complementary code are a V-operation Show. If the answer to this question is "yes", a branch is made to the V instruction sequence 2027; otherwise a branch to the P instruction sequence 2028 is carried out.

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Subroutine 2000 in Figure 20 has tapped and checked the segment "descriptor", the first word 1500 of the "semaphore" descriptor segment 802n, the "semaphore ¹¹ descriptor" 1502, and the current "semaphore" 1506 on which the V or P operation is performed. Accordingly, the necessary preparatory work for the actual execution of any of these commands has been made, and the firmware indicates that the command can be performed correctly.

P commands

If step 2028 of Fig. 20 has been carried out, the next functional group is the one shown in Fig.21. More precisely, in Fig. 21 both the first overall functions performed with the P commands, as well as those performed afterwards with P commands on "semaphores" Functions shown.

Since the answer to the question in step 2026 was "no", the new "semaphore" count (NSCT) is raised in step 2101 the value of the old "semaphore" counter value minus 1 is set. this it results from the fact that a P operation is calling up data and the "semaphore" count value should indicate that the "semaphore" one less information is available. Additionally, this step omits anticipation step 2024, in the SCT has been incremented. Therefore, the old SCT field that is used in Position WC4 is stored, and not the incremented SCT, which is identified in the scratch pad memory at position WC7. This SCT is now decremented and so results the new "semaphore" count NSCT, which is in position WC7 of the scratch pad memory.

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A. P commands for Kicht message semaphores

In step 2102 the question was whether it was a P operation acts on a no-message semaphore. This results from the fact that all P commands are first carried out by subroutine 2028 to be analyzed. In step 2102 the op and complement codes of all of these commands are returned to the IFU 1318 is checked to determine whether a branch to FIG. 22 and the PM subroutine 2103 should be carried out. These Branch is performed if it is a command for a semaphore with messages; when the test is a command for a no notification semaphore, the remainder of the PNM subroutine is completed.

Assuming the answer to the question at 2102 is "yes", the information required by this P instruction is on Signal which can indicate, for example, that a device, which can be a tape unit or magnetic disk, is available. Of the Step 2104 checks the SCT field of the no-message semaphore and asks whether the value contained in the SCT field is less than or equal to 0. If the answer is "no", i.e., if the "semaphore" count is greater than zero, it indicates that a facility is available for the process is which executes the P command; now the steps 2105 to 2114 mark the successful implementation of a P command on a semaphore without messages. More precisely, step 2105 checks the PQHP field of the non-message semaphore, i.e. bits 32 through 47 of "Semaphore" 1600 to ensure that this field is zero. This Status must exist, as no processes are assigned to this semaphore. If this condition is not met, an illegal semaphore exception condition 2105a occurs and the control memory unit 130 processes this, Exception condition.

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In step 2106 the question is whether it is a P-test command acts. As already explained, a test command always causes the process to remain in the functional status. Since, under the current conditions, a non-test command was successful can be performed since the desired facility is available from the semaphore, the test command sets a condition code and then works as a non-test command to take over the setup. This is shown in step 2107, in which the SCT field checks for a value of 1 will. If this condition is met, step 2108 releases the transmission of a condition code "0" to the status register 1311 from. If the SCT field is not equal to 0, this means that the SCT field must be greater than 1, since inr "step In 2104 it was found that the SCT field was greater than zero. In this situation, step 2109 is performed by a condition code is positioned at 2 in status register 1311 .will to indicate that more than one signal is available.

In both situations, step 2110 is carried out, regardless of whether it is a P test command for a non-message semaphore or just a P command acts for a no-message semaphore. Since the SCT count of the P command is positive, it is known that the P command can be carried out successfully on the semaphore due to the preceding steps. This step runs the scratch pad registers WC4 and WC5 share the information that is eventually written to main memory. In step 2110 the TEP field, i.e. bits 48 to 63 in the WC5 position of the "scratch pad memory" contains the JP designation of the process, which executes the P command written therein. This indicates that in terms of the associated semaphore Auxiliary source, the process currently using the auxiliary source is the one whose JP designation is contained in the TEP field. On the other hand, the NSCT field developed in step 2101 now becomes

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from position WC7 as SCT to position WC4 of the scratch pad memory enrolled. This way, the update of the two fields is what makes a successful P operation mark, has been carried out.

In step 2111 the hardware gate is disabled; it indicates that a critical system operation involving an indivisible action is occurring. In step 2112 the updated fields of the semaphore indicate a successful P command and the contents of positions WC4 and WC5 of the scratch pad memory are transferred via the DMU 1321 in the SD-S _e gment transfer of the main memory 102nd These fields replace the previous fields of the semaphore. In step 2113 the hardware gate is enabled and indicates that the critical status ■ is over and the command counter 1312 has been incremented. Therefore, the next command of the current process (CJP) is executed.

If the SCT field of the non-message semaphore is in the response from step 2104 was equal to or less than 0, a branch to step 2115 occurs. Has this status the semaphore addressed by the P command of the current process does not have any auxiliary sources. Therefore the P command is who calls the resource, to no avail. Depending on the P command, the current process will either be in the waiting state offset, i.e. it must wait until the semaphore receives the auxiliary source, or it can continue to run if it is a P test command. In step 2115 the question is whether the SCT field is equal to zero. If so, this means that no messages or processes are linked to the non-message semaphore a check was carried out to ensure that the

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Process queue header is zero. If the SCT count is not equal to zero, this means that it is less than zero and thus indicates that the non-message semaphore Processes are chained. ^ In this case, step 2116 done to check if the PQHP is nonzero and is also a multiple of 8. The PQHP is nonzero because it identifies the first process that started with this Semaphore is concatenated. Since the process chains associated with the process are 8 bytes long, the PQHP is a Multiple of 8 to refer to the first byte of the process chain, which contains the information regarding the am Semaphore waiting process.

If both tests pass, it is known that the Semaphore is appropriate. In step 2118 the question is whether it is an active P-test command. If so, as shown in step 2119, a condition code is provided "1" is set. This condition code indicates that if the P command had been carried out, the current one Process would have entered the waiting status. Therefore the status register 1311 receives the condition code 1 Step 2120 is performed to find the JP designation of the last Process to · determine which is a successful P-operation performed on this no-message semaphore. It should be noted that the process in progress does not have its JP designation transferred to the TEP field of semaphore 1600, since no successful P operation was carried out. The' Designation of the last process that successfully performed a P operation on this semaphore but stored, since this process occupies the resource requested by the current process. This is represented in step 2120 by placing the JP designation in the last 16 bits of the GRO of the current process was enrolled. All first 16 bits contain zeros.

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When the process performing the P test command has a higher priority than the process that has the resource and also its JP designation in the TEP field the process currently in progress may decide to interrupt the process that is the resource used. In either case, however, the instruction counter 1312 is incremented and the next instruction of the current pro Process that performed a P test command is performed as shown in step 2114.

If it was not a test command, i.e. the operation code in step 2118 indicated that it was about a P command on a non-message semaphore, a subroutine E of VP 2121 is performed, which the currently running process placed in the waiting status. The process in progress is not in this way more in the function status and a process chain, which contains the designation J, P, is addressed with the one addressed by the P command Semaphore connected.

Before considering step 2121 which is the ongoing process pending status, consider branch subroutine PM 2103 of question 2102 as this is the Retrieves subroutine for the P operation on a message semaphore. This subroutine also has a branch to E from VP 2121, when the current process puts a P command on a message semaphore into the waiting status shall be. At this time, the explanation of the E of the VP subroutine 2121 will be performed.

.Β «P command on a message semaphore

If the op code indicated in step 2102 that a P command was performed on a message semaphore, then

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a branch to FIG. 22a and step 2200 is carried out. In FIG. 20, the semaphore has already been recorded and is located in positions WC4, WC5 of the scratch pad memory. In step 2200 the question was whether the SCT field, ie the bits up to 31, is less than zero, ie whether processes _; are assigned to the message semaphore, which is shown in Fig. 16 as 1602. When the arithmetic logic unit 1317 checks the SCT field to see whether it is less than zero, step 2201 checks the PQHP and MQTP Fields in the message semaphore to see if they are correct.

More precisely, the message queue tail indication 'MQTP, ie bits 48 to 63, must be zero because the processes and not messages are associated with this message semaphore. Bits 32 through 47 form the process queue header which identifies the first process associated with this semaphore, and these 16 bits are used both for non-zero and a multiple of 8 are tested. The first test is performed to determine that a two word process chain is associated with the semaphore, and the second test indicates the reference to the first byte of the two words in the process chain. In this way, with the aid of these tests in 2101, it was established that a process queue is present at the semaphore Q / PR / S and that the indication according to which the SCT field is lower than. Zero is correct.

In step 2202, the question is whether it is an ILP test command is for a message semaphore. Since a test command does not put a currently running process in the waiting status can move, the same situation arises that already occurred in step 2118 in FIG. Hence the stature register 1.311 on. a. Condition code 1 positioned which

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indicates that the P command for a message semaphore has not been executed and the instruction counter of the current process is incremented by 1 (step 2203) and indicates execution of the next instruction free for the currently running process (step 2204). If the P instruction for a message semaphore is not a test command, the running process that starts the P command would request a message. Since none available is, the currently running process must wait for the message, and the subroutine Ξ of VP 2121 offsets running process in the default status. This is also in Fig.21 shown,

C. Set a running process to the ^T .farte status

The E of the VP subroutine is used for situations in which the current process cannot continue and must be put into the waiting status. Hence be the two situations described above, the non-message semaphores Use 1600 and message semaphore 1602, in the same way Wise edited because a Q / PR / S is formed. Later, when discussing the V commands, it can be seen that the E the VP subroutine is also used when no free message chains are available. In this situation the process cannot send its message and it is therefore placed in a queue at the semaphore FLS 901, to wait for a free message chain Q / PR / SLS. All of these conditions result in that. the firmware as in Fig.23 shown, performs the same functions.

More precisely, since the one to be put on hold Process Bich is currently in the functional status, a process chain, as shown in Fig. 16c and 18, can be retrieved from the PLS semaphore 901. In Fig. 18 the PLS semaphore 901 in GO segment 802 on the process chain

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805a, which in turn contains the remaining process chains identifies sequentially, with all process chains in a queue, those with the process chaining semaphore 901 is connected. In step 2301 of Figure 23a, the APLS subroutine detects the one associated with the PLS semaphore 901 Process chaining 805a. The APLS subroutine is shown in Figure 23c. -

Referring to Figure 23c, the first step of the APLS subroutine is to access an FGO subroutine 2321. The FGO subroutine shown in FIG. 23d develops the address of the PLS semaphore 901, which is constant since the PLS semaphore is always the first before in the GO segment. The first step of the FGO subroutine 2330 indicates that the firmware is generating the address, ie segment number, which the PLS semaphore locates in the GO segment descriptor. This is done by selecting a register in position WC9 of the scratch pad memory and by developing a 12-bit number as described below. The first four bits are set to 0111 to indicate that it is a G number and the last 8 bits are set to zero to indicate that it is the zero segment of the G number . This segment number identifies the position of the PLS semaphore in the GO segment. This segment number is now in step 2331 i ⁿ the associative memory 1319a transmitted to determine whether the associative memory contains the descriptor segment of SegmentrNummer and therefore the base address of the segment or not. As already explained, the associator is a memory with short access time, which relieves the system from having to call up information in the main memory. In step 2332 the question is whether a hit has occurred, ie whether the associative memory 1319a

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includes or does not contain the segment number developed during step 2330. If the associative memory contains this address, the step 2333 asks the question "Is the written bit set in the segment descriptor?" This test is carried out because in the current situation the current process is to be attached to a semaphore and therefore the writing special information, i.e. next chaining index etc. required. The bit written has already been explained been. If the bit written has not yet been positioned, step 2334 branches to the SGW subroutine performed and at the same time the W bit is written both in the associative memory 1319a and in the main memory. If however, the written bit has been set, there is no need to write it, and step 2335 is now carried out.

If the associator does not match the segment number generated in step 2330 contained, i.e. in step 2332 no branch was carried out, a subroutine FGSG 2336 is carried out, which transfers the segment number to the associator, so that the next time the segment number generated in 2330 is transferred to the associator 1319a is reported and a hit condition occurs. This subroutine also sets the U and W bits of the segment number both in the associator and in the main memory.

In any event, step 2335 is performed which sets the segment base and segment boundary for later use specifies. This step mainly transfers the segment base address and segment delimitation from the segment descriptor, which is now in the associative memory, into the working register of the address control unit 1319. The The segment boundary marks the end address in the memory. The exception routine "outside the segment" is carried out if the address to be derived exceeds the segment limit.

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While step 2335 is being performed, a return is made to the APLS subroutine in Figure 23c. Step 2323 is performed. Note, however, that step 2322 indicates a deviation in the APLS subroutine ; which does not retrieve the. FGO subroutine required. This situation occurs if an additional operation was previously carried out for the PLS semaphore address and therefore the use of the FGO subroutine would be superfluous. With the APLS subroutine, step 2323 transfers the PLS semaphore to the arithmetic logic unit 1317 in which certain tests are performed. In step 2324 a test is carried out on the two words of the PLS semaphore 901 (FIG. 16c). In this way the STAG field, bits 0 through 3, is checked to see if all bits are zero; bits 15 through 15 of the SMC field are checked to ensure that they are all zero; bits 16 through 31 of the MBZ field are checked to ensure that they are all zero, and the PLQP field, which indicates the next process link, is checked to determine whether it is a multiple of 8, since all process chains are two words long, as well as determining whether it is not zero, since the PLQP points to the first byte of the process chain.

If these tests pass with success, check step 2325 accesses the first process chain on the process chain semaphore by performing a memory tap operation of the 8 bytes of the concatenation. When the concatenation is not in the correct memory, the result occurs this overhead memory operation raises an exception. If the test is successful, the absolute address will be the chaining in position W30 of the scratch pad memory saved. If the PLQP index was zero, it means that no process chains are currently available.

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In other words, all the process chains available in the system are assigned to processes that are either waiting or ready, and for new ones, to starting processes, no further process chains are available. If this condition occurs, an exception is raised 2325a "missing process chaining" performed. When this very unusual situation occurs, there may be more than one existing Processes are interrupted so that their process links are available to the system. But when all of these tests are successful, the APLS subroutine is completed, so that again a return to Fig. 23a and to step 2302 takes place.

At step 2302 the question is "is this a P command?" If the answer is "no", i.e. if it is a V command, the MTT 2303 subroutine is carried out, which, as shown in Fig. 15, writes the message header. In the current situation, however, the answer is "Yes" and step 2304 of the PRIQ subroutine is performed.

The PRIQ subroutine sets the position of the straight running process that is to be put into the wait status. This positioning occurs on a priority basis in the queue of a semaphore. Priority positioning is required for all processes that are to be integrated or for messages to one Semaphore that has a STAG field, which priority integration indicates. The PRIQ subroutine compares the priority of either the process or the message chain, which is to be classified in the semaphore chains based on priority and ensures, depending on the priority classification type, i.e. FIFO or LIFO its incorporation. Used in the meantime

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the UQLK subroutine developed by the PRIQ subroutine Information and queues a new chain, and additionally changes any if necessary Information from other chains.

For purposes of illustration, the PRIQ subroutine will be described in connection with a situation where a P command has expired on a semaphore without success, i.e. the results of FIGS. 20 and 21. Furthermore, since the PRIQ subroutine 2304 involves a number of variables, one general, not with the result of naming the flowcharts matching designation given. For example, the designation PL in Figures 23e and 23f means the one to be classified Concatenation, the concatenation that is capable of either a process or a message chain to be. The designation QHP stands for a queue head shift, which can be the PQHP or MQHP for the semaphore, will be the designation in subroutine 2304 (I) used to indicate whether a FIFO chaining is used with priority or a LIFO chaining with priority is to be, and for this purpose in the auxiliary memory 1317a a flip-flop positioned. The name SNL is the next chaining field of the process chaining to be entered. The process chaining or message chaining that evolves is somewhere in the queue. Therefore, SNL identifies the next immediately following process or message chain. The first chain indicator indicates .ob the new concatenation in the head of the queue should be enqueued or not, i.e. when the subroutine has ended and the first chaining indicator is still the same One thing is that the added process or message chain is then the head chain of the queue. ULK stands for the process or message chaining that is immediately preceding

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of the new concatenation to be integrated occurs and therefore your "next concatenation" field must now be supplemented with the Identify the position of the newly added chain. The "next concatenation" field of ULK is identified by SREL.SREL is the value of the next link field in the ULK. If therefore the insertion of the process or message chain is required in the middle of the queue, the immediate The chaining before the newly inserted chaining is changed and receives the SREL value. In addition, indicates the newly inserted process or message chain the subsequent chain previously identified by ULK became.

In order to make the conversion currently carried out by the CRIQ 2304 easier to understand, reference is again made to FIG. 18 and in particular to q / PR / S5, to which the process chains 808a, 808b and 808c are attached. The process chain 805a from the PLS semaphore is incorporated into this queue with regard to priority. For purposes of illustration, the process chain 805a is identified as Z and its field ^u next chain "as SML. The process chains 1808a, 1808b and 1808c are later identified as process chains A, B and C. Concatenation A will contain a "next concatenation" field indicating B, and a process chain B will contain a "next concatenation" field indicating C, with the "next concatenation" field following C being zero Priority of the process chain Z corresponds to the priority of the current process that is to be put into the waiting status, are the positions of the process chain in this queue as well as those at the other process chains A, B, C and / or Semaphore S5 shows the changes to be made.

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More precisely, the step 2340 of FIG. 23e characterizes that SNL is set equal to the header of the queue, i.e. equal to the first process chain in the queue. The note »first chaining" is positioned on 1; in the meantime If it is established that the first chaining should not be changed, the first .linkage indicator becomes zero changed. ■

LK, the current chaining that is being checked at this point in time would then be the "next chaining" field of the process chaining Λ. Therefore, LK is originally a process chain A and ULK and the chain to be updated would also be a process chain Ji ..

At step 2341 the next question is whether the queue header equals zero. If the answer is yes, then this indicates an empty queue and step 2342 is carried out, the field ". next concatenation" of Z, i.e. · ' SNL, would be set to zero to indicate that there were no more concatenations in the queue and the process queue header of the semaphore would to indicate the process chaining to be added to the queue. If the concatenation would be a message chaining, the message chaining queue would indicate also positioned to indicate the message chain, as this is the only one Would be chaining in the queue. This would be like in Step 2343 shows the end of the PRIQ subroutine. Therefore, in this example, link Z, i.e. 805a, would be the only link in the queue attached to the semaphore represent.

In the aforementioned particular situation regarding semaphore S3, however, three process chains are associated with this semaphore, and therefore the answer to the question in 2341 would be "no". Hence the first \. ^r ort _f dh

509834/0830

Word 0 of process chain A tapped. In step 2345 the question is whether the priority of the process chain Z is lower than the priority of process chain A. If the answer to the question at 2345 is "yes", i. the priority of the process chain Z is the highest in the queue, this would mean that the process queue Z would be placed in front of process chain A. Therefore the position for the process chain has now been redefined. In the meantime, a subroutine UQLK would in the scratch pad memory in positions V / DB, WDC, WED and Pick up information from the WDE and complete the semaphore.

However, if the priority of the process chain Z is lower than that of process chain A, step 2346 would be performed. In step 2346 the question is whether the priority of Z is equal to A's priority. When this situation occurs, step 2347 asks whether the in step 2304 set I-parameter is equal to 1. If the I parameter is equal to 1, this indicates a LIFO inclusion, i.e. at same priority level "last in, first out". As a result, the concatenation Z would be at the head of the queue and step 2343 would be performed to terminate the subroutine. However, if the I parameter is not equal to 1, this indicates FIFO queuing, i.e., "first in, first out", which are being performed got to. Step 2348 would then be performed. It should be noted that if the process chaining priority Z, which would be greater than the priority of the process chain A, the step 2348 automatically, as in the "no '·' -output of Step 2346 would be performed.

Accordingly, the question in step 2348 is §both for FIFO as well as for the inclusion of lower priority (numerically higher value): "Is the next concatenation equal to zero?".

509834/0830

This refers to the "next concatenation" field of A. If the answer is "yes", this indicates that there are no further process chains with the queue of the "semaphore" connected, i.e. that only the process chain A was connected to the semaphore. Hence the Z process chaining - connected to the Α-process chain v / earth and would become the new end chaining of the queue. If this condition is met, step 2349 writes certain ones Information in the WDB, WDC and WDD positions of the scratch pad memory. This is done by the UQLK subroutine. This information stored in step 2349 is the following: The SNL of Z would be set to zero because there are none there are further links in the queue. The SREL is the "" next chaining "field of A and contains the fourth - which points to the Z process chaining. So SREL would become PL. In addition, the first chain would be changed to zero to indicate that the first chain was the queue is unchanged. Eventually the MQTP would send the semaphore if this was a message chaining would be changed to indicate that the Z message chaining is the last message chain. In the particular situation examined here, however, Z is a process chain and no message chaining and therefore MQTP would stay at zero. This would be done by another flip flop in the associative memory 1317a which would indicate whether a process is placed in the wait or ready state was or not or whether a message was queued incorporated or not. The end of the PRIQ would then be marked as shown in 2343.

However, if the "next concatenation" field is not zero would be what corresponds to the usual situation, since the process chains B and C are to be checked, step 2350

509834/0830

carried out. In order to keep track of the various concatenations now mentioned, concatenation A, which is LK, is now changed to ULK changed and the link B, which was the next link, now becomes LK and indicates that the process link B belongs to those to be checked. In step 2351, the first word of process chain B would be from main memory tapped and transferred to position ¥ 32 of the scratch pad memory. This field "next chaining" The process chain B is now checked to see whether it contains a multiple of 8 and whether it is how represented by steps 2351a and 2351b, respectively, is located within the GO segment. If these conditions are met are, step 2353, Fig. 23 * is performed. In this step the priority of the process chain Z is compared with that of the process chain B. When the priority of the process chaining Z is lower than that of the process chain B. the step 2351 indicates that the process chain Z is positioned in front of process chain B and behind process chain A. Hence, the information will be like at Step 2349 is written in positions WDB to WDE of the scratch pad memory, and in step 234-3 is that PRIQ subroutine ended. Therefore, the hint A "next chaining" would refer to the process chaining Z and the hint "Next chaining" "of the process chaining Z would refer to the process chaining B. This happens as follows: SNL, i.e. the "next chaining" field of Z takes the value ULK, i.e. the position of the process chaining B. Therefore, points Now the process link Z atf the process link B. SREL, i.e. the "next link" field of A, takes the value of PL on, i.e. the position of the process link Z. In addition, the PQHP, the MQHP and the MQTP would remain unchanged.

If the priority of process chain Z was equal to or greater than that of process chain B, a branch is made to step 2354 performed. This is step 2346

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similarly, the question was whether the priority of step 2345 was the same as that of step 2347. if so the priority of Z is equal to the priority of B in the answer to question 2354, and if the flip-flop is in ALU 1317a indicates that a LIFO queue is to be performed, step 2353 is performed and the information written into the scratch pad memory. If the I value however, it is set to zero and a FIFO enqueue indicates or if the priority of Z is lower than that of B, step 2356 is performed. This is a return loops at step 2348 to determine if process chain B is the last chain of the queue is. If this is not the case, the process chain C is tapped in step 2350 and, as already explained, the Completion of fields carried out. So if the priority of the process chain Z with respect to the other chains in the queue as shown in 1808a, 1808b and 1808c, has been determined, the> intermediate registers take the appropriate Information in the positions WDB-WDE of the scratch pad memory, which is then processed by the UQLK subroutine written into main memory.

In this way, the PRIQ subroutine determines whether either the process chaining with a Q / PR / S or Q / PR / FLS or the message chaining with Q / M / S, Q / ML / FLS in the queue is classified. The PRIQ subroutine stores this information in the temporary registers of the scratch pad memory. The subroutine UQLK later accesses these intermediate registers and the information is then stored in main memory along with all the concatenations in the queue written so that a logical sequence is guaranteed.

Upon completion of the PRIQ subroutine, a return is made to E of the VP subroutine 2121 of Figure 23a is performed. More accurate

509834/0830

Said step 2305 is performed next. In Step 2305 is the process chain 805a that resulted from the GO segment and the JP designation, the Priority value and the SRA value of the currently running process «· ses has written into process chain 805a in main memory.

After a process chain has been obtained, the currently running process must save the available information so that the When entering the functional status, no loss of Continuity occurs. Therefore, the next step must be to store what is currently available for the current process Information to be carried out. This is shown in step 2306, which corresponds to the one shown in FIG Subroutine RLLO refers.

The RLLO subroutine transfers the current information in a PCB shown in Figure 4. In performing this Operation is performed in step 2360 which is a URUA subroutine is. This is an offsetting subroutine which brings the runtime of the process up to date, which is about to leave the functional status. The URUA subroutine reports the total amount of computer time used, and therefore the amount of money that the user wished in Must be billed.

Steps 2361 to 2368 enable the contents of the general registers in the central processing unit 104 for transmission to the PCB described above. Therefore, step 2361 transfers the contents of status register 1311 to PCB byte address word 4 of the process control block. The step 2362 stores the contents of the T - "- register 1310 from ¹ S to address 28 of the PCB. Step 2363 computes the segmented address of the next

509834/0830

command to be sequenced contained in register 1312 and transfers this segmented address, as shown in step 2364, to address 32 of the process control block. At step 2365 the base registers identified generally at 1308 are transferred to addresses 52 and 80 of the process control block; Step 2366 transfers the general registers shown as 1307 to addresses 84 through / 144 of the process control block. In step 2367, the capability byte of the PCB is accessed and a check is made to determine if the scientific facility has been used. If so, the contents of scientific registers 1309 are stored in addresses 148 through 176 of the process control block and the subroutine completes its storage of current information. However, if the scientific facilities have not been used, the RLLO subroutine has already been completed. Therefore, the current status of the ongoing process, i. E. of the process that was in the function status and is now placed in the wait status is transferred to the process control block. When the process is over. the .. P. command requested information is available, the process is then restored to the function status, and no ^v erlust of continuity occurs.

At the end of the information transfer to the process control block the subroutine P of VP 2121 (Fig.21a) is again entered. In step 2307, which is executed next, the hardware gate already described is blocked and flagged bo that the system has passed into a critical status. During this time, the Main memory information in addition to the current process * - ses carried out, which changes to the waiting status.

509834/0830

In step 2308, the process chain 805a results from the PLS semaphore 901 in the GOJ segment, which is separated and was therefore released. In step 2309 the status byte of the process control block is changed to indicate that the process is now in the waiting status instead of the functional status is located. This is done in PM number zero, which is byte 3 in FIG. 4 for address 0 of the process control block is shown. In step 2310, address 8 of the process control block, i.e. PM # contains 2 words, the relative segment address and the segment number of the semaphore that was addressed and written here. In this way, the PCB receives the information it needs to set the semaphore on which the process is running waiting to locate.

Then step 2311 (Fig. 23h), which the UQLK subroutine represents performed. Before the PRIQ subroutine specified the position in which the Process chaining within the semaphore queue is saved. The UQLK subroutine performs the write operation, thus completing the contents of the Main memory to reflect the status of the system.

In step 2370, which is shown as the first step of the UQLK subroutine in FIG field transfer of main memory. in step 2371, the indicator is "the first concatenation" checked to determine if it is to 1, that is, whether that is to be updated chaining the head of the queue. If this answer is "yes' is ^1, is the Step 2372 is performed in which the question is, "Is this head process-

509834/0830

Chaining of the head of the ready queue Q / PR / RDY? ". This question is asked because the V command will later change the PRIQ and UQLK subroutines to transfer a process to Q / PR / RDY. If the answer is "yes", the above-described IQW-Y / ort is changed so that it now corresponds to the position of the one to be entered in step 2373 Process chaining indicates what the UQLK subroutine completes.

In the particular situation listed here, however, the answer is "no" and the question is asked at step 2375: "Is this a message chaining? ^11. If the answer is" yes ", the message queue header is updated at step 2376, whereby the position of the process chain is entered and the subroutine is ended.

509834/0830

If the answer to the question in step 2375 is "no", a process chain is updated and Step 2377 updates the PQHP indication of the "semaphore" with the address of the process chain PL from the memory location W31 of the scratch pad memory.

If the answer to the question at step 2371 was "no", this would indicate that the link to be entered was not at the head of the queue, and step 2378 would transfer the "next chaining" field to main memory. Therefore the field would be "next Concatenation "SREL of the concatenation that identifies the concatenation to be entered has been changed, and the" Next "field Concatenation "SNL of the entered concatenation would contain the PL field. In other words, the" next field Chaining "of the process chain Z to be added to the queue takes up SREL. This information are transmitted from the positions WDC and WDE of the scratch pad memory. If this is a Q / M / S, the MQTP is also completed and the UQLK subroutine is thus completed.

Looking back at Figure 23b, in step 2312, the SCT or FLSCT field is created if it is a free concatenation semaphore is now written in position WC4 of the scratch pad memory. The NSCT count has already been determined in step 2101 of FIG. 21 and in position WC7 of the scratch pad memory saved. In step 2313, the entire content of the semaphore that is in positions WC4 and WC5 of the Scratch pad memory is transferred to main memory to update the semaphore. Upon completion of this information conversion, the hardware gate is opened in step 2314 to identify that the critical status is now over and

509834/0830

The unoccupied gate in ALU 1317a is now in step 2315 is positioned to binary one to indicate that the current process has been taken out of functional status became. In step 2316 control of the system is transferred to the dispatcher unit ("FIG. 14) in order to control the next process to determine who is in the functional status should pass over.

This completes the operation of subroutine E of VP 2121, which shows the status of the ongoing process changed to the waiting status. As in the figures: 20 and 21, the current process attempted a P instruction on a no-message semaphore or a message semaphore perform. Since the process is unable to do this, it cannot continue until it the data are supplied, and now it goes into the waiting status on its own initiative. ·

In 'figure, _j 22a block 2200 where the SCT count was checked to determine whether it is lower than zero, thus indicating that a P-command on a message semaphore required a change of the current process in the waiting status, a branch to step 2205 would be carried out if the questions were answered with “no”. In step 2205 the question is whether the SCT field is equal to zero. If the answer to this question is "yes", a branch is made to 2206 of the PMZ subroutine shown in Figure 24a.

509834 / 083Q

D. TRANSMISSION OF MESSAGES WITHOUT USING A QUEUE

The PMZ subroutine is a special subroutine called for a test or non-test P instruction, which is carried out on a message semaphore if the SCT field of the semaphore is equal to zero. To this At this point, the subroutine determines whether a previous process is currently on a free message chain ocüer does not wait to send his message to a Transmit semaphore. This would occur in the situation in which all free message chains were previously were used and no further free message chains are available for carrying out processes who want to send messages. In this situation, described later, the ongoing process, the tries to send a message, put in the waiting status because it cannot send the message. Of the running process that executes a P instruction and first requests a message, tries to determine whether the above-mentioned situation occurred before entering the wait status on its own initiative. When the situation has arisen, the process which attempted to send a message becomes its own Message exempt, so that in this way its execution obstacle is removed; in addition, he is currently receiving running process, which executes the P command, the message so that it can remain in the function status. Therefore In this particular situation, the sending of a message for a message chain does not occur With the help of a previous V command, the process currently running is still receiving the message from a semaphore. So there is more of a mixed situation in which the process currently running is reporting via its PCB to a process that is pending.

509834/0830

- 145 - ■ - · '■

More specifically, in step 2400. Of Figure 24a the message queue tail pointer MQTP and the Message queue header MQHP checks the message semaphore to see if it's zero are, or not. Since the SCT field of the semaphore has the value Contains "zero", both conditions must be present, otherwise the condition of an illegal one "Semaphore" 2400a occurs. After this check, step 2401 executes a subroutine to find a free To tap the concatenation semaphore (FLSC is shown in 'Figure 24b shown). This subroutine uses the free concatenation semaphore and run a series of tests to determine its status. ,

More specifically, in step 2420 of. Figure 24b the first word of the semaphore descriptor segment that contains a free concatenation semaphore to be used should, tapped from the main memory and into the position WD2 of the scratch pad memory transferred. That first word is in. Figure - 15 shown as number 1500 ' represents. In step 2421 the following tests are performed by the ALU 137 on the first word. The TAG field, i.e. bits 0 to 1 are checked to determine whether its value is 11, bits 8-15 of the MBZ field become then checked whether they are "zero" and bits 16 to 31, i.e. the FLSP field, are checked to determine whether they contain a multiple of 8, since they refer to the first byte in the free concatenation semaphore 1504 that is indicated in the diagram of the SD segment in. Figure is shown. ■ "" ..

In step 2422, the FLSP indexed and in Figure. ^ 6d free concatenation semaphore represented as 1504 tapped. These three words are now respectively

5098 3 4/0 830

in positions WCB, WCC and WCD of the scratch pad memory is stored so that the following test can be performed in the arithmetic logic unit 1317 can. In step 2423 the STAG field, i.e. bits through 3, is checked to see if all are zero. In step 2424 the CCT field, i.e. bits 80 to as well as the FLSCT field, i.e. bits 16 to 31 of the in Fig. 16 The FLS 1504 illustrated is checked to see if it is greater than zero. Neither FLSCT nor CCT can ever be greater than zero. These fields are generally cleared to zero if free message chains are available and they can become negative if no free message chains are available. The absolute The value of these fields indicates the number of processes waiting to receive free message chains, i.e. the number of processes integrated in Q / PR / SLS. A check must therefore be carried out to determine whether this is larger are zero to determine whether or not the appropriate coding was performed for the free concatenation semaphore not.

In step 2425 the FLSCT field is checked to see if whether it is less than zero, since if it is less than zero, a Q / PR / SLS is attached to a free concatenation semaphore is. If the answer is "yes", step 2426 checks the PQHP field, i.e. bits 32-37 are then checked to see whether they are not equal to zero and also contain a multiple of 8. if SLSCT is zero, which is the only other possibility, this indicates that free message chaining may be available. Therefore, the PQHP hint of the free concatenation semaphore should be zero be; this corresponds to the test performed in step 2427.

509834/0830

If any of these tests are unsuccessful, an "illegal semaphore" exception occurs on.

In step 2428 the SMC field, bits 415, (the one shown in Fig. 16c also known as MBZ field) to see if it is equal to zero. This is the self-limitation of the free Concatenation semaphore, as it can never store message concatenations. Only free message chains are activated an FLS attached. The SMC field is therefore cleared to zero as the count value of the free concatenation semaphore should never have a positive value.

In step 2429 of FIG. 24c, the free concatenation hint, i.e. bits 48 to 63, which indicate the first free message concatenation, are checked to ensure that it contains a multiple of 8, since FLQP is the first Identifies free message concatenation that is four words long. In step 2430 the CCT field is i.e. bits 80 through 95 checked "to determine whether it is lower than zero. Previously, it was checked in step 2424 whether this field is greater than zero and this Test expresses with a "no" answer that it is the same Is zero and now the FLS subroutine 2431 is completed. If the answer to question by 2430 is "yes" is, step 2432, with which the MBZ field is checked, i.e. bits 64 to 71, is carried out, and the .FLSC subroutine exits. In this way, the FLSC subroutine doesn't just check the free one Concatenation semaphore to ensure that it is within the conceptual requirements of Figure i6d, it also stores the three words of the free concatenation semaphore for later use in positions WCB, WCC and WCD of the scratch pad memory.

5Q9834 / Q83Q

Upon exiting FLSC subroutine 2401, step 2402 in Figure 24a. In step 2402 the question is whether CCT is less than zero. If the answer is "yes" is, this indicates that no input / output channel is waiting for a free message chaining. In step 2403 the question is whether FLSCT is zero. If this is not the case, a process is in the waiting state Q / PR / FLS, and therefore the SPLQ subroutine 2404 is performed.

The SPLQ subroutine searches for the free process chaining queue, to determine whether there is a process in Q / PR / FLS that requires the performance of a V-operation, i.e. sending a message, tried on the same semaphore for which the currently running process issued a P command, i.e. a message query. Expressed differently, It is checked whether a release of the message requested by the P command was attempted beforehand, which was unsuccessful remained because no free message chains were available. This situation occurs when there is a previously running process tried to send a message to the SD segment which contained the free concatenation semaphore. Of the Process was unable to do this because no free message chains were available. Therefore the process is placed on hold and incorporated into Q / PR / FLS by E of the VP subroutine, with the result that it later transmits the message to the corresponding semaphore. However, this situation cannot occur if the current process is executing a P command which can be applied to the same message. The subroutine SPLQ 2404 checks whether this situation has occurred.

More specifically, in Figure 24d, the _e SPLQ subroutine refers to any process concatenations, the PR / FLS are incorporated in Q /,

509834/0830

- Ϊ49

to determine whether the displacement fields of a process chain, i.e. bit fields 48 through 63 of each process chain equal to the displacement field of the current one running process that is executing the P command. If a match is found, i.e. if the Displacement fields are the same, the message from the previously running process is carried over to the currently running process and the currently running process executing the P instruction remains in the functional state. If the values of the However, displacement fields are not the same, the currently running process executing the P instruction will be included in the Waiting status moved.

In Figure 24d, the step 2440 initializes a flip-flop in the auxiliary memory 1317a, which indicates that the first Chaining has been indexed in Q / PR / FLS. This flip-flop determines whether the PQHP field of the free chaining SEmaphor should be changed. If the status of the flip-flop remains the same, it indicates that 'the shift field the first process chain with Q / PR / FLS is the same as the P command and that a message has therefore been tapped. If the status of the flip-flop has been changed, the PQHP of the free concatenation semaphore remains unchanged. To this Thus, in step 2440, the variables PL and UPL are initialized. These variables are in the positions W31 and WE8 of the scratch pad memory and identify the process chain or the updated process chain. Regarding the to be checked Chaining the initial process, both PL and UPL identify the same process queue hint the process chaining.

In steps 2441 and 2442, the first and the second word of the process chain, which is the head-to-process chain from Q / PR / FLS, from main memory to the

509834/0830

ALU 1317 transferred. In step 2443 the field becomes "next chaining" i.e. bits 0-15 of the process chaining checks to see if it is a multiple of 8, since each process chain it addresses is a two-word size represents. In step 2444 the D-field of the process chain, i.e., bits 48 through 63 are compared to the SRA of the currently running process to see if they are the same or not. If the answer is "no", a question is asked in step 2445 whether that is The "next chaining" field of the process chaining is zero. i.e. whether there are additional processes, their process chaining to the free chaining semaphore are affiliated. If the answer is no, step 2446 is performed to reset the indicator Clear "first concatenation" to zero, thereby indicating that the PQHP of the free concatenation semaphore does not need to be changed, since the head-process chain remains the same. In addition, the Process chaining UPL is positioned in position WE8 of the scratch pad memory on the old PL supply, and, PL, i.e. the process chaining, is now changed to identify the "next chaining" field, which is the The next process chain would be incorporated into Q / PR / FLS. Then the steps are repeated 2441 through 2444 are performed on this second process chain to see if this is in the process chain Contained displacement field is equal to the relative segment address (SRA) of the current one Process. Which executes a .- 'P command or not.

If this condition is met, i.e. answered "yes" to the question in step 2444, then the execution takes place from step 2447, which is in auxiliary memory 1317a an indicator clears to zero to indicate that a process chaining

5098 34/08 30

was found that had the same displacement field, and the updated next link, i.e. UNL, is set equal to the next link in the queue. The UNL field contained in position WEG of the scratch pad memory changes the "next chaining" field to the one immediately before the removed process chaining Process link to the value of the process link that has the same displacement field. Therefore, the Queue a continuous sequence of notices for all process chaining that are attached to the free chaining semaphore. When that is done, the Step 2448, the end of the SPLQ subroutine, is performed. Note that step 2447 provides the information for the UPLQ subroutine described below that is used to write the new information into the Q / PR / FLS will.

If the D field (s) of the process chains connected to Q / PR / FLS is not equal to the SRA of the currently running process which is executing the P instruction, the Step 2449 displays the flip-flop described in step 2447 One and indicates that all process chaining of Q / PR / FLS were checked and none of the messages contained the message requested by the P command. Hence the end of the SPLQ subroutine performed and the UPLQ subroutine does not write the variables UPL and PL to the Q / PR / FLS queue.

Upon completion of the SPLQ subroutine 24o4, the step becomes 2405, asking if the process was found. This question mainly says whether the Process has been found which attempted a V command on the semaphore from which the P command retrieved a message. If the answer is yes, i.e. if the flip-flop

50983 ^ / 0830

2458534

is zero in step 2447, step 2406 asks whether this was a P test command; if the answer If "yes", 2407 sets a condition code in the status register 1311 to zero to indicate that the P instruction is being performed. Regardless of the one set in step 2406 Question, step 2408 calls the RNP subroutine which is assigned to the corresponds to the new ready process. Therefore, regardless of whether a P test command or a P command was executed, the Message transmitted to the process currently running that is executing the P command. Additionally, the process that tried one becomes Execute V command from subroutine RNT 2408 to ready status offset. Step 2409 is a transmission to the dispatcher described in FIG.

If the answer to the question in step 2405 is that no process was found, step 2410 poses the Ask if it's a T-test command. If the If the answer is "yes", a condition code in the status register 1311 is now positioned to one in step 2411 in order to indicate? show that the command will not be carried out; in step 2412 the command counter 1312 is incremented, and the current one current process is executing its next instruction.

If there is a P command for a message semaphore in step 24.10 was found and the process in progress received no message, a branch is made to E of the VP subroutine 2121 carried out in Fig.23a, which puts the currently running process in the waiting status and the dispatcher the possibility to select the new process to be placed in the functional state.

If in step 2403 the answer to the question of whether the FLSCT of the free chaining semaphore is zero, read "yes", thereby indicating that there were no process chaining to the free chaining semaphore existed, i.e. that no earlier

5098 34/08

Processes attempted to execute a V command and no free message chains were available, step 2413 is performed where the question is: "Is Is this a test command? ". If the answer is" yes, "a condition code is again set to one in step 2414. In addition, the command counter 1312 of the current process that is executing the P command is incremented in step 2415, and in step 2409 the next instruction is executed. If the answer to the question in step 2413 was "no", i.e. there was a command without a test on a message semaphore, as indicated by E of VP subroutine 2121, the process in progress is placed in the waiting state.

In Fig. 24a it was first assumed that the result of The answer to question 2402 was "no". However, if the answer was "^ a" indicating that processes there would be a subroutine that wanted to transmit a message from the input / output units 2416 carried out. This would be essentially the same operation that was described above for the "no" answer with the exception that it would be sent directly from the input / output unit and not from Q / LC / FLS. If there was no message to be sent, the currently running process would go into the waiting state and to that required for the execution of the P command Message waiting.

E. P command for a semaphore with a message whose SCT is greater than zero.

If it was found in Fig. 22a at step 2205 that the SCT field of the P command is not the same for a message semaphore Was zero, i.e. ' that the SCT field was greater than zero is known,

509834/0830

that the message requested by the current process is available. Therefore, the request of the P command is complied with and the current process can continue. More precisely, a branch to step 2207 is carried out in response to the question in 2205. In step 2207 the question is whether it is a test command. At this point it is known that the P command can be performed; however, a condition code must be positioned for a test command. Therefore, if the answer ^{11 is} yes ", a further question is asked in step 2208 whether the SCT field of the message semaphore for which the P command is intended is equal to one. If the answer is" yes ", the condition code is set to zero in the status register 1311; if the answer is "no", the condition code "2" is positioned in the status register 1311 as shown in steps 2209 and 2210, respectively. Codes identify the number of messages in Q / M / S to which the P command relates.

If the answer to the question in step 2207 is "or vice versa, was "yes" and the condition codes have been positioned, step 2211 is performed. At this point it is known that there is a message queue on the semaphore (Q / M / S) is present and certain tests are carried out on the semaphore to determine its legality. Therefore must in step 2211 both the message queue head MQHP and the message queue tail MQTP des Semaphore must be non-zero and a multiple of 8. In step 2212, the message chain that is in Head of Q / M / S is read out of the queue and the message is in the general register 1307 of the central Processing unit 104 transferred. The contents of the general registers are, according to Fig. 19a, in positions 00 to 03 of the Scratch pad memory transferred.

509834/0830

Next, step 2401 (FIG. 22b) is performed, which the FLSP subroutine already described in connection with FIG. 24b retrieves. This subroutine takes the free concatenation semaphore and checks its current one Status. This subroutine is carried out as a message chain has been released, which is now queued in the queue of the free message chains that are sent by .FLS, Q / ML / FLS has been indexed. In step 2213, the hardware gate becomes locked to indicate that a critical status occurs in the system. The inscription of the critical Status in "the memory is shown with the help of the in Fig.22e Subroutine RML, 2214, performed.

The subroutine RML enables the message chaining, whose Message in the currently running process that is executing the P command, is transmitted and also updates the "semaphore" and the Q / M / S in which the message chain was previously located. This is illustrated by steps 2230 through 2234 in Figure 22e. More specifically, step 2230 separates that in Q / M / S Message concatenation. This separation «Gperation; changed the Message queue header. of the semaphore that is is in position WC5 of the scratch pad memory, in the field "next chaining" of the first message chaining on Semaphore around. In step 2231, the is in the scratch pad position WC7 in the decremented semaphore count amount in the position WC4 of the scratch pad memory to indicate that there is now one message chain less on the message semaphore O / M / S is affiliated. In step 2232, the contents of positions WC4, WC5 of the scratch pad memory are transferred to main memory transferred so that the Semaphore now contains its current status. In this way the main memory position now indicates that the semaphore, whose new queue header identifies the first message chain; in step 2233 the free Message chaining now according to the LIFO rule in the Q / ML / FLS

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Queued up. This requires changing the FLQP hint of the free concatenation semaphore to refer to this Indicate message chaining, i.e. the information of the FLSC subroutine 2401 is now written. Additionally will the previous "FLQP content, which is the first concatenation in the Queue of free message chaining marked in the field "next chaining" of the free message chaining transferred to the Q / ML / FLS queue will. In this way, the logical structure of the free message chain remains intact. In step 2234 the hardware gate enabled to indicate the critical system status is over and the RML subroutine is completed.

At step 2215 of Figure 22b, the instruction counter becomes the current process incremented. This normally ends the P command, but it is a free message chain for Q / ML / FLS has become available and this free message chaining can be the first free message chain within the queue, a special situation occurs. These Situation arises from the fact that a previous process may have tried a V command to send a message to the SD segment of the FLS semaphore, but was unable to do so, so it is now desirable to transfer the Release message.

Therefore, in step 2216, the question is asked whether a carry the new command count has occurred in theB3error counter 1312; this question is asked whenever the instruction counter has been incremented. If the answer is "yes", the shows Step 2217 overflows the relative segment address and positions the command counter SRA to a dummy value (simulated value) from zero and also raises an exception "Exceeded segment limit". This is also done each time the command counter is incremented, e.g., step 2203 (Fig.22a).

509834/0830

If the answer to the question in 2216 was "no", step 2218 asks whether CGT is less than zero. In this situation it is necessary to have the free Check the concatenation semaphore to see if an input / output unit a free message chain at the Q / ML / FLS. If the answer is "no" is, i.e. the CCT count is equal to ZERO, step 2220 (Fig. 22c) is performed. He asks whether FLSCT of the free concatenation semaphore is NULL. If so, it indicates that there is no process at the moment waiting in the free process chaining incorporated in the free chaining semaphore. Therefore, the next instruction becomes 2221 carried out during the current process. If the answer to step 2220 is "no", i.e. processes were waiting to To be able to send messages, the system mode is set in 2222. System mode determines that the command has expired. If an error persists, the command that was just being executed is recognized as successfully executed. In step "2223, the FAR subroutine (tapped and Ready address, Fig. 25b) carried out. This becomes an earlier process which requires the execution of a V-instruction tried to put Q / PR / RDY in the ready queue and as a result, the dispatcher is displayed in step 2224. However, if CCT was less than zero in step 2218, i. there was an input / output unit that tried to send a message and no free message chains were available, step 2225 is performed to enter system mode to position because the command has been completed. Step 2226 in Figure 22d now calls the RLCM subroutine which enables the input / output unit to accept the message chain that has just been released and step 2227 deletes it the system mode and enables the execution of the next command in 2228. Therefore, in FIGS. 22b to 22d there were not only the P commands when requesting messages are successful, but

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_ 158 _

also the free message chaining that was previously sent The message saved is either to a free concatenation semaphore or to the semaphore on which an unsuccessful one V command was attempted, has been transmitted.

This makes the P operation on a message semaphore completed and the various situations that can arise depend on both the status of the semaphore and the Status of the free concatenation semaphore.

V commands for semaphores

If the answer to that asked in step 2026 (Fig.20b) If the question was "yes", i.e. a V-operation was performed, a transfer to VNJtfnterroutine 2027 occurs (Fig. 25a). There now follows a description of the various forms of V commands performed by the process in progress.

It is reminded again that the semaphore in Fig. 20 was tapped and that a pre-fortification was carried out became that a V operation should be performed. In step 2500 the question is whether the old SCT value, the is stored in position WC4 of the scratch pad memory, is less than zero, i.e. whether with the semaphore that detects processes are connected.

Therefore, this question does not concern the new semaphore count, which was anticipated in Fig. 20 and in a scratch pad position WC7 is stored. If the answer to the question in 2500 is "no", then the V command, if possible, queues another signal or message in the semaphore queue a.

More precisely, in step 2501, the operation code and the complementary code of the V command are checked to determine

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indicate whether a V-test command should be carried out. If the response indicates a no-test V command, check Step 2502, whether the maximum count of the semaphore (SMC) is equal to or greater than the new semaphore count that was stored in the scratch pad memory in step 2025. If the semaphore maximum count is less than the new semaphore count, it indicates that more data than were anticipated by the system have been included in a semaphore, and therefore an exception is made in 2502a triggered. However, if the semaphore indicates that more Data that can be saved will branch to it Step 2503 of the VP subroutine is performed, i.e., a V position. Before explaining this branch, steps 2504 to 2507 are carried out.

In step 2504 it has been determined that it is a Test command acted. Thereafter, as in step 2502, the question is asked whether the maximum count of the semaphore is equal to or greater than the new count of the in advance in step 2025 * - semaphore count field taken. If the answer is "no", i.e. if SCT is greater, the V command cannot be End to be led. Therefore, in step 2505, it becomes a condition code "3" is transferred to the status register 131I and to 2506 the command counter of the current process is incremented in order to carry out the next command. If the answer to the Question in 2504 is "yes" - this means that the semaphore store additional data and a branch to the V-positive subroutine occurs at step 2503. the V-positive subroutine shown in Figure 26 enables the integration of additional messages or signals in the semaphore,

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A, V command for semaphores with a positive SCT field 2456534

In step 2600 (FIG. 26), the operation code and the complementary code of the V command are checked in the command acquisition unit 1318 in order to determine whether it is a V operation on a non-message semaphore act or not. If the answer to the question in 2600 is "yes", a branch is made to step 2600a. Step 2600a checks the PHQP field to see if its value is equal to NULL. If the answer is "no", an "illegal semaphore" exception occurs in step 2600d. If the answer to the question asked in step 2600a is "yes", a branch is made to step 2601. In step 2601, the incremented SCT count developed in step 2024 of FIG. 20b is located within the scratch pad position WC7 and transferred to position WC4 of the scratch pad memory. In step 2602 the hardware gate is disabled and in step 2603 the incremented SCT count is written into the semaphore in main memory to indicate that another signal is available on the no message semaphore. In step 2604 the hardware gate is enabled to mark the end of critical system status and the completion of the issue.

However, if the V command in step 2600 is a message semaphore, step 2605 is performed. In step 2605 the question is asked whether the SCT field is greater than zero. It has already been established that the semaphore ^ count is not less than zero and therefore, if it is not greater than zero, it is equal to zero. If the answer is "no", the fields of the message queue tail MQTP and the message queue header MQHP of the message semaphore addressed by the V command are therefore checked for zeros in step 2606, since no Q / M / S should be present.

509834/0830

However, if the answer to step 2605 is "yes", i.e. am Semaphore, if there are messages, step 2607 is carried out, which checks both MQTP and MQHP to see if they are nonzero, as described earlier and are a multiple of 8. If this condition is met, step 2401, the FLSC subroutine, is performed. As already explained in FIG. 24b, this subroutine checks the free concatenation semaphore and stores it in the positions WCB, WCC and WCD of the scratch pad memory.

Upon returning from the subroutine, the type of operation is checked in step 2608. If it's a V command for a message semaphore, SEVFL, SEVTL, step 2609 is performed. If this is not the case, i. E. if it is an input-output instruction, a P instruction or an exception processing V operation, the Step 2608a and the SVP subroutine are performed. This subroutine allows messages to be sent to the "semaphore".

If, however, it is a V command of the current process, the FLQP field of the free Check the concatenation semaphore to see if it is zero. Notice that both the as well as the free concatenation semaphore have been checked for legality. When the FLQP index is not zero this indicates that free links are still available. Therefore, the one asked in step 2610 is Ask if it's a Test-V command. If the answer is "yes", then in step 2611 a condition code is generated is set to "2" and in both cases, i.e. whether it is a test V command or not, step 2612 is taken (Fig.26b) carried out.

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245653A

A check is made at step 2612 to determine whether the message chaining is within the SD segment is located. At this point the free chaining semaphore is about to release a free message chaining, to report the running process that is executing the V command, to write. It must be determined whether the free message chaining is within the spatial limits of the SD segment or not. If the message chain is within the segment, the priority of the current process is transferred to bits 24 to 27 of the free message chain. When this happens is, step 2613 performs a TAML subroutine which is the Access to the message chains is checked and, if the result is positive, the message chain to the semaphore queue Q / M / S queues.

The TAML subroutine is shown in Figure 26c and in step 2630 the question is asked even more specifically whether it is a V command for a message semaphore in which the message is ranked from the point of view of priority. Therefore this question checks the STAG field in the position WC4 of the scratch pad memory located semaphore this test shows a priority semaphore as the result, the question is asked whether the SCT value in step 2631 is equal to zero or not.

If the count of the semaphore is not equal to zero, indicates this. That message chains are connected to the semaphore queue Q / M / S and therefore the one shown in FIG. 23e The illustrated subroutine PRIQ 2304 is shown. The PRIQ subroutine defines, as already explained, the priority point of the message in the message chain and checks the Validity of the adjacent message chain. This information

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'-.163-

is stored in the scratch pad positions WDB to WDE by the PRIQ subroutine, so that the UQLK subroutine then writes the information into main memory. If the answer is "no" to the question in 2630, ie that no message semaphore is queued priority relative, or if the answer in 2631 "Y ^es", it is the SCT count zero and indicates that not report to the Semaphore are attached, the current position of the message chain is determined later. In step 2632 the first free message concatenation of a free concatenation semaphore Q / ML / FLS is transferred from the main memory to the ALU 1317 '. This free message chain would be the one that would be identified by the FLQP notice of the FLS semaphore. In step 2633, the "next chaining" field of the free message chaining is transferred to a position W32 in the scratch pad memory after checking whether it is a multiple of vision. This "next concatenation" field is finally transmitted back and written as the FLQP indication of the free concatenation semaphore. Therefore, the FLS semaphore identifies the second free message chain as the free head message chain of the queue, since the first free message chain is used by the V instruction. Subsequent to step 2633, the subroutine has run, and there is a return to step 2614 (FIG. 26b).

Step 2614 identifies the MTT subroutine shown in Fig. 23a was designated by 2303. The MTT subroutine denotes a movement function and is used for transmission some fields of the message in the buffer area used in the work zone. This is because the first word and a half, i.e. the one shown in Fig. 15 at 1508 Message prefix, must be created. The actual message, made up of the next two and a half words of the message wiring is generated by the running process.

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More specifically, in Fig. 26d, step 2640 becomes the STAG field i.e. bits 0 to 3 of the message semaphore checked. if the STAG field indicates that it is not a priority semaphore step 2641 is performed which sets the MPL field, i.e. bits 28 to 31, of the message header to 1111 this indicates that it is not a priority message. If, on the other hand, the STAG field indicates that it is a Priority message, step 2642 reads from general register number 1309 the priority of the process executing the V command. This priority is now used in the message priority field, bits 24 through 27, is written. Simultaneously a check is made on bits 28 through 31 of the message chain to see if there is a zero value in these four bits. If not, occurs as in the exception generated in step 2642a shown an exception "illegal data". In either case, step 2643 creates the TAG message, i.e. bits 20 through 23. At this particular point in time, all would be message TAGs equals zero because it is not an input / output operation. Therefore, step 2643 transmits the designation of the current process in bits 32 to 47 and thus identifies the process that carried out the V instruction. In step 2644, the message to be issued by the V command is now stored in the memory ″. Positions WE4 to WE7 of the buffer register are transferred. That message would be the next two and a half in the Message concatenation correspond to the words to be incorporated, i.e. bits 48 to 127. In step 2645, the is now in the cache registers The message prefix is transferred to the general register zero and the first 16 General register 1 bits of the current process. In this way there is now a complete message, which is to be fed to the message chain, in the

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general registers 0 to 3 of general registers 1309. If it would have been found that no iff chaining was available the process in progress would have been put on hold and its general registers would have the message held in the general registers zero to three of his PCB. That way, the MTT subroutine doesn't just evolve Messages, but also ensures that they are saved for later use *

Upon completion of the MTT subroutine, step 2616 in Figure 26b This step saves the absolute address of the Message chaining. Since the relative address is derived from the free Concatenation queue header FLQP, results, the absolute address is developed from this and in position ¥ 30 of the buffer register. In step 2617 the TTM subroutine is performed. This subroutine transmits the information, which is lined up in the form of a double word and in positions WE4 to WE7 of the buffer Area are contained in the haptic memory. In this way the TTM subroutine transmits the message chaining into the absolute address of the main memory.

The TTM subroutine is shown in FIG. 26e, and in particular it includes step 2648 which is derived from positions WE4 and WE5 of the buffer register, pulls out the first double word of the message chain and transfers it to main memory, as well as step 2649, which is the second from scratch pad positions WE6 and WE7 Pulls out the double word of the message chain and puts it in writes to the main memory.

After creating the message chain from the corresponding Information, step 2618 locks the hardware gate, thereby indicating that a critical operation is being performed

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and step 2619 executes the QML subroutine, with which the message chaining prepared in the TAML subroutine 2613 is transmitted. The reason for having two subroutines is that there is an undivided operation for the writing is required in the main memory and therefore a blocking of the hardware gate must be carried out. The preparation The information is not a critical operation and can be interrupted. Hence it becomes a separate subroutine carried out to the information before being registered in the Check main memory and if the hardware gate is locked, the second subroutine executes, as in QML 2619 in Fig.26f shown, the actual write operation by.

More specifically, the QML subroutine breaks the free message chaining from Q / ML / FLS and attaches the released message chain to the message semaphore. The released message chain is therefore either added to the message queue at the semaphore Q / M / S or forms the first message chain in the semaphore ^ queue. That way will in step 2650, the first free concatenation of the free concatenation semaphore is severed. This is done by starting from position 32 yen of the scratch pad memory the field "next chaining" of the just released message chaining to the FLQP notice of the FLS semaphore is transferred to the scratch pad position WCC. In step 2651, a V command is passed to the semaphore the question is asked: "Is the semaphore empty", i.e. are there already message chains on the semaphore? If the answer is "yes", there are no additional message chains queued for this semaphore enqueued, in which case step 2652 indicates that the message queue header and message queue tail notice of the Seffiaphor changed should be to the relative address of the acquired in step 2650 Display message chaining. In addition, the "next chaining" field of this message chaining is cleared to zero.

509834/0 830

Qa it is the only message chain that starts with is connected to the semaphore in Q / M / S. In the meantime, in Step 2653 the incremented SCT field of the semaphore from the Position WC7 of the scratch pad memory tapped and transferred to position ¥ C4. In step 2654, the entire Contents of the memory positions WC4 and WC5 of the scratch pad memory to the enabled message chains (step 2650) in main memory. Hence will not only the message in the message chain of the main memory instead, the "semaphore" indicating the message chain is updated via step 2654.

If the answer to the question in step 2651 is "no", i. that additional message chains. attached to this semaphore were, step 2655 asks whether it is an instruction executed on a priority semaphore will or not. If the answer is no, step 2656 asks if it is a FIFO V command acts. This is determined by checking the opcode and the complementary code, i.e. the first 12 bits of the V command in the command acquisition unit 1318. When the The answer is yes, i.e. if it is a FIFO queue this indicates that the message chain will take the last position within the queue. Therefore Step 2657 completes the message queue tailing of the semaphore and deletes the "next chaining" field of the message chaining to be added to the semaphore to zero because it is the last one in the queue. Steps 2653 and 2654 are now performed to both to add the semaphore as well as the message chaining?

If the answer to the question at 2656 is "no", a LIFO ranking is displayed and step 2658 completes that Message queue header of the semaphore and transmits the old message queue header information contained in the semaphore in the "next chaining" field, the message chaining incorporated in the semaphore. This results from

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that the generated by the V command of the currently running process Message is the first to be transmitted to a P command that refers to the same semaphore. Therefore it is sent to the Tip placed by Q / M / S. The steps 2653 and 2654 already described are then carried out.

If at step 2655 the answer to the question of whether priority s ranking was required was "yes", then those for ' the information required by the TAML subroutine 2613 (FIG. 26e) and, in particular, from the PRIQ subroutine 2304, to which the TAML subroutine relates. Therefore, the one in Fig. 23h-with 2311 UQLK subroutine described, and it writes this information for the process link fields in the Main memory. This situation occurs when it may be necessary to chain messages at any point to be inserted in the middle of the message associated with the semaphore. The UQLK subroutine 2311 arranges the message queue according to priorities, so that a sequential order of the fields "next chaining" is guaranteed. the Steps 2653 and 2654 transmit this information for the Semaphores, the message chains of which are lined up according to priority, in the main memory positions. Upon completion of the QML subroutine, Figure 26b indicates that step 2620 is carried out next and enables the hardware gate, which indicates that the critical system status is over After step 2620, step 2621 indicates that the instruction counter 1312 of the current process is incremented and the next instruction from 2622 is continued.

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B. V command for message semaphores if no free message chains are available.

If in FIG. 26a the answer to the question in step 2609 is "yes" read, that is, the FLQP indication of the FLS semaphore was zero, indicating that no free concatenations were available were, step 2623 asks whether it is a test command or not. If it is a V-Test command is, step 2624 indicates that the condition code in status register 1311 is set to one and the Instruction counter 1312 is incremented and in step 2622 the next instruction is performed. If the answer is in If step 2623 is "no", the process performing the V command has no reference point for sending its Message because no free message chaining is available from the free chaining semaphore of the SD segment that is shown in Fig.15. Therefore, in step 2625 the FLS semaphore changed so that it corresponds to a messageSrSemaphor and start a process. This corresponds to a semaphore with a negative SCT field in which a P command is carried out will. Therefore, the V command cannot be executed by the process in progress and for this reason the free one holds The concatenation semaphore defines the currently running process which is transferred to the waiting status. As this is a typical P operation is, step 2625 allows the information of the free concatenation semaphore to be changed, and step 2121, an E subroutine of VP, processes the FLS semaphore in the same way as a message semaphore that processes a P command receives. In step 2625 the free concatenation semaphore indication FLSP becomes the relative semaphore address, i.e. the SRA semaphore. The FLSCT count that was zero or less than zero because no free message chains were previously available are now decremented by one (i.e. minus 1) to indicate that the free concatenation nemaphore is the absolute Includes number of FLSCT processes that are unable

5.0.9034 / 08 30

are to send messages. As shown graphically, is the free concatenation semaphore to a semaphore. After step 2625, the E of the VP subroutine 2121 is performed which has already been described with reference to FIG. 23a and essentially a process queue at the free concatenation semaphore Q / PR / FLS forms by extracting a process chain from the GO segment shown in FIG currently running process placed in the waiting status. This completes V commands for semaphores, their SCT fields are greater than zero.

C.V commands for a semaphore with a negative SCT field

If the answer to the question in step 2500 of Figure 25a, whether the old SCT value was less than zero was "yes", this indicates that processes previously fetched data from the semaphore to have. Since the semaphore did not contain any data, the processes were placed in the wait state until data was available was. Since a V command is now being carried out on the semaphore, not only does the previous process receive the data required to exit the wait state, but the present process The running process is also able to send its message and therefore remain in the functional status describe the remaining parts of Fig.25 functions ,, the be carried out both in the process that is currently running and in a process that has been placed in the waiting status, since no data was available.

More specifically, steps 2508-2512 develop both message and no-message semaphores, and step 2513 transfers the information from the process currently running, which is executing a V command, to the one on the semaphore Process that obtained the data. Therefore, step 2508 asks whether this is a V operation on a no-message semaphore act or not. If the answer is yes, it means there is a queue of processes

509334/0830

is on the no-message semaphore, i.e. Q / PR / S, the process wait The semaphore's snake header is checked in step 2509 to see if it is a multiple of 8 and is non-zero or not. If the answer to the question of whether it is a V operation on a message semaphore if it was "no", step 2510 asks whether it is a test-V command for a training semaphore If it is a test command, a Condition code set to zero in step 2511 and indicates that the SCT value is not only negative, but that "also the process of executing the V instruction in the Waiting status is put. In both cases, i.e. whether it is a test command or not, step 2512 is carried out, to verify that both the message queue tail indicator is zero because it is a Q / PR / S, and the process queue header is not zero either and for reasons already mentioned is a multiple of 8.

If the semaphore is legal, then in step 2513 the FAR subroutine becomes , i.e. the acquisition and readiness process is carried out. Eli-ese subroutine transfers the message to the head process at the semaphore and thus executes the V command for the message semaphore over. Additionally: this subroutine changes the PCB of the process that receives the message so that the dispatcher can put the process on the ready queue.

The FAR subroutine 2513 is shown in Figure 25b. More accurate In other words, the first step of the FAR subroutine is used to access the functions already described in connection with FIG. 23d FGO subroutine 2321. The FGO subroutine develops the head

Index for the GO segment. In step 2520, the first concatenation of the semaphore containing the process is accessed (Q / PR / S). In this way, the process queue becomes the header of the semaphore is added to the address developed from the FGO subroutine to create the required process chaining to create. It should be noted that, in the case of a free concatenation semaphore, the process chaining is derived from the PQHP field which would be added to the address of the GO segment in step 2520. Then takes place at step 2521 an additional operation to the RNP subroutine and the FAR subroutine is brought to an end.

The RNP subroutine 2521 is shown in Figure 25c. Its purpose is to bring the waiting process to the ready state. This subroutine was also performed in step 2408 of Figure 24a when
a process on the FLS semaphore sends its message
It is reminded once again that
the situation the current process, which
performed a P instruction to request a message
force. This message was not sent because no free message chains are available at this point in time
was. Therefore the message was transmitted and the process that was unable to send its message was then taken out of the waiting status and into the
Queued ready. At this point, explanation of the RNP subroutine has been postponed.

In addition to the functions mentioned above, the RNP subroutine can, as a result of the dispatcher function, the
Save the currently running process if the
Process headed by the ready queue
has a higher priority. This will be more detailed
explained in Fig. 14.

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Because the RNP subroutine is in connection with a process other than the one currently in the functional state expires, it must first locate this other process. Therefore, step 2522 calls the PCBA subroutine described in Fig.25h is shown. This subroutine acquires the absolute address of the process control block which the Contains a pending process. More specifically, in step 2560, the P-table hint, who uses the J number is tapped. According to FIGS. 5 and 17, this leads to the J table being derived from the System basis results and now the TabelLe is indexed with the J number to provide a hint for the P table to develop.

At step 2561, the reference to the P table is referenced and the P number is now indexed and added with the note to develop the address of the process control block from the P table. The address of the Process control blocks are now transferred from main memory to arithmetic logic unit 1317 transferred. In step 2562 the first bit is checked to identify that the process control block is in memory, i.e. that it is not an empty process control block acts that could have been interrupted. In addition, tests are performed on bits 1 to 7 to determine whether all are at zero. The remaining parts of the first word are now transferred to step 2563 in the scratch pad memory position NJA, Fig. 19a, transferred, since these 24 bits are the absolute address for the process control block represent.

Upon completion of subroutine PCBA 2522, step 2523 becomes of Fig. 25c performed. In step 2523 the Opera * tionsCode and the complementary code of the command are checked.

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If it is an input / output command, step 2524 is performed which gives the one message representative data and stores them in the PCB address plus 84 which is the address of the general register O is in the PCB. If it is a message V command or is a test message V command, step transmits 2525 the information of the current process stored in GRO to GRj5 of the general register by means of the MTT subroutine, identified as 2614 in Figure 26d is in the cache area. Step 2524 now retransmits the message to PCB address plus 84.

In either case, the TTM subroutine, step 2617, performed to write a message into main memory. This transfer is made by the cache positions WE4 to WE7 carried out to the process control block.

If, in step 2523, the opcode check indicated that a no-message semaphore had a V command was present, it would not be necessary to store messages in positions +84 of the process control block. In either case, however, step 2527 is performed which detects the internal queue word which identified the head of the ready queue. It must be noted that at this point an additional Input from 2528 is shown indicating branching from a start instruction. The start command only requires a few processes to be transferred to the ready queue and therefore requires localization of the IQW word.

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After the internal process queue word has been tapped, the subroutine PRIQ described in FIG. 23e 2304 carried out. This subroutine determines if the process previously performed a P operation on the semaphore has, i.e. a process that is now in the waiting status, is compared to the ready queue,. Q / PR / RDY. The PRIQ subroutine checks the priority of the processes in the ready queue with the help of those in the process chains Priority fields to determine the storage position of the process chain within the ready queue. The PRIQ subroutine does not perform an effective memory write operation by.

In step 2529, Fig. 25d, the UACW subroutine is performed, which updates the accounting words in the process control block. This subroutine calculates the total time that the process has been waiting for. In step 2530, the operation code is again in the command acquisition unit 1318 is checked to see if a start command is being performed. If it is a start command, a Branch taken to step 2531, in which the Process designation and the priority byte of the initialized process are stored in a process chain will. In step 2532 the priority of the PCB the current proceedings in the process »concatenation. Therefore, this step updates the priority byte transferred from the scratch pad memory when a Priority change of the priority byte had occurred.

However, if it is not a start command, the process is taken out of the wait status, i.e.

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a process chain already exists. Therefore In step 2533, the priority of the process which, as indicated by the process chain, is in the Waiting status was transferred to the NJP position (Fig. 19a) of the scratch pad memory. This is done since the priority in the process link field of a process is the latest version of the current priority is. Therefore, if there was a priority change while if the process was in the waiting status, this would not be indicated by the process link field.

In step 2534, Fig. 25e, the operation code is checked again to determine whether it is a P command, either test or non-test command, for a message semaphore whose SCT field is zero. this results from the branching from the PMZ subroutine from FIG. 24a, the RNP subroutine in step 2408 called. If this condition is present, in step 2535 the contents of the process control block of the pro "process, which was in the waiting status, i.e. the values in the address plus 84, in the positions GRO to GR3 of the general register of the process currently executing the P command. It'll point again indicated that the PCB of the pending process. Contains a message because there are no free message chains were available. Therefore the process was incorporated into Q / PR / FLS. A P command is now carried out and the PNZ subroutine has determined that the displacement fields are the same. Therefore, transmission of the message is made from the process in Q / PR / FLS carried out. Then, in step 2536, the hardware gate locked to indicate that the system has passed into a critical functional status and in step 2537 the UPLQ subroutine is performed. This subroutine removes a. Process chain and updates the Q / PR / FLS as shown in Figure 25i.

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Therefore, a test is performed in step 2580 to determine whether the first chaining indicator is equal to zero, i.e. whether this is the process chaining located at the head of the queue that should be removed from the ground. If it does. is, step 2581 indicates that the process chains form the head of the queue and now becomes the process link head Note in the position WE5 of the scratch pad memory with the content of the in the scratch pad position WE9 saved UML updated. However, if it is not the head of the queue, in step 2582 it is the old one Process queue header is the same as the new process queue header and the "next chaining" field The 'removed process link is transferred to the link immediately in front of it. In this way identifies the immediately preceding chaining, the process chaining previously identified by the removed process chaining, and thus ensures a logical connection of all process chains in Q / PR / FLS.Drese chain information corresponds to that of the SPLQ subroutine in the scratch pad positions WE8 and WE9 stored information.

If the answer to the question at 2534 was "no", indicating that no special condition was present, a branch is made to step 2538. Since a number of commands can result from a "no" answer, the question is asked in step 2538 whether it is a SECIN, start, or P or P test command for a message semaphore. If the answer is yes, a branch is taken to 2539. This branch is performed because the disconnection from a Q / PR / S or Q / PR / FLS of step 2555 is delayed (FIG. 25g). However, if the answer to question 2538 is no, how do you do it?

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if this were the case with V commands, step 2540 disables that Hardware gate and step 2541 separates the process chaining from the semaphore Q / PR / S or Q / PL / FLS, i.e. the process chaining is tapped from the queue in which it is located is located. The concatenation removed is also added to Q / PR / RDY. In step 2542 the addressed semaphore with a new SCT field both in the. Scratch pad memory like also written to main memory. This marks the new status of the semaphore. Step 2542 is also performed when the PMZ subroutine has been called. The hardware gate is then enabled in step 2543, to indicate that the indivisible critical operation is over.

At this point the process previously held by the semaphore has received the data it previously requested. But when If the P command cannot be carried out, the content of the command counter of the current process remains the same as in the case where the process is put on hold. Therefore, when a process returns to the functional status, shows the instruction counter indicates that a P instruction is to be performed. Since the P command of the process has now been executed, i. has received its message, the content stored in PCB must of the command counter can be incremented by four «, this will the process at the next instruction before executing its P instruction started, steps 2544 through 2547 perform this Change in the content of the command counter.

In step 2544 the MBZ field became the instruction payer word then checked to see if it was zero. In step 2545 the relative address stored in the instruction counter is increased by four thus enabling the instruction counter to indicate the next instruction to be performed. In step 2546, FIG. 25f, this new Address for the command counter input in the process control block of the Enrolled in the process that carried out the P command,

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A check is made at step 2547 to determine determine whether the incremented address has crossed the segment or not. This situation can occur when the command counter is incremented. Therefore, the process taken out of the wait status is now able to function in the functional state when the dispatcher has transmitted it.

Step 2548 is performed if the branch from Step 2539 which indicates the occurrence of a SECIN, Start, or P or Test-P command on a message semaphore or according to the increment of the command counter of the process that was in the waiting state. In step 2548 the hardware gate is blocked again to identify that a critical system status occurs again and in step 2549 the status byte of the process that is currently has been added, positioned in the ready state so that the dispatcher can put it on the ready queue can.

In step 2550, FIG. 25g, the question is asked again, whether it is a start command. If the answer is "yes", then in step 2551 the process chain that contains the Contains information regarding the initialized process from the queue of the process links at the process link semaphore Q / PE / PL'S removed and the dispute indicator is positioned at one. The dispute indicator is positioned if one or more processes have been carried out by the currently running process since the beginning of the last one Command have been placed in the ready queue. Of the Dispute indicator identifies the possibility of a conflict between the head process of the ready queue and the current one ongoing process in terms of function status. Subsequently, in step 2311, the process already described in connection with FIG. 23h UQLK described subroutine is carried out, which the PRIQ-

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Process chains specified in the subroutine have been added. In step 2553 the hardware gate is released again,

j.

since the critical system operation is now over. Also, the RNP subroutine has ended, so this Branch determine that in the RNP subroutine both the currently running process that carried out a V instruction, as well as the process that was started by the currently running process is completed.

However, if the answer to the question in 2550 was "no", becomes the question already asked in step 2534 in step 2554 asked again, i.e. whether it is a SECIN, or a P or a test or a non-test command on a The message semaphore has an SCT amount equal to zero is. For the P commands, this ranking has already been carried out by the UPLQ subroutine. Hence it becomes a branch to step 2552 because a process is in the ready queue and a comparison of the priorities of the ongoing process with what is in the "head" of Q / PR / RDY Process is carried out. Therefore, at this branch it can be seen that the RNP subroutine as well as the currently running Process that sends a P command to a message semaphore performed and updated the pending process associated with the free concatenation semaphore, since no free message chains were available.

However, if the conditions of the question in 2554 have not been met, i.e. if the SCT count is not equal to zero, or it was not one of the commands listed above, step 2555 'is performed which is the new Process chaining removed from the V / art loop, i.e. either Q / PR / S or Q / PR / FLS, and in step 2556 the supplemented SCT value is taken from position WC7 of the scratch pad memory tapped and transferred to the process chain. At step 2557 the question is asked whether it is is or is not a V instruction for a no-message semaphore.

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If so, step 2558 writes the name of the process whose process chaining is being removed from Q / PR / S in the hold field of the semaphore, i.e. as shown in Fig. 16, bits 48 through 63. In addition, step 2558 updates the semaphore with all in positions WC4 and WC5 of the scratch pad memory, i.e. the new updated SCT generated in 2556 and all changed queue notices that may have occurred previously. When the non-message semaphore is fully updated the controversy indicator is set to one in step 2552 to indicate that a new process is in the ready queue queued because the last command of the current process was executed. The ones already mentioned Steps, i.e., steps 2311 and 2553, are now performed and cause the RNP subroutine to be terminated. Therefore At this branch you can see that an RNP subroutine contains both the process currently running and a V instruction on a no-message semaphore, as well as the waiting! process that uses the no-message semaphore connected, updated.

However, if the answer to the question in step 2557 is "no" and indicated that it was a V instruction for a message semaphore, then step 2559 would in the semaphore located in the main memory a new header note that changes Q / PR / S and writes a new counting field and steps 2552 (the positioning sequence already discussed) are performed. It can therefore be seen that with this Branch the RNP subroutine as well as the current process that is executing a V instruction on a message semaphore, as well as a pending process associated with the message semaphore.

Upon completion of the RNP subroutine, a return is made to step 2514, Fig. 25a, in which the instruction counter

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is incremented for the currently running process. In In step 2515, the dispatcher is called and the previously updated process is transferred to the ready queue and also gives the dispatcher the ability to determine which process is in the functional status should be located, i.e. should respond to the "streak" indicator positioned at "1".

Semaphore initialization command

The structures of a semaphore and all fields that are used to carry it out process synchronization have already been explained. When a semaphore is holding back identifies an unusually large number of events, i.e. messages for a message semaphore and resources for a non-message semaphore, within the processor can be a critical situation occur. For example, if a message semaphore accepts a large number of messages and therefore requests a corresponding number of message chains, are the free message chains shown in FIGS. 15, 17 and 18 within the SD segment not for the other message semaphores within the same SD segment available. This situation can, for example, indicate a breakdown within the communication structure. To a flawless Ensure the functioning of the semaphore or, on the other hand, return the semaphore to its original status a semaphore initialization command (SECIN) is used. This command puts the semaphore in a defined status in which he has either his SCT count field to zero or, in the case of a no-message semaphore, to a value that corresponds to the number of originally intended Resources.

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It has already been explained that a negative SCT field of the Semaphore specifies the number of processes associated with the semaphore. The SECIN command does not initialize a semaphore with associated with the process, since this operation is the process.; would destroy itself. This results from the fact that every process connected to the semaphore is in the waiting state and is waiting for an incident to occur. Since the SECIN command does not generate this incident, the Process cannot be put into the ready state. Hence the process would define itself as "sick" in one Status and not accepted by the processor. Therefore, the job that the process was supposed to do ·· never would executed and the later execution of processes would be prevented.

The same situation would not occur if the semaphore would have a queue of messages or facilities. By removing messages or resources only current data is destroyed. This running data may have caused the error condition. More importantly, there none of the processes has been destroyed, it is a return to an earlier state and the further expiry of Processes is not prevented.

In the case of a message semaphore in particular, the SCT field the semaphore is gradually cleared to zero; this way Q / M / S will be emptied and all related messages and Message chains are released. The SCT field never will initialized for a position number, as this requires the inclusion of unknown messages in the queue would. However, this situation cannot apply to non-message semaphores which can denote auxiliary sources. It is possible to have a specified number of available To have resources ready. Therefore, the number of available sources of help can fall into the SCT field of non-

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Message sempahores are transmitted during initialization, so that the processes use these resources when needed can.

These properties are easier to understand by looking at Figs. 27a and 27b, in which the functions are shown that occur when executing a SECIN command.

In Fig. 20 is the general subroutine for developing a Semaphore descriptors have been represented. This semaphore descriptor acquisition subroutine 2000 is for the operation code, the complementary code and the address syllable of the SECIN command accessible. In response to the operation and complement codes of the SECIN instruction, a branch was made at step 2022 to the SECIN subroutine. Therefore, when entering the SECIN subroutine in Fig. 27a, the segment descriptor, the Semaphore descriptor and the semaphore itself, from main memory tapped and checked for possible errors. The . SECIN subroutine takes effect on the semaphore itself.

More specifically, in step 2701, the SCT field of the semaphore becomes checked to see if it is equal to or greater than zero. If it is less than zero, this indicates that processes are associated with the semaphore. The SECIN command does not change a semaphore, the one Process queue, as this is the later sequence such processes. Therefore, if SCT is less than zero, an illeagle semaphore initialization exception occurs 2702 on. However, if the SCT field was equal to or greater than zero, step 2703 is performed to set the STAG field to check the semaphore for its validity. The codings of the STAG field have already been shown in FIG. In Step 2704 is the question of whether it is a no-message semaphore acts. If the STAG field indicates that it is a no-message semaphore, a branch is made performed to step 2705.

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In the case of a SECIN command for a non-message ^ semaphore, is a general register of the process executing the SECIN instruction has been loaded with a number "N". Because a non-message semaphore Can identify a number of resources that can be found in the general register of the ongoing process The loaded number must be the same as the originally requested number of resources, which is represented by the semaphore. Hence will in step 2705 the contents of the already loaded general register are checked to see if its value is lower than is zero. If the answer is "yes", an illegal occurs Semphore initialization exception 2705a because a negative Counter value something that is not possible, i.e. indicates a number of negative sources of help.

However, if the answer to step 2705 is "no", then in step 2706 the value stored in the general register is checked to see if it is less than the contents of the maximum count field SMC of the semaphore. Since the number in the general register becomes the number of the SCT field, the requirements indicated in Fig. 16 are retrieved. Recall that the SCT count had to be equal to or less than the SMC count to facilitate management of memory space. So if the SCT count is larger, there is an illegal condition for the semaphore because there would be more resources on the semaphore than intended. ₀ If this situation occurred, an exception would be generated every time the semaphore is used. Therefore, if the number contained in the general register is greater than the SMC field, an illegal semaphore initialization exception 2705a occurs »

However, assuming that the value in the general register is less than or equal to that of the maximum semaphore count field, the initialized information of the semaphore is written into its main memory position in step 2707. More accurate

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In other words, the semaphore's SCT-PeId receives the contents of the general register and is therefore set either to zero or to the positive number indicated by the general register; the process queue header, bits through 47, is set to zero, since no process queue is associated with this non-message semaphore; Finally, the TEP field, bits 48 to 63, is set to zero, since no process has performed a V command on the semaphore. The last-mentioned condition results from the fact that the semaphore has just been initialized, and therefore the V commands previously successfully executed on the semaphore are now neglected. In this way, the <hs non-message semaphore is initialized and now contains the information required for a P or V command that relates to this semaphore.

After the semaphore is initialized, step 2708 increments the instruction counter for the process performing the SECIN instruction and in step 2709 the next instruction is executed.

If the answer to the question in step 2704 was "no", i.e., the addressed semaphore was a message semaphore, removed the SECIN command all message chains that start with the More specifically, step 2710 sets a condition code in status register 1311 to a value of 3. If the semaphore count is found to be initial Was zero, this condition code "3-" is retained at the end of the command. 2711 now checks the SCT field des Message semaphore to determine whether the SCT field is equal to zero, i.e. whether message chains are connected to the semaphore are. If there are no message chains, i.e. if the answer is yes, the Message Queue Tail Hint field becomes MQTP and the Message Queue Header field MQHP checks the message semaphore to see if they contain message chains.

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Since step 2711 indicated that none should be present, both fields must contain zeros. Then the Instruction counter for the process that executes the SECIN instruction, incremented again by means of step 2708 and the next command is executed. Therefore, if the SCT field is already is at zero, the SECIN command does not need to remove any messages, and a condition code "3" indicates this situation.

However, if the SCT count is non-zero, i.e. the The answer to question 2711 is "no", it is known that the SCT count is greater than zero and no message chaining have messages associated with the semaphore. Therefore, a branch is made to step 2713, Fig.27b performed. In step 2714 the MQHP and MQTP fields of the message semaphore are checked. Da with the semaphore Message chains are connected, both MQHP and MQTP must be non-zero and a multiple of 8. To Checking the legality of the semaphore in step 2714, a branch is made to that shown in Fig. 24b FLSC 2401 subroutine performed. This subroutine checks not just the free concatenation semaphore to ensure that it is within the conceptual requirements 16D, but also stores the three words in positions WDB, WDC and WDD of the scratch pad memory of the free concatenation semaphore. This free concatenation semaphore will include the message chain to be released.

After subroutine FLSC 2401 is called in step 2715 the counting field of the in the scratch pad position WC4, Fig. 20, stored semaphore, decremented by one and transferred to position WC7 of the scratch pad memory. This is done since it is to be expected that a message chain from Semaphore is released. In step 2716, the MQHP field of the semaphore designated message chain is addressed

50 9834/08 3 0

and transferred to the scratch pad position ¥ 31. This chain of messages is the one from the message queue at the semaphore Q / M / S should be released.

After receipt of the message chaining to be released and the free chaining semaphore that the free message chaining is to receive, the hardware gate is disabled in step 2717 to indicate that a critical system operation is being performed will. This critical system operation consists of rewriting the free concatenation semaphore and the Semaphore, which contains the message chaining, in the main memory. As already shown in FIG of the RML subroutine (step 2214) is performed. The RML subroutine separates the message chain from Q / M / S by it changes the "next concatenation" field of the message concatenation so that it is placed in the queue of the free concatenation semaphore, Q / ML / FLS, is classified. In addition, the RML subroutine updates the fields of the message semaphore so that the released message chain is no longer connected to Q./M/S. This includes writing the new one Semaphore count NSCT developed in step 2715 to position ¥ C4 of the scratch pad memory and adding from MQHP to identify the next message chain in Q / M / S. At this point is the first message chain released from Q / M / S.

Since a free message chain was applied to the free chain semaphore in step 2718, the Question gesture. It, whether the channel count of the free concatenation semaphore, i.e. bits 80 to 95, is less than zero. This question determines in step 2718 whether there is an input / output process has been waiting for the free message chain that has just been released. If the CCT count is less than zero, has a Input / output process waited for a free message chaining, and steps 2719 through 2721 are performed.

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In step 2719, the condition code in status register 1311 is set to 2 to indicate that an input-output operation has included a free message chain. In step 2720 an RLCM subroutine is performed. The RLCM subroutine transmits a message chain to the input / output process by simulating a V command.

At the end of the RLCM subroutine, branch 2721 is taken, which checks the semaphore again triggers in its new status. Therefore, at step 2722, the question is asked whether the semaphore's SCT count is now equals zero. If this is the case, i.e. if no additional message chains are connected to the semaphore the semaphore is checked for legality at step 2712 and the next instruction for the current process is performed. If this is not the case, another message chain is created of the semaphore, as represented by the branch in step 2713, is released.

However, if the answer to the question at step 2718 was "no", a condition code "1" is set to indicate that the message chain has been transmitted to the Q / ML / FLS. The question is then asked in step 2725 whether the count value of the free concatenation semaphore, the FLSCT field, is less than zero. This question determines whether there is a process queue at the free concatenation semaphore Q / PR / FLS, ie whether a process has tried to execute a V command without success and is in the control room connected to Q / PR / FLS Status has been moved. At this point it is known that message chaining has been released. Therefore, the process that attempted to execute a V command without success can now execute it because a free message chaining has been attached to the free chaining semaphore. Therefore, if the answer to the question in step 2725 is "yes" ¹¹ , the FAR subroutine 2513 is performed.

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. 190>

The subroutine has already been described in Fig. 25 and essentially puts the waiting process into the ready state and into the Q / PR / RDY so that he can try again to execute his V command on the message semaphore. Therefore can use the free one that has just been released by the SECIN command Message chaining can now be used to execute a previously attempted V command.

However, if the answer to the question in step 2725 is "no" and thereby indicated that no process was waiting for a free message chain, the free message chain would become incorporated into the free message chaining queue Q / ML / FLS. Now step 2726 would set a condition code in the status register to zero. Then the Step 2722 the question of whether additional message chains are attached to the semaphore. If the answer is "yes", i.e. no further message chains are attached to the semaphore, the legality of the semaphore is checked again and the next command is executed as shown in Fig. 27a. If the answer is "no", the next will Message chaining checked and another message chaining is released. The same steps i.e. the Steps 2714 through 2725 are performed until there are no more Message chains are connected to the message semaphore.

This is how the SECIN command enables message semaphores a release of the message chains attached to the semaphore Q / M / S for single classification in the free message chain control room snake Q / ML / FLS. In addition, the instruction places the same number of processes as in Q / PR / FLS into the ready queue Q / PR / RDY, since each released message chain is a potential chain for a represents previously unsuccessful V command. Continue to be

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the fields SCT, MQHP and MQTP are initialized to zero. At a Non-message semaphore, the SECIN command initializes the FCT field either to zero or to a positive value and the TEP field to zero.

General description of events outside of the process controlling the central unit.

It has already been explained that a process is a unit of work at the level of which the system resources are allocated. While many processes can be in an active state, only one process at a time has control over the central processing unit. If this process requires additional resources to process its procedure, it calls up the resources using a P command that refers to a semaphore assigned to the resource. This semaphore then shows the availability of the resource. In addition, the availability of the auxiliary source is given by a V command on the corresponding semaphore, the semaphore indicating whether a process is waiting for the auxiliary source. The P and V commands can also be used to transfer information relating to certain so-called internal events between processes (internal events are those generated and received by processes known to the central unit and by the process control blocks are PCB ¹ S).

It has previously been written of internal events that them from the process that is in control of the central processing unit has to be transferred by executing a V command,

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However, there is another possibility, such as external events can be transferred to processes of the central processing subsystem. If this transfer is required is, is from the hardware / firmware of the data processing machine via a mechanism called the system event query mechanism called, a poll is performed. This call is made between the processing of commands by the active process that has control over the central processing unit, registers and causes a simulated V-operation, the Relays information regarding the external incident to an active process.

These external happenings that are processed between commands do not relate directly to the active process that has control over the central unit. More accurate in other words, these occurrences are usually input / output interruptions or certain exceptions.

A central exception mechanism manages the communications regarding the exception conditions. When a break-like condition or system exception occurs, a simulated V-operation is performed, to transfer the communication to an appropriate process in the central unit. This communication informs the relevant process of the type and cause of the exception and enables the Operation of the data processing system, the action corresponding to the exception condition being carried out, which includes both by the relative importance of the exception as well as the status of the central processing subsystem is determined.

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In addition to the communication processing of the exception events the system occurrence polling mechanism also maintains communications regarding the input / output interrupts by. The term input / output interruption identifies all information transfers that originated in the input / output subsystem. This includes communications from the entry / exit control unit (IOC) and all Peripheral units ('1 / O). ■

The input / output subsystem performs asynchronous input-output operations and ensures a high degree of overlap with the operations of the central unit the input / output subsystem is the grouping of all devices used to transmit data in a peripheral subsystem generated information between the main memory of the central unit and any peripheral unit required are. The input / output subsystem will not as many known designs can be used. However, there is a brief introduction in the operation of the input / output subsystem to handle the delivery to explain a message to the central unit.

More specifically, the input / output subsystem operates asynchronously with the. Central unit. It follows from this that the input / output subsystem has its own programs, hereinafter referred to as channel programs, consisting of a complete instruction set and addressing information for performing the desired input / output operations. The channel programs consist of a channel program header and contain the channel number of a logical channel, to which the program is directed and a set of channel command input, which are the basic building blocks of a channel program represent. To carry out communication with the aid of an IOC from an input / output unit to the

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Central unit, a logical channel is used. A logical channel is conceptually a communication path between main memory and a single peripheral in the input / output subsystem. A logical channel is used to carry out one or more operations that relate to a peripheral unit logical channel is identified by its channel number LC.

As the input / output subsystem and the central processing Subsystems can work independently of one another during the execution of a channel program occur that have to be transmitted to the central unit. As these happenings during or at the end of the implementation of the channel program can occur, the channel program is interrupted and the input / output subsystem generates an Event description message that contains an LC number corresponding to the channel program.

These input-output label messages can identify the following occurrences: first, the occurrences which relate to the implementation of the channel program and which are subsequently as intermediate or final events to be designated; second, the events that relate to a specific peripheral unit, however are not included directly in the execution of the sewer program and are referred to here as marking events; thirdly, those events which trigger a change in the functional conditions of input / output hardware elements may and hereinafter be referred to as spatial channel exceptions or input / output malfunction exceptions. However, the exception conditions listed last are not dealt with in more detail here.

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The message designation of input / output events is located in the central unit as follows Process given: When an input / output message is detected, the mechanism called the system incident query mechanism is accessed which runs as a pseudo-process. This mechanism then ensures a simulated V operation on a message semaphore to get the message to a process within the central processing unit. Therefore, the input / output interruptions can be considered processes in the same sense as processes within the central processing unit be viewed, i.e. they exchange information with the Process of the central unit via message semaphores and simulated synchronization primitive commands the simulated V-operation transmits the message via a logical channel in the same way as a V-command transmits the message by means of a process controlling the central unit.

In the event of an input / output interrupt, the input-output subsystem generates a signal that positions a flip-flop to indicate that a message is due to some input / output incident was generated. This special signal is recognized by the central unit as a determination that an incident designation message waiting to be attached to a semaphore. This flip-flop, which has been positioned and is an interface between the input / output subsystem and the central processing unit, is referred to in this text as an interface flop. When this interface flop is positioned, the central unit recognizes that a simulated V operation must be performed. At the end of the current command, the one shown in FIG System incident query mechanism entered by the central unit.

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System-incident-abfraceme chani smus

The system incident query mechanism is a hardware mechanism which, as shown in Fig. 27, comprises a set of Operations enabled. The polling mechanism can be either hardware or firmware structure which would be familiar to those skilled in the art is known. The query mechanism works as follows:

In step 2700 the interrogation mechanism is activated by the central processing unit at the end of the current command that is being executed by the active process. The first one asked by the query mechanism Question is whether external incident occurred during execution of the first command occurred. This is carried out with step 2702, which checks whether the hardware gate is locked. If the hardware gate is locked, as above, this marks the implementation of a critical operation. An indivisible action is performed by positioning the hardware gate.

piese indivisible action can for example be in the transfer of information in the main memory or in the transmission of messages to semaphores. If the hardware gate is disabled, i.e., if it is set to binary one, a branch is made to step 2704, in which the next instruction of the currently active process will be executed. Therefore, the data processing system specifies when the hardware gate is locked, states that the process being carried out is more important than the communication of an input / output event is.

However, if the hardware gate is not locked, will a branch is made to step 2706 and the system mode is entered. This step in 2706 initializes a flip-flop in auxiliary memory 1317a that the execution a system control operation. The query mechanism

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is the mechanism that performs this system control operation. More specifically, the polling mechanism calls all input-output interrupts and exception conditions and enables the processing of these events.

In step 2708, the query mechanism checks the interface flip-flop the input / output subsystem to determine whether it is positioned. If so, there is an input / output interrupt and a branch to step 2710 is performed. This step enables the input-output-event processing mechanism, which is shown and described in Fig.28.

However, if the interface flip-flop has not been positioned, a test is made at step 2712 to see if an exception condition has been encountered. If so is the case, in step 2714 a branch is made to the central exception mechanism carried out.

The central exception mechanism enables the processing of the exception condition and informs an exception processing facility.

Both for the input / output event processing unit and for the central exception mechanism at the end of the processing of a certain retrieved event, a branch back to the query mechanism and more specifically performed to step 2708. Because of this operation, all input / output interruptions and processed all exception conditions before the next instruction of the currently active process in the central processing unit is processed.

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Since both the input-output-event-processing unit as well as the central exception mechanism as part of their processing of external events Performing a simulated V-operation can send one or more messages to the corresponding processes within have been transferred to the central unit. Depending on the configuration of the semaphore that is simulated via the V-Operation have received a message, one or more processes of the central processing unit can use the semaphore message queue (O / M / S) must have been transferred to a ready queue (Q / PR / RDY). Hence, in step 2716 the dispatcher started. The one shown in Fig.i4 Dispatcher now defines the process that is to take control of the central unit. Hence the Messages of external events integrated with the internal messages of the central unit, depending on the priority of the processes in the ready queue, the more important communications are processed first. "As can be seen, all messages are conditionally fed to the central unit. Those messages that are accordingly the conditions now present in the central processing subsystem are of greater importance, are now being processed.

Input / output event processing unit

As shown in Fig. 28, the input / output event processing unit 2710 started when the query mechanism detects the presence of an input / output incident message pending. This would go through the fault flip-flop, which in turn would trigger an input that is more logical in a queue Channels for an incident would be assigned, i.e. Q / LC / EVQ, see Fig. 19b. These incident messages will be

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attached to a message semaphore that is located in the main memory of the central processing subsystem. Before discussing that of the input / output event processing unit 2710 would be those of the input / output subsystem tables used with regard to the simulated V operation.

After incident description messages are generated in the input / output subsystem, they are stored in a suitable logic channel table (LCT), which stores a large number of logic channel table entries owns (LCTE). Each LCTE contains an incident description message, which lead to a process in the central unit must be transferred using the simulated V operation. Each LCTE can have two fields in an incident description -Own queue Q / LC / EVQ. For all logical channels in the input / output subsystem there is a single Q / LC / EVQ queue. If at least one message has occurred, the A queue is formed and a signal is generated to set the interface flop to signal the occurrence an input / output event. If the queue is empty, there is no signal, and the interface flop is at logic zero. If the interface flop is a logical one, the interrogation mechanism gives as many simulated V-operations free to perform as to empty the Q / LC / EVQ queue required are; then the interface flop is set to logic zero.

Those transmitted from the input / output subsystem to the LCTE Messages are queued in the order in which they arrive in the Q / LC / EVQ queue; i.e. accordingly rule "first in, first out" (FIFO). Every

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simulated V-operation performs several functions on the queued message. First, the initial incident description message is removed from Q / LP / EVQ. After that, the simulated V-operation will either try this Message to the semaphore corresponding to one of the semaphore system names, i.e. Gi, Di for Intermediate or final reports, and Ga, Da for marking reports or to send the report to a forward the waiting process specified by this semaphore. Third, if the message is either attached to the semaphore or to a waiting one Process can be sent, it is made up of Q / LC / EVQ and the corresponding memory area of the corresponding LCTE withdrawn. Fourth, when a message is prevented from getting due to lack of free Message chains within the corresponding SD segment to be attached to the corresponding semaphore, the message is withdrawn from Q / LC / EVQ and attached to the free message chaining semaphore of the SD segment, which corresponds to the semaphore originally associated with the message (Gi, Di) or (Ga, Da). The message remains in the memory area of the LCTE, but the message chains are exchanged, i.e. those LCTEs that are connected to the free message concatenation semaphores are placed in a new queue, Q / LC / FLS, i.e. in the queue of the logical channels at the free concatenation semaphore. Q / LC / EVQ and Q / Lc / FLS, are easier to understand in connection with Fig. 29a, in which the LCTE is explained.

The input / output subsystem uses specific tables, one of which corresponds to the different logic channels, which represent a communication path to the main memory. The input / output tables are located behind the

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absolute address 0, but before that already in F ± g.12 Basic Address Register (BAR) shown. The one shown in Fig. 29a However, as shown in FIG. 29b, LCTE is an entry in the logical channel tables (LCT).

Each logic channel table entry consists of 16 words and is used to provide information relating to the logical channel in addition to information relating to the channel program identify, store intermediate or incident completion messages, and marker messages.

Only those fields of the LCTE that are within the scope of this Invention are explained here. Therefore, the Information that is independent of the program is stored in word 1 and contain the LC status and the designation of the marker semaphore Ga, Da in the bytes in the first byte to 3 of word 1.

In words 8 to 11, the intermediate message to be transmitted is or event completion message. More precisely, the first two bytes of word 8 are the Note "next chaining" (NL) which identifies the queue in which the logic channel table entry is located is located. As already described, this can either be the event designation queue Q / L / EVQ, which occurs when a message is initially transferred to the table, or at a free concatenation semaphore queue Q / LC / FLS, which is built up because the message cannot be saved in the corresponding semaphore. Byte 2 of Word 8 defines the event type, which is a reason field described in Fig. 16 for input / output operations is equivalent to. The justification field gives the type and

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_ 202.

Way in which to end the input / output operation is; it can also provide information for a normal or not included normal closure. In the fourth byte of Word, the first half of the byte is the message priority, the corresponds to the channel · program priority described in the input / output operation. If this message is a Message semaphore is fed to its queue with regard to the priority is set, the field identifies the position of the message within the Q / M / S ii queue. The next half-byte is the TAG-PeId, which indicates that this message is the result of an input / Output operation is. Word 9 of LCTE contains specific information to identify the logic channel number (LC) and other information that does not fall within the scope of this invention. The word 10 contains the Channel command entry hint that contains the intermediate or final occurrence label message generated.

Word 11 can contain the status of both the input / output unit and the IOC.

The words 8 through 11 contain the message, the V-operation is transferred to a semaphore simulated using de ^r, the system address Gi, Di has. Words 12 to 15 contain a marking message which is fed to a semaphore whose system address Ga, Da is specified in word 1 of the LCTE table.

In the marking message is located in the first half-word a "next concatenation" field, which indicates its position within the LCTE and provides information about the fact indicates whether it is in the Q / LC / EVQ or Q / LC / FLS waiting area is located. The reason field, i.e. byte 3 of word 12, has the code 10001101 shown a defined completion message. This field indicates

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this semaphore message as a marker type message. The priority field, consisting of the first four bits of the fourth Bytes is positioned on coding 1111, which indicates the highest priority. The message TAG is the same as the interim or final message, as this indicates an input / output message In word 13 the first two bytes are the same as in the messages already described; the last two However, bytes identify the designation of the unit that generated the marking message. There is a marking message identifies an event that is assigned to a specific peripheral unit, but not for Channel program execution is returned, are the fields generated in the intermediate or final event, namely the residual count field and the current LCTE address field are not required Unit is required, however, and 'word 13 identifies the unit. The word 15 is similar to that described above Word 11 identical. In the case of marking messages, all the required information is given in just three words (the words 12, 13 and 15 shown here) are generated. Therefore word 14 is used to store the semaphore, the refers to the intermediate or final event and is therefore in the last three bytes.

All of the LCTE gifts now described form initially one or two fields in the event designation queue Q / LC / EVQ, i.e. marking and / or Intermediate degree types. Every entry marks that Occurrence of an input / output event that requires communication to a process in the central processing unit. This communication can be carried out using words 8 to 11 or words 12 to 15 depending on the type of message to be reported Incident to be carried out. In an interim

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or the final message will be the simulated V-operation on Gi-Di semaphore performed. In the event of a marking message, the V operation is carried out on the Ga-Da semaphore. In this way, the system designation Gi, Di identifies the semaphore to which all messages are to be sent with regard to the channel program. The system designation Ga, Da denotes the semaphore to which all messages relating to a specific peripheral unit are to be sent.

In Fig. 29b is a plurality of logic channel table entries shown. As the LCT all LCTE entries contains, both the Q / LC / EVQ and the Q / LC / FLS are shown. The Q / LC / EVQ queue has already been explained and contains an incident label message queue Q / LC / EVQ that is captured. As shown in Fig. 19a, an input is made in the position 2F of the scratch pad memory, which identifies the head of Q / LC / EVQ. Hence this input a reference to the first LCTE entry in the Waiting line. This absolute address is picked up from position 2E and its address is used for access used on the first logic channel table entry. The notice had been transferred to the scratch pad memory as the asynchronous input / output subsystem had a message queued.

According to FIG. 2B, the question is asked in step 2802, whether it is a marking incident. If so, in step 2804 becomes the Ga-Da address of the semaphore for which the message is intended, tapped from LCTE. If it is not a marking, Message is, in step 2806 the Gi-Di designation of the semaphore for which the message is intended is selected Word 14 of the LCTE tapped.

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In step 2808, the first LCTE is removed from the Q / LC / EVQ queue separated by the position LE of the Scratch pad memory is changed to identify a new header of the LCTE table and the "Next concatenation" field is captured by LCTE. Therefore the LCTE entry has been removed and theirs Message must be attached to the message semaphore identified by the GD system name. In In step 2810 the message is transferred to positions ¥ C4 to WC7 of the scratch pad memory. If If it is an interim message, words 8 to 11 are transferred to this position; if if, on the other hand, it is a marking message, words 8 to 15 are transferred there.

At step 2812 the message now becomes the appropriate one Semaphore transmitted via a simulated V-operation was identified by the system designation. When the V operation is completed, the polling mechanism restarted and its next LCTE entry (if any) is transmitted.

FIG. 28 enables an overview of the event designation report steps performed when communication with a process in the central processing unit is required is. The steps illustrated in Fig. 28 are explained in more detail in Figs. 30 to 32, which together with FIGS. 20 to 26 show the operations which are required for converting the message of the corresponding process are.

Simulated V operation on a semaphore with a positive SCT field

It is recalled again that a V command is a send operation is that a transmission of a message to a

509834/0830.

Allows intermediate point, which is referred to as a semaphore. The semaphore stores the data until another Process is able to take it up. Previously, the V command was performed by the process that is controlling possessed via the central unit ·. A simulated V operation is almost identical to the V instruction in that it contains information about another process or any group of Processes in the central unit. It differs from the V instruction in that the process that created the Central unit controls, is a pseudo-process, i.e. the 'V command is either from the query mechanism or from the general exception mechanism implemented. Between V-operations and V-commands only one semantic command is present, this is regarded as a V command for reasons of time when the mechanism tries to receive the message transferred to.

The main peculiarities of the V-operation simulated by the query mechanism are: (1) the status update of the logic channel on successful transmission of the message, in contrast to the status update the process performed by the process that was in control of the central unit; (2) the integration of the logic channel in Q / LC / FLS, if no process is found that is connected to the corresponding Semaphore waiting and no available free message chains are connected to the free concatenation semaphore (Q / FL / FLS) in the corresponding SD semaphore, in contrast for the integration of a process in Q / PR / FLS when it is determined that no free message chains are available and (3) checking the G field of the free concatenation semaphore in the corresponding SD segment, if

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the count field of the logic channel (CCT) is lower than zero. In FIGS. 20 to 26 it has already been indicated that the field has been checked; the operation, however, has not been described.

In addition, both in terms of the input / output event and the exception conditions, two additional differences were found. The first difference consists in that the content of the message is generated and passed on by the simulated V-operation. The content of the message for the input / output interruption is with regard to Fig. 29 and the description of the LCTE table. Second, there is a difference between the address of the semaphore and the address described for the P and V commands. Each Semaphore can have two names, i.e. a local name SEG, SRA and a system name G, 0. It is recalled that the local designation SEG, SRA is used to identify the semaphore was used for the process that was in control of the central processing unit. For the interim and marking messages, a GD system designation is available.

The system designation of a semaphore is the GD address of the semaphore in the corresponding SD segment. This gives derives from the fact that, as shown in FIGS. 4, 12 and 17, the G-segment table (G-table) has G-segment descriptors contains. The G-segment descriptors describe the general system segments. Since there is only one G-segment table is located in the data processing system, the size and address of the G-segment table are determined by the content of the G-table word (GTW) determined. This word is in the address BAR + 4 in the system base.

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The G table note also in the system base indicates the absolute address of the G table. When accessing this G table, the G number enables the shift in the G-segment table. In the G-segment table the identified G segment descriptor identifies the SD segment used. The D number enables the shift to the SD segment and the selection of the corresponding semaphore for which the message is determined.

Since the system designation G, D as shown in Fig. 17, Regardless of the local process designation SEG, SRA is developed, the input is a simulated one V command via a different input point, Fig. 20, than the Development of the semaphore address from the JP designation.

FIG. 20 describes in more detail the semaphore descriptor acquisition routine which is triggered by each P and V command. At the time this subroutine is called, an operation code has been transferred to the command acquisition unit 1318 to identify a simulated V command. As the system name for the input / output interruption or the exception? condition has already been generated, the semaphore descriptor does not need to be checked and recorded. The semaphore detection routine is therefore entered in step 2019 (FIG. 20b) with the absolute address of the semaphore for which the message is intended. This absolute address is the system designation G, D. In step 2020, as shown in Fig.i6b, both words of the message semaphore are tapped from the main memory and transferred to positions WC4 and WC5 of the scratch pad memory. The same steps 2021 to 2026 are performed as for a V command, and the answer to the question in step 2026 is "yes" and enabled

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thus performing step 2500 of FIG. 25a.

If the message semaphore is assumed to have a SCT count that is less than zero a branch is taken to step 2508. Since the If the simulated V command is intended for a message semaphore, step 2508 would be answered with "no". Hence, step 2510 and would also be answered with "no", since the simulated V command is not a test command. A simulated V command cannot be a test command because it does not negate if the SCT field of the semaphore is positive.

In the FAR subroutine, step 2513, the message that has already been transferred to positions WE4 to WE7 of the scratch pad memory is transferred to the general registers GRO to GR3 of the process that is located in the head of the queue of the semaphore ( Q / pR / S) v / related processes. In addition, the FAR subroutine changes the Process ^Ü expensive block of the, process. Which receives the message, so that the dispatcher may be classified in step 2515 the process in the ready queue Q / PR / RDY. The priority of this process would then determine the purposes of the process that takes control of the central unit.

After completing the FAR subroutine in step 2513, a test would be performed prior to performing step 2514. This step would check a flip-flop in auxiliary memory 1319 to see if the simulated V command was an input / output simulated V-operation. If that If the flop is positioned, it will branch back to Q / LC / EVQ carried out at which the next logical channel table entry is tapped, referred to by the header contained in the position LE of the scratch pad memory will.

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Simulated V operation on a semaphore with a non-positive SCT field

If the answer in step 2500 of Figure 25a indicated that the SCT field of the message semaphore is either the same or was greater than zero, a branch to the V-positive subroutine (Fig. 26a) is carried out. At this point it is known that the semaphore is not a queue of processes that are waiting for a message, i.e. Q / PR / S and may contain a queue of messages, Q / M / S if the Count of its SCT field is greater than zero. In wing 16a the first question in step 2600 would be answered with "no" since it is a V command for a message semaphore Therefore, steps 2605 and 2608 are performed. In step 2608 a flop in auxiliary memory 1317 is checked to see if it is a simulated V command acts. If so, a branch is made to step 2608a and the SVP subroutine shown in FIG carried out. These. Subroutine enables the message to be sent to the semaphore and the Q / M / S queue.

In the simulated V-positive subroutine shown in FIG Step 3000 asks whether free message chains are available, i.e. whether FLQP of the free chain semaphore equals zero. Previously, the SD segment free chaining semaphore was obtained by the FLSC subroutine at step 2401 (Fig.26a) detected. The FLQP field is in the scratchpad position WCC has been saved and is now checked by step 3000. If free message chains are available are, i.e. the answer is "no", a simulated V operation is carried out, which corresponds exactly to the V command, i.e. a branch to B from the VP is carried out, which in 26b is shown as step 2612. Through this

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Branch is the message that is either in the LCTE or was generated in the central exception mechanism from the scratch pad positions WE4 to WE7 are transferred to the available free message chain. In the meantime, the message chaining to the semaphore ¥ arte queue O / M / S, where it waits for a process requesting information. on this way the simulated V-positive subroutine transmits through this branch the message to the semaphore. In step 2622 (Fig. 26b), the next instruction would cause a return to the system incident query mechanism, which, if present, performs the next simulated V-operation. If no further simulated V commands. are present, the The next command of the process that has control of the central processing unit is carried out.

Simulated V operation on semaphores if there are no free ones Message chains are available.

If the answer to the question in 3000 (Fig.30a) is "yes", and this indicates that there are no free message chains are available, step 3004 is performed. Step 3004 asks whether this is an input / Issue operation. If this is not the case, it must be an operation by the central exception mechanism Act. Since the central exception mechanism does not have any free message chains to integrate the If this message is generated, an exception "missing" occurs in step 3006 Message concatenation ". This is a system exception because the system mode was started in step 2706 of FIG. 27, and step 3006 generates a "System Check" status that is model dependent Diagnostics generated. In this way, step 3006 ends the simulated V commands for exception conditions. Of the The rest of the information to be discussed relates only to input / output simulated V-operations.

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If the answer to step 3004 is yes, i.e. a flop in auxiliary memory is positioned to do an input / output operation to identify, the G-System designation is tapped from the main memory in step 3008 and placed in the position WCO of the scratch pad memory transferred. It is reminded again that the FLS semaphore, as shown in Fig.i6, contains word number 2, which contains the G field in bits 72 to 79 and the CCT field in bits 80 to 95. With the P and V commands already described, these fields are not used because there is no input / output operation took place and therefore no logic channel or system designation was initialized. However, these fields are now used in the Incorporation of the logic channel. used to the free concatenation semaphore, so that the specified by the G designation Message in the free message chaining of the free chaining semaphore is transmitted if a free message chaining for this SD (or G) segment corresponds to the free chaining semaphore is supplied.

In step 3010, the channel count (CCT) becomes the free one Checked chaining semaphore, which is stored in the scratch pad position WDO. If the CCT field is the same Is zero, i.e. the answer to the question is "yes", then in step 3012 the G-System designation, i.e. bits 72, becomes to 79 of word 2, which was tapped in step 3008, are written into the G field of the free concatenation semaphore. This identifies the G-segment number of the logic channel that requested free message chaining. If that However, CCT field is less than zero and indicates that before an input / output simulated V operation on the same SD segment has been carried out and that in this case no free message chains were available is shown in step 3014 the G system designation tapped in step 3008 with the G system designation contained in the free concatenation semaphore

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compared. The G-system designation acquired in step 3008 must be identical to the G-System designation contained in the free concatenation semaphore, as each SD segment has its own and owns only G address. Since there are various semaphores within the SD segment on which simulated V-surgeries can be performed this would through Another shift field, i.e. the Ε number, is displayed, but the same G system designation would remain. Therefore, if the G-system designation is not identical to the system designation contained in the free concatenation semaphore an illegal semaphore exception occurs in step 3014a on.

If, however, it is assumed that with the G system designation If no problems occur, the hardware gate is locked in step 3016 in order to carry out a critical Display system operation.

In step 3018, the CCT field becomes the scratch pad position V / CD stored free concatenation semaphore is decremented by one. The absolute value of the CCT field gives its Number of logic channels that are waiting for free message chains. In step 3020 the content the positions WCB to WCD of the scratch pad memory in the main memory and transferred to the address of the free concatenation semaphore developed via the FLSC subroutine to indicate the current status of the free concatenation semaphore. Step 3022 becomes a EWLC subroutine performed. This EWLC subroutine integrates the message of the logic channel into a queue Q / LC / FLS and is shown in Fig.3Ob.

At this point it is known that those from the Q./LC/EVQ queue tapped message not to its corresponding one

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Semaphore could be attached either to Gi, Di or to Ga, Da, because there were not enough free message chains in the SD segment. In addition, the steps are carried out which provisionally connect the message with the free concatenation semaphore of this SD segment by adding the Transfer the G system designation to the FLS semaphore and the CCT count shown in steps 3010-3020 is, has been decremented. The message must now be saved in such a way that it is included in the newly available free message chain can be transmitted / grounded when a P command is a message chain makes available in the SD segment.

A Q / LC / FLS queue is set up for this purpose, in which the message is stored in the waiting status until a free message chain is available in the G segment. The Q / LC / FLS queue performs the same function as Q / PR / FLS with V commands. A Q / LC / FLS queue concatenates them all Logic channels that wait for a free message chaining in an SD segment, therefore there is only one Q / LC / FLS for all free concatenation semaphores in main memory. This Q / LC / FLS has a variety of different system names, the the various free concatenation semaphores identify in the SD segments. The Q / LC / FLS queue has a note and an absolute address, as shown in Fig. 19a, in position 2F of the scratch pad memory be transmitted. This word identifies both the head and the tail of the queue. if checking which concatenation in the queue is connected to the free concatenation semaphore, the The G designation stored in the free concatenation semaphore is compared with the G designation in Q / LC / FLS If the concatenation is removed from Q / LC / FLS, the "next concatenation" field of the previous LCTE is changed to include the

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Identifies the concatenation pointed to by the removed concatenation. If LCTE is the first concatenation, will the header note in position F changed.

In Fig.3Ob, the logic channel table entry is made at step 3030, which was tapped from Q / LC / EVQ, now incorporated into Q / LC / FLS. If an entry is made in this Y / type queue beforehand would have occurred, this would be in accordance with the FIFO rule with the previous one LCTE input connected. If there were no LCTE entries before, the queue is put into operation. Therefore, in step 3030, the tail would be the changed absolute address in main memory to indicate that the new LCTE now the tail of the queue is up.

In step 3032 the logic channel status byte is updated. Although the message was not forwarded to the appropriate process the status byte is changed to indicate that a simulated V command is currently being performed. this results from the fact that the message was placed in Q / LC / FLS. However, since the message is not the corresponding process reached, the status bytes would indicate that the simulated V operation was unsuccessful.

This terminates the EWLC subroutine and now a branch back to step 3024 is performed. Step 3024 enables the hardware gate to indicate that the indivisible function of data write and transfer carried out has been. In step 3026, the next simulated V operation is performed, if any.

Transmission of a message from Q / LC / FLS to the semaphore when a free message chain becomes available.

After the construction or the development of a Q / LC / FLS must now Described as the queued

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Message is transmitted to the corresponding semaphore, ^ ur this Situation, a P command for a message semaphore is required, to enable a message chain. This released message chaining now becomes a free chaining semaphore returned in the SD segment where it can be used to store the message contained in Q / LC / FLS. this would occur if the CCT-PeId of the free concatenation semaphore would be less than zero .__

Fig.22a contains a more detailed description of a P command for a message semaphore. When the situation in which message chaining is required to be released occurs, will a branch from step 2200 to step 2205 and Consider step 2207 as it requires an SCT count of the message semaphore greater than one. Of the The P command is carried out on the semaphore and enables a message chain by receiving a message from the semaphore. In Note at step 2205 that if the SCT field counts zero, no free message chaining is made available would. This situation will be described later.

For the sake of simplicity, it is assumed that step 2218 in FIG. 22b would be reached, since the situation occurs here where in word number 2 the channel count of the free concatenation semaphore is checked to see if it is less than zero. If this value is less than zero, it means that this is a free concatenation semaphore a Q / LC / FLS is conceptually available. The system mode is therefore set in step 2225 and a branch is made to FIG. 22d and step 2226 is carried out. This is the RLCM subroutine shown in Figure 31a. RLCM subroutine means: "Release of message chains for the logic channel ". This subroutine identifies

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the LCTE input, the semaphore for which the message is determined and transmits the message to this semaphore

Thus, in step 3100 (Figure 31a) it becomes an FLC subroutine "Retrieval of the logic channel" carried out, as shown in Fig.31b. In step 3120 the Q / LC / FLS is searched for identify the semaphore that has the same name as the free concatenation semaphore in the SD segment. Therefore the Q / LC / FLS header is used to create the first LCTE entry and check the corresponding G designation. If the G designation in the first LCTE entry is not equal to the G designation in the free ^ chaining semaphore of the SD segment the next LCTE entry is detected in which the same comparison is made. If the entire Q / LC / FLS is checked and no identical G designation is found, an illegal semaphore exception occurs in step 3120 on. However, if the first G label is identified, step 3122 is performed.

It should be noted that the Q / LC / FLS have several identical G designations that correspond to the absolute value of the channel count in the FLS semaphore. If e.g. If the channel count of the semaphore is "2", there should be two LCTE entries for the Q / LC / FLS in a free one Message concatenation of the free concatenation semaphore must be stored in the SD segment. At this point it is however, only the first entry with the G designation incorporated, as only a free message chain from the current one executed P command is released.

In step 3122 the system name is derived from the LCTE tapped and in position WD4 of the scratch pad memory

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transfer. In step 3124 the hardware gate is disabled to indicate that a critical system operation is occurring an indivisible action is carried out. In step 3126 the channel count value (CCT) of the free concatenation semaphore in position WCD of the scratch pad memory is incremented by one, to indicate that a logic channel LC is less waiting for a free message chaining. In step 3128 the logic channel table entry is removed from Q / LC / FLS. This step pulls change in the "next chaining" field the previous LCTE to form a serially ordered queue. This is done largely in the same way Way like capturing a message or 'process. -Chainment from a Q / M / S or Q / PL / PLS described above.

After the critical operation has been performed on the Q / LC / FLS queue, step 3130 returns the hardware gate In step 3132 the aforementioned absolute address of the semaphore is developed. Since the P command, the released the message chain, can refer to a different semaphore than the one identified by the system designation Semaphore, step 3132 must be performed. In step 3134, the Transfer the message to positions WE4 to WE7 of the scratch pad memory and the FLC subroutine is ended.

Upon completion of the FLC subroutine, a return is made to Figure 31a and step 3102 which is the PSEM subroutine retrieves. This subroutine performs checks on the semaphore because the semaphore count is greater than zero. The PSEM subroutine is shown in more detail in Fig.31c.

Specifically, in step 3140, the D number becomes the GD system name checked to see if it is a multiple of 8. The D number is the identification of the corresponding semaphore

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within the SD segment and must be a Be a multiple of 8. In steps 3142 and 3144 the two words of the semaphore are developed from the one developed in step 3132 of Figure 31b The absolute address is tapped and transferred to positions ¥ C4 and WC5 of the scratch pad memory.

If the semaphore is available, checks are made that match the semaphore detection routine. step 3146 checks the STAG field of the semaphore to see if the semaphore is a message semaphore. In step 3148 ~ the SCT field of the semaphore is checked to ensure that it is lower than the SMC field. In this way, steps 3146 and 3148 check the validity of the tapped Semaphore.

In step 3150 the SCT field is checked. When the count of the SCT field is less than zero, an illegal semaphore exception 3150a occurs. This results from the fact that the The SCT field count was less than zero as this would indicate that processes were chained on the semaphore. Processes will however, it never pauses when there are messages are in Q / LC / FLS for the semaphore on which a process has a P command performs (will be described later). With the P command situation the notification would have been transferred to the proceedings if Q / LC / EVQ had been outsourced. If that SCT field is greater than zero, a branch is made to step 3152 in which the information fields of the semaphore More precisely, these fields form the Message Queue Header (MQHP) and the Message Queue Tail Hint (MQTP) which must be non-zero and a multiple of 8, since the semaphore is a double word structure (8 bytes). If the SCT field in step 3150 was zero, step 3154 is performed. Since the SCT

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Field is zero, there is no queue and now the MQHP and MQTP fields must be zero. If either of these conditions is not true, go to step 315Oa raised an illegal semaphore exception. This completes the checks performed by the PSEM subroutine.

When the PSEM subroutine is terminated, a branch back is made to Fig.21a and the subroutine TAML shown in Fig.26c 2613 carried out. This subroutine checks the access to the message chain, since it is known that a free one Message concatenation in the free concatenation semaphore has been incorporated, i.e. a Q / ML / FLS has been set up or added. The relative address of this message chain is now from step 3104 in the position ¥ 35 des Scratch pad memory transferred. This address would be the free one

Concatenation queue indication PLQP of the free concatenation semaphore, which identifies the position of the free message chain. In step 2617, indicated by Fig. 26e As will be explained, the message in the scratch pad positions as a result of step 3134 will be in the main memory position the newly developed free message chain.

Step 3106 disables the hardware gate. In step 2619 the QML subroutine, the message queue of a semaphore, Q / M / S, built up. The message chain that has just been released, which stores the LCTE message must now be attached to the semaphore. There are none for message chaining Checks are necessary, since it was guaranteed when moving to Fig. 31 that the SCT field of the semaphore is greater than Was zero. The QML subroutine writes the new semaphore into main memory and updates the hint fields (if required) in the message semaphore to indicate that a new message has been added to the semaphore queue Q / M / S became.

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In step 3108 the logic channel status is updated to to indicate that now a successful simulated V command has been performed and in step 3110 the hardware gate is enabled because the information on main memory have been transferred.

This exits the RLCM subroutine step 3112 and allows a branch back to Fig. 22d and step 2227, in which the system mode is cleared. As a system control operation, the execution of the simulated V command controlled and since the simulated V command has now been completed, it is possible to switch back to process mode will. In step 2228 of Figure 22d, the P operation has ended, and at that point is proceeded to the system occurrence polling mechanism to determine which other logic channels are being served got to.

Therefore, Figure 31 shows the actual separation of the logic channel table entry from the Q / LC / FLS of the corresponding semaphore, so that from the input / output interruption delivered message can be fed to a corresponding process. This would be the case either for an interim or Completion message in words 8 to 11 of LCTE or for a marking message · in words 12 to 15 of LCTE.

5Q9834 / 083Q

Removal of a message from Q / LC / FLS for transmission to the process requesting the report.

The Q / LC / FLS queue can be accessed in an additional way. This situation occurs when the Process which has control over the central processing unit, executes a P command on a message semaphore and the SCT field of the semaphore is zero. This situation became with regard to FIG. 24a and the subroutine PMZ 2206 in which the message is transmitted from a process in the Q / PR / FLS queue? the message is never with the Semaphore queue Q / M / S connected.

In the following description, the emphasis is on the concept of creating a message, making it available a V command was tried before, i.e. this led to the establishment of a Q / PR / FLS, or vice versa, an attempt was made using the simulated V command, i.e. a Q / LC / FLS and not the currently available P command generated, which is only described for explanatory reasons. Recall that the PME subroutine determines whether a previous process is currently waiting for a free message chaining to send its message to the message semaphore to join, i.e. the previous process could not send its message, and is therefore located the previous process is still in possession of this message. Hence the situation occurred in which everyone Free message chains have been used in the SD segment and a V operation has been carried out without success was tried. Because of this situation, the process has been placed on the Q / PR / FLS queue for the Wait for a message chain to be released in the SD segment. If there is a free message chain in the SD segment becomes available, the process can be removed from Q / PR / FLS and perform its V instruction. Before the occurrence of this

50 9834/08 3

Situation, however, a process is performing a P command on the same SD segment. Since the message that was attempted could not be sent due to a lack of free message chains, which can be the message that the process that has control of the central unit requests with its P command, the Q / PR / FLS searched. / If the message is identified, the process executing the P instruction receives the message directly from the process in Q / PR / FLS and removes this process from the queue of the free concatenation semaphore, ie Q / PR / FLS . Since this same situation can occur with messages from simulated V commands, it follows that the Q / LC / FLS queue would also be searched, since this queue could contain the message requested by the process via its P commands. This would be determined if the CCT field of the free concatenation semaphore is less than zero. Under these conditions, it is known that there is a Q / LC / FLS queue. and has the ability to save the requested message. This possibility is checked by comparing the DG number of the LCTE entries in Q / LC / FLS with SEG, SRA of the process that executes the P command.

In particular, in step 2401 of FIG Concatenation semaphore detected and in step 2402 the channel count field of the free concatenation semaphore is checked, to see if it's less than zero. If the CCT field is less than zero, this indicates that a simulated V command was unsuccessful in sending its message has tried and has now entered the queue of the logic channels on the free concatenation semaphore Q / LC / FLS. Therefore, if the answer to the question in 2401 was "yes", step 2416 (Fig. 24) is carried out, which searches the Q / LC / FLS queue to determine whether the message requested by the P command is available.

, 549834/0830

The first step in Figure 32a is the SLCQ subroutine 3200. The SLCQ subroutine searches the logic channel queue and sends back the message and the count of the LC number. As shown in more detail in FIG. 32b, in step 3230 the Q / LC / FLS is searched for the semaphore which contains the same G designation as the G number in FLS word number 2 and the same G designation as the SRA of the semaphore designation of the D command. This is done by acquiring the absolute address from position 2F of the scratch pad memory and accessing the queues to check the system designation. When the G names are the same. ie the semaphore is in the SD segment, the D numbers are compared. These would be the D number of the system designation, which is stored in the LCTE of Q / LC / FLS, and the SRA designation of the semaphore that was generated by the P command. If these numbers are the same, it means that an attempt was made to route the message to the corresponding semaphore on which the P command is executed. When this situation occurs, the process that is performing the P command receives the message and continues its sequence away. *

Furthermore, the LCTE entry of the ö / LC / FLS queue removed because it forwarded its message to the appropriate process. This comparison operation of the Semaphore labels in this situation indicate why there is never a waiting process and a message in Q / LC / FLS waiting for a free concatenation for this semaphore.

The question is therefore asked in step 3232 whether the logic channel LC has the same system designation as the one found Semaphore. This results from a search operation that the. SPLQ subroutine in Fig. 24d corresponds. It's closed

509834/0830

note that the G number of the system designation would have to be found, since the FLS semaphore indicates through the CCT field, that a simulated V operation was attempted without success. If this G-number is not found, step 3230a occurs raises an illegal semaphore exception.

Although the G designations can be identical, the offset number can be different from SRA; when this condition occurs, step 3234 is performed which positions an indicator in auxiliary memory 1317a to zero. This terminates the SLCQ subroutine, since no _Λ message had to be transmitted to the message semaphore on which the P command is carried out. However, if the G and D numbers of the system name are identical to the SEG and SRA numbers of the semaphore, the answer to the question in step 3232 is ¹¹ “yes” and step 3238 is performed Auxiliary memory 1317a is positioned at one to indicate that the message was found and can be transferred to the process executing the P instruction. In step 3240, the table address of the logic channel in position WD4 of the scratch pad Memory stored, and in step 3242 the message is transferred to the scratch pad positions WE4 to WE7.

After storing this address, a return to Fig. 32a will be made carried out. Again the question is asked whether the LCTE input was found. If the answer is "no", a branch back to FIG. 24a, 2403 is carried out, in which the Q / PR / FLS queue is searched. If the answer is "yes" indicates that the message is available, step 3204 is performed. In step 3204 the Questioned whether the executed P command is a test command. If so, at step 3206

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Am conditional code positioned at zero to indicate that the command is completed and step 3208 becomes carried out. If the answer is "no", it indicates that the P command is not tentative, and therefore will now Step 3208 performed.

Step 3208 is a TMGR subroutine that controls the transmission of reporting in the general registers. This subroutine is shown in Fig. 32c and includes the Step 3250, which is those in the scratch pad positions WE4 to WE7 reads the message contained and transfers them to the general registers GRO to GR3 of the process in step 3252 executes the P command. In this way the message from Q / LC / FLS is transferred to the general registers of the process which executes the P command without ever being queued for the message semaphore P / M / S to have become.

Upon completion of the TMGR subroutine, step 3210 is performed which disables the hardware gate. Since the message has been forwarded to the appropriate process in the logic channel table entry, the indication that a unsuccessful simulated V-operation has occurred is negated. Now the operations to supplement the status of the various queues. In step 3212 the channel count field becomes the idle concatenation saphore of the SD segment is incremented by one. This indicates that one unsuccessful message transmission is less is available. The updated channel count is now written into the free concatenation semaphore in main memory in step 3214. In step 3216 the logic channel table entry removed from the Q / LC / FLS queue and the serial order of the queue is changed,

509834/0830

to prevent this concatenation from being removed. The address this LGTE was from the SLCQ subroutine in position WD4 of the scratch pad memory. In step 3218 the status of the logic channel is updated to indicate that a successful simulated V-operation was performed because the message was sent to the appropriate process. Step 3220 enables the hardware gate to indicate that the indivisible operation has been performed. In step 3222 the instruction counter is incremented and the next command is performed as shown in step 3224.

If during the search operation, from Q / LC / FLS not the relative Segment address SRA is found to be equal to the displacement number "D" of the system name, the process becomes the executes the deiP command, as shown in Fig. 24, in the Waiting status moved.

In addition, the Q / LC / FLS would not be changed as the P command has not generated an LCTE entry that stores a message.

This shows that both the central exception mechanism as well as the system incident query mechanism work as a pseudo-method and the transmission of Data through simulated '^ operations to processes in the The central processing unit enables access to the semaphore for the simulated V operation with the help of the system designation G, D, on the other hand, the SEG, SRA designation is used in all situations when the basic check is carried out of the semaphore count field is carried out with the V operation. This check checks the eventual transmission of the report. Therefore, when the SCT field is negative, am is

50983 4/083 0

Q / PR / S semaphore attached to a queue of processes. When the simulated V operation sends a message to the semaphore feeds, the first process in the queue is removed and placed in the ready queue Q / PR / RDY. the The message generated by the simulated V operation is transmitted by transmitting the content of the scratch pad positions WE4 to WE7 into the general registers GRO to GR3 of the process control block of the process attached to the Seroaphore ^ In addition, the SCT field of the semaphore to which a Process less affiliated, incremented by 1.

If the SCT field is not positive, no process is waiting at this semaphore for which this message is intended.

The message is now transferred to the SD segment, the contains the semaphore and is connected to the Q / M / S semaphore is «If the message cannot be transmitted in a free message chain, a Q / LC / FLS constructed for the input / output interruption. The central exception mechanism would not call Q / LC / FLS because it generates a different exception and thereby the system check status «

It has therefore been described how 'an input / Output interrupt results in a conditional operation. The first condition is the blocking of the hardware gate. In this situation, a determination has been made that the current procedure execution is more important than the transmission the message from the input / output subsystem. The second condition occurs after the input / Output message to the central unit. This message originally depends on the current status of the central unit i.e. whether a process has already requested the message or whether the message is sent to the corresponding semaphore

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-.229 -

can be. Eventually, however, the message will be the appropriate one Process fed. This transfer can through the priority of the message can be accelerated. In the same way, the priority of the process will now be given, if it is not had control over the central unit, important because the process was integrated into the Gl / PR / RDY in a priority-related manner will. The message is now integrated with the internal messages and depends on the status of the data processing system as a whole away. The transmission of messages therefore depends on the status of the semaphore on which the simulated V-operation is running and also on the status of the system, i.e. on the priority the running process and the other processes in the Q / PR / RDY queue

Although the invention in connection with a specific Embodiment has been described, however, numerous modification possibilities will be apparent to those skilled in the art. It is therefore intends to the invention as far as possible in the sense and in To cover the scope of the attached patent claims.

5Q9834 / G83Ö

Claims (19)

Claims 1. Semaphore device for a multi-program data processing system, in which data are exchanged between processes, characterized in that the system contains in its main memory data structures called semaphores and for storage by data or by processes requesting data, the system automatically sending a Carries out a group of process synchronization commands, each of which enables a transfer of data from one process to another that the system contains a device which, depending on each command, addresses one of the semaphores that the system contains a facility which, depending on a specific field in a semaphore, indicates whether the data can be transmitted that the system is dependent on the display device Means for transmitting the data through the semaphore corresponding to each of the commands and that the System a device dependent on the transmission device for updating the semaphore accordingly the type of each command executed. 2. Semaphore device for a data processing system which has several semaphores according to Claim 1, characterized in that each of the semaphores has a selected status, the can be traced back to the various operations of the system, the status being such that that some of the semaphores can store data at any given point in time and other semaphore processes save while the remaining semaphores neither 509834/0830 Data still store processes that the system executes a command to initialize one of the semaphores, that a device responsive to the commands is provided which addresses a semaphore, that a device is provided, which depends on the addressing device the status of the semaphore is addressed, and that a device dependent on the destination device is provided that executes the command according to the status of the semaphore. A semaphore device according to claim Λ for a data processing system having a central processing subsystem which processes information under the control of a process selected from a plurality of processes, each of which comprises a plurality of instructions, the system also being out of execution of the commands, events occur while the commands of these processes are being executed, characterized in that a device for enabling the transmission of information about the events to the processes is provided, which device is dependent on the selected command processing process, one on the end of the command dependent device for determining the occurrence of the external incident as well as a device operating independently of the determining device for transmitting the information about the incident to one of the plurality of processes. 4. Semaphore device according to claim 1, characterized in that that the transmission device transmits the data from the one semaphore to one of the processes, and that the update device decreases the count of the particular field in the one semaphore. 5. Semaphore device according to claim 1, characterized in that that the transmission device receives the data from one of the processes to the one semaphore and that the update device transmits the count d3S certain field of a semaphore increased. 6. Semaphore device according to claim 1, for a multi-program data processing system with several processes, with a queue organization for processes in the ready state and in the waiting state in the main memory, with several semaphores, each of which can hold processes in the waiting status, whereby each process is in standby or is represented in the waiting status by a process chain, and a process in the '• function status executes an instruction in the system that requests data via multiple control signals by one depending on the command one. the device addressing several semaphores, a depending on the command a plurality of control signals generating device, each of which for one Distance operation in the system provides a facility which, depending on a first control signal, checks whether the one semaphore is holding the data, a Device which, depending on a second control signal, transmits the data from one semaphore to the process, if the test facility indicates that the one semaphore is holding data, and facilities that depend from a third control signal that updates a semaphore to indicate that there is one less amount of data contains. 7. Semaphore device according to claim 6, characterized in that that a device is provided which, depending on a fourth control signal, the process a queue connected to the one semaphore when the test equipment indicates that the 509834/0830 a semaphore contains no data. 8. semaphore device according to claim 7, characterized by a device which, depending on a fifth control signal, indicates whether the command is a test command, and a facility dependent on a sixth Control signal prevents the data request if the Command is a test command, the process being dependent from the prevention device executes its next command. 9. semaphore device according to claim 6, characterized in that the data is a message, and that the Transfer device this message to the process from a message that stores the message, with the one Semaphore connected queue when the Test facility indicates that the semaphore contains messages. 10. Semaphore device according to claim 2, characterized in that the status of a semaphore indicates that it stores data, the execution means initializing the one semaphore to a predetermined value, 11. Semaphore device according to claim 10, characterized in that that the data is a message and that the predetermined value is the value zero. 12. Semaphore device according to claim 10, characterized characterized in that in the case where the data is not a message, the predetermined value is a number which is stored in the general registers of the Irocess executing the instruction. 509834 / 13. Semaphore device according to claim 2, characterized in that that the status of one semaphore indicates that this semaphore is storing processes, the executor blocks the commands and enables an exception routine depending on this status. 14. Semaphore device according to claim 3, characterized in that that the event will occur if one of the commands cannot be fully carried out, whereby the event sets the exception handling flop to indicate an exception condition, and that the scanner samples the exception handling flop. 15. Method of transferring information about a happening outside of the operation of a central processing subsystem. one of several processes in a central processing unit via a semaphore device according to the claims 3 to 14, characterized in that the information stored in a queue of logical channels in a logical channel table Q / LC / EVQ, the at the end of the current command of the process in the central processing unit it is determined whether an external Incident has occurred and that for the transmission of the! Information to one of the several processes in the central len processing unit performed a simulated V operation will. 16. The method according to claim 15, characterized in that When the end of the current command is determined, it is checked whether a hardware gate is enabled, that it is checked whether an interface flop is set and that the execution of the simulated V operation is suspended if one of the test steps shows a negative indication. 5Q9834 / Ö83 - .235 - 17. The method according to claim 12, characterized in that a semaphore when executing the simulated V-operation is addressed to which the information is passed that a selected field of the semaphore is checked, to determine the status of the semaphore and that the information about one queued with the semaphore Process if the selected field is negative. . 18. The method according to claim 17, wherein the selected field is not negative, characterized in that the Execution of the simulated V-operation a selected field of a free concatenation semaphore in the same Segment is checked to determine whether free message chains are available when the The information is transmitted to the semaphore when free message chains are available, and that the information is transferred to a queue Q / LC / FLS if there are free message chains are not available. 19. Semaphore device according to claim 3, characterized in that in a data processing system with a central ^ processing subsystem and with an input-output subsystem a device for the transmission of messages about events in the input _r output subsystem to a is contained by several processes in the central processing subsystem that this device contains memory devices, which work as a function of the events, for storing the messages from the input-output subsystem and second memory devices for storing a plurality of semaphores which are each identified by the messages, that the device contains devices that depend on the first storage device 5Q9834 / G'83G Each of the messages is conditionally dependent on the status of the identified semaphore transmitted to one of the processes that a hardware gate is provided that indicates, when there is a critical operation, that the facilities are conditionally transmitting the messages fourth devices for checking the hardware gate contain, the checking devices the Block transmission of messages when the hardware gate is set, that first test equipment for Check a selected field of the message identified semaphores are provided, the selected field indicating that the semaphore processes contains if the selected field is negative and contains messages if the selected field is positive is, and that the first test equipment is the transmission of the message to one of the processes if the selected field is negative. 503834/0830