DE2453873A1 - FOURIER ANALYZER - Google Patents

Description

Patent attorneys:

Dipl.-Ing. Tiedtke
Dipl.-Chem. Bühling Dipl.-Ing. Chins

8 Munich 2

Bavariaring 4, PO Box 202403

Tel .: (089) 539653-56 Telex: 524845tipat
cable address: Germaniapatent Munich

Munich, ^{November 13th} 1974 B 6312

Imperial Metal Industries (Kynoch) Limited
Birmingham, UK

Fourier analyzer

The invention relates to Fourier analyzers, particularly but not exclusively a real-time device, - with which the Fourier analysis of ^a n non-stationary data executed can v / ground.

It should be noted that stationary data, i.e., data which repeat themselves either in a deterministic or in a statistical sense, over an extended period of time can be analyzed across the board, the sampling of which can be adjusted according to requirements in order to

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to get nimble results. Non-stationary data are characterized by the relatively random generation of the data, so that their analysis is often heavily dependent on the Period of data collection to be analyzed.

The Fourier analysis for non-stationary data is necessary for the purpose of analyzing, for example, atmospheric Pressure changes, sea level levels, voice patterns, wing beats and vibrations in general, such as vehicle vibrations. That is within the latter category a particular area with which the invention is particularly, but not exclusively, concerned, namely analysis of acceleration forces and dynamic forces in general that result from the ignition of a rocket motor with liquid or solid fuel.

According to the invention, a real-time apparatus for Fourier analysis of data includes an input system with a linear graduated multi-decade filter against secondary stocks (anti-alias) and an analog / digital converter, a switch system connected to the input system, two parallel memories that alternate are supplied with digital data via the switch system, a filter arrangement through which the content of each Memory has to wrap around in sequence to each Fourier component analyze the stored data, an averaging device for similar Fourier components, as well as an output system.

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The invention is illustrated below by way of a typical Example explained in more detail with reference to the drawing.

Fig. 1 is a block diagram of part of a

Fourier analyzer that does the data reduction shows;

Fig. 2 is a block diagram of a portion of a

Fourier analyzer showing Fourier processing;

Fig. 3 is a block diagram of a portion of a

Fourier analyzer showing the averaging and display assembly;

Fig. 4 is a block diagram of a portion of a

Fourier analyzer showing digital controls;

Fig. 5 is a graph showing a possible test signal to be analyzed;

Figure 6 is a circuit diagram of one useful form a filter against secondary values (anti-alias filter); and

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FIG. 7 is a circuit diagram for explaining the filter shown in FIG. 6.

The analyzer shown in a block diagram in FIGS. 1 and 2 is intended to be operated on an analog signal generated by playing back a recording of a test event such as a rocket ignition. That Signal can be of the form shown in Figure 5, i.e., it can show a sudden burst of activity that is then triggered by a general level drops. It is desirable to have the energy content of the shock at each of a variety of component frequencies to find out the shock. The duration T of the shock cannot be predicted before the test, although it is of course known after the test result has been recorded and checked prior to analysis.

It is known that the energy content of a shock at a given frequency can be calculated by dividing the shock into sections, for example with the duration f? is divided, the Fourier transform is calculated at the given frequency for each section, the result for each segment is squared, and the mean value is formed over the entire collision. The minimum frequency for which the method applies is given by λ / χ . The maximum frequency depends on a number of factors discussed below. In the case of a digital analyzer, this maximum frequency is an integral multiple of the minimum frequency

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sequence, a result being obtained for each intermediate integer multiple of the minimum frequency, if every accessible information should be extracted from the incoming signal.

In the present case it is desirable to have a digital System manufacture, with the scanning of the incoming analog signal is necessary to convert it into a series of digitally represented sample values · Therefore, the sampling theory is limited the maximum analysis frequency to half the sampling rate. An input filter must be provided in order to exclude higher frequencies from the signal fed to the scanning device. However, the closer the maximum analysis frequency is brought to its theoretical maximum, the better the operation of this input filter must be on the Be cutoff frequency. In order to avoid difficulties in the filter structure, it is therefore customary to use sampling rates with at least three times, if possible four times the maximum analysis frequency to use. This input filter is common known as the "anti-alias filter" (filter against secondary values).

The analyzer shown includes an input part 70 (FIG. 1), a storage part 80 (FIG. 2) and a processing part 90 (Fig. 2). The input section 70 is arranged to receive an incoming analog signal, es

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filters to remove components outside a desired bandwidth, periodically samples the filtered signal, and provides a digital output representative of the results of the sampling function. The memory section 80 is operated to divide the flow of incoming samples into successive blocks representing equal time fragments of the analog signal. Each block of samples is repeatedly fed to the processing part 90, which acts on it a corresponding number of times in order to calculate a corresponding number of Fourier components for this time fraction. The Fourier components for the successive time fragments are fed to an average value image shown in FIG. 3, where they are averaged over the entire collision. The structure of the parts shown in FIGS. 2 and 3 will first be described. The averaging generator and a control part shown in Fig. 4 will be described later.

The input signal, which is in the form of alternating current or direct current, is assumed to be an acceleration representation. It is fed into an input attenuator or amplifier 10 which is used to reduce the input signal to a Set the maximum level that is most efficiently processed by the analyzer.

From the attenuator / amplifier 10, the signal goes to a filter unit 110 with an input filter 11 and a

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Main filter 14 out. The structure and the interrelation
these filters will be described later. The effect of the filter unit 110 is to block frequency components above the maximum analysis frequency. The output of the filter
11 is shown connected to a first integrator 12 with respect to time, by means of which a speed component can be generated if desired. The integrator signal can be routed via a second integrator 13 for further integration with respect to time, whereby the path can be represented if necessary.

From the filter unit 110, the filtered signal arrives at a sampling and holding or tracking and holding device 17, which, under the control of the control part, samples the signal at a rate of four times the maximum frequency set by the filter unit 110. From the scanning
and holding device 17, the samples are transferred to an analog /
Digital converter 19 fed to the sample data in a
digital form with an output signal comprising 8 binary digits + sign converted into offset binary code. The output signal of the converter 19 arrives at a code converter 20 (which changes the code to the size -f sign), from which the output leads to the memory part 80 and also to a comparison circuit 22. The other input of the comparison circuit 22 comes from a 3-decade coding switch 23, which is used to generate a standard variable which is in the comparison circuit 22 with the input variable of the

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Code converter 20 is to be compared. When the signal from the transcoder 20 is larger, it causes a signal D to be fed to the control section to indicate that a usable Input signal has been received, whereby the Fourier processing part. can be operated to receive and process the relevant signals.

According to FIG. 2 of the drawing, the memory part 80 contains two circumferential parallel memories 24, 25, which have a Switch system 26 from the transcoder 20 are fed. Each memory has a sufficient number of parallel dynamic Shift registers with a length of 1024 bits each to receive the input signal from the converter 19, i.e. in this example 9.

Each memory is operated cyclically by the control section, with each cycle consisting of a write and a circulation mode consists. The memory 24 is operated in the write mode while the memory 25 is operated to circulate, and vice versa. In the write mode, the memories are operated in the sampling cycle, so that the data from the converter directly from the memory that is then in the write mode. The saved However, data circulates under the control of a wraparound clock at a rate much higher than the sample rate, i. they are effectively compressed in time. In this way, a given block of samples in the "first" memory

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rather many times, for example, circulated 256 times at a time / which is no greater than the time to feed the following block of samples into the "second" memory. The control part then reverses the switch system "26, so that the in the "Second" memory block stored the same number of times - circulated while the next block is fed into the "first" memory. In each register-will be at the beginning entered a lap marker in its write mode. For each round trip of a given block of samples, a corresponding data flow branched off from the circulation path for feeding the processing part 90.

In a digitized system such as this one, the Fourier transform can be any integer multiple the minimum analysis frequency by the expression

N-1 · ■ ■ ■.

F (k) = / x (n). exp (-j2 knN ~ ¹ j

n = o.

where N is the number of samples in each data block (i.e. in each full memory) and k is the number in question standing multiple is. In the present case, the Fourier components are calculated in successive rounds .. In the first round, k = 0 to represent the direct current state ..

In the second round, k = 1 to represent the minimum analysis frequency, while thereafter k increases by 1 with each lap until the maximum analysis frequency is reached.

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Within the summation symbol, the exponential expression can be represented by sine and cosine components of the same basic waveform, which depends on the current value of k. For each value of k, the corresponding waveform can be represented as a series of digital values. The processing portion 90 operates by supplying a flow of sample data, χ (n), to a complex multiplier 27 which also receives digital data representing the sine and cosine components with a waveform corresponding to the current orbit. The data flows are combined in the multiplier, the resulting flows of products being summed up, each representing the real and imaginary parts of the transformation.

The digital data representing the exponential function are generated in a read-only memory (ROM) 28. This owns two rows of addresses, a number of which have respective ratings up to 90 ° one. Sine curve shape? ,the other which assigns a cosine waveform; the remaining 270 of the full cycle can in any case by reversing the reading of the read only memory addresses and inserting a appropriate polarity change at corresponding points in the readout sequence.

The complex multiplier has a pair of multiplier sections each of which receives the sample data flow, but the respective data flows from the sine and

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the cosine address strings of the fixed value spexcher 28 received. These multiplier sections generate respective output signals which are fed to the summing devices 29 and 290, respectively which are set up for summing over N input products are.

All the required waveforms are generated from these same two address series in the read-only memory 28; the process is the same in both cases, so that only one is described. In the control part (Fig. 4) a summer 40 is provided, the output signal of which can be supplemented * when it reaches a predetermined value. The running total appears on lines P, Q and R and is fed to read-only memory 28 to store the To effect reading out a corresponding value stored therein. The summer 40 operates with a clock that is controlled by the circulation cycle, but not necessarily is equal to this; in the present case it is sufficient to set the summer 40 to half the cycle rate to increase gradually. Every time it is operated, the summer 40 adds to itself the output value of a counter 41. The latter is counted at every turn increased by one, responding to the above lap marker and returning to 0 when all the laps of a given data block have been completed.

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In the first round, 4Ik = 0 in the counter, which blocks the read-only memory 28 so that the Fourier output of the processing section represents the direct current state. In the second round, k = 1 is stored in the counter 41 and causes the counter 40 to increase in unit steps. In this way, all the addresses of each row in the read-only memory 28 are read out in succession. The flow of sample data is thus combined with a full cycle in sine and cosine form. In the third round, k = 2 in the counter 41, the adder 40 increases in steps of two and every second address in the read-only memory 28 is read out. Since this happens with the same clock speed as in round 2, the sample data are combined with two full cycles in sine and cosine form.

The output signals F (k) and F (k) of the summing

S C

Devices 29, 290 provide the sine and cosine components the transformation; these are fed to the respective digital squaring devices 30, 300. the Output signals of the latter are fed to an adder 310, the output signal of which is the square of the required

Γ 1 * 2

Transformation ^ F (k) J represents. This in turn represents the energy of the frequency component (k. f ^.) in the time segment represented by the data block,

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which has just been processed. As in this case only is the energy of interest, the phase information carried by the components F (k) and F (k) became at the Squaring process made to disappear. It is worth noting that every squarer gives a true square, since it only operates with numbers, whereby those with analog squarers associated difficulties can be avoided.

However, this result only applies to the period 'C of the joint shown in FIG. To get a result for the entire thrust, the results for T / £ r sections to be averaged. The one shown in FIG Mean value images must be added to add the appropriate number of outputs of the processing part 90 and to divide the result by that number be. This is preferably accomplished as a running averaging, in which the running sum is divided by the Number of output signals added to obtain the sum is divided.

The most common type of averaging in a binary digital system is one that divides by 2 ^, as this can be done by simply moving data. The mean value image 31 is set up to work in this way, combining the existing stored data with the incoming data

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by circulating the former in synchronism with the feeding the latter is accomplished. The factor a varies as the analysis proceeds from 0 to T / ■ # and becomes below explained.

The mean value former 31 can be a static shift register with a length of 256 bits and a width of 32 bits. The jagged output from this register is in 16-bit format and it is impractical to use a 16-bit digital-to-analog converter to operate the display. It is therefore appropriate to convert the power value into its logarithmic equivalent, which is carried out in a logarithmic converter 32. The logarithms based on base 2 are typically used, as only one constant normalization factor is included. Simply decoding the position of the most significant binary digit of the 16-bit format results in the characteristic value of the logarithm as a 4-bit number. The four next-value binary digits form the address for a read-only memory, the output signal of which is on. + 0 _{P represents} 1 dB exact equivalent 4-bit mantissa. This 8-bit composite number can be used to operate a simple. 8-bit digital / analog converter 33 can be used, from which the result is displayed on an oscilloscope> or curve recorder 34, which is horizontally deflected in an adjustable clock that is adapted to the displayed data. The original resolution of the analog / digital conversion in 19 will be

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retained in 33 for the digital / analog conversion.

It can be seen that. a mean value image that can ^{only average 2 a} sections exactly, restricts the duration t of each section, which by 2 =? Τ / 2Γ is given, where in the present case T is not controllable. This actually forms a restriction on the maximum analysis frequency, which is given by a fixed length N of each memory 24, 25, because ^ = N * fs, where fs is the sampling rate and fs = mx f; there is the

Max

the last factor is the maximum analysis frequency and m is a constant, usually 3 or 4, as explained above.

To ensure that the number of averaged sections is precisely adapted to each desired analysis time can be, it is therefore desirable to have a continuously variable or at least very high in the input part Triggering filter against secondary values (anti-alias filter) to have. In the present case, this is done with a filter structure which is shown in Fig. 6, which shows in greater detail the filter 14 in Fig. 1, such as shown in Fig. 6, three filter sections are connected in series. Each section has a similar one Second order filter. On, where the combination is a Butterworth low-pass characteristic results in sixth order. · The one for a tactile clock in the size of four times the maximum

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Analysis frequency is sufficient.

Since the sections are similar, only the first described. It should be noted that the overall structure a second-order low-pass filter with voltage-controlled Voltage source (VCVS) Similar, but with the resistance component of the normal filter (VCVS) is replaced by a capacitor reversing device shown in blocks 50, 51. The mode of action this structure can be better understood by considering the corresponding first-order filter shown in Fig. is shown.

The first-order filter shown in Fig. 7 has a resistor R, which is only provided to ensure a current limitation at the input source, a first capacitor with the value C, which is connected in series via a bridge circuit of switches with R, as well as a parallel capacitor with the value pf C. Opposite switches of the bridge circuit are coupled and operated in antiphase, so that the connection of C into the series line is alternately reversed. This creates transient effects that affect the rise time of the voltage across oi C.

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It can be proved that, in response to a stage input signal, the circuit shown in FIG a voltage output signal via cK C in the form

V (t) = 1 - exp

<X + I) ^-1 y

results, where f is the polarity reversal frequency and t an integer Is a multiple of l / 2f. A corresponding voltage drop

with the same time constant is determined across the bridge circuit. Filter designers will recognize that this Term includes that the circuit shown for Achieving a first order filter characteristic in high-pass or low-pass type can be used and that the Mode of action of the polarized capacitor a resistor with the value

Is equivalent.

The one in .Fig. 6 second order filter structure shown is generally achieved by inserting blocks of reversed capacitors in place of their equivalent resistances in derived from the VCVS structure. However, an additional amendment should be made to prevent the second Polarity reversal stage 51 actually short-circuits the connection of the first stage 50 with the counter coupling loop 52. Around

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- .18 -

To prevent this, an additional isolation amplifier 53 is inserted. This can optionally have signal amplification. The capacitor polarity reversal is actuated by a common polarity reversal frequency via a phase separation stage 54, which ensures that the pairs of switches in each bridge are operated in phase opposition. For given values for cK and the isolation amplifier gains (which are defined in the construction phase and can be different for the filter sections) the cutoff frequency is determined by the polarity reversal frequency. This is preferably, but ¹ "not necessarily the same for each section and each stage, since the effects of multiple polarity reversal frequencies can be offset by changing the component values. that they produce the required filter characteristics, ie the WelMgkeitskomponente in the pass band, the slope, etc.

Since the filter shown uses 14 polarity reversal switches, it is by nature a scanning device and can be used in the same way as the digitization part of minor values (alias) bring in. The possible secondary values be arranged so that they appear sufficiently far from the cutoff frequency point to allow their removal by a "demarcation" filter 11 (Fig. 1) with relatively simple structure and with exclusive reference to the most significant part of the cut-off frequency value of the main

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filters 14 is made possible.

Those familiar with spectrum analysis technology will find that the present apparatus does not use a "Window function" changed the tent domain. This course of action would inherently introduce errors in the test results, when transformed into the frequency domain. It should be noted that careful use is made of the use of a high resolution filter at the input end of the analyzer Allows selection of the minimum analysis frequency so that "leakage" into "sidelobes" in the frequency domain is avoided (see article "The fast Fourier transform's errors are predictable, therefore manageable", "Die Fehler with the fast Fourier transform are predictable, therefore disposable "by Robert W. Ramirez in" Electronics ", Edition June 13, 1974). This can have an undesirable effect on the entire duration of the analysis if the mean value images cannot be adjusted accordingly, but in any case the analyzer has an additional degree of freedom In this regard.

4 shows a control part for the analyzer The filter unit 110 is operated via a multiplier operated by a quartz clock generator 16 through a typical four-decade coding switch 15 controlled, creating a polarity reversal curve shape "B" is generated which determines the maximum analysis frequency. The most significant decade of switch 15 becomes at "A"

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Used to control the demarcation filter. The use of a four-decade switch 15 enables the linear Graduation of the maximum analysis frequency over a range from 10 to 9999 Hz in steps of 1 Hz.

The signal B is also fed to a divider 18 in order to to generate a control signal "C" for the sample and hold device 17 and the analog / digital converter 19. So will expediently the maximum analysis frequency and the corresponding sampling frequency by operating the same Switch 15 controlled. A signal derived from the signal "C" is fed to the switching system 26 to one of the. Lines E or F to supply the memory 24 or 25, whereby the writing of the scan data in the corresponding Clock is made possible. From the clock generator 16, the switching system 26 circulating pulses are supplied. Switching over the switching system is acted upon in response to counters that set the respective Memories 24, 25 are assigned and show their memory status.

In an alternative arrangement, the controller is of the polarity reversal sampling clock by incorporating the switch 15 separated into a separate oscillator circuit for providing the output signal B from the clock 16. The desk 15 can then be arranged for changing resistance values in the oscillator for changing the Umool clock.

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The analysis is triggered by using the comparator 22 which generates the signal D, but it can only can be started by a clock control 35 from the recorded data or a clock 36. To this Way, the control signal D interacts with another signal from the clock 36 or the recorded Clocking 35 to initiate the operation of a four-decade counter 37 is controlled to introduce a certain Delay from receiving the signal D on is used can be. When the count is equal to a count set in a code switch 38, the switching control becomes 26 pressed to start the analysis.

When the analyzer described above is used to analyze in real time the output of an accelerometer coupled to a rocket motor during the ignition test, the output is first recorded and the length of the ignition or the ignition period to be analyzed is noted. This length determines the length of time over which the Fourier components are to be averaged, whereby it can be equated with a function of a power of two. The power of two determines the division of the period into the required periods of time; if, for example, the duration of a test is T seconds, it can in this way be broken down ^{into 2 a} time segments with a respective duration T / 2 ^a.

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If the test duration is broken down into such time segments, the minimum frequency that can be analyzed is 2 ^a / T. The a is defined together with the time segments, so that the operation of the averager is such that the duration of the test will exactly coincide with the duration that is being averaged. Once the time segment has been defined, the maximum is

_o a

Frequency - ψ times the number of filters that have been artificially produced from the processing part, ie the number of processing rounds. The code switch 15 is then set to adjust the anti-aliasing filter to provide the appropriate maximum frequency, the delimitation filter automatically removing signals of a much higher frequency. The coding switch 15 also controls the analysis sampling via the sampling and holding device 17.

It should be noted that in this example the coding switch 15 has four decades. Typically he will a maximum recru ^ n ζ range from 10 to 9999 Hz in 1 Hz steps result. If, for example, a six-decade switch is used, this would be in 0.01 Hz steps, from 10.00 to 9999.99 Hz work.

In the control part, the lap marker G could

by dividing the round-trip clock output by the number of samples stored in synchronism with the ordered one Contents of the memory can be derived. That

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Switch system can be made by counting the appropriate number are actuated by scans, the counter being actuated independently of, but synchronously with, the write pulses will. The clock generator 36 can be derived internally or externally. The system was considered to be on record of test results derived data, but it could of course also work on direct data. the Using a "window function" brings in the treatment Non-stationary data errors, but they can be useful if the data processor is to process stationary data Data or random data is used.

The read only memory 28 can be operated as follows, certain binary digits of the running sum in the adder 40 can be routed to lines P, Q and to Addressing different subsections of the read-only memory 28 are decoded. In this case there are four sections each sine / cosine. Each subsection is of the same type and can have other binary digits of the sum, the appears on corresponding lines R, whereupon he creates a corresponding weighted size for the Sine or cosine waveform responds. However, alternative arrangements for creating a sine-cosine output signal can be used can be used.

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It can be seen that, as described, all ' data collected in each time period for each Fourier component can be used without losing any data. The averaging is therefore performed during real time of the data to be analyzed is carried out at the same time with high accuracy. Because of the limitations of the Memory amount, the sampling rate and the circulation rate can however, real-time operation above certain maximum frequencies cannot be achieved.

It can also be seen that by disabling the operation of the exponential complex read-only memory 28 and the summation at 29, the incoming data can be carried out directly to the squaring system at 30, whereby an immediate square value of the data is generated which is timed with the same Dividing each time signal can be totaled and averaged to produce a display showing the mean distribution of power over a time segment when a = 2 . If a = »0 or, either 1/4 or half of the time period is displayed. Alternatively, each time period can be totaled to provide an indication of the distribution of power over the fixed period. Since the vertical scale has a logarithmic format, this distribution is proportional to the currently sampled effective values (root-mean-sguare).

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The invention is intended to provide a spectrum analyzer, which has an input filter whose upper cutoff frequency is essentially stepless within a given range is variable or set with a high resolution

• I

can be. '.

As an alternative, the invention is intended to provide a spectrum analyzer create a device for operation on an analog input signal, which is derived from a series of digitized, derives representative samples for a period of the input signal, a device for Creating a complex exponential function digital data to connect to said series in order to to calculate a Fourier component of the time segment of the input signal, and a device for combining the Samples and the data to form the component.

Furthermore, a spectrum analyzer is created with the invention, which is a device for processing digital, data representing an analog input signal for generating its Fourier components, a device for operation at the input signal for generating the data, as well as a filter device for controlling the maximum frequency, which is introduced into the data generation device with the upper limit of frequency of the filter device in response on an electrical input signal supplied to it,

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is cash. It is desirable to derive this electrical input signal from a control device ^ which also controls the device for generating the data from the input signal.

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Claims (10)

.- 27 '- Claims ('ll) spectrum analyzer characterized by a first device for receiving an analog input signal and for generating a series of blocks of digital Data, which represent its successive time segments, by a second device for individual processing the data blocks for producing output signals which represent their individual Fourier components, as well as by a third device for averaging Fourier components derived from a number of consecutive Blocks have been generated, the first and the third device being controllable so that the duration of the subsection of the analog signal represented by the averaged blocks to a required value substantially same value can be controlled. 2. spectrum analyzer according to claim 1, characterized in that the third device daft components for can average a number of blocks given by 2, where a = 0 or a positive integer, and that the first Device a filter device for limiting the maximum frequency of the analog signal and a digitalization device for generating digitized samples representing the filtered analog signal, wherein the filter 509823/0823 τ W- device is essentially continuously variable or with a high resolution over a given range. 3. spectrum analyzer according to claim 2, characterized characterized in that the filter device is controllable by an electrical input signal fed to it has upper limit frequency value. 4. Spectrum analyzer according to claim 3, characterized in that that a control signal for the filter device and the digitizing device in one common control device is generated. 5. Spectrum analyzer according to one of claims 2 to 4, characterized in that the filter device a 'combination of series and parallel capacitors as well as a device for cyclic polarity reversal of the connections which has series capacitors. 6. Spectrum analyzer according to one of the preceding claims, characterized in that the second device an apparatus for generating digital data representing a complex exponential function for combination with the block data for calculating their Fourier components and a device for combining the block data and the has data representing the exponential function. 509823 / Q823 7. spectrum analyzer according to claim 6, characterized in that the-to be combined with the blocks digital data represent sine ^ and cosine waveforms, the real and imaginary parts of a Fourier component to create. 8. spectrum analyzer according to claim 6 or 7, characterized characterized in that the combining device comprises a device to multiply the data flows with each other and a summing device for summing the products thus formed. 9. spectrum analyzer according to claim 8, characterized by an adder for squaring the summed products. - 10. Spectrum analyzer according to one of claims 6 to 9, characterized by means for repeatedly supplying the data representing a given block to of the combining device, as well as by a device for supplying the respective exponential functions to form the respective Fourier components every time, when the data block is fed to the combining device will. 509823/0823