DE2453247C3 - Arrangement for digital frequency measurement - Google Patents

Description

The invention relates to an arrangement for digital frequency measurement according to the preamble of the claim I. Such an arrangement is essentially known from I) S-PS 24 51 202.

Digital speed measurements are usually carried out in such a way that the speed is converted into a pulse train, for example by means of a pulse generator coupled to the molar shaft, the frequency of which is so high that a certain number of pulses per revolution is generated. The speed to be measured is therefore proportional to the frequency of the pulse train. The pulse sequence is fed to a counting mechanism, and the number of pulses selected within a certain period of time is a direct measure of the speed.

Due to a quartz-controlled time base, such a method results in high resolution, measurement accuracy and high time and temperature stability.

In order to achieve a resolution of z. B. to obtain 0.1%, 10,000 measuring pulses must be can be counted at full speed. If the pulse generator gives 10 kHz at this speed, then is the counting unit 1 sec.

This measuring speed is insufficient for control purposes , since in the worst case a change in the measuring frequency is only detected after two measuring periods, ie after 2 seconds. For controls it is often desirable to get by with a counting time of only about 20 milliseconds . In this case, a speed measurement of the type described above must be supplemented by an analog tachometer generator, which makes the measurement complicated and expensive.

By described from US-PS 29 51202 A higher resolution is achieved in the arrangement, but when the measured variable changes, the Transition of the measured value to the new value according to an exponential function, the time constant of which is relative is great. Although a measure is provided in the known arrangement by which at a Change of the frequency to be measured of the counting unit additional counting pulses are supplied, whereby a faster transition of the measured value into the new equilibrium state is achieved. These The measure only has a significant effect if the change in the frequency to be measured is relatively large. In control loops, however, the change in a frequency occurring as an actual value is regular tiny. In addition, the described additional Measure very complicated in their construction, and the calculation of the construction of a control system parameters to be set is extremely difficult, which is the practical value of the known arrangement degrades. Another disadvantage of the known arrangement is that the output signal is at the known arrangement carries out constant fluctuations even at a constant frequency to be measured as a result of the continuous going back and forth of the Meter reading. This means (. Leave the output signal Contains harmonics, which complicate the further processing of the output signal.

The present invention is based on the object of providing an arrangement of the type mentioned at the beginning to develop further in such a way that the Adaptuni; of the measured value to a change in the to measuring frequency takes place relatively quickly, but the structure of the arrangement is simple and for the Setting a control loop parameters required can easily be calculated. I want the output signal be as free from harmonics as possible.

To achieve this object, an arrangement is proposed according to the preamble of claim I, according to the invention has the above-mentioned in the characterizing part of claim I Feil characteristics. Advantageous further developments of the invention are mentioned in all of the subclaims.

Using the Aiisfuli in the I igmcii il.irgcsldllen ι ungsbeispieles the l'iliiuliing is explained in more detail It shows

I i g. I an unified Ulm. Km left to the frieze tion of the principle of the invention.

2 shows a detailed representation of the basic circuit according to FIG. 1,

3 shows the time relationship between a series of signals in the circuit according to FIG. 2,

F i g. 4 shows in diagram form the result of a practical case in which the arrangement according to the invention is applied.

In the embodiment shown in FIG. 1, the arrangement according to the invention consists of a pulse generator CLC, which generates a pulse train CP of a certain frequency , a synchronization and control unit SCL, which is supplied with a pulse train FX with the unknown frequency Λ from a measuring element PU and the pulse train from the pulse generator CLC , a Counting unit UDC, into which a first control signal Ni is fed from the synchronization and control unit SCL , one connected to the counting unit UDC with several connections for transferring the content C in the counting unit UDC and can be influenced by the synchronization and control unit by means of a second control signal 7CH Register unit RL

Further, a digitaie be frequency unit DRM is present, in which the pulse train CP from the pulse generator CLC and the content F become the register unit RL fed by means of several compounds · The digital frequenzmuhiplizierende unit D /? A- / are doing a pulse train / R, which via the synchronization and control unit SCZ. the content in the counting unit UDC by means of a third control signal / V influenced.

With reference to Fig. I first the principle of Fiinkiion described before referring to the detailed illustration in FIG. 2 is received.

The output signal from the multiplying unit DRM, i.e. the pulse train FW, the frequency / «of which is proportional to the product of the frequency l \ of the pulse train (/ 'delivered by the pulse generator (/.('and the content Fin of the register unit Rl.)

where ^ jeine Proportioruilitäiskonstanic and HS / <Λ /

With each pulse in the pulse train FR , the content in the target unit i '/ X' is reduced by N, units. After each pulse increase in the unknown pulse train FX with the frequency l \ , the synchronization and control unit initially generates a control signal / V for the counting unit UDC. where the content ('· increases by N _: units. Then the S synchronization and control unit generates another control signal HH for the register unit RL, the content C of the register unit UDi being transferred to the register unit Rl. and control unit .S '(I. in this case controls the timings for said subtraction and addition, so that they do not babble together. the addition /V.· animal units and the I Iberführung the contents i! effected / wipe two pulses of the pulse sequence (/ '(see in Fig.) the mutual position of the li.ipiilsliilgen (/'. FV /V.·. IR, N, and IC II).

Aul Fig. 4 is (the ratio / w is *, hen den ( I and Cl at different frequencies / eu /, can be seen if Λ / - 10 000. M - Ι.ΛΛ 100 / i = I MII / during a Period 7 \ of the unknown frequency

the content in the counting unit UDC gradually (if N \ = 1) decreases by a total of / «■ T, and then increases suddenly by A /? at the time of a pulse of frequency /, i.

If the content in the register unit RL is denoted by Fi at the beginning of the η-th period of the unknown frequency Λ, then the following applies:

Fi-i = F _k - / "■ 7 \ + N ₁ - F _k - '" + M.

(2)

By combining equations (I) and (2) one obtains:

is /, constant and

Vv Λ /

1 .

d. H.

so F _k converges to f geniäli in equation (3)

F = lim h \ - ' ² ■ l \. (51

ι. ■ ι h

ie the content F in the register unit Rl. is proportional to the unknown frequency / \. If besides

... il. h .. if

ΛΛ /

., si »the convergence is monotonic.

From equation (2) one obtains Im a change I / \ of F during the k- \ c \\ period of the frequency A,

This change \ l \ takes place during the line / ,. I in F, · Od h. / \ - · "is obtained

IA ₁ . d / _t

i \ d / ■

and the (K naiiiisi he Vcihallen tier arrangement! .ηίιι.ιΙ '

of the invention can be expressed by the differential equation

are described which have a solution

(9,

shark. For / ■■ ♦ / one obtains

Jc

(10)

The quotient -J ^ according to equation (9) corresponds to this

reciprocal value of the time constant of the exponential function

hi = r ■ ^(ll)

Jc

It can be stated here that F, ie the content in the register unit RL, increases exponentially for high frequencies

Af · A ₂

converges with the time constantc

™ - Te '
From equations (11) and (6) one obtains

Hi = -λ- = T _Xmix , (12)

Y A min

Convergence Λλ mm = 50 Hz. Where the
Measuring frequency 9999 Hz and the measuring range

maximum

ie the time constant r «is equal to the period T, ma« for the lowest measuring frequency which results in a monotonic convergence. The convergence curve at low frequencies differs from the exponential so as from the more, the more f \ to f \ """approaches. However, the correct measured value is obtained just as quickly as with high frequencies, ie in a time corresponding to 3–5 times TM.

For a practical case shown in FIG. 4, one obtains a resolution of F with 0.1% o, tm = 10 msec, lowest measuring frequency for stable convergence fxmin = 100 Hz, lowest measuring frequency for stable

= 100

F i g. 2 shows a detailed embodiment of the basic arrangement according to FIG. 1.

The pulse generator CLC consists of a crystal-controlled oscillator OSC and a number of negation elements IN \, IN ₂ and INi with additional elements R], /? 2 and C. The negation element INi and the amplifying negation element INi ₁ contained in the synchronization and control unit SCL amplify this Output signal from the oscillator und_form it into a square pulse train CP or CP . See FIG. 3, which describes the time relationships between the pulse trains given below. The digital frequency-multiplying Einheil DRM consists of four cascaded multiplication elements

DRMO, DRMi, DRM2 and DRM3 as well as a NAND element / * ,.

The cascade connection is established through the connection between the inputs IN and OUT of the relevant multiplication elements.

The pulse train CP is fed to each multiplication element and the elements are connected via their inputs .4, B, C and Dan to the relevant inputs Q _A , Qb, Qc and Qo of the register unit RL comprising four elements RLO, RL 1, RL 2 and RL 3. Each multiplication element DRMO, DRMX, DRM2 and DRM3 generates a pulse sequence Fnro, Fun, FuT2 or Ftin, the center frequency of which is as follows:

/ l7 3 = F ₃ -0, \ f _c

J ₁₁₂ = F ₂ -O ₁ O! / ,.
f _lrl = F ₁ ■ 0.001 f _c

and

/, ·, "= F ₀ 0.0001 /,

where F ₀ , F ,, Fi and F3 is the content (preferably in BCD code) of the relevant register element RL 0, RL 1, RL 2 and RL 3 and where fc is the frequency of the pulse train CP. _ _ _ _

Negated output signals Furo, Futu Fut2 and Fart are added to a pulse sequence FR by means of the NAND element A \ , the mean frequency of which is />

Jr = fun + fvTi + fun + / ντο = / _c (0, l F ₃ + 0.01 F ₂ + 0.001 F ₁ + 0.0001 F ₀ )

The counting unit UDC consists of four reversible counting elements UDCO, UDCi, UDC2 and UDC3. Each counting element has separate inputs for up and down counting, here called FORWARD and BACKWARD. A change in the FORWARD or BACKWARD state of a counting element occurs with the positive edge of the relevant input signal for UP or DOWN, while the input signal on the other FORWARD or BACKWARD has the logical value "L" has, ie voltage present, in contrast to the valency "0" = voltage not present.

When counting up and down, a counting pulse goes to the CRR- (BR ^ output when the state of the counting element changes from 9 to 0 (0 to 9). This means that the counting elements can be cascaded by a CRR- (BRW-) from gear to a VORWARTS- (backward) Ei _n transition closest counting element is connected. Dei

fts the respective state of a respective counting element is accessible to its Q _A , Qb, Qc and Qo outputs which are connected to the A, B, C or D inputs of the associated register element in the register unit RL .

sen are.

Corresponding to the circuit in FIG. 2, all counting elements UDCO-UDC3 for the downward counting of -1 pulses at the BACKWARD input of the counting element UDCO are cascaded. At the FORWARD input at UDCO there is a logical L Only the counting elements UDC2 and UDC3 are cascaded to count up a pulse at the FORWARD input of the counting element UDC2 , which means that every down counting with -1 unit at the counting element UDCO contains the content of the entire counting element UDC decreased by 1, while each signal N _{2 increases} the content of the entire counter by 100 units.

The synchronization and control unit SCL consists of four flip-flops FFl, FF2, FF3 and FF4, a number of negation elements // v », / Afc, / A4, / Li, IL ₂ , IL3, IIm, ILs and ILf, as well as the NAND Outline A ₂ , A3, A *, As and Ab.

With each falling edge of the pulse train CP (ie with each rising edge of the pulse train CP) the output Q of the flip-flop FF3 flips and its output signal DCP assumes the valency L. The signal DCP is delayed in the negation elements / Li, IL ₂ and INs to signal 51, which toggles the flip-flop FFR 3 and thus also the signal DCP to zero via the CLÄ input of the flip-flop FFR.

The signal DCP thus becomes a positive pulse of a certain width.

A negated logical product of the signal DCP, the output signal FR from the multiplication unit DRM and the signal DC £ is formed by the NAND element _{A 2} (with regard to DCE, see below).

If the signal DCE has the valency L and a pulse of the pulse train FR occurs during the continuous pulse generator period T _c , a signal is obtained at the output of the NAND element A ₂ which emits a negative pulse with the same width as that formed by the signal DCP Pulse, and that reduces the content of the counting unit UDC by one unit. If no pulse of the pulse train FR occurs, the output signal from the NAND _{gate A retains 2} as valence L, and no subtractions are carried out

The aforementioned subtraction is repeated as long as the content of the counting unit UDC is positive, if the content of the counter unit t / is DCnegativ, ie 9999, one obtains a negative pulse at the BWR output of the counting element UDC3, and as a flip-flop connected and working NAND gates Ai and At, change the state of the output signal DCE, and a further downward counting of the counting unit i / DC is stopped

It is assumed that the signal FX, the frequency f _{x of} which is to be measured, is transformed into a pulse sequence with logic levels according to 7TL

When the signal FX has the value 0, the flip-flops FFl, FF2 and FF3 are set to zero, that is, the signal N ₂ from the Q output of the flip-flop FF2 is L, and the signal TCH from the O output of the flip-flop FF4 is 0. If the signal FJf assumes the value L, the flip-flop FFl is set to L on the following positive edge of the signal 51, ie a certain time after the signal A / i am from the NAND gate A ₂ L and a unit from the counting unit UDC has been subtracted.

An L signal 52 at the O output of the flip-flop FF1 flips the flip-flop FF2 to L, whose signal at the O output, ie N ₂ , becomes 0. After a certain time the flip-flop FF2 is toggled to 0 in that the signal 54, which is the output signal for the (^ output of the flip-flop FF2, which was negated and delayed by the negation elements JLz, ILa and INt , becomes 0.

The signal AZ ₂ is fed to the FORWARD input of the counting element UDC2 , the total content in the counting elements UDC2 and UDC3 increasing by one unit and consequently the content in the whole counting unit UDC by 100. The signal N ₂ also influences the flip-flop ArA ,, so that the

Signal DCE goes low if it is not already

is

The signal 54 is in the negation elements ILs and

/ L ₆ and in the NAND elements As and Af ₁ , which are connected like negation elements, are delayed to form signal 55, the growing edge of which flips flip-flop FF4 when its D input has the value L. The time delay of signal 54 is longer than the time

which is necessary for changing the status of the counting elements UDC2 and UDC3 after adding 100 units.

If the flip-flop FF4 is set to L and the signal TCH assumes the value L, the content in UDCO, UDC i, Udc2 and transferred to the respective Regibterelemente AELO, ALI, AL2 and AL3 UDC3, wherein the RL register unit receives a new measured value of the flip-flop FF4 and the signal TCH go by the rising edge of the The next pulse in the pulse train CP to the value 0. From the last-mentioned pulse, the multiplying unit DRM generates a pulse train with a mean frequency which corresponds to the new content F in the register unit RL

If the signal FX assumes the value 0, the flip-flop FF1 is toggled to 0 and the method described above is ready for a repetition when the signal FX assumes the value L at the beginning of a new period of the measuring frequency / _{x next May} The number unit UDC and the multiplication unit DRM can also be arranged so that they operate with a different code than the BCD shown here. For this purpose, the elements in question are exchanged, for example, for elements with work a binary code in which the ratio NtZN ₂ becomes a power of 16.

By means of an arrangement according to the invention, a speed in digital form with sufficient Speed can be measured, which also means the Possibility to form a command or setpoint within a desired control time and before Get control deviation of high precision and resolution, making it quick and easy Speed control is possible

The arrangement according to the invention can also be used as a speed sensor instead of DC tacho generators in positioning servo systems with digital incremental or absolute Measured value acquisition or used with step motors will.

By means of the arrangement according to the invention one also obtains the possibility of an accurate and fast measurement of very low frequencies. For example, for a measuring range of 0.01 - 1 Hz and A resolution of 1% is obtained by means of the arrangement according to the invention, a measurement time of only 100 seconds, while the conventional pulse measurement would require a time of 2½ hours.

For this purpose 3 sheets of drawings

809 610/257

Claims (5)

Patent claims: 1. Arrangement for digital frequency measurement, in particular for digital speed and speed measurement with a pulse generator, a control unit, a multiplying unit and a counting unit, the pulse generator generating a first pulse train of constant frequency and the multiplying unit generating a second pulse train whose frequency depends on the Product of the frequency of the first pulse train and the content of the counting unit is dependent, the counting unit also reducing its content by a first value for each pulse of the second pulse train, a measuring element being present which supplies the control unit with the pulse train to be measured in terms of its frequency and further wherein the Zählein- at each pulse of the increased integrated to be measured pulse train their content to a second value, characterized in that said second value (7V.?) is greater than said first value (N ₁₎ and that the Contents (C) of the counting unit (UCD) after each such addition reaches a new maximum value (F) , which represents the frequency (f _x ) of the pulse train (FX) to be measured in digital form. 2. Arrangement according to claim 1, characterized in that the frequency (ίκ) of the second pulse train is equal to the product of the frequency (f () of the first pulse train and said maximum value (F) , divided by a proportionality constant (M), the greater than the specified maximum value (F) \ sl. 3. Arrangement according to claim 1 or 2, characterized in that a register unit (Rl) is present between the counting unit (UCD) and the multiplying unit (DRM) which has a first maximum value (Fk) of the content (Ci) in the / iihleinheit (LlCD) stores until a second maximum value (Fi ,,,) is available. 4. Arrangement according to one of claims 1 to 1, characterized in that the ratio between said first value (TVi) and said second value (N <) is 10 ", where /> is an integer. 5. Arrangement according to one of Claims 1 to 3, characterized in that the ratio between said first value (Ni) and said second value (N>) is lh · ', where q is an integer.