DE2443870A1 - SETTING A RECEIVER - Google Patents

Description

Applicant's file number: FR 973 002

Setting a reception clock

The invention relates to a method for setting a reception clock for data transmission systems according to the preambles of claims 1 and 2.

When receiving data, a common receive clock indicates the times for the evaluation of the received data signals as precisely as possible. The individual samples of the received signals should take place at the most favorable times. Usually the goal is to use the receive clock whenever possible
run at the same frequency as the clock on the transmitting side. An approximate match in terms of frequency and phase between the two clocks is achieved with signals that are transmitted before the actual useful signal transmission, and with the help of the useful data signals themselves. Before a useful data transmission, the phase position of the
Receive clock set and then continuously corrected during the user data transmission.

The ongoing correction is very important. She educates

S09820 / 0680

the subject of the present invention. For data transmission systems with a relatively low transmission speed, in which it is usually possible to work without an equalizer at the receiving end, the problem of phase correction is essentially solved. German patent application P 2 027 554.9 can be cited as an example of this.

The use of equalizers is essential for higher transmission speeds of 4800 baud and above. Such equalizers are mostly characterized in that their transmission path is continuously readjusted with an error signal derived from their output signal. At very high transmission speeds, which are now being used more and more, the distortions to be compensated are generally so great that the correction information for the receive clock can no longer be readily derived from the equalized signal.

An interesting method for solving the aforementioned problems was given in French patent application 71 20097. Thereafter, the clock control information is obtained from one of the data signals superimposed signal and not derived from the data signal itself. A weak amplitude modulation becomes the phase-modulated one Data signal superimposed. The disadvantage of this method, however, are additional noise influences on the transmission of the useful signal and in particular a limitation of the data transmission speed . Above all, a multi-level multi-phase transmission is not possible.

Another method uses the transmission of two pilot tones on both sides of the frequency spectrum of the data signal for transmitting the clock information. In doing so, however, the usable bandwidth restricted for data.

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It was also proposed that the clock information from the already derive the equalized data signal. It should be taken into account here, however, that with a combination of equalizer and clock control circuits a feedback circuit arises in which for the two tasks to be carried out, equalization and Clock recovery, completely different functions are to be performed. When such a combination is designed in digital technology serious problems arise. Adaptive equalizers mostly use only one sample per modulation period for setting. The derivation of clock control signals, however, requires at least several samples per modulation period. This results in a combination for processing several samples per modulation period; in order to the effort for the equalization functions is unnecessarily increased.

The purpose of the present invention is to solve the foregoing Problems regarding effort, correction accuracy, usability for multi-level multi-phase modulation and usability for data transmission speeds of 4800 baud and

The object of the invention is to specify a receiving clock setting method, worked directly with the signal received via the transmission medium before entering it into the equalizer will. The transmission of superimposed clock signals should be avoided.

The solution to this problem is characterized in claims 1 and 2. Advantageous refinements are set out in the subclaims described.

^{FR 973} ° ⁰² 5098 20/0 68 0

An embodiment of the invention is shown in the drawings and is explained in more detail below. Show it:

1 shows the block diagram of a receiver accordingly

of the present invention,

Fig. 2 shows the block diagram of the required clock control circuits of a particular embodiment and

3 shows the representation of a standard signal so designated.

In Fig. 1, a data receiver is shown which contains, among other things, an equalizer according to German patent application P 24 16 058.5. It is also assumed that the transmission method used uses multilevel differential phase modulation * The data in the form of the amplitude ρ and the phase φ are transmitted at discrete points in time of the transmitted signal.

The signal transmitted via a line is recorded in the receiver in the form of an analog signal r (t). This signal is fed to an automatic level control 1 and then to a scanning device 2, which scans _{at times t., Controlled by a clock generator 3 #.} Let l / T be the repetition rate of the data transmitted over the line, usually expressed in baud. The sampling frequency defined by means of the clock generator 3 is a multiple M / T of this repetition frequency, with a sufficient number of sampling values r. Being output during each period T for the correct definition of the signal r (t). The samples r. are then fed to a phase shifter 4, the sequences of samples x that are in quadrature with one another. and x. generated. The design of such a phase shifter is already mentioned in the above-mentioned German patent application P 24 16 058.5. The samples x. and x. are fed to an equalizer 5 according to FIG. This German patent application. Samples y, and y,

JK ic

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are used as the Cartesian coordinates of the equalized signal Detector and decoder 6 entered, after converting the Cartesian Coordinates y, and y, in polar coordinates p, and φ, on the one hand the recovered data and, on the other hand, the signals

cos Φ _{] ς} / Ρ _{] ζ} and sin Φ _{] ί} ./Ρ _{] ζ}

gives away. These signals become one side of the clock control circuit 7, which on the other hand also contain the samples x. and x. offered get and thereby a clock error signal CS to the clock 3 submit for its ongoing correction.

The FIGS. 2 and 3 explain in more detail the clock control circuits 7 according to FIG. 1. M samples x., Which come from the phase shifter 4, are fed to a second sampling with the repetition frequency 1 / T per modulation period T. The sample values obtained in this way (namely only one sample value per modulation period) are fed to a transversal equalizer 8, which uses them to produce the equalized sample value components y. forms. The samples x. subjected to a sampling with the repetition frequency l / T and the sampling values x. is fed to an equalizer, which outputs the equalized orthogonal components y _{k of} the equalized signal therefrom. It is assumed that the length of the delay lines of the two equalizers 8 and 2 is NT, where N is a positive integer. The equalizer functions of the two equalizers 8 and 9 shown separately correspond to the function of the equalizer 5 according to FIG. 1. They are not described in more detail here, since they are already known from German patent application P 24 16 058.5.

The samples x. are also fed to a delay chain consisting of the two delay elements 10 and 11. IO has a delay θ and 11 has a delay of 2 τ. Two taps P. and P ₂ form the beginning and the end of the delay element 11. The value θ is chosen so that the two taps

FR 973 002 S 0 9 8 2 Ö / 0 6 8 0

handles ρ _un d ρ are symmetrical in time to the main tap of the equalizer 8. The main tap of the equalizer 8 is its mid-taper tap with a time interval NT from the input point A. The value θ is chosen equal to NT equal to τ, so that the tap Ρ _χ lies at a time interval ΝΤ-τ from A and the tap P ₂ at a distance ΝΤ + τ. τ is chosen to be smaller than a value R, which will be explained later. (Let τ = T / M be given as an example.)

The samples x. are fed to a second delay chain, which consists of the delay elements 12 and 13. Their delays θ and 2 τ are equal to the delays of the elements IO and 11. The taps P and P ₄ are located at time intervals ΝΤ-τ and ΝΤ + τ from the input point B.

P is connected to the input of two multipliers 14 and 15, the other inputs of which the signals cos φ / ρ and sin φ / ρ are fed from the detector and decoder 6. P- is also with two multipliers 16 and 17 are connected, the other inputs of which are also supplied with the aforementioned signals from the detector and decoder 6 will.

The outputs of the multipliers 14 and 17 are connected to the two adding inputs of an adder 18, the output of which continues via an integrator 19 as a mean value generator to a squaring element 20. The output of the multiplier 15 is connected to the subtraction input and the output of the multiplier 16 is connected to the addition input of an adder 21. The output of this adder 21 leads via an integrator 22 to a squaring element 23. The output signals of the squaring elements 20 and 23 are added algebraically with the aid of an adder 24, the output signal of which _{emits the amplitude α χ of} a first point on the signal curve according to FIG.

In a similar way, the amplitude d _{2 of} a second point on this curve is obtained from the signals

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at the taps P ₂ and P ₄ . The intervening circuits are not shown in detail in order to keep FIG. 2 clear; However, similar circuits are provided for this purpose as for the tap signals at Ρ _χ and P ₃ .

The values d ₂ and α _χ are subtracted from one another in an adder 25 and the resulting difference is normalized in a calibrator 26. Its output signals are fed to a counter 27. This counter belongs to the clock generator 3 _f, which also has a high-frequency oscillator 28. The counter 27
serves as a frequency divider for the oscillator output pulses and emits clock pulses at times t.

The principle of operation of the circuits described above
will now be explained. For this purpose, a few mathematical considerations of a multilevel differential phase modulation signal are first given, as was taken as a basis for the description at the beginning. The incoming signal on the line can be specified as follows:

r (t) = I p _k [s (t-kT) cos <j> _k + S (t-kT) sin <f, _k ] (1)
In it are:

p (t) is a signal element that occurs when a carrier is modulated or through

S (t) = g (t) cos

gers or results from a baseband signal g (t); is there

S (t) is the quadrature signal for S (t); d. H. S (t) = g (t) sin ω t;

p _k , <j> _k discrete amplitude and phase values which contain the transmitted data at times kT in coded form; the values with the. are certain values from a large number
discrete values ρ. and φ., which are used in the transmission.

Equation (1) shows that the signal on the line results from the superposition of a large number of signal elements

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which are transmitted one after the other. The equation expresses a phenomenon that is usually referred to as an intersymbol overlay. The signal r (t), which is present at the center tap of the equalizers 8 and 9, not only contains information components of a single signal element, but also superimposed components of other signal elements that are earlier or later. In the equation (1) k varies from - ⁰⁰ to + oo, or at least from -n to fn when the viewing of the information elements 1 elements will be limited to 2 η +.

The phase shifter 4 generates two quadrature signals x (t) and x (t) from the signal r (t). To the description to make something clearer? shall be assumed that x (t) is identical to r (t) and that χ (t) is therefore the quadrature signal of r (t) is. The scanning operations carried out should also not be taken into account further, since the mathematical Theory is not influenced by this «,

So it can be written:

x (t) = £ p _k [S (t-kT) coscf> _k + S (t-kT) sin φ _{] ς} ) ^k

x (t) = Tp _k [ö (t-kT) cos (j> _k - S (t-kT) sin <f> _k 3

(2)

Based on Fig. 2 it can be seen that the arrangement, consisting performs the following operation from multipliers 14 and 17, adder 18 and integrator 19:

(PT) cos φ sin φ

x (t-T) _ + £ (t-r) ~ ö Ο)

^μ ο ο

This expression gives, over a given number ρ of periods T, the correlation result of the signals at P. and P. ,, namely tx (tT)] or. [x (tT)] ^ an. It should be pointed out at this point that when choosing the center taps of the equalizer as the reference point in time, the values Φ _ο and p _{Q are} variable depending on the pe-

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period T are.

When considering the aforementioned correlation & operation, it can be seen that in the sum of all elements that form the signal x (t) according to equation (2), the only element that is correlated with cos Φ _ο / ρ is that with k = O is. That is, the element that is assigned to the corresponding period T. All other elements with k values other than zero, ie the preceding and following interference signals, have no correlation with cos φ / ρ.

The same applies to the correlation between x (t) and sin Φ _ο / Ρ _ο The only element of the sum from which x (t) is formed and which is correlated with sin Φ _ο / Ρ _ο is the element with k = O. All other terms are irrelevant and are therefore irrelevant for the formation of the mean value according to expression (3).

The values given by expression (3) can be written using (1):

P _o [s (tT) cos Φ _ο + S * (tr) sin φΐ

(pT)

cos φ _ο ~ "pö

(pT)

p _n Γ S (t ~ r) cos φ _Λ - S (tT) sin φ 1 · ^sin Φο OL ^ o oj -p ^

These values are reduced to S (t-x). The correlation result is available at the output of the integrator 19. The same applies to the correlation arrangement that the multipliers 15 and 16, the Adder 21 and integrator 22 comprises. The following applies here:

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(ρΤ)

x (tx) ^COS Φο - x (tT) ^Sln »ο (4)

^Po 'Pp

This value is reduced to S (t-τ). The corresponding correlation result is available at the output of the integrator 22.

S (t-τ) and S (t-τ) are in the squarers 20 and 23 squared. The adder 24 then outputs:

d _x = £ S (t ~ r)] ² + [S (t-τ)] ² .

Usually the envelope of a transmitted signal element as defined by fplgt:

R (t) = ys ² (t) + S ² (t).

The output signal d. of the adder 24 stands for the amplitude at time -τ of the square of the envelope of the transmitted signal element. The amplitude of the envelope itself at time -τ could be determined by inserting a root-pulling term after the adder 24. For the purpose of application in the context of the present invention, however, it is irrelevant whether the envelope itself or its square is used. To simplify the further description, this signal, which represents the square of the envelope, is to be referred to as the "standard signal". The circuits following the taps P ₂ and P ₄ work in the same way and produce the signal value

d ₂ = [S (tK)] ² + [S (t + T)} ² This is the amplitude of the standard signal at time + τ.

3 shows the dependence of the standard signal amplitude on the time in the vicinity of the equalizer center taps selected as reference time 0. The values vpn ä _± and d ₂ correspond to

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at the amplitudes at the times -χ and + χ.

It was found by observation that at the optimum setting of the receiving clock, the center tap of the equalizer corresponds to the maximum amplitude of the pending envelope and thus also their square in the form of the standard signal. Each adjustment of the scan results in an offset of the envelope compared to the appropriation of funds after himself; either to the left, like shown in Fig. 3 if the scan is too early, or to the right if it is too late. The difference d_ - d is proportional to the distance At between the maximum of the standard signal and the main signal at the equalizer center tap.

This difference d ₂ - ä ^ is determined in the algebraic adder 25. After a suitable normalization in the calibrator 26, this difference is used to determine the position of the sampling pulses at the times t. to adjust. Such adjustment can be made in a number of conventional ways. According to FIG. 2, a high-frequency oscillator 26 with a downstream counter 27 serving as a frequency divider is used. The position of the outgoing sampling clock signals can take place by forced interventions in the counting operations of the counter 27. Here the intervention in the counting takes place with a value λ (d ₂ - α _χ ); χ is the selected normalization coefficient. The choice of λ is to be made in such a way that the entire system does not oscillate, λ must not be too large. On the other hand, λ must not be too small so that an adjustment can be made with sufficient speed.

With this method, the clock that defines the sampling times t ^ is continuously readjusted during the transmission the amplitude difference between two points of the standard signal that are symmetrical to the reference point (center tap), if possible to keep it small.

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The preceding description was based on an exemplary embodiment for phase modulation. It is easy to see that the application of this invention is not limited to phase modulation or the example described alone.

As a modification of the exemplary embodiment described, it would also be possible to determine the time slot of the standard signal with the aid of more than two points. Furthermore, the amplitude of the standard signal at the reference point can be taken into account by providing a tap in the middle of the two 2x delay elements and corresponding circuits as for the tap pairs P ₁ and P-. Further delay sections τ could additionally be added to either side of the reference point. In all cases in which more than two location points are defined for standard signals, the night position information for the clock generator corresponds to the distance of the temporal focus of the standard signal points from the reference point in time.

A readjustment could also only be possible with a single standard signal position point but the amplitude of the standard signal at the reference time O would have to be taken into account. For this purpose, this amplitude would have to be compared with a reference level.

According to the exemplary embodiment described, two points are used? this is a good compromise on accuracy and effort.

On the other hand, the choice of the equalizer center tap should be used as the equalizer main tap as in the example described, there should be no restriction. It is known in the art that some transmission lines as intersymbol overlays generate more lagging echoes than leading pulses. The main tap can therefore closer to or further away from the equalizer input; This affects the principles of the present invention but neither.

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It should also be pointed out that, contrary to the type of formation of the setting criterion described as difference d, - d 'also other ways for the clock setting would be possible. The type described is only one possibility. For example, a Execute a purely binary influencing of the clock generator, in which only the sign of the setting information would be taken into account. Included Either two oscillators or a common oscillator with two frequency dividers could be used. For reenactment The timing would always have to switch back and forth between the two generated frequencies.

As for the correlation operations, those are as described according to (3) and (4) the cheapest. However, the circuits used can be reduced while reducing the correlation speed simplify by saying that x (t - r) and x (t-x) only with

cos Φ _ο / ρ _ο or with sin φ _ο / p _{Q can be} correlated. Then one can write:

(PT)

^COS * o (3)

Po

(PT)

^{COS φ} ο

Po

The expression (3 ¹ ) then corresponds to a value 1/2 S (t ~ r) and (4 ') corresponds to a value 1/2 S (t - r). However, this factor 1/2 does not affect the basic principle of the correlation operations. It can also be used as described in the exemplary embodiment.

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Another, more simplified option would be pure correlation of x (t) with

cos Φ _ο / ρ _ο and sin φ _ο / ρ _ο
x (t) is not used to set the clock.

It should also be pointed out that the principle described can be used if no equalizer is used at all. The data sampling point is then selected as the reference point in time.

Another simplified solution, instead of providing for the delay elements 10, 11, 12 and 13, would be to tap the ones to be correlated Signals directly at taps on the equalizer delay line (s).

When the principle of the invention is applied to amplitude modulation, the data information ε _o recovered in a given modulation period is correlated with the signals r (t ~ r) and r (t + x) after they have been converted into the baseband by modulation. In this case, the standard signal used is no longer the envelope of the transmitted signal elements or the square of this envelope, but the baseband signal itself.

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Claims (5)

- 15 PATENT CLAIMS 1. A method for setting a receive clock for systems for data transmission with phase modulation, in which data signals are transmitted via transmission media of limited bandwidth that contribute to distortion and receive clocks are provided on the receiving side to define sampling times for the recovery of the transmitted data,
characterized by the following process steps: a) Deriving a signal (r (t)) from the received signal (r (t)) ,. which is phase orthogonal to this received signal is. b) Sampling of the received signal (r (t)) and the orthogonal signal (r (t)) with M times the transmission frequency (I / T), where M samples are obtained per modulation period (T). c) Correlation (multiplication) of the sampled values obtained in this way with signals (cos φ / ρ, sin φ / ρ), the amplitude and phase information of the recovered data signals, where M samples of one such designated standard signal can be obtained that the Envelope corresponds to the transmitted signal elements. d) Comparison of the timing of this standard signal to a reference time given by the sampling times (O), a clock error signal (CS) defining the timing error of the sampling times being obtained will. e) Regulation of the intended clock generator (3) by means of acceleration or delaying the output sampling clock pulses with the aid of the clock error signal obtained (CS). fr 973 002 509820/0680 2. Method for setting a receive clock for systems for data transmission with amplitude modulation, in which data signals are transmitted via transmission media of limited bandwidth that contribute to distortion and receive clocks are provided on the receiving side to define sampling times when recovering the transmitted data,
characterized by the following process steps: a) Demodulating the received signal (r (t)) and generating a demodulated signal in the data baseband. b) Sampling of the demodulated signal with a repetition frequency, which is M times the transmission rate (I / T), where M samples per Modulation period (T) can be obtained. c) Correlation (multiplication) of the sampled values of the demodulated signal obtained in this way with amplitude information from the associated modulation periods (T), where M samples of a so-called standard signal, corresponding to the data baseband signal can be obtained. d) Compare the timing of this standard signal to one reference time given by the sampling times (O), where a is the timing error of the sampling times defining clock error signal (CS) is obtained. e) Regulation of the intended clock generator (3) by means of acceleration or delaying the output sampling clock pulses with the aid of the clock error signal obtained (CS). fr 973 002 609820/0680 3. The method according to any one of claims 1 or 2, characterized in that that M = I that the sampling of the received signal (r, (t)) to by means of the provided clock (3) defined sampling times (t.) Takes place and that the clock error signal (CS) is the difference between the amplitude of the respective standard signal sample and a predetermined reference level is used. 4. The method according to any one of claims 1 or 2, characterized in that M = 2, that the two values sampled by the received signal (r (t)) are symmetrical in time to the associated sampling time (t.) Defined by the clock generator (3). and lead or follow this sampling time (t,) by a time τ, where τ is significantly smaller than a modulation period (T) and that the clock error signal (CS) is the difference (d ₂ - d _± ) between the amplitudes ( d., d ₂ ) two associated samples of the standard signal is used. 5. The method according to any one of claims 1 or 2, characterized in that that M is any integer greater than 1, that the M are sampled from the received signal (r (t)) Values symmetrical in time to the associated, by the clock (.3) are defined sampling time (t.) And lead or lag this sampling time (t.) By η τ, where η is an integer and M · χ is maximal equal to twice the value of a modulation period (2T) with an even M, but (M-I) τ a maximum of twice that Value of two modulation periods (2T) for odd ones M is, and that the amplitude difference as the clock error signal (CS) between the sample values of the standard signal located in the center of frequency and a predetermined one Reference level is used. FR 973 002 B09820 / 0680