DE2433658A1 - DIODE MATRIX - Google Patents

DIODE MATRIX

Info

Publication number
DE2433658A1
DE2433658A1 DE19742433658 DE2433658A DE2433658A1 DE 2433658 A1 DE2433658 A1 DE 2433658A1 DE 19742433658 DE19742433658 DE 19742433658 DE 2433658 A DE2433658 A DE 2433658A DE 2433658 A1 DE2433658 A1 DE 2433658A1
Authority
DE
Germany
Prior art keywords
conductor
diode matrix
conductor track
track arrangements
selenium elements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19742433658
Other languages
German (de)
Inventor
Gerhard-Guenter Gassmann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel Lucent Deutschland AG
Original Assignee
Standard Elektrik Lorenz AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Standard Elektrik Lorenz AG filed Critical Standard Elektrik Lorenz AG
Priority to DE19742433658 priority Critical patent/DE2433658A1/en
Priority to GB2867275A priority patent/GB1471122A/en
Priority to FR7521542A priority patent/FR2331862A1/en
Priority to IT2528775A priority patent/IT1039786B/en
Publication of DE2433658A1 publication Critical patent/DE2433658A1/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/102—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
    • H01L27/1021—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components including diodes only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/06—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using diode elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0286—Programmable, customizable or modifiable circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Electronic Switches (AREA)

Description

STANDARD ELEKTRIK LORENZ
AKTIENGESELLSCHAFTSTANDARD ELECTRICS LORENZ
SHARED COMPANY

StuttgartStuttgart

G.G.Gaßmann - lolG.G.Gaßmann - lol

DiodenmatrixDiode matrix

Die Erfindung betrifft eine Diodenmatrix, die aus zwei jeweils, in einer Ebene liegenden parallelen Leiterbahnanordnungen besteht und einzelne Leiterbahnen der beiden Leiterbahnanordnungen durch Dioden in einem vorgegebenen Code miteinander verbunden sind.The invention relates to a diode matrix which consists of two parallel conductor track arrangements, each lying in one plane consists and individual conductor tracks of the two conductor track arrangements by means of diodes in a predetermined code are connected to each other.

Allgemein sind zwei unterschiedliche Techniken zum Aufbau einer Diodenmatrix bekannt. Bei der ersten Art sind zwei räumlich getrennte und elektrisch gegeneinander isolierte Leiterbahnanordnungen vorgeschlagen, zwischen denen an bestimmten Kreuzungspunkten diskrete Dioden eingelötet sind. Die zweite, allgemein bekannte Art ist der Aufbau in integrierter Technik, bei der als Dioden arbeitende Transistoren in einem Diffusionsprozeß aufgebracht werden.Generally there are two different techniques to build a diode matrix known. In the first type, two are spatially separated and electrically isolated from one another Proposed conductor track arrangements, between which discrete diodes are soldered at certain crossing points. The second, well-known type, is an integrated technology structure in which transistors operate as diodes be applied in a diffusion process.

Solche Diodenmatrizen können beispielsweise als festverdrahtete Speicher, auch Read Only Memory (ROM) genannt, verwendet werden.Such diode matrices can, for example, be hardwired Memory, also called Read Only Memory (ROM), can be used.

Beide Arten des Aufbaus haben Vor- und Nachteile. So können bei einer Diodenmatrix mit diskreten Bauelementen beliebig viele Anschlüsse durch einfaches Herausführen jeder der Leiterbahnen vorgesehen werden. Nachteilig bei diesen Anordnungen ist der fertigungstechnisch hohe Aufwand für das Einlöten der einzelnen Dioden.Both types of construction have advantages and disadvantages. So can in the case of a diode matrix with discrete components, any number of connections by simply leading out each one the conductor tracks are provided. The disadvantage of these arrangements is the high level of manufacturing effort soldering in the individual diodes.

9.7.1974, Pl/K -/-July 9, 1974, Pl / K - / -

509885/1065509885/1065

G.G.Gaßmann - ΙοίG.G.Gaßmann - Ιοί

In integrierter Technik können auch sonst fertigungstechnisch aufwendige Strukturen verwirklicht und auf engstem Raum untergebracht werden.In integrated technology, structures that are otherwise complex in terms of production technology can also be implemented and in the smallest of spaces Space.

Nachteilig ist hier jedoch, daß die Zahl der nach außen führenden Anschlüsse sehr beschränkt ist und demzufolge die Anwendbarkeit auf vielen Gebieten erschwert wird. Unter Umständen sind dann externe Köder und interne Dekoder notwendig, um mit den wenigen Anschlüssen auskommen zu können.The disadvantage here, however, is that the number of outward leading connections is very limited and thus the applicability in many areas is difficult. Under The circumstances are then external baits and internal decoders necessary to be able to get by with the few connections.

Ziel der Erfindung ist es, eine Diodenmatrix anzugeben, die sowohl fertigungstechnisch als auch in der Anwendung im Rahmen einer Schaltungsanordnung leicht zu handhaben ist,The aim of the invention is to specify a diode matrix that is useful both in terms of production technology and in use is easy to handle in the context of a circuit arrangement,

Die Aufgabe wird dadurch gelöst, daß an durch den Code vorbestimmten Kreuzungspunkben der beiden Leiterbahnanordnungen Selenelemente durch eine Lochmaske auf die Leiterbahnen aufgedampft sind und die Selenelemente eine räumliche Trennung der beiden Leiterbahnanordnungen bewirken.The object is achieved in that at predetermined by the code Crossing points of the two conductor track arrangements Selenium elements through a perforated mask on the conductor tracks are vapor-deposited and the selenium elements cause a spatial separation of the two conductor track arrangements.

Die Vorteile sind darin zu sehen, daß seitens des Herstellers eine Codeänderung durch einfache Änderung des Lochmaskenmusters möglich ist. Der Anwender kann je nach Einsatzgebiet alle geeigneten Anschlußtechniken benutzen, wie Steckverbinder, Löten oder Wire-Wrap. Im Gegensatz zu der integrierten Technik braucht bei dieser Diodenmatrix keine separate Stromversorgung vorgesehen zu werden. Verwendet man diese Diodenmatrix als ROM, so können zusätzliche Köder und Dekoder In gleicher Form aufgebaut werden.The advantages are to be seen in the fact that the manufacturer can change the code by simply changing the shadow mask pattern is possible. Depending on the area of application, the user can use all suitable connection techniques, such as Connector, soldering or wire wrap. In contrast to the integrated technology, this diode matrix does not need any separate power supply to be provided. If this diode matrix is used as a ROM, additional baits can be used and decoders are constructed in the same way.

509885/1065509885/1065

G.G.Gaßmann - ΙοίG.G.Gaßmann - Ιοί

Pig. 1 zeigt ein Ausführungsbeispiel einer Diodenmatrix gemäß vorliegender Erfindung. Die Diodenmatrix besteht aus zwei Leiterbahnanordnungen 11 und 12. Auf einer isolierenden Trägerplatte sind jeweils die Leiterbahnen 13 bzw. 14 aufgebracht. Die parallelen Leiterbahnen 13 und 14 jeder der Leiterbahnanordnungen 11 und 12 sind hier als Geraden ausgeführt und sind so zueinander gelegt, daß die Leiterbahnen 13 und l4 rechtwinklig zueinander verlaufen. Es sind aber auch andere Konfigurationen möglich. Wie in dem Beispiel gezeigt, ist die Leiterbahnanordnung 12 teilweise geschnitten und man sieht, daß sich auf den Leiterbahnen 13 der Leiterbahnanordnung 11 in einem bestimmten Muster mit Selen bedeckze Stellen 15 befinden. Diese Selenelemente 15 sind erhaben ausgeführt, also werden beim Aufeinanderlegen der beiden Leiterbahnanordnungen 11 und 12 nur die Selenelemente 15 Berührungs- und Kontaktstellen sein. Falls erforderlich, sind zwischen den Leiterbahnen an den Kreuzungsstellen ohne Selenelemente (15) Isolierungen vorgesehen.Pig. 1 shows an embodiment of a diode matrix according to the present invention. The diode matrix consists of two conductor track arrangements 11 and 12. The conductor tracks 13 and 14, respectively, are on an insulating carrier plate upset. The parallel conductor tracks 13 and 14 of each of the Conductor track arrangements 11 and 12 are designed here as straight lines and are placed in relation to one another in such a way that the conductor tracks 13 and l4 run at right angles to each other. However, other configurations are also possible. As shown in the example the conductor track arrangement 12 is partially cut and it can be seen that on the conductor tracks 13 of the conductor track arrangement 11 are areas 15 covered with selenium in a certain pattern. These selenium elements 15 are raised, so when the two conductor track arrangements 11 and 12 are placed on top of one another, only the selenium elements 15 become contact points be. If necessary, between the conductor tracks at the crossing points without selenium elements (15) Insulations provided.

Fertigungstechnisch am einfachsten und vorteilhaftesten lassen sich die Selenelemente durch ein dem vorgegebenen Code entsprechendes Lochmuster einer Lochmaske auf die Leiterbahnen 13 oder l4 aufdampfen. Prinzipiell ist es aber auch möglich, Selen als diskrete Scheibchen aufzubringen.The simplest and most advantageous manufacturing technology for the selenium elements is by means of a code that corresponds to the given code Vaporize the hole pattern of a shadow mask onto the conductor tracks 13 or 14. In principle, however, it is also possible Apply selenium as discrete slices.

Wie aus Fig. 1 leicht erkennbar ist, können die Anschlüsse ΐβ leicht an den Enden der Leiterbahnen vorgesehen sein..As can be easily seen from FIG. 1, the connections ΐβ easily provided at the ends of the conductor tracks ..

Wird die zweite Leiterbahnanordnung (12) so mit der ersten (11) zusammengebracht, daß die Leiterbahnen (14) nach dem Aufbringen der Selenelemente (15) auf die erste Leiterbahnanordnung (11) in einem weiteren Aufdampfprozeß aufgebracht ist, dannIf the second conductor track arrangement (12) is brought together with the first (11) in such a way that the conductor tracks (14) after application the selenium elements (15) is applied to the first conductor track arrangement (11) in a further vapor deposition process, then

509885/1065509885/1065

G.G-.Gaßmann - ΙοίG.G-.Gaßmann - Ιοί

ist in einfacher Weise sichergestellt, daß die sichere Kontaktierung zwischen den Leiterbahnen und den Seleneleraenten vorhanden ist und nicht erst durch mechanischen Druck erzeugt werden muß« ·is ensured in a simple manner that the safe contact is present between the conductor tracks and the selenium elements and is not generated by mechanical pressure must become" ·

2 Patentansprüche 1 Bl. Zeichnungen, 1 Fig.2 claims 1 sheet drawings, 1 Fig.

509885/1065509885/1065

Claims (2)

G.G.Gaßmann'- Ιοί 'G.G.Gaßmann'- Ιοί ' Patentansprüche:Patent claims: 1J Diodenmatrix, die.aus zwei jeweils in einer Ebene liegenden parallelen Leiterbahnanordnungen besteht und einzelne Leiterbahnen der beiden Leiterbahnanordnungen durch Dioden in einem vorgegebenen Code miteinander verbunden sind,1J Diode matrix, which consists of two parallel conductor track arrangements, each lying in one plane, and individual ones The conductor tracks of the two conductor track arrangements are connected to one another by means of diodes in a predetermined code, dadurch gekennzeichnet, daß an durch den Code vorbestimmten Kreuzungspunkten der beiden Leiterbahnanordnungen (11, 12) Selenelemente (15) durch eine Lochmaske auf die Leiterbahnen (IJ, 14) aufgedampft sind und die Selenelemente eine räumliche Trennung der beiden Leiterbahnanordnungen bewirken. characterized in that selenium elements (15) are vapor-deposited through a perforated mask onto the conductor paths (IJ, 14) at the intersection points of the two conductor track arrangements (11, 12) predetermined by the code and the selenium elements cause a spatial separation of the two conductor track arrangements. 2. Diodenmatrix nach Anspruch 1, dadurch gekennzeichnet, daß die zweite Leiterbahiianordnung (12) nach dem Aufdampfen der Selenelemente (15) auf die erste Leiterbahnanordnung (11) in einem zweiten Aufdampfprozeß aufgebracht ist.2. Diode matrix according to claim 1, characterized in that the second conductor path arrangement (12) is applied to the first conductor path arrangement (11) in a second vapor deposition process after the evaporation of the selenium elements (15). 509885/ 1065509885/1065 LeerseiteBlank page
DE19742433658 1942-07-12 1974-07-12 DIODE MATRIX Pending DE2433658A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
DE19742433658 DE2433658A1 (en) 1974-07-12 1974-07-12 DIODE MATRIX
GB2867275A GB1471122A (en) 1974-07-12 1975-07-08 Diode matrix
FR7521542A FR2331862A1 (en) 1942-07-12 1975-07-09 Diode matrix with two systems of parallel paths - systems lie in plane and individual paths connected by diodes
IT2528775A IT1039786B (en) 1974-07-12 1975-07-11 DIODE MATRIX

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19742433658 DE2433658A1 (en) 1974-07-12 1974-07-12 DIODE MATRIX

Publications (1)

Publication Number Publication Date
DE2433658A1 true DE2433658A1 (en) 1976-01-29

Family

ID=5920438

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19742433658 Pending DE2433658A1 (en) 1942-07-12 1974-07-12 DIODE MATRIX

Country Status (3)

Country Link
DE (1) DE2433658A1 (en)
GB (1) GB1471122A (en)
IT (1) IT1039786B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6887792B2 (en) 2002-09-17 2005-05-03 Hewlett-Packard Development Company, L.P. Embossed mask lithography

Also Published As

Publication number Publication date
GB1471122A (en) 1977-04-21
IT1039786B (en) 1979-12-10

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