DE2423817A1 - METHOD AND CIRCUIT ARRANGEMENTS FOR CODING TWO-DIMENSIONAL PICTURE INFORMATION - Google Patents

Description

Boeblingen, May 7th 1974 ker / se

Applicant: International Business Machines

Corporation, Araionk, N.Y. 10504

Official file number: New registration File number of the applicant: WA 972 008

Methods and circuit arrangements for coding two-dimensional 'image information

The invention relates to a method for coding two-dimensional Image information according to claim 1 and circuit arrangements for performing this method.

The coding method involved is for the transmission of image data Can be used when transmitting still images. The invention enables two modes of operation for coding successive ones Blocks, which consist of matrices of picture elements. For processing blocks of data containing black elements a series of comparisons is made in succession against a given set of simple geometric patterns. The comparison takes place in a sequence with decreasing black content. A bit comparator according to the present invention is shown in FIG as soon as all elements of a pattern recognized first match the picture elements present in a data block. Of the The bit comparator then notes in each case whether any bit positions in the data block are not yet in the comparison with the first pattern are recorded. Remaining elements are compared with a further pattern which is coded on it and via the output line is transmitted. The comparison procedure is continued until each individual data block is complete as a result of comparison patterns is coded. All consistently ascertained

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Uniform patterns are coded and one after the other over the output line transmitted for transmission, storage or playback. A second mode of operation possible with the present invention is the run length coding of connected white areas.

The method under consideration thus affects the digital representation of two-dimensional images and, in particular, a data packing method and corresponding device for encoding and decoding such images.

The transmission of two-dimensional images via transmission media requires the translation of the image content into a signal format, which can be sufficiently transformed back into the original two-dimensional form in the receiver. The two-dimensional Images are scanned in the usual way and converted point by point from an analogue reproduction to a digital reproduction. The elements of such a digital signal obtained stand for the individual elementary points of the image, usually using a black & white level. Such digital Representations contain a great deal of redundant information. A typical image may take a few 500,000 or more pixels to achieve an acceptable image resolution.

A possibility for reduction given according to the state of the art The redundancy of a punctiform image reproduction uses the scanning of the image in contiguous small areas successive blocks of picture elements and the coding of these blocks, which are all a geometric pattern from a correspond to the given sample stock. An existing problem for the detection of all possible geometric patterns that can appear in an image can be seen in the fact that an immensely large stock of samples must be kept ready. See US-PS 3,215,773.

The object of the present invention is to provide a comparatively improved picture coding method in which the

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The total number of geometric reference patterns to be kept available is reduced; the product of time and bandwidth for playback images with high resolution should be kept small; the image data should be packed as tightly as possible.

The solution to this problem is characterized in claim 1. Circuit arrangements for implementation are in the subclaims described.

The solution to the problem is based on the coding of the individual data blocks of the image as compilations of simple geometric ones Block pattern. An n «m element data block to be encoded is loaded into a data block register connected to an n «m bit comparator. A reference pattern store that contains a plurality of simple geometric block patterns is connected to a reference pattern register, which in turn is connected to the bit comparator. The reference patterns are sequentially transferred from the reference pattern memory to the reference pattern register transferred with decreasing black content of the individual elements. The bit comparator checks each reference pattern for determination the correspondence with the occupied elements in the image data block. As soon as the first match with a reference pattern is detected, its code number is coded and made available for transmission via an output line. If there are no more elements in the data block that have not been recorded in terms of code, an indication is given that the data present - block has been completely coded and output and that the next data block can be loaded into the data block register.

If, on the other hand, there are not yet captured elements in the data block that have not yet been captured with the found reference pattern are, the code information of the first comparatively detected pattern is kept ready in the bit comparator and an identifier for this encoded, which indicates that the next encoded reference pattern should be reproduced together with the previous one during decoding is.

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The successive loading of the reference patterns used from the reference pattern memory into the reference pattern register takes place in a sequence with decreasing black content. The bit comparator checks whether the individual reference patterns match the occupied ones Elements of the individual image data blocks. If, as already indicated, a second comparison should be carried out in exceptional cases is, its code number is also coded and transmitted. If none are occupied, for the first and, if applicable, the second comparison detected elements are more present, an identifier is given with the coded output signals that the current The data block is completely encoded and the next data block can be loaded into the data block register.

If elements of the data block that are still occupied are not recorded after the first and second comparison, the positions of the are already encoded elements of the first and second comparison pattern stored in the bit comparator and the second pattern with a Identifier coded that a further code specification follows, which is combined with the first and second code pattern during decoding is to be processed. The process of searching for the components of a composite geometric figure lasts so long until there are no more unrecognized black elements of the data block after the individual comparisons. A complex part of the picture is represented in this way as a composite of several individual patterns.

If successive data blocks with only white elements are detected, an output word is output in coded form, the indicates the number of all data blocks containing only white elements according to the type of run-length coding.

Thus, there is a significant limitation with the present invention of the simple geometric patterns to be kept available and thereby a reduction in the product of time and bandwidth possible. A very economical image data transmission can be carried out with the packaging technology described.

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An embodiment of the invention is shown in the drawings and is described in more detail below.

Show it:

Fig. 1 is a block diagram of the image data transmission system described ,

Fig. 2 shows the subdivision of the digitally transmitted

Image in data blocks,

3 shows the stock of simple geometric reference patterns,

4 shows the format of the coded information,

FIG. 5 is a block diagram of the data compressor 6 according to FIG. 1,

6a shows the circuit diagram of the comparator logic for one

of 16 data elements within the bit comparator 28 in FIG. 5,

FIG. 6b shows a time diagram for the logic according to FIG. 6a,

7 shows the block diagram of the data decompressor 12

according to Fig. 1,

Fig. 8a the status of the logical variables D _n , A .., D ₇ ,,. ,,

K JM Jddi

C, N, A _{n + 1} and D _{T} TsTi1} for the individual 16 data

elements in the bit comparator 28 after comparing the reference pattern no. 0 with the complex geometric pattern of a data block according to FIG. 8e,

8b shows the status of the same variable when compared of the reference pattern No. 14 with the data block according to FIG. 8e,

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8c shows the variable status when comparing the

Reference pattern No. 23 with the data block according to FIG. 8e,

8d shows the variable status when comparing the

Reference pattern no. 39 with the data block according to FIGS. 8e and

Fig. 8e the complex geometric chosen as an example

Pattern which is in the data block register 26 in each case.

Overall structure

An image data transmission system constructed according to FIG. 1 can be e.g. for a facsimile transmission or for the storage of image data. A document with legible characters 1 is scanned with the aid of a television camera 2 which emits a conventional gray level signal via a line 3. A Threshold value detector 4 converts this gray level signal on the line 3 into a binary image signal via a line 5, the leads to a data compressor 6. This data compressor, in turn, divides the 1,024 x 1,024 picture element into 216 x 216 Data blocks, each of which has 16 data elements, as shown in FIG. contains. The data compressor, the details of which are shown in FIG. 5, successively compares the ones shown in FIG. given stock of simple geometric patterns with the black elements in the data block. The reference sample stock is in accordance with 3 compared in the order of decreasing black level. The bit comparator logic of the bit comparator shown in FIG. 6a 28 according to FIG. 5 within the data compressor 6 determines when for the first time one of the reference patterns compared with those in the data block register 26 stored black elements matches. This reference pattern recognized first is coded with information its reference pattern number is output with the aid of a pattern counter 40 via an AND gate 42 and an output register 46.

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The output register 46 is divided according to FIG. Positions 1 to 7 of the output register 46 take the pattern number codes and the positions 8 and 9 a jump code which is generated by a jump logic 32 according to FIG. The bit comparator logic of the bit comparator 28 indicates if any bit positions of the data block when compared with the first recognized Patterns have not been recorded. If there are any elements left, this is indicated by the lack of a signal on line 50 to the control circuit 34 is recognized, the jump logic 32 loads a 0 in the 8th position and a 0 in the 9th position of the output register 46. This indicates that the currently coded pattern is only part of several to be overlaid. The decoder in the receiver will then not advance to the next data block but to the current data block remain to the next geometric pattern, which is output as a signal from the data compressor, to the current pattern to add.

Each reference pattern recognized first is sent via an output line 7 transferred to an image buffer 8. The remaining picture elements are associated with a second reference pattern brought, which is also transmitted via the output line 7 as a code number. The comparison procedure takes time until all of the picture elements contained in the data block register 26 are complete as individual geometric elements that belong together Reference patterns according to the stock of Fig. 3 are coded. All matching reference patterns found are coded and one after the other via the output line 7 and further via a transmission line 9 to a frame repetition memory 10 transfer. This image repetition memory can either be a core memory or a monolithic memory which processes input and output signals that do not occur periodically can.

The data compressor according to FIG. 5 operates in a second operating mode, when successively data blocks containing only white elements are recognized. A single starting point is

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word that identifies the number of consecutive blocks without black elements. In this operating mode, White length counter 30 of the data compressor according to FIG. 5 determines how often no black elements occur in the data block register 26, and accordingly lets its counter switch one step forward. This enumeration of the counter takes so long how successive blocks of data without black elements are recognized. The maximum capacity of the output data register 46 is 128. If the first no longer completely white block after a number Δ of consecutive white blocks or else 128 consecutive white blocks have been determined, the white length counter enters its content as the value Δ via OR gate 44 to output data register 46 in its positions 1 to 7. Jump logic 32 then loads a 1 into position 8 and a 1 in position 9, which indicates that the coded word is to inform the decoder, Δ white blocks, as in FIG Fig. 4 shown to proceed. The coded word will also transmitted via line 7 to image buffer 8. This twofold operating mode of displaying image details in form of 4'4 data blocks or with run length coding a substantial reduction in the total number of simple geometric reference patterns to be kept available that are stored in the reference pattern memory are to be kept ready. In this way, the reduction of the product time times bandwidth on the transmission line 9 is advantageous feasible.

The image repetition memory 10 forwards compressed image data via a line 11 to the data decompressor 12, whose Details are shown in FIG. In this decompressor, the encoded reference patterns and those in the form of run lengths encoded white blocks with the associated jump codes recognized. The incoming data via line 11 are transmitted by means of a Operating mode detector 202 monitors, which in turn indicates whether the receiving-side reference pattern memory 204 the encoded geometric reference pattern into a rendering data block register

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210 or whether a white length indicator 206 of the control circuit 208 is intended to indicate that Δ successive white blocks are to be skipped.

If the data word according to FIG. 4 contains zeros in positions 8 and, which indicate that reference patterns to be assembled are present, the mode detector 202 of the control circuit 208 indicates that the reference pattern just recorded is in the data block register 210 is to be recorded. The next encoded reference pattern that is retrieved from the reference pattern memory 204 from the supply corresponds to the next data word received via line 11. The pattern belonging to it now becomes the previous one, the pattern still in register 210 is superimposed. The two superimposed patterns then form the composite image block. This reassembled block is transmitted over a line 235 via one of two registers 212/214, which then the binary image output signal via a line 13 a TV monitor 14 transmitted for playback.

Bit comparator details

The bit comparator 28 of Figure 5 is a 4x4 picture data element comparator. However, its size is not necessarily limited to 4 * 4; it can generally be built up in size n * m. The comparator 28 compares complex arrangements of black elements in a 4x4 image data block register with simple ones Arrangements of black elements also in 4 «4 blocks. For this purpose, simple reference patterns are selected one after the other the reference pattern memory 38 is loaded into the reference pattern register 36. The code number α of the individual loaded reference samples is available each in a sample counter 40 ready. When the bit comparator 28 determines that the pattern just loaded into the reference pattern register 36 does not contain any Schwärζelements that do not match the Black elements in the data block register 26 match, and if at least one black element of the simple reference pattern is found that matches a black element in the data block register 26 that has not yet been used in a preceding WA 972 008

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Previous comparison has been detected, then there is a component of a pictorial representation to be composed. The bit comparator 28 then transmits the match indicating output signal via the line 48 to the AND gate 42, the in turn, the code value corresponding to the pattern number α of the pattern currently in the pattern register to the output register 46 passes on.

The bit comparator 28 contains a 4 * 4 arrangement of data comparison positions, which contain logical blocks according to FIG. 6a. Each of these logical blocks has a data input in the form one of the 4 x 4 data element input lines 27 for reception of data elements which in their entirety form the block to be processed. Each of these logical blocks has furthermore a reference pattern input for receiving reference pattern elements via an input line 54, via which in each case a reference pattern element is entered, which in their entirety form the current reference pattern.

The bit comparator 28 includes a bit comparison OR gate 180 with 4 * 4 input lines 103, each of which is connected to one of the total provided logical blocks as shown in Fig. 6a is. The OR gate 180 leads each occurring bit comparison signal N further via a line 119, if such a bit comparison signal N is supplied via one of the input lines 103. This means that a Schwärζelement one of the in the reference pattern register 36 stored reference pattern is found matching a black element in the image data block register 26, which has not yet been recorded by a previous comparison.

The bit comparator 28 also contains an overall comparison • AND element 190 which, as shown in Figure 6a, has (4x4) +1 input lines. One of these input lines is the line 119 from the output of the bit compare OR gate 180. The others 16 lines 117 are each with an output of the individual logical

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Blocks connected according to Fig. 6a. The overall comparison AND element 190 gives an overall comparison signal via a line 48 to the aforementioned AND element 42 (FIG. 5). This always happens when it is determined that a reference pattern loaded into the reference pattern register 36 does not contain any black elements, which do not match the black elements in the image data block register 26. The overall comparison signal on line 48 lets through the AND gate 42 the code number α of the reference pattern currently stored in the reference pattern register 36 to the output register 46 arrive. Information that a matching reference pattern has been found is from the AND gate 42 via a Line 201 passed on to control circuit 34. This information is provided in the absence of an output signal on the line 50 logically combined by the bit comparator 28 and indicates that an image block partial analysis has ended. The control circuit informs in turn, the jump logic 32 according to FIG begins. As shown in FIG. 4, zeros in positions 8 and 9 mean that that contained in positions 1 to 7 α code and the pattern corresponding to it are only part of a representation to be composed and that at least another related reference sample will follow.

Output line 48 from overall compare AND gate 190 is across a line 107 in turn with the input of all 4 * 4 comparator blocks connected according to Fig. 6a and causes the storage of an identifier in the A flip-flop 130 of all of the logical blocks, which are given a comparison signal N via their associated line 103 to have. If the associated data element is a black element, the D -flip-flop 140 is also activated via the input line 27 switched on. If the first reference pattern that meets the data item under consideration is encoded, then the overall comparison signal goes via lines 48 and 107 on. The bit comparison signal N via line 103 is also on. Thus becomes the AND gate 110 and also the AND gate 120 switched on. That The DG flip-flop is switched off and the A flip-flop 130 is switched on

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switched. This is the indicator that the associated data element is coded. The data element is a black element and belongs to a reference pattern which belongs to a related The reference pattern group that contains the image data in the image data block register 26 reproduces.

The A flip-flop 130 and the D flip-flop 140 become both triggered by the trailing edge of a clock pulse on line 52. Fig. 6b explains the timing of the switching operations Flip flops.

A compilation AND element 170 is provided in the bit comparator 28. It has 4 x 4 input lines, which are individually connected to a complete output 121 of all of the comparator blocks according to FIG 6a are connected. This assembly AND gate 170 sends a "assembly completed" signal over the output line 50 to control circuit 34. If none have not yet been detected If there are more black elements in the Bxlddatenblockregxster 26, this signal "Compilation finished" is given.

Each logical comparator block according to FIG. 6a thus contains a D flip-flop 140, a reset UN]
AND gate 110 and an A flip-flop 130.

a D flip-flop 140, a reset AND gate 120, a switch-on

The enable input of the D flip-flops _R 140 is connected to the associated data element input line 27th The D flip-flop stores an indicator that the data item being analyzed is a black item. The out-side output of the D flip-flop leads to one of the 16 inputs of the compilation AND element 170.

Each comparator block according to FIG. 6 has a bit comparison AND gate 100, whose first input is the sample input line 54 is connected and its second input is connected via a line 101 to the one-sided output of the D flip-flop

JD

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is. The output of the bit comparison AND element 100 is connected to the line 103, which is connected to the already mentioned bit comparison OR element 180 leads. If a considered data element is a Schwärζelement, an on-signal is via the input line 27 added. If the supplied reference pattern has a black element in the position under consideration, then likewise an on-signal is supplied via line 54. Then, when both lines 27 and 54 are on, the D_ flip-flop becomes 140

JB

switched on. The signal from its unidirectional output is output on line 101 and combined with the on condition of reference pattern input line 54. The bit comparison AND element 100 thus also goes into the on state. A signal N now reaches the bit comparison OR gate 180 via the line 103. This signal also goes via the line 119 to the overall comparison UL gate 190. This process takes place every time a blackening element is in related positions in the data block register 26 and is present in the reference pattern register 36 until the first successful overall comparison occurs. Then the D flip-flop 140 is cleared and the A flip-flop 130 is switched on, the bit comparison AND element 100 with D _n

is turned off.

Each data element comparator block according to FIG. 6a contains a mismatch AND element 160 with a downstream one Inverter 115. The first input line 109 of the AND gate 160 is connected to the reference pattern output line 54. The second Input line 111 of AND gate 160 is with the out-side The output of the D flip-flop 140 is connected and a third input line 123 is connected to the out-side output of the A flip-flop 130 tied together. The output of the downstream inverter 115 leads via line 117 to one of the inputs of the overall comparison AND element 190.

Each data element comparator block according to FIG. 6a has the aforesaid Reset AND gate 120, its first input line 103 comes from the output of the bit comparison AND gate 100 and its

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second input line 107 from the output of the overall comparison AND gate 190 is coming.

Furthermore, each data element comparator block has the switch-on AND element 110, the first input of which is connected to the output of the bit comparison UND element 100 via the line 103 and its second input to line 107, from the overall comparison AND gate 190 comes, is connected.

Each data element comparator block according to FIG. 6a contains the A flip-flop 130, whose switch-on input is connected to the output of the switch-on AND element 110 is connected and its out-side output via line 123 to the third input of the mismatch AND gate 160 leads. The A flip-flop stores an indicator that the data element is black and with a corresponding Schwärζelement corresponds in a found reference pattern which has no black element which not with the black elements of the image data in the data block register

26 matches.

The functions of these data element comparator blocks according to FIG. 6a can be summarized in a table. D_ represents the binary value for a black element in the reference pattern via the input line 54. The binary variable A ^ represents the on state of the A flip-flop 130 and the binary variable D _n ^ das

U.N.

Presence of a black element in the data block over the line

27 and further the on-state of the D flip-flop 140. The binary variable C ₀ reproduces the auxiliary output signal via the line 117, the variable N finally a bit comparison signal via the line 103. The identification of the binary variables A and D_, with an N. means the state of the A flip-flop or the D_ flip-flop before the arrival of a trigger pulse via the line 52. The identification of the variable A or D with an N + 1 means the state of the two flip-flops after the triggering via the line 52. Below is the logical summary table:

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D.

D.

BN + 1

O O O 1 0 I do 0 0 Z T 1 O O O 0 Tabel 0 0 , is O O 1 1 0 0 1 1 ' O 1 1 1 1 0 O 1 O 1 0 1 0 1 1 O 1 0 1 0 1 1 N USER One Equation, the this logical reproduces

C _n = AD _n D _n . A condition that is always fulfilled according to this logical table is A. = D_ "" = N = D _n D _n . - A and

a υ from κ α

D_, are both 0 when the bit is 0. When A and D _{n are} 0 and 1, B ο

then a bit 1 is present, but has not yet been coded. When A and D _{n are} 1 and 0, bit 1 is present and is encoded. The overall comparison signal is formed by the AND combination of all auxiliary output signals C via lines 117. The exit

of the overall comparison AND gate 190 is only switched on when in addition, a bit comparison signal N emanates from a bit comparison block. The completion of a composition of several Pattern is recognized by the compilation AND element 170 when all 16 D flip-flops are switched off again.

At the beginning of a comparison operation, all of the A flip-flops and D flip-flops become deleted via a line 53 on the part of the control circuit 34. The D flip-flops are then displayed according to the Arrangement of black elements in the data block register 26 switched on if necessary.

Function of the bit comparator

The function of the bit comparator 28 of the data compressor according to FIG. 5 can be based on the identification and coding of a sequence of reference patterns from the pattern stock according to FIG. 3 are explained. An example of a 4x4 bit data pattern is shown in Fig. 8e.

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represents. In order to facilitate the addressing of the bit arrangements of the data elements in the data pattern according to FIG. 8e, reference is made to FIG taken. The upper left corner of Fig. 2 shows a data block which is divided into 16 data elements. The data elements are in Columns and rows are arranged, counting from 1 to 4 from left to right or from top to bottom. It is expedient to the individual Addressing data elements within the data block in matrix form. The data element at the top left, for example, is called an element and the top element furthest to the right as data element 14, the data element in the second row on the far left is the Element 21 and the element on the far right in the second row is element 24, and so on. The elements of the data pattern according to FIG. 8e and the reference pattern in FIGS. 8a to 8d are also designated.

For the further explanation it should be assumed that the line buffer 24 has just entered the data pattern according to FIG. 8e into the data block register 26 under the control of the control circuit 34 according to FIG. invited. The control circuit 34 then outputs via the line 53 to all A flip-flops 130 and D flip-flops 140 in the bit

JD

comparator 28 the reset signal already indicated. Well done the control circuit 34 the data block register 26, its stored data elements via 4 * 4 output lines 27 in load the corresponding D flip-flops according to FIG. 6a. Each data element comparator block according to FIG. 6a, which has a black element is supplied from the data block register 26, sets its D flip-flop 140 in the on state. According to Fig. 8a

for the binary variable D zeros for the elements 11, 12, 13, 21, 22 and 23 and ones for elements 14, 24, 31, 32, 33, 34, 41, 42, 43 and 44 are entered. At the same time, the white length counter provides 30, to which the input lines 27 are also fed, determines whether the data block word in the data block register 26 is even contains no black elements. If this is the case, • the white length counter counts up by one step, the control circuit 34 informed about the white-only condition and the next image data block is transferred from the line buffer 22 into the data block register 26. Should be the next block of data

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also only contain white elements, the white length counter switches again one step upwards. Is. The next block of data but not all white, the white length counter 30 informs the control circuit 34 that a white-only block alone has been detected became. The control circuit 34 then leaves the jump logic 32 a 1 in the position 8 and a 0 in the position 9 as Insert jump code in output register 46. This indicates that the data contained in items 1 to 7 must be evaluated and then immediately afterwards a block has to be skipped. When a sequence of white-only data blocks through the data block register 26 passes, the white length counter counts 30 is the number of consecutive white data blocks. If then the first data block containing a black element is determined, the white length counter gives the determined number of consecutive white-only blocks as the value Δ in the positions 1 to 7 of the output register 46. The control circuit 34 causes the jump logic 32, a 1 in the two positions 8 and 9 of the jump code must be set in the output register 46. This jump code indicates that on the receiving side by Δ White blocks is to advance. In this way, white-only data blocks are thus encoded by run-lengths.

In the present case, the elements according to FIG. 8e not only contain white information. Thus, a normal reference pattern matching operation is performed. The control circuit 34 allows the reference pattern No. 0 according to FIG. 3 and FIG. 8a to pass from the reference pattern memory 38 into the reference pattern register 36. The reference pattern counter 40 is cleared to 0 in the process. All elements of the reference pattern now in the reference pattern register 36 are black; this means that the on condition prevails on all 16 reference pattern input lines 54. In FIG. 8a it can be seen that the binary variable D _n is 1 for all 16 reference pattern elements. The binary variable A _n , which in each case contains the status of the A flip-flop before the triggering via line 52, is 0 because all A-flip-flops were initially switched off by the reset signal via line 53. The binary variable C _R ,

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which characterizes the bit comparison in each case of an element is zero for the elements 11, 12, 13, 21, 22 and 23 and zero for the Items 14, 24, 31, 32, 33, 34, 41, 42, 43 and 44 one. As for the 16 data items compared, not all of the compare output lines 117 are switched on, the overall comparison AND gate is also activated 190 not switched on. This switching state is communicated to the control circuit 34 via line 201, which then causes the transfer of the reference pattern No. 1 from the reference pattern memory 38 to the reference pattern register 36 and thereby lets the reference pattern counter 40 increment by 1.

This process is repeated 14 times until the reference pattern no. 14 according to FIGS. 8b and 3 reaches the reference pattern register 36. This reference pattern No. 14 is the first recognized component of a reproduction of the data pattern according to FIG. 8e to be composed. This results in a C value = 1 for all elements of the reference pattern no. 14. The upper two rows of elements according to FIG the line 109, which is connected to the line 54 for the binary variable D, enters. The lower two rows of elements in FIG. 8b also fulfill the associated mismatch AND inverters 160-115 for the following reasons: D is switched on and thus also line 109. D _n on data element input line 27 is also switched on and sets this DG flip-flop 140 originally in its on state. With this, the status output line 101 is turned on. In combination with the on state of the line 54 from the reference pattern element D_, the AND element 100 is switched on and, via the line 103 and the bit comparison OR element 180 and the line 119, a signal N is sent to the 17th input of the overall comparison AND -Glange 190 given. The out-side output line 111 of the still switched on D flip-flop ensures, since it is itself still in the off state, that the non-comparison AND inverter 160-115 is fulfilled, so that it emits a signal. Since all 16 first input lines 117 of the overall comparison AND gate 190 are connected

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can be switched and also the signal via the 17th line pending, the overall comparison AND gate 190 sends a signal lines 48 and 107. The signal via line 107 in combination with the comparison signal N via line 103 is effected the switching on of the AND gate 110 and the AND gate 120. Thus, the D flip-flop is reset and the A flip-flop is switched on

£ 5

switched, which indicates that the corresponding data element was black and is coded. The overall comparison output signal via the line 48 prepares the switching on of the AND gate 42 and allows the number 14 as an α value from the pattern counter 40 to Output register 46 arrive. The sample code 14 is entered into this. After coding this pattern number 14 and input the control circuit 34 points to positions 1 to 7 of the output register 46 due to the fact that there is still no terminating Signal is given via the line 50 from the bit comparator 28, indicating that the reference pattern number 14 alone is not yet reproduces the entire geometric pattern arrangement according to FIG. 8e. The control circuit 34 therefore leaves the jump logic 32 zeros set in positions 8 and 9 as a jump code. Then the control circuit 34 causes the output register 46 to output the code word which contains the reference pattern number 14 in coded form as the first indication of a sequence of patterns to be assembled.

The control circuit 34 now allows the following patterns 15 to 23 from the reference pattern memory to pass into the reference pattern register 36. The reference pattern 23 shown in FIG. 8c contains black elements in positions 31, 32, 33, 41, 42 and 43. However, this element arrangement of the pattern 23 is already fully covered by the reference pattern 14. Another consideration would be uneconomical. The bit comparator 28 rejects the reference pattern 23 because no new bit comparison signal N is generated by means of the comparison AND element 100. The binary values A _n of elements 31, 32, 33, 41, 42 and 43 are indeed one, but the binary value of D _ßN is zero. Since the Dg flip-flops 140 remain in the off state, the line 101 does not emit a signal. This means that no bit comparison signal N can be transmitted via the line

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are given to the bit comparison OR gate 180. This becomes a Signal on line 119 to overall comparison AND gate 190 prevented. As a result, no overall comparison output signal is output via line 48 and AND element 42 is not switched on. The control circuit 34 is informed via the line 201 that no valid comparison has taken place. the Control circuit 34 thus continues to transfer successive reference patterns from the reference pattern memory 38 into the reference pattern register 36 to load.

The known processes now run up to the appearance of the reference pattern 39 according to FIG. 8d. This reference pattern 39 contains again a reasonable component for reproducing the geometric pattern according to FIG. 8e. The D flip-flop for the elements

ti

14 and 24 and the A flip-flop for elements 34 and 44 are already switched on. For elements 14 and 24, a comparison signal N is sent via line 103 to the bit comparison OR gate 180 delivered and continued via line 119 to Overall comparison AND gate 190. The elements in the first three columns of the lower two rows of the reference pattern 39 are empty. However, the variable A ^ is still 1. The corresponding out-side Output lines 123 are off, causing the on state of output lines 117 (C = 1). The items in the first three Columns of the top two rows cause a comparison output on their associated lines 117. This is because via the lines 109, there is no on-signal from the reference pattern input. Consequently output signals for all 16 elements are present on their associated output lines 117 and ensure that they are switched on of the total comparison AND gate 190. Via line 48 can the total comparison signal, the AND gate 42 open and the pattern number 39 as ct ~ value from the pattern counter 40 to the positions 1 to 7 of the output register 46 arrive. Because now all D flip-flops 140 of the bit comparator 28 comprising 16 data elements are reset are, the assembly AND gate 170 responds and gives an output signal via the line 50 to the control circuit 34. This indicates that the current reference

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pattern is recognized as the last necessary component for the complete Reproduction of the data pattern according to FIG. 8e. The control circuit 34 takes care of the loading of the next data block the line buffer 22 to the data block register 26. The white length counter 30 with its 16 input lines 27 from the data block register 26 now determines whether the next block may only contain white. If the next data block is not in all positions contains white, the control circuit 34 causes the jump logic 32 to position 8 of the output register 46 a 0 and to load a 1 in position 9. This identifies the coded word as a code number, which is the last component of a compound Rendering corresponds. The decoder on the receiving end then steps by one block after the decoding of the word Further. However, if the white length counter determines that the next If the data block in the data block register 26 only contains white, the white length counter counts up by 1 and leaves the second next data block get into the data block register 26. If the next data block is not pure white, the control circuit leaves 34 the jump logic 32 insert a 1 in position 8 and a 0 in position 9 of the jump code in the output register 46. this indicates that the coded word contains a code number α and an instruction that the receiving-side decoder by two Blocks following the last decoded pattern. However, if the next data block in the data register is only white Contains data, then the jump logic sets zeros in positions 8 and 9. This means that the output register has a code number α and the instructions for the decoder on the receiving end, stay at the current block. The white length counter then counts the number of consecutive pure white blocks, which are successively loaded into the data block register 26 from the line buffers. This number is transmitted encoded in running length, when the next not pure white data block appears in data block 26. The white length counter does not recognize the first one that is pure white Data block if it appears in the data block register after a sequence of pure white data blocks. The white length counter 30 informs the control circuit 34 of this and initiates the OR-WA 972 008

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Member 44, the number counted in the white length counter as Λ "value in to insert positions 1 to 7 of output register 46. The control circuit 34 now causes the jump logic 32 ones into the Insert positions 8 and 9 of the jump code in the output register 46. This means that the coded word is a run-length coded sequence marked by Δ pure white data blocks.

The present invention enables a significant reduction in the simple geometric patterns used in an image data transmission system of the type concerned to carry out the required reduction of the product from time to bandwidth are. The image data to be processed is packaged in a very advanced manner, either for storage or for immediate storage Playback or transmission, using a single or possibly multiple pattern comparison combined with the technique of run length coding of image details containing only white elements.

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Claims (4)

PATENT CLAIMS • 'Method for coding two-dimensional image information in an image processing system with subdivision of the image into a plurality in a matrix-like manner arranged pixel blocks, which in turn consist of n-m picture elements like a matrix, whereby the information content of these individual picture elements is evaluated in binary as black or white, characterized by the following process steps: a) Loading the n-m binary picture elements one at a time Information content of a binary black / white data block in a data block register (26) with n * m positions. b) Successive loading of simple geometric reference patterns (Fig. 3) each with n «m binary black / white elements from a given sample stock in a reference pattern register (36). c) Comparison of all individual picture elements in the data block register (26) with the corresponding pattern elements in the Reference pattern register (36). d) Marking of the n «ni matrix positions of the picture elements if a match is found between reference pattern elements and corresponding data block elements and output of a one-dimensional data word which contains the marked matrix positions in the form of binary information clearly reproduces. e) addition of block change information to the aforementioned data word, which identifies the recipient, whether the corresponding reference pattern elements for all picture elements of a data block being processed have been found and the complete coverage of all picture elements of the block with the formed Data word has occurred (01 = change) or whether not yet to all picture elements of the in Processing the corresponding data blocks WA 972 008 409886/0863 Reference pattern elements have been found and not yet a complete detection of all image elements of the Blocks until then (OO = no change). f) Continuation of the loading of predetermined reference patterns into the reference pattern register (36) and continuation of the Comparison with the sum of the picture elements of the pending data block, but not so far for all picture elements corresponding reference pattern elements have been found in the data block register (26), and others Delivery of data words with the addition of the block change information (01 or 00) until all are in each case Data block register (26) standing picture elements of the block are detected. g) Successive loading of another, still for Processing of pending data blocks with their n-m picture elements in the data block register (26) and Repeat the loading of reference patterns into the reference pattern register (36), the comparison of related ones Elements, the marking of matrix positions and the delivery of data words until all data blocks of the two-dimensional image to be processed (document 1) into a sequence of found Data word di reproducing reference patterns are implemented. 2. Circuit arrangement for performing the method according to claim 1, characterized by the combination of the following features: a) Data block register (26) with n «m positions, the one above its input (line 25) can be supplied with the binary black / white information of a pixel block (according to FIG. 2) are. b) Bit comparator (28), the n * m comparator and marker blocks and whose n «m first inputs are connected to the n« m outputs of the data block register (26) are. WA 972 008 409886/0863 c) reference pattern register (36) with η · πι positions, whose Outputs are connected to the n «m second inputs of the bit comparator (28). d) reference pattern memory (38), the outputs of which are connected to the inputs of the reference pattern register (36) and which holds a multitude of simple geometric reference patterns ready (Fig. 3). e) reference pattern counter (40), which loads predetermined reference patterns from the reference pattern memory (38) into the The reference pattern register (36) is tracked in a counting manner and in each case the sequence number of the currently offered to the bit comparator (28) Reference pattern as code value (α) ready. f) Jump logic (32), which if a match is found between the offered reference pattern and the data block pending in the data block register (26) either a code signal (01) as block change information forms if the corresponding reference pattern elements are found for all picture elements of the current data block have been, or a code signal (00) forms, if not yet to all Picture elements of the current data block the corresponding reference pattern elements have been found, h) Output register (46), which is used when a match is found between the reference pattern and the data block in the data block register (26) the code value (α) from the pattern counter (40) and the code signal formed by the jump logic (32) (01, 00) can be supplied. 3. Circuit arrangement according to claim 2, characterized by a bit comparator (28) with the following features:
a) Arrangement of n «m comparator blocks, each with a first input for entering an image data element (D) from the assigned position of the data block register (26) and each with a second input to the feed WA 972 008 409886/0863 a reference pattern element (D _n ) from the corresponding position of the reference pattern register (36). b) bit comparison OR gate (180) with n * m inputs, whose each is connected to one bit comparison output each of the individual n «m comparator blocks, with am Output of this bit comparison OR gate (180) Signal can be removed if at least one black element of the offered reference pattern is compared with the one being compared Black element from the data block register (26) is found to match. c) total comparison AND element (190) with (n * m) +1 inputs, one of which is connected to the output of the bit comparison OR gate (180) and the other n «m inputs are each connected to an auxiliary comparison output of the individual comparator blocks, whereby at the output of the overall comparison AND gate 190, a signal can be removed is when a reference pattern is found which does not contain any black elements to which there is never one matching black element is given from the data block register (26). d) compilation AND element (170) with n «m inputs, each of which is connected to a "complete" output of the individual comparator blocks, with a The "compilation complete" signal can be removed from the output of the compilation AND element (170), if there are no more black elements in the compared data block that are not already due to the corresponding Schwärζelemente in / in the found matching Reference pattern (s) are recorded. 4. Circuit arrangement with a bit comparator according to claim 3, characterized by n-m comparator blocks with the following Features: a) First flip-flop (140) whose setting input (S) denotes corresponding first input of the bit comparator (28) WA 972 008 409886/0863 and its out-side output (ÖT) forms the "complete" output which leads to one of the inputs of the compilation AND gate (170). b) Bit comparison AND element (100), the first input of which with the associated output of the reference pattern register (36) and its second input with the one-sided output (D) of the aforementioned first flip-flop (140) is connected and the output of which is connected to one of the inputs of the Bit comparison OR gate (180) leading comparison output of the comparator block under consideration. c) mismatch AND gate (160) having an inverter (115) is connected downstream, the first input of this AND element (160) being connected to the corresponding output of the reference pattern register (36), the second input of the AND element (160) being connected to the out-side output (D ~) of the The first flip-flop (140) and the third input of the AND element (160) is connected to the external output (K) of a second flip-flop (130) to be described, the output of the downstream inverter (115) also forming the auxiliary comparison output , which goes to one of the inputs of the overall comparison AND gate (190) leads. f) reset AND element (120) for the first flip-flop (140), wherein the first input of this AND gate (120) with the output of the bit comparison AND gate (100) and the second Input is connected to the output of the overall comparison AND gate (190). g) Second flip-flop (130), the setting input (S) of which is connected to the output of a setting AND element to be described below (110) is connected and its out-side output (A ") is connected to the already mentioned third input of the mismatch AND gate (160). h) setting AND element (110), the first input of which with the Output of the bit comparison AND element (100), the second input of which is connected to the output of the overall comparison AND element (190) and whose output is connected to the setting input (S) of the second flip-flop (130). WA '972 008 409886/0863 i) Reset signal / the reset inputs (R) of the two flip-flops (130, 140) with each image data block change is feedable. WA 972 008 409886/0863 Blank page