DE2415408C2 - Si-MESFET on insulator substrate and process for its manufacture - Google Patents

Description

thin active layer (20) of the same conductivity type

how the silicon body lies. .

2. MESFET according to claim 1, characterized in that the silicon body is η-conductive. ^ao

3. MESFET according to claim 2, characterized in that Frfindune relates to a Schottky gate field that is close to that between the silicon "ΐ?" _{τ "η; ςΙΟ Γ} (MESFET), as lying in the preamble of the body (2) and said insulator substrate (1)" ^r n ^ s is _specified, and a process interface a layer of p-type silicon (21) claim ₆ e

Grenzf p ^ SSHKtellu

is arranged. ³ _U pn _F p _T c _s y _n a known and for example in the

4. MESFET according to claim 2, characterized in "h ™ publications shown: 1. K. E. Dran-

shows that the following ° ^^ ™ ^ _{£ Γ} | below the silicon body (2) _ΒΜ j. _Res . Develop.,

bflh i ti flhen f? ^:

draws that the below the silicon body (2) g ^^^ _{£ Γ} | _ΒΜ j. _Res . Develop.,

lying substrate surface a negative area f? V, 07η c 82 to 94 ^: 2 Th. O. Mohr, IBM

having charge (16) in the substrate March iy / u. ^ ^ _g ^ _{2 to] 4? Au $}

Adjacent boundary layer of the silicon body 30 J. ^{Kesu C} p _ru ^ _{writ ge} ht shows that with e

ne p-layer (210) influenced. MFSFFT a power gain also noc

5. MESFET according to claim 1, characterized in that MESFET emews g ^ MESFETs made from

ld t GHzBer cn ™

adjacent boundary layer of the silicon body 30 J. ^{Kesu C} p _ru ^ _{schrift ge} ht shows that with a

a p-layer (210) is influenced. MFSFFT a power gain even in the

5. MESFET according to claim 1, characterized in that MESFET emews g ^ MESFETs made from shows that the silicon body is sliding, st GHz-Ber cn ™ limit value of about

6. MESFET according to claim 5, characterized in that silicon is constructed s η < _{dje from Ga} " _ium .

draws that close to that between the silicon cor- 35 ¹² G " ^z , ^ ^a Ä _r ~ are set, 30 GHz were used as

per (2) and the insulator substrate (1). lying arsend (GaA _s ) mountains> e ^ _Beside ^

Interface one layer "-conductive"! Silicon an- ^^^^^^ stti is another upstream one. f ^u . ^l ~ " . _{p (;} pr _T , _{that s} i _it i _c h relatively easy with good

7. MESFET according to claim 5, characterized marked part of the MESFETs that "eg £ _hers J _tn is characterized in that the below the Siliziumköφers (2) 40 reproduz.erbarer, low mnsaiap g underlying substrate surface can be a positive area- circuits is a construction having means of charge in the substrate notify Fur integri ^ J ^ na g _ejnem _ hard boundary layer of a SIzumkörpers ^{SLi 'z} ™ ^m "" ^^ _However influenziert switching elements "layer. ^same. let ⁿ ^ substrate SiCN j GaAs base

8. MESFET according to one of claims 1 to 6 45 * ^^ j £ ^ teS ^ realize, so eis'iÜefri ^k _s r ^nZeiChnet ' ^{Isolatorubstrat} "^ J JSÄng iS MESFETs from GaAs in the ^eiI 9. MESFET according to claim 8, characterized is restricted in the known sense

draws that the spinel is a magnesium-alumi- ^ ^r ^ äffiSS «» n.iii.

nium spinel (MgO · Al ₂ O ₃ ) «t .. ⁵ ° Jer Stondder T ^ hnrik ur M _used ^

10. MESFET according to one of claims 1 to 3. As a substrate iur _u «ι

and 5 to 7, characterized in that the previously preferred silicon by mi ^ inem high elek

The insulator substrate is a sapphire. Irish resistance. On the S 142 14 ^ this one

11. MESFET according to one of claims 1 to 10, document is shown that «n such bu.zrum characterized in that between the source 55 as a substrate only one ^ J ™ ^ ™ ^ SeJSS (3) and the gate electrode (5) and are not uleal between the polishing properties Therefore, the gate and the drain electrode (4) within the has to build MESFETs ge, in which the active -ae silicon body (2) is particularly highly doped loading rich hm outwards 1 ^ P ^ ifJ ^ J ¹ ^ i

S " ^{ih lit i dr} SSX

SmioSegS: p

MESFET extended to one of claims 1 to 11.

characterized in that the, electrical

ziumkörper close to the substrate facing away from the substrate during the "^" "

Surface of the silicon body a specially integrated circuit other highly doped active layer (200) of the same * 5 were ^ l ^^^ P ^

Conduction type as the silicon body is arranged. S. iz.um-M ESFETs on ^^. ^ B ^^ egen-

13. MESFET according to claim 11, characterized in that silicon MESFETs »» 'J »^ ™" ™ ¹ J ^ JgJ; f _o f _m .

indicates that the highly doped areas (230) are above other heterogeneous S.hzium MESFEl s

draw. The reason for this is that the Schottky gate silicon layers with a thickness of 0.2 μπα or electrode 5 lie between these electrodes a voltage source for the drains is not provided on substrates other than silicon substrates with a voltage U _D. Between the source and the near-high crystallographic and electrical drain electrode there is a -doped silicon area, which can be produced in quality. through which the current can flow. The strength of the

Accordingly, it is an object of the invention to provide so-called high-quality silicon MESFETs flowing through the semiconductor body on insulator substrates to drain current 1 _D can be achieved in a known manner by, at the same time, higher switching speeds than Control to Masio Tnian potential with silicon MESFETs. This forms below the siv-silicon substrate to be achieved. the gate electrode in the silicon body a space

This object is achieved by a charge zone 13 like the one at the beginning, one opposite to the rest specified and according to the characteristics of the areas of the silicon body very high electrical Proverb 1 trained MESFET. Possesses resistance and in its breadth of strength

In the invention, therefore, relatively thick 15 of the electrical contact with the gate electrode Silicon body used, so that close to that depends on the sub-potential. The silicon body consists of strat facing away from the surface of the silicon body is essentially made of -doped silicon. At the border charge carrier possibility is achieved as it is between the semiconductor body and the sub-one Silicon crystal corresponds to high crystal quality. Strat, however, is a p-doped silicon layer 21. This charge carrier mobility at the surface ao This can be generated in different ways, is used for silicon bodies on sapphire or spinel due to the pw transition between the p-conducting a thickness of the silicon body of about 1 μπι achieved. Layer 21 and the -conductive material of the silicon der Part of the silicon body near the substrate, a space charge zone 22 forms which, through those which form due to the p «transition due to their high electrical resistance, The space charge zone is electrically switched off and thus practically all of the space it occupies ineffective for the function of the MESFET. Those at the boundary of the silicon body to the substrate for actual, for the electrical function of the MESFET the electrical function of the invention effective active layer between the space charge MESFETs makes ineffective, so that between the zone and the surface facing away from the substrate of the gate electrode and this space charge zone only one According to the invention, the silicon body can be thin active to a thickness of 30 compared to the thickness of the silicon body of about 0.2 μπι or less can be set. Layer 20 lies.

Since the MESFETs according to the invention as half-The p-doped layer 21 can with the known

Being a leader on highly insulating substrates, methods of epitaxy or ion implantation det are, and since the entire metallization for conductor or also as influenced by interface terms Tracks and pads can also be fabricated on the high-35 p layer.

insulating substrate, arise only extraordinarily- In the first case, for example, the gas mixture,

borrowed little parasitic capacitance. This is one from which the silicon layer is deposited in an oriented manner A special advantage over MESFETs on silicon is that the dopant is added. This one will Substrates. There the parasitic capacitances are deposited on then with the layer and in the grid The reason for the remaining conductivity of the silicon substrate 40 is also built in. In the second case, ions are the greater. Since in the invention the insulation to all dopants in the partially or completely deposited shot in different silicon bodies outside the MESFETs according to the invention. One of Because the island arrangement is complete, interfacial term induced p-layer can be required here in contrast to arrangements on solid mass produced by that on the surface of the Silicon no additional shielding measures. 45 substrate 1 has a surface charge of negative charge carriers Circuits with the ger according to the invention is generated. This can be done, for example MESFETs can therefore advantageously be done at a height that a magnesium element used as a substrate Produce a packing density than with arrangements like aluminum spinel in a hydrogen atmosphere gene on silicon substrates would be possible. Heated for 5 min at about 1150 ° C.

In the following, the invention and examples 5 “The upper” -doped part of the silicon body can be represented in preferred embodiments with reference to the figures, for example likewise by epitaxy or ^l ° ⁿ . In accordance with the invention, MESFETs are fabricated with implantation. Another Mog-active layer of both -doped and -doped silicon is made possible by diffusion into this part of p-doped silicon. Generate on the basis of the figure. In this case, in a manner known per se, transistors are described with -doped active doping material on the silicon body ^on g ^e ^ a layers. Transistors with p-doped gene and by heating with the desired binactive layers have a corresponding structure introduced into the silicon penetration depth, and are explained further below. The electrode metal for the MESFETs can be

Fig. 1 shows a basic representation of the use as in known integrated circuits, aluminum invention ^6o "ium. When transistors are produced

FIGS. 2 and 3 show exemplary embodiments. those should, with those without external gate voltage none

4 shows an example circuit. Drain current is to flow, one can use

In Fig. 1 is on a highly insulating substrate 1, electrode but also other metals and compounds that consists, for example, of spinel or sapphire, a use. For example, with Flatinsiiizia island-shaped silicon bodies 2 with the source area 5 as gate electrode material, MESFETs can be produced oei 30, the drain area 40, both from highly doped silicon only above a gate voltage Ut - u, iv. On these areas 30 and 40 are the source electrode 3 and the drain electrode 4, electrode a current can flow through the transistor from the source to the urine.

5 6

A first embodiment corresponded in the cross section of the gate 5 over the full width of the silicon body. The silicon body had one extended. All electrodes have pads with a thickness of about 1 μm. The / »- doped layer 21 was connected for connection to further circuit parts, produced by doping during the epitaxy, the source electrode with the connection pad 300, the« -doping of the silicon body by diffusion. The gate electrode with the terminal pad 500, the charge carrier concentration N _{n of} the negative La drain electrode with the terminal pad 400. The carrier of the -doped silicon body was on the same substrate 1 on which the MESFET

about 10 ¹⁷ cm ^-3 . The lower / »- doped layer 21 showed, further circuit arrangements can have the same carrier concentration N _{P of} the positive, the MESFET according to the invention with the charge carriers, so that the space charge-free other circuit arrangements are in different zones 22 to extends towards the substrate 1. Overall, however, it can be electrically connected in a known manner, is thus at the boundary to the substrate within the. The previous examples referred to

Silicon body a layer of about 0.3 μπι, depending on the MESFETs with n-type silicon in the active part of the Thickness of the / »- doped layer for the transistor radio transistor. But they are also / »-type transistors tion switched off. »5 can be produced, which z. B. with hafnium as Schottky

A particularly preferred exemplary embodiment can be realized with gate electrode material; the suitability is explained with reference to FIG. 2. On the substrate 1 of this material, for. B. in the work of AN is again the approximately 1 μm thick silicon body 2 Saxena in Applied Physics Letters 19 (1971) p. 71 with the source area 30, the drain area 40, to 73 have been shown.

the drain and source electrodes 3 and 4 and the ao these / »- type transistors can be connected to gate electrode 5. The examples of« -type MESFETs on insulators that are shown in the semiconductor body have a surface of the substrate - Build up, with the opposite line charge in the form of negative interface terms 10 . type is to be selected, ie instead of / »- doped areas. These interface terms were generated in the above-mentioned« -doped, instead of «-doped /» - doped way. Through these charges is in the as in the case of the interface Terme those having posi-silicon body a / "- influenziert layer 210th For generating the tive sign, which then an n-conductive surface density of the interface terms, values were to influence layer. This interface Terme könbis to 3 x 10 ¹² cm ² is set. The silicon body is to be NEN, for example, produced in that a than in the regions which are adjacent to the substrate, the substrate for use sapphire about 5 min in hydrogen relatively lowly doped, for example with 30 is annealed at about 1100-1200 ⁰ C, a value of 3 x ^{10 16} cm ³ to 5 x 10 ¹⁵ cm ³ . By combining both MESFET types in

Because of the relatively low doping, a single circuit can also use a large width of the space charge zone 22. Complementary transistors according to the invention ion implantation will build up circuits under the substrate, ie circuits that both face away from the surface of the silicon body within 35 "-type -Transistors as well as / »- type transistors entdes the silicon body hold an approximately 0.2 μm thick active.

Layer 200 to a value of N _n = 10 ¹⁷ cm ^-3 do- Fig. 4 shows a circuit example that uses an inverter

animals. The silicon is represented in areas 30 and 40 : on a common substrate, a body is highly doped over its entire thickness by means of diffusion so / "type transistor 2000" and a "type transistor 2001". After the implantation takes place 40 The /> - type transistor has, at the interface with the heat treatment at, for example, 900 ⁰ C, the implanted substrate 2100. To enable the W-type oriented atoms, the "doped layer, that is, in the layer Transistor the / »- doped layer 21. The space charge introduced ions are designated by 2200 or 22 , preferably by zones. The n-type heat effect, made electrically effective. The transistor has the source electrode 3, the drain

This is followed by the production of the metal electrodes. ₄₅ electrode 4 and the gate electrode 5, all z. B. This is followed by another full-area implant made of aluminum. The / »- type transistor betation, where the source, drain and gate electrodes sit the source electrode 3000, the drain electrode serve as a masking mask: Between the source electrode 4000, both of which, for. B. made of aluminum, and the and gate electrode and between the drain electrode gate electrode 5000, the z. B. consists of hafnium, and the gate electrode are still additional charge 50 The two transistors are implanted, as shown in the figure, carrier, it can be seen in the interior of the silicon, interconnected, ie on the body a maximum of the charge carrier concentration of the source Electrode 3 of the n-type transistor is set from about 10 "cm- ³ to 10 ²⁰ cm- ³ . This ground potential, at the drain electrode 4000 of the /» - type-way is obtained in these areas of the silicon transistor opposite to the ground potential body, the high "+ -doped regions 230 with high 55 positive voltage Ubb. the output voltage Ua electrical conductivity. near the bottom of the gate is obtained the value of the ground potential or to the value electrode exposed surface of the silicon body Ubb, depending after the whether the gate electrodes with a, the charge carrier ^{concentration must be smaller than negative or positive 10 17} cm ~ ³ compared to the earth potential, so that the Schottky gate breakthrough uch voltage U _{G are} applied. The voltage in Fig. 4 is not affected. 60 only symbolically shown electrical connection

Fig. 3 shows a lines produced according to the invention can, for. B. with well-known evaporation technology MESFET in top view. One recognizes that niken have been established.

For this purpose 2 sheets of drawings

Claims (1)

have a charge carrier concentration of about IO »cm-» ■ · IQ20 cnj-3. Claims: 'Dlb. 'MESFET according to claim 12, characterized in that the highly doped active layer 1. MESFET (Schottky gate field effect transis- * '' · _Ladungstr ägerkonzentration of about disturbing) _has conducting p a n or Siliziumkor- 5 egg. per on an insulator substrate and with at least '"MESFET ^{nacii one of the requirements} ' ^{bls I4} - a source, a drain and a gate elec- ij ' _rc h characterized in that the silicon body trode, characterized in that ° * ^uu _adl 7 _n g carrier concentration of less than substantially parallel to the surface of the sub- a l. ^^ starts (1) within said silicon body (2) a ₁₆ io y _er f _a h _r s for the production of a MESFET pn junction is arranged, which within the · ^ _of claims 4 or 7, thereby Silicon body a space charge zone (22) indicates that the surface charge of the sub- which essentially covers the areas of the silicon 'surface' by means of tempering the sub- body near the substrate surface occupies the sirai _Wsscrsto ff atmosphere at about 1100 to and in that between the gate electrode (5) 15 strats " ¹ J ^ ^ and this space charge zone has a relatively izuu ^ c _B