DE2407011A1 - FIXED STORAGE - Google Patents

Description

Boeblingen, February 11, 1974 lw-fe

Applicant: International Business Machines

Corporation, Armonk, N.Y. 10504

Official file number: New registration λ / η η η Λ i applicant's file number: KI 972 030

Read-only memory

The invention relates to a read-only memory with a memory matrix, their binary coded memory content through logical connections or logical separation points at the crossing points of rows and columns is fixed. Word lines running in the row direction are used to query memory words of the memory contents. The bits of each memory word read out during a memory cycle are used as output signals the bit lines running in the column direction can be removed in parallel.

In known methods for addressing a sequence of content contiguous memory words by word lines in a memory matrix becomes a binary address counter each time advanced by one step when the next word line is to be energized. The binary output values from the counter are each decoded to energize each word line individually. Another method uses a ring counter that starts with each stage is connected to a different word line.

One of the disadvantages of having a separate address counter for addressing of word lines of an integrated semiconductor read-only memory is that essential parts of the area the substrate are necessary to make the necessary wiring connections between the counter and the memory arrangement. Another disadvantage is that every line

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Connection is subject to a statistical probability of causing a circuit failure. The considerable number of Lines that are used to connect an address counter to a Memory array are required, therefore reduces the production yield and the reliability of integrated circuits essential.

Further disadvantages occurring when using address counters for addressing a program memory arrangement are the complex special counter switching connections that are necessary if there is a branch or even a conditional branch should be performed.

The object of the invention is to save the individual lines of a read-only memory without separate address-forming circuits to address.

The object of the invention is achieved by the in the characterizing Part of the main claim described device. By eliminating the addressing circuits, the number of necessary connections from the memory matrix to external circuits can be drastically reduced. Especially when it comes to execution of the read-only memory in integrated circuit technology, this greatly simplifies the construction of the memory and also saves space on the semiconductor substrate. The simpler design increases the reliability of the read-only memory increased considerably.

A preferred embodiment of the invention is characterized in that that branching to other word lines can be carried out from the output of a word line. Through this program branches can be carried out in a simple manner without the need for complex address-forming devices would be necessary. This applies equally to conditional and unconditional branches. The facilities to carry out According to a preferred embodiment, these branches contain an AND element which is triggered by an inhibit signal

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is controlled. By providing suitable outputs on the word lines, it can be achieved that both a branch takes place, and at the same time the following memory word is read out. This gives you great program flexibility achieved with simple means.

An embodiment of the invention is shown in the drawings and will be described in more detail below.

Fig. 1 shows schematically an embodiment

of the invention with field effect transistors and

Fig. 2 composed of Figures 2a and 2b

shows the two upper word lines as an example of an integrated circuit arrangement the memory arrangement according to FIG. 1 with its associated switching elements.

In Fig. 1 is a matrix-shaped memory arrangement with logic Switching elements shown, which column switching elements 21, 23, 25 and 29 contains. Each column switching element can be used for its bit position provide an output signal, which can be picked up in the figure below. In the described embodiment a read-only memory is used as a microprogram control memory. Therefore each of the bit position outputs is abbreviated to a specific memory control function, such as "Toggle the instruction counter Step next "," Switch through to register 1 "," Control the working memory ", etc. The bit position output can of course can be used for any type of function including the definitions of the binary value in an output word, if For example, the read-only memory is used as a general memory and not just as a microprogram control memory. Each such column switching element therefore defines a bit position in the read-only memory.

In the line direction, the read-only memory in FIG. 1 has KI 972 030

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a variety of word lines. Each row includes a line such as a word line 105. Each word line forms At the crossing points either logical connections 11, 12, 14 or logical separation points 13 with the respective inputs of the column switching elements 21 to 29. Logical connections are created by producing a thin oxide layer and a logical OR-FET gate metallization over source and drain diffusion regions such as 139 and 137, a conditional Memory deactivation circuit. Logical separation points are created by placing a thick layer of oxide over the Source and drain diffusion regions, as a result of which no effective field effect transistor is formed at these crossing points that could serve as a switching element.

Each word line after the first row is one of several word lines comprehensive control sequence has dynamic switching elements, which they with the previously excited word line associate. The input switching element 57 and the output switching element 53 are examples of such dynamic switching elements. The output switching element 5 3 and the input switching element 57 are switched here one after the other, for example, in order to connect the dynamic switching connection to the following Establish word line, the switching elements 53 and 57 together have a delay of one memory cycle time. The output switching element 53 can, however, also be absent, so that a direct connection from the end of the word line 165 to the The input of the input switching element 57 exists, if it is ensured that the time delay caused by the input switching element 57 is large enough for one memory cycle is. On the other hand, the input switching element 57 can also be omitted and then the output gate 53 turns the necessary delay between the time of arousal of the row of word line 165 and the excitation time of the next following row of word line 167. When a single switching element is used to connect a word line with a following word line, this switching element must be a non-inverting switching element. KI 972 030

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As can be seen from the illustration in FIG. 1, a branch is from a word line 105 to one, for example Word line 167 can be produced very easily by using line 150 shown in dashed lines in the figure as an extension the line 149 to the output of the output switching element 33 to a logically negative OR input of the input switching element 57 leads.

The column switching element 167 in Figure 1 is with its output connected so that a branch from the row with the word line 107 and also from the row with the word line 167 to the row with the word line 175 is possible. The branching operations mentioned are replaced by positive logical ones OR input connections 12 and 14 with the interverting column switch 21 established. The outcome of the Column switching element 21 is connected to a negative AND input of the inverting input switching element 61. As soon as one or both word lines 107 and 16 7 are excited, it therefore appears at the output of the column switching element a negative signal and energizes an input of the AND gate 61. If the second input of the AND gate 61 with the Designation D is also negative, word line 175 is energized and in this way a conditional branch is performed.

FIGS. 2a and 2b show the arrangement of diffusion and metallization areas of a section from the FIG Figure 1 schematically shown circuit with field effect transistors in integrated circuit technology «The diffusion areas are outlined in dashed lines, the metal layer areas in solid lines.

The input switching element 31 is a dynamic switching element with a specific, predictable time delay. the A time delay is achieved by unconditionally activating a memory element and then deactivating it Storage element a predetermined time later. In the KI 972 030

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The storage element consists of FET circuits of FIGS. 2a and 2b from a rechargeable node capacity. This node capacity also contains the switching capacity of the Wiring, as well as the gate-source capacitance and the gate-drain capacitance the field effect transistors operated by the node.

The junction capacitance at the output of the switching element 31 is for example through the diffusion area 113, the metallized Area 105 and the gate capacitance of transistor 6 are formed. The storage element of the switching element 31 in the form of the output node capacitance is in phase 1 of the storage cycle time via a field effect transistor unconditionally, i.e. regardless of the result in the relevant program step is achieved, charged, which consists of the diffusion regions 113 and 115 and the metal region 122. The diffusion regions 113 and 115 form the source diffusion zone and the drain diffusion zone, while the metal · area 123 forms the gate electrode of transistor 1. A thin oxide layer separates the metal layer 123 from the diffusion zones 113 and 115 in the region of the transistor 1. The diffusion region 115, which forms the drain diffusion of the transistor 1, is via a feedthrough with the voltage metallization region 125 connected, which is connected to a positive voltage source. The metal area 123 is connected to the output of phase 1 of a four-phase memory cycle trigger, not shown. The memory cycle clock may be any known circuit as it is often used in computers to divide a storage cycle into four separate time intervals, which are called phases.

The storage element of the switching element 31 is switched off due to the conditional discharge of the output node capacitance of the switching element 31 by means of a second

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FET circuit comprising transistors 2, 3 and 4. The conditions for deactivating the memory element appear as signals at inputs A and B to the metallization areas 101 and 103, respectively. A part of these metallization regions 101 and 103 forms the gate electrodes of transistors 2 and 3. The diffusion zone 113 runs below the metal areas 101 and 103 and there forms the drain diffusions of the transistors 2 and 3. In the same The diffusion zone 111 runs underneath the metal areas 101 and 103 and there forms the source diffusion of transistors 2 and 3. As with transistor 1, the Gate electrodes of transistors 2 and 3, and in this regard of all transistors of the embodiment, of the Source and drain diffusions separated by a thin layer of oxide.

A positive voltage on the metal layer 101 and 103 causes the transistors 2 or 3 to conduct and displaces thereby the second field effect transistor circuit in the conductive state for the discharge of the output node capacitance of the switching element 31. Although they are prepared to discharge the output node capacitance, namely, conduct the transistors 2 and 3 only supply the current when the series-connected transistor 4 also becomes conductive. the serial connection of the transistor 4 with the transistors and 3 is achieved by forming the drain diffusion of the Transistor 4 as an extension of the diffusion region 111. The source diffusion of the transistor 4 is an extension of the diffusion region 109, which is connected to a reference potential such as earth. The gate electrode of the transistor 4 is an extension of the metallization area 121 associated with the phase 2 output of the memory clock connected is.

In this way, the transistor 4 is made conductive only at the time of phase 2, whereby the output node of the

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Switching element 31 is only conditionally discharged at the time of phase 2, determined by the signals at inputs A and B. If inputs A and B both carry negative signals, transistors 2 and 3 are made non-conductive and the output node of the switching element 31 remains at a positive potential. When the input signal is A or B is positive, the capacitive charge stored at the output node of the switching element 31 is discharged. Even though the switching element 31 and all sister switching elements in the example, field effect transistors operating in the enrichment mode that are driven by a positive voltage source, equivalent switching elements can also be used that respond to negative input signals and are connected to negative voltage sources. the Use or the need for special capacitors in the form of extended capacitors provided at inputs A and B Areas of the metal layers 101 and 103 above the base diffusion zone 109 depend on the circuit design chosen and the total capacitance of those nodes to which the metal areas 101 and 103 are connected are.

In addition to an input switching element, each row contains a word line, such as the strip line of the metal area 105. This metallization also forms the gate electrode of a field effect transistor in a crossing point of the memory matrix, if a logical connection between a Word line and a column switching element is desired. Thick layers of oxide separate the conductor metal areas from the Source diffusions of the column switching elements, and thus prevent field effect current passage, if a logical Separation point between a word line and a column switching element is to be realized. For example, since those shown in FIG Column switching elements 21, 23, 25 and 29 are all logically not connected to the word line 105 of the associated word row there is a thick layer of oxide between the metal region 105 and the source, channel and drain Be KI 972 030

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range where the input transistors would be made if logical connections were desired there. Various such logical separation points, characterized by the lack of input transistors, are denoted by 13 in FIGS. 1 and 2a, for example.

In Figure 2b are the diffusion and metal areas of an output switching element 33 for the row of word line 105 and an input switching element 35 for the row of word line 107. The diffusion layer areas are outlined by dashed lines, the metal areas in solid lines. As the output switching element 33 also belongs to the logic switching elements that form the read-only memory, it has an unconditional switch-on circuit in the form of the transistor 5, a storage element in the form of the output node capacitance of the switching element and a conditional memory shutdown arrangement in the form of transistors 6 and 7. The unconditional precharge transistor 5 is located below a portion of the metal area 127 which is connected to the phase 3 output of the memory clock. Part of the diffusion zone 145 forms the source diffusion and part of the diffusion zone 147 forms the drain diffusion of the transistor 5. The diffusion zone 147 is connected via a bushing to the metal area 125, which in turn is connected to a positive voltage source. The diffusion zone 145 also forms the drain diffusion of the transistor 6, which is the output capacitance of the switching element 33 is conditionally discharged at a point in time which is determined by the transistor 7. The diffusion zone 145 is also connected to the metal conductor 149 and thus forms a connection from the output of the switching element 33 to the input of the switching element 35. The diffusion region 143 forms the source diffusion of the transistor 6 and the drain diffusion of the transistor 7. The gate of the transistor 6 is as widening of the metal region 105 and is excited by the output signal from the input switching element 31. The source of the transistor 7 is a branch of the diffusion region 109, which is connected to a reference voltage potential, such as

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is explained above in the description of the switching element 31. The gate of transistor 7 is made by expanding a junction the metallization 129 is formed, which is connected to the output of phase 4 of the memory clock. A Adjustment capacitor 22 is (from those mentioned above for the capacitors at the inputs A and B of the switching element 31 Reasons) connected to the output of the switching element 33. The capacitor 22 is formed by a metallization area, which lies over part of the grounded diffusion area 109 and is separated from it by a thin oxide layer. The metallization area of the capacitor 12 is connected to the diffusion zone 145 by a feedthrough.

Similar to the switching element 31, the transistors 8, 9 and 10 the input switching element 35, which is connected to the word line 107. The diffusion zone 153 and the diffusion zone 147 form the source and drain of the unconditional precharge transistor 8. The gate of transistor 8 is an extension of the metal area 123, which is connected to the output for phase 3 of the memory clock. The diffusion zone 153 also forms the drain diffusion of the transistor 9 and it is connected to the metal region 107, which is the word line the next following row of the memory matrix. The diffusion zone 151 forms the source of the transistor 9 as well the drain of the transistor 10. The gate of the transistor 9 is due to the expansion of the metal region 149 over the source and Drain of the transistor 9 is formed and is separated from it by a thin oxide layer. The source of transistor 10 is a branch of the grounded diffusion zone 109. The gate electrode of transistor 10 is part of metal area 121, which is connected to the output for phase 2 of the memory clock connected is.

The mode of operation of the dynamic switching elements 31, 33 and 35 described will then be explained in order to show that there is always a delay by one memory cycle time due to the logic circuits of each word line, be-KI 972 030

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before the next word line is energized. At the time of phase 1, word line 105 is unconditionally charged. Phase 2 becomes the word line 105 conditionally and under control of the signals at the inputs A and B are discharged. The capacitor becomes phase 3 22 loaded. The capacitor belonging to the output node of the switching element 33 is used in phase 4 of the same storage cycle 22 conditionally discharged under control of the residual charge remaining on the word line 105. If the conductor is 105 remained charged at the time of phase 2 because for this phase 2 a negative signal appeared at both inputs A and B the capacitor 22 discharges in phase 4. In phase 2 of the next memory cycle, the word line 107 is then not discharged because the transistor 9 does not conduct. Therefore, during phase times 3 and 4 of the first descriptive memory cycle the word line 105 energizes and actuates the logical connections of the first word line. During the phase times 3 and 4 of the next memory cycle, the word line 107 is then validly energized and thereby reads the logic operations into the next word line.

The memory content of each row of the memory matrix of the exemplary embodiment described is by means of the wiring or the formation of the integrated circuit by means of logical connections and separation points. Based on Figure 2a For example, the logical connections 11 and 12 to the column switching elements 25 and 21 are described. The input transistors to the column switching elements are through several line-like, vertically running diffusion regions 131 to 141 are formed, the intermediate areas of which are capable of being used as FET channels. A logical connection the word line 107 with the column switching element 25 is, for example formed by the transistor 11, the source of which is part of the diffusion zone 139 and the drain of which is part of the Diffusion zone 137 is. The gate of transistor 11 is through a widening of the metallization of the word line 107 is formed, below which and above the source, drain and Channel areas of the transistor 11 are a thin oxide layer KI 9 72 030

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is located. The metalization of the word line 107 could also be a uniformly wide strip line with in all areas a thick oxide layer are formed thereunder except for the area where a transistor is to be formed. Of the The metalization of the word lines is for the sake of clear illustration of the position of the input transistors in relation to the logic circuits 105 and 107 are shown here more broadly as soon as a transistor is to be formed as a logical connection. In a similar way Thus, the transistor 12 of the column switch 21 is formed over the drain diffusion 131 and the source diffusion 133. The diffusion zone 133 can be used as a source diffusion as well for the column switching element 21 as well as 2 3 can be used. So three diffusion zones drain (131, 135) and source (133) for the input transistors of the two column switching elements (21, 23).

Like the input and output gates of each line of words, so the logic circuits of each column switching element also contain an unconditional capacitance precharge transistor, like transistor 17 (Fig. 1), which is activated at the time of phase 3, a capacitive storage element and a conditional discharge circuit containing the transistors of the logical word line connections and one in series switched transistor, such as transistor 16, which is made conductive during phase 4. According to the description of the 2a, the source diffusion 139 and its series-connected transistor 16 of the column switching element 25 are common used by the next column on the right (not shown in FIG. 1). The unconditional precharge transistors, like transistor 17, are connected to the drain diffusion, which are the output nodes of each column switch form, and therefore a separate unconditional precharge transistor and a Drain diffusion can be provided.

In the exemplary embodiment described above, inte-KI 972 030

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integrated circuit only a single metallization layer and one only diffusion layer used, which in metallization zones and diffusion zones are divided, which are separated by thick or thin layers of oxide and in this way the logical Form a connection or separation point at the intersection of the storage matrix. However, a plurality of metallization and / or diffusion layers are provided.

In the above exemplary embodiment, the node capacitance of the field effect transistor circuits was used as the storage element. However, the invention is not limited to this embodiment, Instead of the node capacitance and instead of the field effect transistors, equivalent switching elements can also be used to achieve the necessary predetermined time delay.

The invention can advantageously be implemented in a microprogram memory be realized. Successive word lines are read out one after the other by the automatic sequence control and thus the microprogram can be processed in the machine. For each word line, as described above, dynamic, logic circuits for feeding a signal to the next word line after each memory cycle intended. These inverter circuits for automatic sequence control are arranged directly in the integration area of the memory matrix, which results in a high level of reliability results and the wiring can be reduced.

When using the read-only memory as a microprogram memory the memory matrix is divided into several sub-areas, each of which corresponds to a microprogram routine and all of them have an automatic sequence control. To initiate such a subroutine, only one signal from the first is required Word line are fed to the routine. Since each word line entails a delay of one memory cycle and

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is connected to the next word line, a separate timing or addressing device is unnecessary. after the Subroutine is initiated with the supply of a signal to the first word line of the routine, it is automatically continued, where unconditional and conditional branches are also carried out automatically. To achieve a branch becomes an output of the output gate circuit of a word line connected to an input of the input gate circuit of the word line, to which the branch is to be carried out.

To achieve a conditional branch, an AND gate is used, which sends the branch signal to the input gate circuit the word line to be branched to only under a certain condition. With the device described it can also be achieved that both the microinstruction following a microinstruction is read out as also the instruction to which the branch was made. After this, both the word lines of the original routine and also the word lines of the routine to which the branch was made, read out at the same time. The branching routine can be used as a modification routine in order to change the Modify microinstructions of the original routine.

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Claims (17)

P AT CLAIMS QJ Read- only memory with a memory matrix, the binary-coded memory content of which is predetermined by logical connections or logical separating points at the crossing points of rows and columns, word lines running in the row direction serving to query memory words of the memory contents and the bits of each memory word read out during a memory cycle as output signals of the bit lines running in the column direction can be removed in parallel, characterized in that word lines (e.g. 105) belonging to a sequence of content-related memory words are connected to one another in series via dynamic switching means (e.g. 31, 33) which have a delay time of one Have memory cycle and that an automatic sequence control is achieved. 2. Memory according to claim 1, characterized in that each word line with at least one switching element is equipped. 3. Memory according to claim 2, characterized in that each word line (105) with an input switching element (31) and an output switching element (33) is equipped. 4. Memory according to claim 1, with column switching elements (21, 23, 25, ... 29) which have an output, the one Embodied bit position, and which have at least one input that comes from a logical connection (11, 12, 14, ...) with a word line (107, 167, ...), characterized by switching elements for preparation (17) and reading out (16) of the memory locations, which have a delay time of less than one memory cycle exhibit. KI 972 O3O 409838/0702 5. Memory according to claim 1, characterized in that the memory matrix and the switching means are implemented using integrated semiconductor technology. 6. Memory according to claim 5, characterized in that the delay time by memory elements (e.g. 22) and a clock pulse train (jrfl - # 4) is obtained. 7. Memory according to claim 6, characterized in that each memory element embodied by a capacitance (22) whose charging and / or discharging can be controlled by means of field effect transistors (e.g. 1, 5). 8. Memory according to claim 7, characterized in that the input switching elements (31) and the output switching elements (33) each have an unconditional precharge field effect transistor (1, 5) for charging the storage element (22), that the discharge of the storage elements via each in Series with the unconditional precharge transistor connected further field effect transistors (2, 3, 4, 6, 7) takes place and that a 4-phase memory clock control is provided, the first clock (jdl) the precharge transistor of the input switching element, the third clock (03) the precharge transistor of the Output switching element and its second and fourth clock (φ2, φΑ) controls the conditional discharge. 9. Memory according to claim 8, characterized in that logic input switching elements for the conditional discharge (2, 3) are provided. 10. Memory according to claim 8, characterized in that the dynamic switching means (16, 17) of the column switching elements from the third phase (# 3, 17) to charging the column line and from the fourth phase (f54, 16) KI 9 72 030 409838/0702 can be controlled for the conditional discharge of the column line. 11. Memory according to claim 3, characterized in that to achieve a program branch an output switching element (33) both with the next line (149) as well as with a further line (150, 57) 12. Memory according to claim 3, characterized in that to achieve a program branch the output of a column line (21) with an input switching element (61) is connected, in order to achieve a logical link on this input switching element (61) another logical control input (D) is provided and that in the crossing points of the column in the Lines a logical connection (12, 14) is provided, from which a branch is possible. 13. Memory according to claim 12, characterized in that the memory lines in groups of consecutive Microprogram steps are divided, each group corresponding to a subroutine. 14. Memory according to claim 8, characterized in that the word lines (e.g. 105) of the memory are applied to a semiconductor substrate and the input switching elements (e.g. 31) at one end and the output switching elements (e.g. 33) are attached to the other end of the word line. 15. Memory according to claim 7, characterized in that the capacity (22) is wholly or partly by the node capacity is formed. 16. Memory according to claim 12, characterized in that 409838/0702 the column switching elements (21) as inverting switching elements are executed and connected to the lines (107, 167) via positive logical OR connections (12, 14) are. 17. Memory according to claim 12, characterized in that the input switching element (61) as negative, inverting AND gate is designed, which is provided with an inhibitor input (D). KI 972 030 409838/0702