DE2362854A1 - Radio receiver with digital frequency display - oscillations of AM or FM oscillator are counted during certain time interval - Google Patents

Abstract

The electronic counter is used for amplitude or frequency modulated oscillations, differing from the received oscillation by the number of intermediate frequency oscillations. The counting is done periodically and in order to subtract the intermediate frequency, the counter is at the beginning of counting delayed by a time corresponding to the respective intermediate frequency. An additional counter counts the number of oscillations corresponding to the intermediate frequency and when this number is reached, it starts the new counting cycle by the main electronic counter. During the additional counter operation it may have its period extended, to correspond to the intermediate frequency time duration.

Description

Licentia Patent-Verwaltungs-GmbH 6 6 Frankfurt / Main 70, Theodor-Stern-Kai 1

Hanover, December 17th, 1973 PT-TÖ / gn H 73/99.

Circuit arrangement for digital 'frequency display in a radio device -

It is "known" for radio sets (Radio-Mentor 1973, p 389-390 and Funk-Technik-1971, pages 157-159), a digital one ! Frequency display to be provided. This has opposite dej? usual Display on a scale by means of a pointer has the advantage of greater accuracy of the display of the received frequencies and thus the better selection of desired stations. It has been shown that the initially obvious solution, the received Counting frequencies directly is disadvantageous because on the one hand the antenna voltages are too low and on the other hand through a disturbance of the York trip, which has only a low selectivity, by neighboring transmitters a falsification of the counting can occur. The well-known principle of the digital frequency display is therefore the vibrations of the AM or FM oscillator according to the received waveband counting with electronic counters. The oscillations of the AM or FM oscillator are counted periodically each for a certain period of time. For example, every 20 ms for a period of 10 ms, the oscillations of the oscillators are counted.

Since the received frequencies are to be displayed, is a

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Correction by the amount of the IF is necessary because the oscillator frequency and input frequency are around. the IF differ, whereby the oscillator frequency is usually higher. A known way of correcting is to start counting not at zero, but at a vert below full, which ^{: is set} as the complement of the respective IF. The counter, which, appropriately preprogrammed, begins to count at the Vert zero minus ZF, has reached Hull after counting the ZF and then counts the true value of the received frequency.

The current technology of electronic digital counters is characterized by an increasing degree of integration. Counters with a higher degree of integration, e.g. counting levels, memories and decoders are cheaper than counters with a lower degree of integration. However, they have the disadvantage that they are not pre-programmable and therefore not suitable for the correction mentioned above.

The invention gives another way of correcting the counted Oscillator oscillations, which also enables the use of counters with a higher degree of integration.

The invention is based on a circuit arrangement for digital frequency display in a radio device, in which the oscillations of the AM or FM oscillator, which differ by the number of oscillations of the respective IF from the number of received oscillations, periodically within a certain period of time are counted by means of an electronic counter and in which, to subtract the ZF, the start of the counting process of the electronic counter is increased by a time corresponding to the respective ZF, so that only the number of oscillations of the AM, reduced by the respective ZF, of the electronic counter or FM oscillator is counted and is that an additional counter

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is provided, the one corresponding to the respective ZP Number of vibrations counted in advance and "when the ZF is reached corresponding counter reading triggers a new counting process of the electronic counter starting at zero.

In the event that the oscillator frequency is lower than the receiving frequency and instead of the above-mentioned subtraction . An addition is required, the invention consists in that an additional counter is provided which is at the end of the mentioned time span counts a number of vibrations corresponding to the respective ZF and the time span counts by one corresponding to the ZF Time is extended, so that the entire period of time ends only after the additional counter has one of the ZF corresponding Has count and the count is increased by the amount of the ZF.

Advantageous further developments of the invention are set out in the subclaims described.

The invention is explained in more detail below with reference to the drawing. FIG. 1 shows a basic circuit diagram of the invention. FIG. 2 shows part of the additional counter 3 shows a further basic circuit diagram

At the terminal, 1 in FIG. 1, there are rectangular oscillations 12 available, the frequency of which corresponds to the frequency of the respective oscillator, e.g. the AM oscillator (not shown) is the same. In the prescaler 4- there is a division of the number of oscillations in a ratio of 10: 1, for example. The prescaler consists of four flip-flops. As is well known, one changes Flip-flop on the positive or negative edge of an input pulse its initial state from logic 0 to 1 or from logical 1 to 0, thus halving the number of oscillations and with it the frequency. When several are connected in series

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Flip-flops can be ^{generated 1/2} I-, 1/8, 1/16 etc. of the input frequency. A decimal divider can be obtained from 4 flip-flops when connected appropriately.

To the prescaler 4, a gate closes ^at 5>, which is driven by a time base 7 in such a manner that the door 5 is opened at regular intervals, only during a certain period of time and lets the rectangular oscillations happen. This period of time is called the gate time and is, for example, one hundredth of a second. The time base 7 contains a quartz oscillator as the time standard.

According to the invention, an additional counter 8 is provided, which is also controlled by the time base 7. The vibrations passing through the gate 5 during the gate time reach the counter 6 and the additional counter 8, both of which begin to count. If the count of the additional counter 8 corresponds to the ZF, it sends a start pulse ₍ to the counter 6, which is set to zero and now counts the number of oscillations until the end of the gate time actual counting process of the counter 6 is delayed by a time corresponding to the respective ZF, as can be seen in the timing diagram in Fig. 1. From the beginning txj of the gate time to the time t ~, the ZF is counted in advance, while the counter 6 in the time t ^ until the end of the gate time t ^ counts the oscillations falling in this period starting at 0. The counter 6 therefore only counts the actual reception frequency instead of the oscillator frequency which is higher by the IF, which is optically displayed in a known manner (not shown) After the end of the gate time, the two counters 6 and 8 are again prepared for a new pulse count by means of pulses from the time base 7. The last of the count The 6 result displayed remains displayed until the next one is available.

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Since the IF is different in AM and FM operation, the additional counter 8 can be switched accordingly. The additional counter is activated via terminal 3 depending on the Operating mode (AM or FM) of the radio device, not shown, controlled in such a way that the correct IF is pre-counted will.

Fig. 2 shows a section of the additional counter 8. This consists of several counting levels, one of which is the counting level

10 for the n-fce and the counting stage 11 for the (n + 1) -th digit are shown. Each counting stage 10, 11 consists e.g. of four flip-flops connected to form a decimal divider and has four outputs A, B, C, D.. The counter stages 10,

The number of oscillations counted 11 is present at their outputs A, B, C, D in binary code (BGD numbers in 8-4--2-1 code). The logic states at the four outputs A to D are, for example, with a counter reading O: A = 0, B = O ₁ C = O, D = O, with 1: A = 1, B = O, C = O, D = O, ie 2: A = O, B = 1, C = O, D = O etc. The additional counter can also be constructed as a binary counter.

There is also a NAMD gate 9 with four inputs and one output. As is known, a pulse (logic 0) occurs at the output of the NAND gate 9 . if there is a logical 1 at all four inputs. Three of the inputs are connected to the outputs B and C of the counter stage 10 and to the output C of the counter stage 11. These outputs are selected in such a way that they have a logical 1 with a counter reading corresponding to the IF in AM mode. The input of the NAND gate 9, which is still missing, is also supplied with a logic 1 by the voltage UM which characterizes the AM operation and which is permanently present during the AM operation. The described connection ensures that at the output of the NAND gate :; 9 at a counter reading of the additional counter 8 corresponding to the IF, a pulse occurs. This is the start impulse for counter 6,

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whose counting process is thereby initiated anew. the Circuit can be made accordingly with the same mode of operation also set up for FM operation or switch over accordingly.

When the oscillator frequency, the IF is lower than the receiving frequency is, in Fig. 3 by means of the additional counter 8, the gate time of the gate 5 by one of the IF corresponding Extended time, so that also in this case the payer 6 the true value of the receiving frequency counts. Gate 5 will Opened via line 13 and blocked via line 15. At the end of t ^ of the original gate time, the additional Counter 8 via line 14 a start pulse and begins to count. If the counter 8 has the one corresponding to the ZF When the counter reading is reached, the gate 5 is closed by a pulse at the time t ^ via the line 15.

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Claims (4)

23628b4 - 7 - H 73/99 Claims '1 ./Circuit arrangement for digital frequency display in a radio, "in which the oscillations of the AM or FM oscillator, which differ by the number of oscillations of the respective IF from the number of received oscillations, periodically within a certain period of time by means of of an electronic counter and in which, to subtract the ZF, the start of the counting process of the electronic counter is delayed by a time corresponding to the respective ZF, so that only the number of oscillations of the AM or the respective ZF reduced by the electronic counter. FM oscillator is counted, characterized in that an additional counter (8) is provided which pre-counts a number of oscillations corresponding to the respective IF and, when the count corresponding to the IF is reached, triggers a new counting process of the electronic counter (6) starting at zero (Fig . 1). 2. Circuit arrangement for digital frequency display in a radio device, in which the oscillations of the AM or FM oscillator, which differ by the number of oscillations of the respective IF from the number of received oscillations, periodically within a certain period of time by means of an electronic counter are counted, the number of oscillator oscillations being less than the number of received oscillations, characterized in that an additional counter (8) is provided, which at the end of the period mentioned counts a number of oscillations corresponding to the respective IF and the time period by one of the IF corresponding time is extended, so that the entire period of time ends only after the additional counter (8) has a counter status corresponding to the ZF (Fig. J) and the counting result has been increased by the amount of the ZF. . 509825/062 1 23628S4 - 8 - η 73/99 3. A circuit arrangement according to claim 1, gekennz characterized eichnet that gates are provided (9) or matrices of diodes or transistors, the inputs so to outputs (A, B, C, D) of counter stages (10, 11) of the additional counter (8) and are connected to a voltage (U ,, other electronic counter (6) is started (Fig. 2). 4. A circuit arrangement according to claim 1 or 2 and 3, dad urch in that the additional counter (8) counting a plurality of intermediate frequencies is used for d-as and can be switched by gate circuits at the output. BATH ORIGINAL 509825/0621 Empty soap