DE2361637A1 - ANALOG / DIGITAL OR DIGITAL / ANALOG CONVERTER - Google Patents

Description

L M Ericsson Pty. Ltd., Broadmeadows, Victoria, Australia Analog / digital or digital / analog converter

The invention relates to an analog / digital or digital / analog converter for converting between a digital bit stream and an amplitude variant analog signal such as speech into each other.

A well-known form of conversion is delta modulation, in which the analog signal is converted into a one-bit-coded bit stream and transmitted as this, in which in a equally spaced blanking intervals bit pulses are available ("one" bit> or are not present ("zero" bit). In such a system it is known

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use companding to determine the range of input levels encodable by the system for a given blanking frequency to increase so that a desired transmission quality can be maintained. The companding can be achieved by detecting a sequence of "ones" and "zeros" in the bit stream and providing a feedback signal in response to that. The feedback signal is compared with the analog signal, and depending on it, whether the feedback signal is smaller or larger than that Is an analog signal, a "one" or a "zero" is transmitted.

In a conventional delta compander, a predetermined Sequence of "ones" or "zeros" is detected and causes a positive current pulse device to have a capacity for the duration of a clock period charges when the determination is present. The linear build-up of the voltage across the capacitance causes a «proportional increase or decrease in voltage in the exchange signal, which is compared with the analog input will. The capacitance is discharged through a resistor and the decay speed depends on the time constant the circuit.

There are a number of problems inherent in the above conventional system. For example, the step size of the tension build-up in terms of capacitance, a compromise between a large step that allows the feedback voltage to act quickly on the analog input signal, which, however, causes large excess amounts for low analog signals, and a small one Stage that allows acceptable operation for low level analog signals, but which results in a slow rate of action for high level signals. Therefore, conventional companders cannot achieve optimal results for high and low signal levels.

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It is therefore an object of the invention to provide an improved converter to convert between a digital bit stream and an analog signal from one to the other, in which the above disadvantages can be avoided.

This task is performed by an analog / digital or digital / Analog converter solved in which a feedback signal is compared with the analog input signal or for reconstruction of the analog signal is used, which is characterized in that the feedback signal is dependent on the digital bits in the bit stream output from or input to the converter that the converter is a companding loop with a device for determining the presence of a special bit sequence in the bit stream and means for generating a compand signal for modulating the feedback signal, that the Korn pandsignal with a non-linear characteristic the feedback signal in a first sense by one Amount changes, which is large when the frequency of occurrence of this bit sequence is high, and by a small amount, if the frequency of occurrence of this bit sequence is low, and in an opposite sense if this' Follow by an amount that is large when the compand signal is high and by a small amount when the compand signal is high is low.

Further features and usefulnesses of the invention emerge from the description of exemplary embodiments on the basis of FIG Characters. From the figures show:

Figure 1 is a block diagram of a delta encoder for conversion an analog signal into a digital bit stream;

2 shows a block diagram of a delta encoder for converting a digital bit stream into an analog signal;

3 shows a circuit of an antilogarithmic converter and a current pulse amplitude modulator of the embodiment according to FIGS. 1 and 2;

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4 shows a circuit of a compand current pulse unit of the embodiment according to FIGS. 1 and 2;

Fig. 5 shows a uniform analog input signal on the Encoder according to Fig. 1 and the generated digital bit stream and the feedback signal from the encoder from the non-linear companding according to the invention and the feedback signal from one linear companding in a known encoder; and

6 shows a representation similar to that in FIG. 5, to illustrate the improved tracking properties of the non-linear companding versus the known linear companding in the case in which the Analog input signal suddenly changes from high to low level.

The encoder shown in FIG. 1 has a comparator 20 with two inputs 21 and 22. An analog input signal at the input 21 is compared with a feedback at input 22, and the comparator provides an output signal in the form of a high or a digital "one" when the analog signal exceeds the feedback signal, and a low Output signal or a digital "zero" if the feedback signal exceeds the analog signal. The comparator is clocked at 64 kHz and its output 23 supplies a digital bit stream of "ones" and "zeros" depending on the values at the analog input and the feedback signal relative to each other.

The output 23 of the comparator 20 is connected to the input of a four-bit shift register 24. The output 25 of the shift register is the digital bit stream which is given on the line. Since the data at output 25 are the same as the data are delayed at input 23 and only by four clock periods,

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it is evident that the line connection is also on Input 23 of the shift register 24 could be made. The 64 kHz clock signal for the device is on connection 25 to the shift register 24 is provided.

Each stage of the shift register 24 is connected to a compand logic unit 27. The compand logic unit 27 has a number of gate circuits and determines the occurrence of four "ones" or four "zeros" in the shift register 24. The output of the compand logic unit 27 is connected to a current pulse unit 28. During the period in which the compand logic unit 27 detects four "ones" or four "zeros" in the shift register _{g it} oscillates the current pulse unit 28 and activates it so that it supplies a constant current of positive polarity at its output 29 over time in which it activates isto During the period "in which the Kompand logic unit 27 does not four" ones "or four" zeros "states in the shift register 24, the current ■ generates pulse unit at its output 29 a constant negative current. In this embodiment, the positive current provides an increase in current (attack, current) which causes the Rückkopplungssxgnal increases toward in its value to the analog signal, and the negative current supplies the Aussehwingstroia which reduces the Rückkopplungssxgnal, when the feedback signal exceeds the analog signal _t as it is described below. The positive current from the current pulse unit 28 is on the order of one hundred times the negative current in this embodiment, but can also be trimmed to a different ratio. During the period "in which the constant current device is activated" the positive output current of the same charges a compand integration capacitor 30 and causes a linear build-up of the voltage across the capacitance. The value of the capacitance 30 and the positive current are selected so that during a Clock period (15.6 / us) the voltage built up on the capacitance is about 1Q0my each time four "ones"

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or four "zeros" occur. As stated above, the Value of the current can be trimmed and in this way the built-up voltage can be changed. During a clock period When the constant current device 28 supplies negative current to the capacitance 30, the capacitance is discharged and the voltage drop at the capacitance 30 is about 1mV.

The voltage parallel to the capacitance 30 is fed to an initial converter 31. The anti-logarithmic converter 31 is arranged such that the signal at its output 32 is an anti-logarithmic current function of the input voltage according to equation (3). Therefore, for lower voltages across the capacitance 30, a voltage change causes a smaller change in the output current from the antilogarithm converter 31, while for higher voltages parallel to the capacitance 30, the same voltage increase produces a significantly larger change in current. It is obvious that when four "ones" or four "zeros" occur frequently in the shift register 24, the voltage across the capacitance 30 is high, that is to say the co-pand voltage becomes high.

The output 32 of the antilogarithm! See converter is with a Current pulse amplitude modulator 33 connected. The modulator 33 provides an output current which is proportional to the voltage signal from the anti-logarithmic converter 31 = the current from the modulator 33 is fed to an integration network 34, which converts the current signal into a voltage signal which is fed back to the comparator 20 to the terminal 22. The voltage at terminal 22 is the feedback voltage that follows the analog input signal. As already explained above, the output signal of the comparator s -20 depends on whether the analog signal is greater or less than the 'feedback signal = In addition to the signal from the antilogarithm! Scheu converter 32 e & |) the modulator 33 e captures a digital signal via its connecting line 35 from the first stage of the shift register 24 "

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The supply of the digital signal to the modulator 33 is a polarity connection which determines the polarity of the step change in the feedback signal to the comparator. If, for example, a “zero” occurs on the connecting line 35 immediately after the occurrence of a "one", then the polarity of the step change in the feedback signal is reversed, because the feedback signal exceeds the analog input signal ο For a "flat" analog input signal at the comparator, the bit stream to the shift register 24 would alternate Would have "ones" and "zeros" and the polarity of the step change would be reversed for each successive clock period.

The associated decoder is shown in FIG. 2, and it has essentially the same structure as the encoder described above, with the exception that the comparator 20 is eliminated and a filter 36 is added. The transmitted digital bit stream enters the shift register 24 at an input 25, and each bit is clocked successively into the shift register »The rest of the device is identical to the encoder down to the integration network 34 the feedback ^{signal to ok 1} connection 22 of the encoder and is therefore a signal which approximates the original analog input signal strongly approximated »

Reference is now made to FIG. 3, which is a combined Circuit from the antilogarithmic converter 31 and the Current pulse amplitude anodulator 33 shows “The voltage in parallel to the capacitance 30 ^ hereinafter referred to as V_, is the antilogarithmic converter 31 is supplied to terminal 29 and passed through a resistor 38 to the base of a transistor 39 » The base of the transistor 39 is through a resistor 40 with the

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Base of another transistor 41 connected. The two resistors 38 and 40 form a voltage divider network. The transistor 39 is supplied with a constant collector current I_

CL

a feedback network having an amplifier 42 and a resistor 43 is applied. The current I comes from a positive one Mains voltage 44, which in this case is + 5V, and is dependent on the value of a series resistor 45. The basis of transistor 41 is connected to a negative mains voltage 46, in this case -5V.

The operation of the anti-logarithmic converter relies on the collector current (I) - base-emitter voltage (V _ßE ) characteristic of a transistor, which is characterized by the following equation (1):

q v

¹ C ^{= x} a ^ex P * "" W ^C1) '

q = the electron charge (coulomb)

K = the Boltzmann constant

T = the absolute temperature ( ⁰ K).

The equation shows the logar itic transmission behavior. The emitter voltage of the transistor 41 is controlled by the low impedance of the temperature-compensated emitter of transistor 39, i.e. the emitter voltages of the two transistors are controlled by V in the ratio

BE R _{38 +} R ₄₀ C

where R._ is the ohmic value of resistor 40 and R _{38 is} the ohmic value of resistor 38.

Since I of transistor 41 is shown as 1 _R from current pulse amplitude modulator 33, holds

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^R 4O * ^U (3).

R _{38 +} R ₄₀

The current I "is switched by the current pulse amplitude modulator 33 with respect to the polarity. If the voltage at the polarity connection 35 to the modulator 33 is greater than a reference voltage 47 at the base of the transistor 48, then a further transistor 49 is switched on and a current I _n flows from the integration network 34 (FIGS. 1 and 2) to the Collector of transistor 49. If the voltage at polarity connection 35 is less than reference voltage 47, transistor 49 is blocked and there: transistor 48 is conductive. The current I _R flows in this way from the associated transistors 50 and 51, which are connected as current reflectors, and a current I _R flows from the collector of the transistor 51 to the integration network 34 via line 52.

Reference is now made to FIG. 4, which shows a circuit of the compand current pulse unit 28. This unit is similar to the modulator 33 and consists essentially of four transistors 53, 54, 55 and 56, which are interconnected in the manner shown. A constant current source Ia is connected to 62. The connection 57 leads to the antilogarithmic converter 31 and a capacitance 30, while the line 58 is a connection from the compand logic unit 27 to the base of the transistor 54 via a resistor 59. If the voltage at connection 58 (hereinafter referred to as the compand control) is greater than the reference voltage 47, the transistor 54 is conductive and a current I flows from the capacitance 30 to the collector of the transistor 54. If the voltage at the compand control is lower than the reference voltage 47, then the transistor 53 is conductive and the transistor 54 is blocked. The voltage across the resistor 60 V_ is equal to the product I = Rf where R is the ohmic value of the resistor 60. Another resistor 61 connected to the emitter of transistor 56 has a value of dR, where d should be 100 in this case. the

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Voltage across dR is ungeSir equal to I _a R / and therefore a current of approximately I ^ / d flows from the collector of transistor 56 into capacitance 30. By adjusting the value of resistor 61, ie by changing d, the ratio becomes the rise step size and the decay step size varies.

The operation of the A / D converter in FIG. 1 can be explained on the basis of a sinusoidal input signal for the comparator 20 will. Initially, when the sine wave rises, there is no feedback signal and the first bit from the comparator is a digital one. The "one" is fed to shift register 24 and blanked into the first slot. The digital "One" in the first slot is transmitted to modulator 33 through polarity connection 35. The modulator 33 generates a signal to be fed back to the comparator 20, and the step size of this feedback signal is very small and depends on the value of the background noise, which is before the sinE-shaped Input signal enters the system. During the next clock period, the feedback voltage is still far below the analog signal, and so another "one" is fed to the shift register and the original "one" becomes in pushed the next slot. The polarity connection 35 provides the modulator 33 with an output signal in the same way as before, and another feedback signal of the same step size as before is added to the previous signal and fed back to the comparator. Operation continues in this manner and the feedback signal grows approximately linearly until four "ones" appear in the shift register 24. When showing four "ones" the logical unit controls the current pulse unit on, so that a constant current is passed into the capacitance 3O, so as to increase the step size of the feedback signal added signal «The feedback signal affects the analog value to a greater extent than before. However, the signal through the anti-logarithmic converter 31 has been at a low level so far, and therefore lies

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the output of the antilogarithmic converter is lower than its input. The feedback signal is even smaller than the analog signal, and another "one" bit is supplied from the comparator 20 to the shift register 24 during the next clock period. The logic circuit again detects four "ones" in the shift register and controls the constant current device in order to further increase the step size of the signal fed to the feedback signal h . However, the input signal to the anti-logarithmic converter 31 quickly reaches such a value that its output value exceeds the input value. Therefore, the rate at which the feedback signal affects the analog signal is increased rapidly and the feedback signal soon exceeds the analog signal. To the first clock after the feedback signal HAT exceeded the analog signal, the comparator 20 provides a "zero" to the .- shift register 24 ', the logical unit 27 performs not four consecutive identical bits, and therefore no output is present for the current pulse unit 28 .. The current pulse unit 28 therefore supplies a -ve polarity current, which begins to charge the capacitance 30 and reduces the voltage V to the antilogarithmic converter 31 »The polarity connection 35 is now at" zero ", so that the step change of the feedback signal from the previous value is subtracted. The value of the step is smaller than for the previous clock period because of the lower charge on the capacity 30 »

The feedback signal continues to exceed the analog signal in opposite directions, but a smaller amount each time, until the minimum step size is reached and exceeding it assumes a minimum.

FIG. 5 shows a uniform audio frequency burst signal 64 which fed to the digital encoder of the embodiment shown

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to generate a digital bit stream 67 to be transmitted on a line. Superimposed on the audio frequency burst signal is the feedback signal 66, which results from the non-linear companding of the embodiment, and a feedback signal 65, which results from a linear companding of a known type. The feedback signals are also the signals which would be reconstructed in the respective decoders according to the invention or according to the Sband of the art, although a suitable filter would ensure that the reconstructed signal approximates the analog input signal more closely. The main difference between linear and non-linear companding is that a system with linear companding can only change the step size of the feedback signal or reconstructed signal by a fixed amount upon receipt of a signal by increasing the step size zvl , while non-linear companding with a antilogarithmic converter changes the step size by a fraction of the old step size. In other words, for linear companding, the new step size is equal to the previous step size + a constant Cc) and for nonlinear companding the new step size is equal to the previous step size + the previous step size times a constant (k).

In this way, nonlinear companding affects that Audio frequency burst signal in the. by line 66, while linear companding takes longer. to do the same To achieve step size, as shown at 65 ', make the constant ic) large enough to allow the linear companion system changed at the same time as the non-linear system, then the linear system will operate at lower Entrance levels completely unstable.

Fig. 6 is similar to the illustration in Fig. _5f , but shows the operation of a non-linear companding, as it is often used according to the invention, and a known "linear companding for an analogue input signal, aessSffsfctivspanaung (SMS) kon-

is / its changes in the curve over a single however, iöriode are larger. The one indicated by curve 65 linear companding makes the step size roughly proportional to the average slope (line time average) one, and so the step size is not big enough to accommodate the high Slope ranges of the signal with low disturbances or deviations are to be followed. A system with the fast nonlinear companding according to the above embodiment can change the step size within the signal period and therefore let it increase in order to follow high current gradients, and decelerate to follow low instantaneous slopes, i.e. the companding adjusts its step size so that it follows the current slope and can follow the analog signal shown. "'

From the above it can be seen that the invention has a considerable scope Represents improvement. The use of a current pulse unit 28, which can produce rise and decay waves, can reduce the step size faster if exceed one takes place. In addition, the use of a antilogarithmic converter 31 or another suitable Apparatus reducing the step size for low level signals and increasing it quickly for one sudden increase in the analog signal level? so that yourself result in significantly better tracking properties. ·

According to a modification of the embodiment described above the companding can be oriented in such a way that it is less than four data bits determined by changing the view! from Bits in the shift register 24 and corresponding to the compand logic unit 27. The antilogarithmic converter can also have a resistance device, which a number of linear functions of different slopes, which the continuous antilogarithmic function of the above embodiment

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can approximate, generate. The voltage levels and frequencies can of course also be used for special applications of the device be adjusted. The embodiment described above is particularly applicable to a dial-up digital automatic telephone system (PABX system) applicable »

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Claims (12)

Claims 1. Analog / digital or digital / analog converter, in which a feedback signal is compared with the analog input signal or used to reconstruct the analog signal, characterized in that the feedback signal is dependent on the digital bits in the bit stream output from or input to the converter that the converter comprises a companding loop with means (27) for determining the presence of a special bit sequence in the bit stream and means (28 , 30, 31, 33, 34) for generating a compand signal for modulating the feedback signal, that the Compand signal with a non-linear characteristic changes the feedback signal in a first sense by an amount which is large when the frequency of occurrence of this bit sequence is high and by a small amount when the frequency of occurrence of this bit sequence is low and in an opposite direction Does it make sense if this sequence is not proven by an amount _? which one is big? when the compand signal is high, and by a small amount ,? when the compand signal is low. 2 ο analog / digital or digital / analog converter according to claim 1, characterized in that the non-linear characteristic a continuous characteristic is » 3 ο analog / digital or digital / analog converter according to claim 1 or 2, characterized in that the non-linear characteristic is achieved by an anti-logarithmic converter (31) which forms part of the device for generating a compand signal, the compand signal being the output signal of the anti-logarithmic converter (31) and is an anti-logarithmic function of the input signal fed to it represents » 4098 24/1038 4. analog / digital or di ^ tal / analog converter according to claim 3, characterized in that the device for generating of a compand signal has a current pulse unit which a constant current for changing the voltage across a capacitance (30) in a first sense when a special one is detected Sequence of bits and a constant current to change the voltage on the capacitance (30) in the opposite sense in the absence this sequence supplies, the voltage on the capacitance (30) a linearly increasing or decreasing signal which supplies the input of the antilogarithmic converter (31) is supplied. 5. Analog / digital or digital / analog converter according to claim 4, characterized in that the constant current when the sequence is detected is about a hundred times greater than the constant current when this sequence is not detected. 6. analog / digital or digital / analog converter according to claim 4 or 5, characterized in that the output signal of the antilogarithmic converter (31) is a current signal _ff which is fed to a current pulse amplitude modulator (33) which determines whether this output signal is added to or subtracted from the feedback signal of the previous clock period, the modulator (33) receiving the last bit of the special sequence for making this decision » 7 »analog / digital or digital / analog converter according to claim 6, characterized _s that the anti-log converter (31) comprises a pair / emitter circuit connected transistors (39, 41) together, comprising that the emitter of a transistor is temperature compensated and the The voltage across the capacitance is applied to the emitter of the other transistor, the collector current of the other transistor providing the output signal which is an antilogarithmic function of the voltage across the capacitance. 409824/1038 8. analog / digital or pigital / analog converter according to one of claims 4, 5, 6 or 7, characterized in that the Current pulse unit a constant current source and a first Transistor network, which acts as a two-way switch and in response to the aforementioned position in a position in which the constant current source derives current from the capacitance, switched is, and that the first transistor network is switched to another position without the detection, in which a transistor network with two transistors is caused to supply a current to the capacitance which is smaller than the current drawn from the capacity, and is dependent of the ratio of a pair of resistors> each of which with the emitter of one of the transistors of the second transistor network connected is. 9. Analog / digital or digital / analog coaverter ■■ after a of claims 6, 7 or 8, characterized in that the Output of the modulator (33) is connected to an integration network (34), which the modulator output signal from converts a current signal into a voltage signal and which causes the voltage signal to match the feedback signal the previous Taktperlo.de depending on the case at hand added or subtracted from this » 10. Analog / digital converter according to any one of the preceding claims, characterized in that the feedback signal is fed to a comparator (20) _f which compares the Rückführuhgssignal with the to be converted analog signal and a digital "one" generated when the feedback signal is smaller than the Is analog signal, and a digital "zero" is generated when the feedback signal exceeds the analog signal during a particular clock period. 11 »Digital / analog converter according to one of the preceding Claims, characterized in that the feedback signal a filter is fed, which sudden level changes 9824/1038 levels in the feedback signal to produce a signal which closely approximates the original analog signal. 12. Analog / digital or digital / analog converter after one of claims 2 to 11, characterized in that the predetermined Number of consecutive identical bits, which / are detected by a shift register (25) / in the digital bit stream is four and that a logic unit (27) is provided which generates an output signal when four is "one" or four "Zeros" occur in the shift register (25). 409 8 2 4/1038