DE2357651C3 - Circuit arrangement for the formation of a delayed pulse of a defined duration - Google Patents

Description

a) that a capacitor (C) can be charged from the input signal (E) via a series resistor (R _e ) ,

b) that two limit indicators (1, 2) with different response thresholds (Sl, SX ) monitor the capacitor voltage (U _c),

c) that a gate (3) forms the pulse (A) by conjunctive linking the input signal (E) with the output signal (a1) of the first limit indicator (1) and with the inverse output signal (52) of the second limit indicator (2).

output signal of the first limit value reporting and the inverse output signal ¹ · ^ι « ™ ή ** η Γτγρπτ. value indicator forms.

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The invention relates to a circuit arrangement for forming a pulse from a binary input signal that occurs after a predetermined delay time and a defined pulse duration having.

Such delayed pulses with a defined pulse duration are particularly automatic Control and monitoring systems are required. To a known such impulse formation become two timing elements with different running times for the delay time and the pulse duration which are triggered by the input signal and their output signals in a gate to the desired Impulse can be linked. In this known solution, for each of the two timing elements a separate capacitor is required to determine the running time.

The invention is based on the object of a circuit arrangement of the type mentioned for generating pulses to create that can be implemented as easily as possible in integrated technology and that is as simple as possible requires a small number of connections and only a single capacitor.

The circuit arrangement according to the invention is characterized in that

a) that a capacitor can be charged from the input signal via a series resistor,

b) that two limit indicators with different response thresholds control the capacitor voltage monitor,

c) that a gate generates the pulse by conjunctive linking the input signal with the off-on Embodiment of the invention is shown in the drawing and will be described in more detail below described. It shows

Fig. 1 is a circuit diagram of an inventive Circuit arrangement,

F i g. 2 shows the time course of some signals in the circuit according to FIG. 1.

The circuit arrangement according to the invention contains the two limit indicators 1 and 2 for monitoring the capacitor voltage U _{c of} the capacitor C. The limit indicator 1 has the lower response threshold 51 and the limit indicator 2 the higher response threshold S1 .

If a binary input signal £ (Fig. 2a) is applied to the input terminal 5, the capacitor C is charged via the series resistor R _e according to an exponential function. The course of the capacitor voltage U _c is shown in FIG. 2b. As soon as the capacitor voltage U _c exceeds the response threshold S1 of the limit indicator 1, it generates the output signal A1 (FIG. 2c). If the capacitor voltage U _c exceeds the response threshold 52 of the limit value indicator 2, the latter emits the output signal a 2 (FIG. 2d), which is converted in the inverter 4 into the inverse signal a1 (FIG. 2e). The output signal a I of the limit value indicator 1, the inverse output signal al of the limit value indicator 2 and the input signal E are fed to the gate 3 on the input side. After the delay time t _x, the desired pulse A with the pulse duration t ₂ (FIG. 2 f) appears at the output 7 of the gate 3.

The delay time f i is thus predetermined by the time in which the capacitor C charges up to the response threshold 51 of the level indicator 1. The pulse duration t ₂ is defined by the time in which the capacitor C charges from the response threshold S1 of the limit value indicator 1 to the response threshold S 2 of the limit value indicator 2. When the two response thresholds S 2 and 51 are passed through again after the input signal E has ended , no further pulse can occur, since at this point in time the input signal E has already disappeared and therefore the AND condition of the gate 3 is no longer met.

The particular advantage of the circuit arrangement according to the invention is to be seen in the fact that only a single capacitor C is required, which is implemented as an external capacitor in a circuit implemented using integrated technology. The circuit according to the invention only requires the three circuit connections 5, 6 and 7, which enables the use of a correspondingly small housing.

1 sheet of drawings

Claims (1)

Claim: Circuit arrangement for the formation of a pulse from a binary input signal, which according to a predetermined delay time occurs and has a defined pulse duration, thereby marked,