DE2346931B2 - TRANSISTOR CIRCUIT WITH HYSTERESIS PROPERTIES - Google Patents

Description

The invention relates to a circuit arrangement having a first and a second transistor, from each of which has a control electrode and a first and a second additional electrode, wherein forms a conductive path between the first and second electrodes when connected to the control electrode a control voltage exceeding a predetermined value is applied, having an input terminal and an output terminal, with a first resistor between the input terminal and the Control electrode of the first transistor, with a second resistor, which is the first additional Electrode of the first transistor connects to one terminal of a voltage source, with one Connection between the first additional electrode of the first transistor and the output terminal with a connection between the second additional electrode of the first transistor and the other terminal of the voltage source, and with one Connection between the second additional electrode of the second transistor and the other terminal the voltage source.

Such a circuit arrangement is known (IBM Techn-Disc. Bull. 14, No. 12, 5/1972, p.3746). In the known circuit arrangement, the first additional electrode of the first transistor is directly connected The control electrode of the second transistor is connected. Furthermore, the control electrode of the first transistor is connected connected directly to the first additional electrode of the second transistor. The known circuit arrangement has the disadvantage that the levels of the output voltage and the input voltage in are in a fixed, unchangeable relationship.

It is also a circuit arrangement of the kind described type known (US-PS 37 37 657), in which the first additional electrode of the first transistor is connected to the control electrode of the second transistor via a third resistor and in which the control electrode of the first transistor with the first additional electrode of the second transistor is connected via a fourth resistor. Instead of a single input port this circuit is provided with a large number of input connections. Any of these input ports is connected to the first additional electrode of the second transistor via a resistor (whereas the input terminal of the circuit arrangement according to the type described above via a resistor connected to the control electrode of the first transistor). In addition, the first is additional electrode of the second transistor via a further resistor with one at a negative potential lying connection connected. Furthermore, in addition, the control electrode of the first transistor has a another resistor with a terminal at a positive potential and via a diode with connected to the second additional electrode of the first transistor. The known circuit arrangement is supposed to function in such a way that the first transistor becomes conductive when input signals at a certain combination of the input terminals occur and that the second transistor lasts the first transistor as long keeps conducting until all input signals from the input terminals have been removed.

Finally, a circuit arrangement of the type described above is known (magazine "Electronics", Vol. 40, 1967, pp. 95 and 96), in which the first additional electrode of the first transistor via a RC parallel combination and one with this in Series-connected third transistor is connected to the control electrode of the second transistor. Further is the control electrode of the first transistor via another RC parallel combination and one with this Series-connected fourth transistor connected to the first additional electrode of the second transistor. In addition, the control electrode of the second transistor has a further resistor is connected to a terminal at a negative potential. Finally, the first is additional The second transistor is connected to one terminal via a further resistor connected to the voltage source. The known circuit arrangement works as a symmetrical flip-flop circuit. However, it has the disadvantage that the

Trigger signal must be around zero potential and that a negative reset voltage is required with amplitudes equal to the amplitude of the input trigger level. For the operation of the known circuit _{arrangement, a sinusoidal voltage with an} average value of 0 volts is provided, which is entered into the circuit arrangement via a potentiometer. The negative half cycle is required to reset the flip-flop circuit.

The invention is based on the object of providing a circuit arrangement of the type described above designed so that the input level and the output level are set independently of each other can and that this is possible with the smallest possible number of circuit elements. Further the circuit arrangement should only be able to be triggered and reset with a voltage, which has only one polarity with respect to ground.

The object is achieved according to the invention in that the circuit arrangement is used as further switching elements only contains a third resistor and a fourth resistor, the third resistor the first additional electrode of the first transistor with the control electrode of the second transistor connects and wherein the fourth resistor connects the control electrode of the first transistor to the first additional electrode of the second transistor connects.

In the above circuit arrangement according to the invention, the absence of any reactive elements makes the circuit particularly suitable for being formed as an integrated circuit on a single semiconductor die. The direct or low resistance connections of the second or emitter electrodes of both transistors to ground also enable the circuit to be operated reliably by an input signal of a relatively low level. The circuit arrangement described is also particularly advantageous because the difference between the input signal threshold voltage levels which result in the hysteresis property can be designed independently of the range of change in the output signal voltage, and also because the range of change in the output signal voltage is almost as large as the voltage of the supply current source can be done.

The above features, configurations and advantages of the invention emerge from the following detailed description of an embodiment in connection with the drawings; in it shows

F i g. 1 is a circuit diagram of a Schmitt trigger circuit with hysteresis properties according to the prior art Technology,

F i g. 2 is a circuit diagram of a transistor circuit having a hysteresis property according to an embodiment of the present invention,

F i g. 3 is a graph of an input signal increasing linearly with time and then decreases linearly and the state of a transistor in the circuit according to the invention in different Shows times during this input signal,

F i g. Figure 4 is a graph showing the input signal ratio of Figure 4. 3 to the output signal from the circuit according to the present invention, also showing its hysteresis property is and

F i tz. 5 is a block diagram of a color television

receiver, in which the transistor circuit according to F i g. 2 is used as a color killer circuit.

Before describing the transistor circuit having a hysteresis property according to the present invention and in order to better understand the problems overcome by the present invention, reference will first be made to FIG. 1, which shows a typical Schmitt trigger circuit of the type which is widely used in the prior art when a hysteresis property is required. In the Schmitt trigger circuit shown, an input or switching signal £, ", which is received from an input terminal 1, is applied to the base electrode of an input transistor Q ₁ , the collector electrode of which is connected through a resistor R ₁ to a terminal 3, which has a supply voltage + V _cc receives from a side (not shown) of a power supply source. The other side of the supply current source, which can be at ground or reference potential, is connected through a common emitter resistor R ₂ to the emitter electrode of the transistor Q ₁ and also to the emitter electrode of an output transistor Q ₂ . The collector electrode of transistor Q ₁ is connected through a parallel circuit of a speed-up capacitor C ₁ and a level shift and coupling resistor R ₃ to the base electrode of the transistor Q _2, while the base electrode of the last transistor through a resistor R _4. is connected to ground which forms part of a base bias circuit for transistor Q ₂ . The collector electrode of the transistor Q ₂ is connected through a load resistor R ₅ to the supply current voltage terminal 3, from which an output signal E _{011 is} derived.

In the working state of the circuit described above according to FIG. 1, when the voltage of the input signal E _{1n is} below a predetermined first threshold level or threshold value, which is described below, transistor Q ₁ is non-conductive or is in its off state, while transistor Q _{2 is} conductive or in its on state is located. When the transistors Q ₁ and Q _{2 are} in their off and on states, respectively, the base voltage V _{b2 of} the transistor Q _{2 is} approximated by the equation

V ^ = r ^ ~. V " (D

determines where r _{1, r 3} and r _{4 are} the resistance values of the resistors R _1, R ₃ and R _4, respectively. are.

When the transistors Q ₁ and O _{2 are} in their switched-off and switched-on states, respectively, the voltage of the output signal E ₀₁₁₁ , which is derived from the output terminal 2, is determined by the following equation:

_ y

(H)

where r ₂ and r _{5 are} the resistance values of the resistors R ₂ t> ^zw - ^ 5, while F ₁ ^ _{2 is} the base-emitter voltage of the transistor Q ₂ .

When the transistor Q _{2 is} in an on state, the voltage across the

'm ^

= Ki -

(111)

r, + 's + r.

When transistor Q _{1 is} turned on, transistor Q _{2 is} turned off, the base voltage V ' _h2 of transistor Q ₂ then being determined as follows:

(V)

where Z _{1 is} the current flowing through resistors R ₃ and R ₄ to earth.

It can also be seen that when transistor Q _{2 is} in its off state and transistor Q _{1 is} in its on state, the situation is as follows:

V «= (r ₃ + r ₄ ) I ₁ + r, (I ₁ + / _c ). (Vl)

where I _{c is} the collector current of transistor Q ₁ .

Equation (VI) can be rewritten as follows:

If equation (VII) is substituted for I ₁ in equation (V), equation (V) becomes as follows:

Vl, =

V ^ -r _x tJ _c

r, + r ₃ + r ₄

(VIII)

As soon as the transistor Q _{1 is} in its switched-on state, it remains in this state until the voltage V _bl applied to the base electrode of the transistor Q _{1 by the input signal E 1n is} reduced to or below a second threshold voltage V _{lh2, which} can be written as follows:

V _hl = s

= V ' _h2 - V _b

η, ύ v, _h2 = --f ^ r-

(IX)

When the transistor Q _{1 is} in its on state and the transistor Q _{2 is} in its off

gang J, where the emitter electrodes of transistors Q ₁ and Q _{2 are} connected to resistor R ₂ , equal to V _h2 - V _hi . ₂ (where K _{61-2 is} the base-emitter voltage of transistor Q ₂ ). Thus, the transistor Q _{1 is switched} from its switched-off state to its switched-on state only when the voltage K ₆₁ , which is applied to its base electrode by the input signal £, "is _{at least equal to a first threshold voltage K 161} , which is determined as follows will:

switched state is, the voltage at the output terminal 2 is determined only by the supply current voltage V _cc , ie

'' ill "cc ■

(Xl)

where V _{bcl is} the base-emitter voltage of transistor Q ₁ .

Since it can be assumed that K _61. , And K _{61-2 are} equal and in view of equation (I) above, equation (III) can be rewritten as follows:

(IV)

When comparing equation (IV) and (X) above, it can be seen that the first threshold voltage K _{161 of} the input signal at which transistor Q _{1 is switched} from its off state to its on state and transistor Q _{2 is switched} from its on state to its switched off state is switched by the amount

_, '- ■ * '. greater than the second threshold span, + c ₃ + c ₄

voltage K _{162 of} the input signal, in which the transistor Q _{1 is returned} from its on-state to its off-state, while the transistor Q _{2 is returned} from its off-state to its on-state. Thus, the circuit of FIG. 1 has a hysteresis property according to the prior art. A comparison of equations (II) and (Xl) above shows that the output voltage at terminal 2 is smaller when transistor Q _{2 is} in its on state than when this transistor is in its off state.

In the case of the above with reference to Fig.! described, known circuit, however, the operating voltage level of the input signal E _{in must be} relatively high, due to the relatively large voltage drop from the common emitter resistor R ₂ . It can also be seen from equations (IV) and (X) that the first and second threshold voltages K ₁₆₁ and K ₁₆₂ are dependent on the values r _{1 , r 3} and r _{4 of} the resistors R 1, R ₃ and R _{4, where} from equations (II) and (XI) it can be seen that the difference or range of the change in the output circuit of the circuit for the switched-on or switched-off state of the transistor Q _{2 is} also partly dependent on _{the resistance values T 1} , r ₃ and r ₄ . Thus, the difference between the threshold voltages K ₁₆₁ and K ₁₆₂ cannot be designed independently of the range of change in the output signal voltage. If the working level of the input signal voltage does not have to be excessive and if a sufficiently large difference between the threshold voltages K, _M and K _{162 has to be} provided in order to obtain a suitable hysteresis property, only a relatively narrow or small change in the output signal voltage E. ₀₁₁ . It has been found that with a supply voltage V _cc of 12 vol · the maximum range of variation of the out put signal voltage about 2 or 3 volts, E _om that is, in the equation PCI) is 12 volts, while E _011, ir the equation (II) is about 9 or 10 volts. The ver relatively large voltage drop across the common emitter resistor R ₂ is another reason for the described narrow range of change de: output signal voltage, which is derived from the known circuit, such a narrow or small range of change in the output signal voltage the areas of application of the known Restricts circuitry or creates circuit design problems in certain uses thereof.

Referring now to FIG. 2 shows this figure

that the circuit according to the invention, as shown there, comprises a first and a second transistor Q ₃ and Q ₄ , each of which has a control or base electrode and a first and second electrode, such as, for. B. collector or emitter electrodes, as shown. The input signal £ "is applied to an input terminal 1 which is connected to the base electrode of the transistor Q ₃ through a resistor R". The first or collector electrode of transistor Q ₃ is connected through a load _{resistor R 8} to a terminal 3 which _{receives a supply voltage + Vcc} from one side of a supply current source (not shown). The other side of the supply current source, which can be at ground or reference potential, is directly connected to the second or emitter electrodes of the two transistors Q ₃ and Q ₄ . The first or collector electrode of the transistor Q ₃ is also connected to an output terminal 2, from which the output signal E _{OM is} derived, whereby it is also connected to the control or base electrode of the transistor Q _4, preferably through a resistor R ₉ . which is selected to control the range of change in the output signal E _om , as described below, and which can be omitted in theory. The control or base electrode of transistor Q ₃ is finally connected through a resistor R ₇ to the first or collector electrode of the transistor Q. ₃

In the working state of the above with reference to FIG. _{2 described circuit according to the} invention, when the voltage of the input signal E jn is below a predetermined first threshold level V, _hl , as described below, the transistor Q _{3 is} non-conductive or is in its off state, while the transistor Q _{4 is} conductive or is in its on state. The first threshold level V _{lhi of} the input signal E _in . in which the transistor Q _{3 is} switched or switched from its switched-off state to its switched-on state. is approximately determined by the following equation:

Voltage of the input signal £, „. Accordingly, the transistor Q ₃ remains in its switched-on state, while the transistor Q ₄ remains in its switched-off state until the voltage of the input signal £, "has dropped to a second threshold voltage level V _lh2. which is approximately determined by the following equation:

r "+ r ₇

Vu.

τ * _

(XII)

where r _b and r _{7 are} the resistance values of resistors R ₆ and R ₇ , respectively, and V _{hc3 is} the base-emitter voltage of transistor Q ₃ .

When the voltage of the input signal E _1n rises to the first threshold level V, _hl or above, the transistor Q _{3 is} switched on to create a conductive path between its collector and emitter electrodes, while the transistor Q _{4 is} switched off. Since there is only a very small voltage drop in the conductive path between the collector and emitter electrodes of the transistor Q ₃ , the voltage of the output signal £ "" is approximately determined by the following equation:

* -Oui -

S 0.

(XlII)

where V _{cci is} the collector-emitter voltage of transistor Q ₃ .

When the transistor Q _{3 is} in its on state and the transistor Q _{4 is} in its off state, the base voltage of the transistor Q _{3 is} approximately equal to = K

at ■

(XlV)

When the voltage of the input signal £, " drops to the second threshold voltage level V _lh2 or below, the transistor Q _{3 is switched} to its switched-off state and the transistor Q _{4 is switched} to its switched-on state, ie. the circuit is returned to its original state, the voltage of the output signal E _{0111 being} determined by one or the other of the following equations (XV and (XVl):

a) If the resistor R _{y has} a final resistance value other than zero, then

E "u, = -ζ-ΊΓΓ- ^ίν " - ^V "^ · ^{(XV |}

where r ₈ and r _{9 are} the resistance _{values of the resistors R 8} and R ₉ and V _{hc4, respectively,} the base-emitter span of the transistor Q ₄ or

b) if the resistance value r _{g of} the resistance R _{v is} zero. ie if the resistor R ₉ is omitted from the circuit. so

E ₀ U, = V _h , _A. (XVI)

A comparison of equations (XII) and XIV) shows that the circuit according to the invention has a hysteresis property, ie. that the first threshold voltage level V _lhl, in which the transistor Q is switched from its off to its on state _3, the value TJR ₁ ■ V _hc3 greater than the second threshold voltage level V, _h2 of the input signal, wherein the transistor Q ₁ from its switched-on state is switched back to its switched-off state. As shown in FIG. 3 can be seen if the voltage of the input signal E _jn . which is applied to the circuit according to the invention. increases linearly during the period i ₀ to r ₂ , as shown at A , and then decreases linearly during the period f ₂ to r ₄ , as shown at B , the transistor Q _{3 is} in its off state in the Time periods t ₀ to i, and r ₃ to f ₄ and in its switched-on state ir the time period f to r ₃ . In particular, during the period r ₀ to f, the voltage of the input signal E, "is below the first threshold voltage level K _{IM of} the equation (XII), so that the transistor Q _{3 is} in its switched-off state. In the time i, this is achieved Input signal the first threshold voltage level V _M , accordingly the transistor Q _{3 is switched} to its on state. The transistor Q then remains in its switched-on state, while the voltage of the input signal increases in the period r to t ₂ and then decreases in the period t ₂ to / _3, the voltage in the last-mentioned period

of the input signal is still above the second threshold voltage V, _{h2 of} the equation (XIV). In the time r ₃ , the voltage of the input signal i falls to the second threshold voltage level. so that the

9 ίο

Transistor Q ₃ , then into its off state R ₈ 10 ^ j;)

is switched, in which he during the time R ₉ 200 U

span / ₃ to / _{4 of} the further decreasing input V _n . 12 ν

signal voltage remains.

If the voltage of the input signal £, "again - 5 Referring now to FIG. 5 cements this figure. fetches is increased and decreased linearly, such as the transistor circuit according to the invention as at A and B in FIG. 3, the point of the output color killer signal generator circuit 24 forms a hysteresis loop or curve in the case of a color path signal voltage E _{1n, relative to the input signal television receiver, voltage E 1n, as shown in FIG.} 4, the designation I ₀ J ₁ J ₁ J ₃ and r ₄ , 0 antenna 11 and an antenna tuning device 12 corresponding to the similarly designated times in FIG. From Fig. 4 it can be seen that the external antenna 11 is received, and for converting the output signal voltage the value ^r "(V -Y ') HF signals into IF signals, which are

'« ^{+ R} » "stronger 13. A video detector

during the time span r ₀ to r, and t ₃ to r ₄ and the 15 circuit 14 is provided for television signals

Has value zero during the period r to / _3. If see from the output of the IF amplifier ? U cr-

the resistor R ₉ is omitted from the circuit, the luminance and color difference

or has a resistance value of zero, self-components of these television signal mixtures have passed

understandably the output voltage during a luminance channel 15 or a color difference

Time periods t ₀ to r, and f ₃ to r ₄ the value V _bc4 , as in 20 amplifiers are selected or amplified

of the above equation (XVl). A deflection and synchronization circuit * 17 separates

It should be noted here that in the case of the invention, synchronous signals from the Siunakemischen from which

according to the transistor circuit, as shown in FIG. 2, are selected by the video detector U, and

the above-described disadvantages of the circuit that generates line or horizontal and vertical deflection

Fig. 1 according to the state of the art, 25 signals that are connected to terminals X and y of a color

derK as follows: cathode ray tube 27 are fed. The scarf

Since the emitter electrodes of the transistors ß ₃ and device 17 also generates row torsionals, which one

C _{4 are} connected directly to earth, the working color sync signal separation switch 18 can be

level of the input signal voltage ^ "relative to that to control the gate control of the ktzteren ^.

ⁿ ^ * ^se _t '"· · .-., · uj, ³ ° ^{through which} color sync signal of chrominance

Since the difference between the first and second signals are separated from the circuit 18

_{Swell voltage levels In} V lhl and V _{lh2 of} the input from the color diflerence or chrominance amplification MO

output signal ^ are received by the resistor values and r. A color sync over-

of the resistor K "or R ₁ and the base-emitter oscillator circuit 19 sets the from the color synchronous

Voltage of the transistors used is determined 35 signal separating circuit 18 received intermittent

becomes like from the equations (XII) and P (IV) earth the color sync signals in continuous color

Sichtl.ch, and since the area of the change in the synchronous signals, gives way to a carrier wave oscillator

Output signal voltage E ₀₁₁₁ fed through the resistor 20 to the one TräperwpHe with its

values K ₈ and V _{9 of} the resistances R _s and R _{9 of} the freaks? vnnT «mh carrier shaft with your

Feed current voltage V _n and the base-emitter spa " ₄₀ F eSueiz with Hen ν f ™" ^ ^ ^eIch ^ " ^Phas f ^and

Determination of the transistors used is S uSerSe T ¹ " ¹ ΐ"

as can be seen from equations (XIII) and (XV)! overshoot circuit 19 are locked

can the difference between the threshold span- Die knnHnmei-iiVi, »., cuu 1 a _r

voltage levels K and Y ', _h2 independent of the V öb ^ SSX ^ Ä ^ TuT ^ F ^

Tu'stleoi Sn ^erUng ^ ™ ^ ™ ^ ™haben ^ 45 Synchronous detector circuit 21 supplied to the soft

The best of the change in Ausaanussi.nal- ch'SaieeS! if ", ^{continliierlic} i ^e "

voltage, ie the difference ^ chen ^ e ^^ values t ^ S ^^ S

the output signal voltage, as from the DC amplifiers % -y f-, J

genes (XIII) and (XV) can also be ₅₀ glSvSSrteiS ^Γ Η ΤΪ ^ ϊΐ Ζ

moderately large and almost equal to the value of the food S _ne , kS 1 λ J / ^lsEingan f ^SI g " ^{al £} - ^der

Voltage V _n can be made by the widet schfu It Ξ ί " ^erfi " ^du ng ^ measure transistor

stand value r _{9 of} the resistance R ₉ according to aus- aebeSltu ^ Sl? hTn t "" ¹ !, ΐ ^F f ^bkllIcrsi ? ^nal ; is selected "f feCDerscnaitung 24 is formed. The output signal

The transistor circuit according to the invention is furthermore ₅₅ Sbei3ί "ΐ" p ^ ST ^^ T ^ im

advantageous in that it consists of a minimal number CnromnSver,. ^ ιί ^F "bkillersignal K dem

consists of components, ie only two ™ JSS I ¹⁶ J ^ leads to the latter

Transistors and a maximum of four cons- oTr · eSSrW oJZ 7 ' ⁸ ° Λ ^Β ^ ^monochroma ' ^IS , ^che

stands including the resistance R ₉ . Since the will if Γ I ⁸ * ¹ * ^ J ^{TV pictures received} "

The circuit does not contain any reactive elements, it is 60 SleT ⁰ ^ ⁰ ™ " ¹ ^ TV signals through

Sonders to be suitable for forming as an integrated circuit sianaS overall dim Λ-Ι ™ """""''" / W "GNAIE from the amplifier 22 below the threshold

In a specific practical example of a SÄÄ ' ¹ ™ «24, as shown below,

circuit according to the invention have their components πΙρΑ ,,! » ⁸ described,

th, the film ends values: ^P _6s "° A ^{le us} g ^a" gssignale be from the amplifier 22

65 also an automatic chrominance control circuit

K ₆ 4 3 _kü ~ supplied, soft the gain value of the chrome

R ₁ . 3 9 _k o minance amplifier 16 according to the level of the

Output signals from the amplifier 22 controls. A

Farbsynchiondcmodulator 25 demodulates Farbdiffcrenzsignale of chrominance signals, which are supplied by the Chrominanzverstiirkcr 16, by means of the carrier signal from the oscillator 20, which Farbdiffercnzsignalc and Leuchtdichtesignalc be combined out of the channel 15 in a matrix circuit 26 to produce Farbkomponentensignalc R, G and B which are supplied to the respective cathodes of the color cathode ray tube 27.

The one from the common transistor circuit Existing color killer signaling circuit 24 may be implemented as an integrated circuit on a semiconductor board or a substrate or carrier are formed, which also other circuits, such as. B. the Chrominan / amplifier circuit 16, oscillator circuit 20, color sync detector circuit 21. Amplifier circuit 22 and the chininance control circuit 23 and the like.

In the case of the color television receiver described, the color killer signal generator according to the invention works 24 as follows:

If the level of the input signal voltage £ _in , which is supplied to terminal 1 of the sound line 24 and which corresponds to the level of the color sync signals that are separated from the received television signals, is high enough to switch on the transistor Q ₃ , the output signal or color killer signal K has a low level. This low level output signal from the circuit 24 makes the chrominance .erstärker 16 effective, so that color images through the color cathode ray tube 27 are displayed. On the other hand, when the level of the input signal voltage E, "supplied to the circuit 24 to turn off the transistor Q ₃ , the output signal K from the circuit 24 has a high voltage level, whereby the chrominance amplifier is ineffective, so that monochromatic images through the Cathode ray tube 27 can be reproduced.

Due to the hysteresis property described above the circuit which forms the color killer signal generator circuit 24 corresponds to the level of

ίο color sync signals, in which the reproduced images change from monochromatic images to color images, the first threshold voltage level V _lhl and is by the value r ₆ / r ₇ V _{t (} , higher than the level of the color synchronous signals, in which the reproduced images are made from color images change into monochromatic images, which corresponds to the second threshold voltage level V _lh2 . The hysteresis property of the color killer signal generator circuit 24 thus ensures that a stable color killer mode of operation is realized, that is, that the switching or the transition from the reproduction of color images to monochromatic images by small changes or fluctuations the level of the burst signals is not caused.

Although an embodiment of the present invention and a desirable application area of the same with reference to the drawings were described in detail above, is the inventor Of course, this does not apply to this specific embodiment and application area, with various modifications and other uses by the person skilled in the art in within the scope of protection of the attached patent claims can be selected.

For this purpose 2 sheets of drawings

Claims (3)

Patent claims: ! Circuit arrangement with a first and a second transistor, each of which has a control electrode and a first and a second additional electrode, wherein a conductive path is formed between the first and the second electrode when a predetermined value exceeding control ι to the control electrode ο voltage is applied, with an input terminal and an output terminal, with a first resistor between the input terminal and the control electrode of the first transistor, with a second resistor, which connects the first additional electrode of the first transistor to one terminal of a voltage source, with a connection between the first additional electrode of the first transistor and the output terminal, with a connection between the second additional electrode of the first transistor and the other terminal of the voltage source, and with a connection between the second additional electrode of the two th transistor and the other terminal of the voltage source, characterized in that the circuit arrangement contains only a third resistor (.R ₉ ) and a fourth resistor (R ₁ ) as further switching elements, the third resistor (R _q \ being the first additional electrode of the first transistor (Q ₃ ) connects to the control electrode of the second transistor (Q ₄ ) and wherein the fourth resistor [R ₁ ) connects the control electrode of the first transistor (Q ₃ ) to the first additional electrode of the second transistor (Q ₄ ). 2. Circuit arrangement according to claim 1, characterized in that the control electrode and said first and second additional electrodes of each transistor (Q ₃ and Q _4, respectively) are base-collector and emitter electrodes. 3. Circuit arrangement according to claim 1 or 2, characterized in that the first and the second transistor (Q ₃ or Q ₄ ) and all resistors (R ₆ , R ₁ , R ₉ and R ₉ ) as an integrated circuit on a single semiconductor wafer are formed.