DE2331484A1 - BRAKE CONTROL SYSTEM - Google Patents

Description

TEXAS INSTRUMENTS INCORPORATED
13500 North Central Expressway-Dallas, Texas, V.St.A.

Brake control system

The invention relates to an anti-skid brake control system and in particular to a brake control system that brings about a pumping or pulsating brake actuation and more advantageous! .se contains the following units; (1) a speed sensor; (2) a frequency converter; (3) a slip and ramp signal generator and comparison circuit; (4) a DC value detector and zero speed switching unit; (5) acceleration and deceleration differentiators; (6) Acceleration and Delay switching units with variable thresholds «v / ert; (7) an acceleration programmed oscillator circuit; (Θ) a pulse generator circuit with fixed Threshold and variable duty cycle; (9) a reset timing and reset circuit; (10) a Brake control logic circuit; (11) an error monitoring and display device.

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When the driver of a land vehicle has to brake his vehicle or when the road conditions are poor wants to bring to a stop, there is the possibility that the land vehicle is uncontrolled or controlled skidding, which prevents the driver from keeping his vehicle within the available space To bring the route to a safe stop. One factor that indicates an impending spin is among these Circumstances, the relative relationship between the vehicle wheel speed and the vehicle speed. From security experts and professional drivers have recognized that the stability of the vehicle can be achieved if those associated with the wheels of the vehicle Brakes can be actuated automatically, pumping or pulsing, in a predetermined manner, which is dynamic with the acceleration and deceleration values of a land vehicle is related.

More recently, several systems have been developed which work on the principle that the normal brake actuation initiated by the driver of the vehicle is more selective Way is prevented. One of these systems uses wheel speed sensors that generate AC signals that which are proportional to the wheel speed. The wheel speed signals are then processed in a control module, which generates a DC signal to energize an electromagnet in an actuator called the hydraulic Brake system to control the vehicle wheels. If a spin is imminent, a command signal from the causes Control module that the actuating electromagnet closes a vacuum passage in a diaphragm chamber. Through the Effect of the diaphragm and the effect of normal hydraulic pressure on the master cylinder of the braking system of the Land vehicle generated by the driver, the hydraulic pressure on the vehicle wheels is released, so that the

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Braking effect of the vehicle wheels is prevented. When the vehicle wheels come back as fast as the vehicle speed or a selected low speed, then the control module generates a signal to turn off the Actuator electromagnet. This will make the Line pressure in the vehicle braking system restored so that the brakes re-engage. What about this System is actually achieved, is a pumping or pulsating brake application, which for a controlled Braking in adverse driving conditions is often recommended.

The control module of the system mentioned contains a frequency converter for converting one for each wheel speed sensor frequency-variable signal into a proportional variable direct current signal. A summation of the Output signals from each of the frequency converters result in a total signal of the vehicle wheel speed signals. Appropriate Deceleration and acceleration value detectors respond to the output signal of a summing amplifier in such a way that that output signals are generated which the deceleration or acceleration values of the wheels of the land vehicle are proportional. A signal proportional to the output of the summing amplifier is applied to a vehicle speed ramp generator and transmitted to an input of an automatically adjustable switching unit. The vehicle speed ramp generator generates a transition function Ramp signal with an overall slope equal to the actual speed of the land vehicle when braking to a stop. The automatically adjustable switching unit receives as an input signal also a signal from the vehicle speed ramp generator and another input from a deceleration force detector, and it produces an output

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signal if the sum signal of the wheel speed signal, the speed ramp signal and the deceleration force signal reached a first threshold. The deceleration force detector generates an output signal, the one with the braking factors including the condition of the tires, the condition of the brakes and the condition the road surface is related. To generate a control signal for the electromagnet of the actuator, the output signals of the delay value detector, the acceleration value detector and the automatically adjustable switching unit in a certain Relate to each other. These three signals are the input signals of the brake controller, which is the last component of the control module.

Further details of the known anti-slip control system described can be found in patent application P 21 16 303.1.

Other brake control systems that work on the principle that they are initiated by the driver of the land vehicle Disabling normal brake actuation are described in US Pat. No. 3,578.

With the help of the invention, an anti-slip pulp control module is intended for processing wheel speed signals in an anti-slip brake control system. The one with the help the invention to be created brake control module in an anti-slip brake control system is a pumping or pulsating Generate brake actuation. Furthermore, the brake control module to be created should brake lock signals in a brake control system produce. The brake control module to be created with the aid of the invention is also intended to control brake control signals the brake system in an anti-slip brake control system. Also engaging and releasing the braking system of the

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Vehicle should be using the brake control system according to the invention can be controlled according to preselected braking conditions. The with the help of the invention too sbhaffende brake control module for processing vehicle speed and wheel speed signals in an anti-skid brake control system contains a frequency-voltage converter, a slip and ramp signal generator, a Value differentiation circuit with variable threshold value and a monostable frequency control circuit.

According to the invention, the brake control system includes a Frequency converter, padded incline and delay switch units with variable threshold value, an acceleration-programmed one Oscillator, a pulse generator with a fixed threshold value and variable duty cycle, Acceleration and deceleration differentiating circuits, a DC value detector and zero speed switching unit Git, a brake control logic circuit, a slip signal and ramp signal generator and comparison circuit, an error monitoring and error display unit and a reset time control and reset switch unit »

Embodiments of the invention are shown in the drawing. Owned in it

Figure 1 is a block diagram of an embodiment of a Control module for an anti-slip brake control system,

2 shows a block diagram of a further embodiment the invention,

Fig. 3 diagrams of signals produced by the various Structural units are generated in the block diagrams of Fig. 1 and Fig. 2,

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4a to 4D a circuit diagram of a solid-state construction executed control module to generate a pumping or pulsating braking effect in an anti-slip brake control system, with the individual figures on the numbered connecting lines at the edges are to be connected to each other,

5A shows an embodiment of a frequency-voltage converter, which can be used in the brake control module according to the invention,

5B shows a further embodiment of a frequency-voltage converter,

Fig.6 shows another embodiment of the one shown in Fig.1 Deceleration and acceleration differentiating circuits as well as the deceleration and acceleration switching units with variable threshold,

7 shows a more detailed circuit diagram of an embodiment the generator and comparison circuit for slip and Ramp signals,

8 shows a detailed representation of an embodiment of the Delay and bevel differentiation circuits and

9 shows an embodiment of the acceleration programmed Oscillator and the pulse generator with fixed threshold and variable duty cycle of Fig.1.

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In one embodiment of the brake control system to be described here, a speed sensor coupled to the wheels or the ₍ drive shaft of a land vehicle) generates alternating current signals with a frequency that changes according to the vehicle wheel speed (FIG. 3A). The signals A, which change with the frequency, are sent to a frequency converter which generates a direct current signal whose voltage value changes proportionally with the frequency of the alternating current signals generated by the speed sensor (Fig. 3B). and zero speed switching unit applied.

The slip and ramp signal generator and comparator _T circuit performs three main functions: (1) It modifies or offsets the variable wheel speed DC signal B applied to it by a predetermined amount referred to as the "slip" signal (Fig. 3C1); (2) under the control of slip signal C1, it generates a jolt signal (Fig. 3C) having a programmable constant current discharge rate; (3) It compares the ramp signal C with the variable wheel speed direct current signal B, and when the wheel speed drops below the discharge speed of the ramp signal, it generates a slip switch signal (Fig. 3D). The slip switching signal D is then fed to one of the inputs of a brake control logic circuit.

The DC voltage level detector and speed switch unit performs three main functions: (1) It generates two equal voltage signals (Fig.3G and 3H) if

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the frequency of the AC signal A is 0 or less than one with respect to the vehicle wheel speed preset value is; (2) it generates a zero speed switching signal (Fig.3l) if the variable direct current signal B reaches a selected direct current value; (3) it prevents one from attending Deceleration differentiating circuit and to an acceleration differentiating circuit Ripple components of the variable direct current signals B applied to it which often occur when the land vehicle is operated at low speed. The two DC signals are sent to the deceleration and acceleration differentiating circuits, respectively while the zero speed switching signal I is applied to the brake control logic circuit.

The delay differentiating circuit differentiates the direct current signal G applied to it, and it couples a delay differentiating signal (Fig. 30) to a Delay switching unit with a variable threshold value, which in turn generates a delay switching signal (Fig. 3K) generated when the deceleration value of the vehicle wheels exceeds a preset value. the Delay switching unit with variable threshold value generates an output signal with a switch-on threshold value, which differs from a switch-off threshold. This means that the delay switching unit switches on at a lower threshold value than it switches off, so that a desired rapid switch-off with respect to the deceleration value of the vehicle wheels is achieved. That from the delay switch unit The delay switching signal generated is then applied to the brake control logic circuit.

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The acceleration differentiating circuit is the same as the deceleration differentiating circuit except that it as a function of the acceleration value the vehicle wheels are working. This circuit differentiates the direct current signal H supplied to it, and it inserts first acceleration differentiation signal (Fig.3J) to an acceleration-programmed oscillator and a second Acceleration differentiating signal (Fig.3P) to an acceleration switching unit with a variable threshold.

The variable threshold acceleration switch unit is the same as the deceleration switch unit with the exception that it works as a function of the acceleration value of the vehicle wheels. This circuit also has a variable threshold value, so that the switch-on threshold value is lower than the switch-off threshold. The acceleration switching signal (Fig.3Q) is sent to the Bremsregelloglk circuit and applied to a reset timer and reset switch unit.

The acceleration-programmed oscillator generates J as a function of the acceleration differentiation signal an acceleration oscillator signal (Fig.3L), which is one of the acceleration value of the vehicle wheels having proportional frequency. This acceleration oscillator signal J is then sent to a pulse generator fixed threshold value and variable duty cycle applied.

The pulse generator with fixed threshold and variable duty cycle can be of a duty cycle from 0% up to a duty cycle of 100%

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programmed with respect to an output signal. This pulse generator generates a duty cycle switching signal (Fig.3M) which is applied to the brake control logic circuit.

The reset timer and switch unit receives Input signals from both the brake control logic circuit (Fig. 3T) and from the acceleration switching unit with variable threshold value (Fig. 3Q), and it begins at the end of the reset time period with a reset time cycle, what a reset switching signal (Fig.3V) for the optional application of the acceleration switching signal Q to the Brake control logic circuit generated.

Basically, the generator and comparison circuit generates the slip signal and the ramp signal a slip signal D, which is a switch-on signal for controlling the braking system of the land vehicle in a dynamic Ratio to that of the zero speed switching unit and the acceleration and deceleration switching units with variable threshold conditions. On the other hand, the braking system of the land vehicle is also controlled by the reset switching unit. In this way, the braking system of the land vehicle becomes dependent from the wheel speed acceleration values and controlled by the wheel speed values, i.e. switched on or off.

The brake control logic circuit generates in response to the presence of multiple input signals (i.e., the slip signal D, the zero speed signal I, the delay signal K, the duty cycle signal M, des Acceleration signal Q and the reset signal V) output signals (Fig. 3E, 3N, 3S and 3T), which are to be switched on

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or to turn off the braking system of the land vehicle to an output trä berschaltung be applied to Setting the generator and comparison circuit for the slip and ramp signals and for generating the slip signal P can be applied to the slip and ramp signal generator and to reset the slip control circuit can be applied to the reset timer and reset switch unit for the subsequent cycle of operation.

A variable ac output signal A generated by the speed sensor is also to a fault monitoring circuit created in the various states of the control circuit, the vehicle and the vehicle brakes be monitored, so as a result of a malfunction of the Control circuit either a visible or audible error display is generated, a fuse is blown or a switch is operated, or all of these effects are brought about. The visible or audible The display is intended to warn the driver of the land vehicle that there is a fault in the control circuit, while the through ' burning the fuse or pressing the switch should disconnect the supply energy from the control circuit, so that their destruction is prevented. The fault monitoring circuit can observe many selected properties inside or outside the control circuit. For example, it can have an overcurrent condition (fault protection I) monitor the control circuit and generate a visible or audible display for the driver, and disconnect the supply energy from the circuit, since this state means that the braking system of the land vehicle works so incorrectly that the control circuit module can be destroyed can also generate a visible or audible display when there is no supply energy on the control circuit module there is more (error protection II); in this

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In this case, there is no blown fuse and no switch actuation, since this state controls the control circuit module cannot destroy. Furthermore, the error monitoring circuit can be a visible or audible Display without disconnection of the supply energy from the control circuit module generated when the speed sensor line is open (error detection III), since this state is only indicates that the brake control module has an error that does not result in the module being destroyed Has. A visual or audible indication can also be generated by the fault monitoring circuit when the solenoid of the brake system is "open" (fault protection IV), but in this case too there is no burnout the fuse or disconnection of the supply energy brought about, since this state does not cause any destruction of the brake control module.

The fault monitoring circuit can also be visible and generate audible indications for the driver and disconnect the supply energy from the brake control module when they detects that there is a short circuit at the output so that the brake control module is protected from burning out will. Monitoring the vehicle brake light switch determines incorrect cycle conditions, such as when the driver is the vehicle brakes are not applied. Bad cycle signals can be accumulated for the duration of a given finite period of time after which both a display for the driver and a disconnection of supply energy take place, so that a malfunction of the brake control module is indicated and the module is protected from further destruction. It is also easily possible to have further error monitoring conditions in the brake control circuit described here to be provided.

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1 shows, in the form of a block diagram, the structural units of an embodiment of a control module in an anti-slip vehicle brake control system with a speed sensor 10 and a frequency converter 12. The speed sensor 10 is either to the wheels or to the drive shaft of a land vehicle, for example electromagnetically, optically or mechanically coupled; he creates a changeable alternation tr omsignaO. (Fig.3A), whose frequency changes the Wheel speed are proportional. That is to say, the frequency of the signal A applied to the frequency converter 12 the higher the wheel speed, the higher it is. The alternating current signals generated by the speed sensor 10 A are applied to the frequency converter 12, which converts them into a variable direct current signal (Fig. 3B) converts whose DC value is proportional to the vehicle wheel speed. The generated by the frequency converter 12 variable direct current signal B is sent to both the generator and comparison circuit 14 for slip and Ramp signals as well as applied to the DC value detector and zero speed switching unit 16.

The generator and comparison circuit 14 modifies or offsets the variable direct current signal B by a preselected value, and it generates a slip signal (Fig.3C1) as well as under the control of this Slip signal C1 is a ramp signal (FIG. 3C) with a dynamically programmable constant current discharge rate. The ramp signal C is then compared to the variable DC signal B; if the Vehicle wheel speed below unloading speed of the ramp signal C drops, then a slip switching signal (Fig. 3D) is generated. This slip switching signal D is then applied to one of the inputs of the brake control logic circuit 18.

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The DC value and zero speed switching unit 16 generates depending on the frequency converter 12, variable direct current signal B generated two output signals (Fig, 3G and Fig.3H), each of which is clamped to a preselected DC value of the applied input signal, these signals applied to the deceleration differentiating circuit 20 and to the acceleration differentiating circuit 22, respectively are. The main reason for noting the preselected DC values of signal B and for the Generation of the output signals G and H consists in the waviness properties that often occur when operating the land vehicle at low speeds of the applied signals from going to the deceleration and acceleration differentiators 20 and 22 respectively. The DC voltage value detector and Zero speed switching unit 16 generates a zero speed signal (Fig.31), and they applies this signal I to an input of the brake control logic circuit 18 to.

The delay differentiating circuit 20 differentiates the variable direct current signal G applied to it, and it generates a pulse-shaped output signal (Fig. 30), which is applied to the variable threshold delay switching unit 24. The acceleration differentiating circuit 22 differentiates the variable direct current signal H applied to it, and it generates a pulse-shaped output signal (Fig.3P), which at the variable threshold acceleration switching unit 26 is applied.

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The delay switching unit 24 has a variable threshold value, <fer an output switching signal (Fig. 3K) generated with a switch-on threshold that differs from a switch-off threshold. It has to be means that the delay switch unit 24 switches on at a lower threshold value than it switches off, so that the desired quick shutdown with respect to the deceleration value of the wheels of the land vehicle is achieved.

The pulse-shaped output signal K from the delay switching unit 24 is generated is present when the deceleration change speed of the vehicle wheels exceeds a preset value; this" ) Output signal K is at one of the inputs of the brake control logic circuit 18 and at the acceleration programmed Oscillator 28 applied.

The threshold variable acceleration switching unit 26 is the same as the deceleration switching unit 24 with variable threshold except for the fact that it is based on that of the acceleration differential circuit 22 generated pulse-shaped output signal P responds and generates a pulse-shaped output signal (Fig.3Q) that indicates the rate of change in the acceleration of the vehicle wheel speed. The switching unit is also with equipped with a variable threshold, so that switching on at a lower threshold than it is switched off. The pulse-shaped output signal Q the acceleration switching unit 26 is connected to one of the inputs of the brake control logic circuit 18 to the acceleration differentiating circuit 22 and applied to the reset timer and reset switch unit 30.

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The acceleration programmed oscillator 28 receives an input from the acceleration differentiating circuit 22 Analog signal (Fig. 3J) which programs the oscillator in such a way that it generates a sawtooth pulse output signal (Fig. 3L), whose frequency is proportional to the acceleration speed of the vehicle wheels. The sawtooth-shaped output signal L is applied to the fixed threshold, variable duty cycle pulse generator 32.

The pulse generator 32 with fixed threshold and variable Duty cycle can range from a duty cycle of Oyo up to a duty cycle of 100% of that generated output signal (Fig.3M) can be programmed. The output signal M of the pulse generator 32 is a the inputs of the brake control logic circuit 18 supplied.

The reset timer and reset switch unit 30 is from one of the output signals of the brake control logic circuit 18 (Fig.3T), and it begins at the end of the reset time period with a reset time cycle, which is a reset switching signal (Fig.3V) for controlling the selective application of the by the acceleration switching unit 26 (Fig.3Q) generated pulse-shaped output signal Q at one of the inputs of the brake control logic circuit 18 causes.

In addition to the pulse-shaped output T, the brake control logic circuit 18 also generates an output pulse (Fig. 3E) and it applies the pulse signal E to the output driver circuit 34, which in turn has two pulse-shaped output signals (Fig.3F and Fig.3W) generated. The pulse-shaped output signal F is to a (not shown) brake control element of the braking system of the land vehicle and applied to the fault monitoring circuit 36. The output signal W

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is to the brake control logic circuit 18 and to the fault monitoring circuit 36 created. The pulse-shaped output signal W applied to the brake control logic circuit 18 sets the logic circuit in the state for a subsequent brake control operating cycle.

The fault monitoring circuit 36 also receives the variable AC signal A from the speed sensor 10; it monitors the operation of the brake control module, and it generates signals that either control a display such as a lamp or a buzzer, or disconnect the supply energy from the module, ie that a fuse is blown and / or a switch is opened so that a visible or audible display of a fault is generated in the brake control module or in the brake system, and / or the supply energy is separated from the brake control module to prevent further destruction. The fault monitoring circuit 36 applies control signals to the fuse blow circuit 38 and / or to the lamp control circuit 40.

2 shows the structural units in the form of a block diagram another embodiment of a 'control module for a vehicle brake ^ ystem, which in many respects in particular in terms of function and mode of operation, the block diagram described with reference to FIG equals. The main differences between the circuit of FIG. 2 and that described in connection with FIG Circuits are shown in the areas surrounded by dashed lines; it's about the frequency converter 12, the generator and comparison circuit 14, the DC value detector and zero speed switching unit 16, the brake control logic switch

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tung 18 Rückstellzeitgeber- and reset switching unit 30, the error monitoring circuit 36, the fuse blow circuit 38 and the lamp drive circuit, the speed sensor 10, the delay differentiating circuit 20, the acceleration differentiating circuit 22, the delay unit 24, the acceleration switching unit 26, the output driver circuit 34 and the controller 42 operate functionally as , as has been indicated in detail in the description of FIG.

A frequency converter 12, which can be used in the brake control system to be described here, contains a square wave generator 44, a double differential circuit and an integration circuit 48. The square wave generator is responsive to the variable AC signal A and it generates a square wave signal A1. The square-wave signal A1 is coupled to the double differentiating circuit 46. in which it is differentiated to generate the doubly differentiated signal A2 which is proportional to the vehicle wheel speed. The integration circuit 48 receives the double integrated signal A2 and integrates this signal in such a way that variable direct current signals B and B1 are generated, the magnitudes of which are related to the vehicle wheel speed v / ground are applied to the generator and comparison circuit 14 for slip and ramp signals or to the direct current value detector and zero speed switching unit 16. Other frequency / voltage converters are described in connection with FIGS. 5A and 5B.

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The generator and comparison circuit 14 contains a slip signal generator 50, a ramp signal generator 52 and a comparison circuit 54. As a function of the speed-dependent, variable direct current signal B the German signal generator 50 modifies or offsets the variable direct current signal B by a preselected one Value, and it generates a slip signal C1. The slip signal C1 is applied to the Rarapensignalgenerator 52, in which the ramp signal C is generated, the one dynamic having programmable constant current discharge rate. Both the ramp signal C and that Variable direct current signal B v / ground is applied to the comparison circuit 54, in which they are compared with one another v / earth; when the wheel speed of the land vehicle falls below the unloading speed of the ramp signal C, will the slip switch £ ignal D generated. The slip switching signal D is fed to one of the inputs of the brake control logic circuit 18. A detailed description of a slip and ramp signal generator is contained in the following description of FIG.

According to FIG. 7, the slip signal generator 50 of FIG a slip signal dividing circuit 112B which operates in response to the variable direct current signal B that the Wheel speed represented. The slip signal dividing circuit 112B modifies or offsets the variable DC signal B by a preselected value. A hysteresis circuit 114b selectively becomes so operates to generate the slip signal C1. A slip signal logic 118b supplies the selective switching signal corresponding to the slip switching signal D and the ramp hold signal N to a differential amplifier 116b. The hysteresis circuit 114 is of a

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Reset signal! ^ Selectively switched, typically is supplied by a timing control circuit, the output signal of which has a sufficiently long brake release cycle as a result of a The output signal from the anti-slip module. Such a timing circuit is from the reset timer and reset switch unit 30 of Fig. 1 of the above Anti-slip brake control system formed.

The ramp signal generator 52 which shows the vehicle speed as opposed to the vehicle wheel speed indicative ramp signal C generated typically includes a memory device 122b, which is connected to a programmable Power generator 124b is coupled. The current generator 124b is operated with the aid of a ramp logic unit 126b optionally placed in suitable operating states. The ramp logic unit 126b operates in response to the Ramp hold signal N and a slow ramp switching signal S, combinations of these signals being the programmable Set the current generator to the appropriate state, typically generated by a slow ramp signal S operating state generated a relatively slow discharge speed of the slip signal C, which indicates a slow deceleration value of the vehicle speed. The ramp stop signal N is offset the current generator 124b to the zero current state in which the discharge of the signal C is prevented. In absence of signals A and N (or in their logical "Off" state) becomes the programmable current generator 124b is placed in its highest current sink condition, which has the relatively greatest discharge rate of the signal C allows, which indicates a relatively high deceleration of the vehicle speed.

The comparison circuit 54 typically includes one second differential amplifier 132b, which is responsive to the slip signal C

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responds and to a second hysteresis circuit 136b is coupled. The hysteresis circuit 136b operates as a function of the variable direct current signal B, which indicates the wheel speed ·, and as a function of the output signal D of the comparison circuit 54; it is switched by the above-mentioned reset signal IL. The output signal the hysteresis circuit 136b is typically proportional to the signal B, but has a DC offset so that the coupling of a more sensitive differential amplifier 132b is made possible. An output circuit 134b provides the slip switching signal D, the one Indicates the condition of the wheels at which the wheel speed is lower than the vehicle speed. It should be noted that the slip switch signal D to the slip signal logic 118b of the slip signal generator 50 and to the hysteresis circuit 136b is fed back so that a selective ^ voltage offset or hysteresis of the signal G is achieved.

The DC value detector and zero speed switching unit 16 includes a DC value detector and a zero speed switching unit 58. Dependent The direct current value detector 56 generates signals B and B1 from the speed-dependent variable direct current two variable direct current signals G and H; each of these signals is at a selected DC value of the applied input signals, and the signals G and H are sent to the delay differentiating circuit 20 or applied to the acceleration differentiating circuit 22. The DC voltage value detector basically prevents the creation of any V / ellness components the variable direct current signals B and B1 to the delay differentiating circuit 20 and

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to the acceleration differentiating circuit 22. In addition to the variable DC signals G and H the DC value detector 56 generates a DC value signal 11 to be sent to the zero speed switching unit 58 is created. The zero speed switching unit 58 in turn generates a zero speed switching signal I, which is applied to one of the inputs of the brake control logic circuit 18. A delay differentiator and an acceleration differentiating circuit are detailed in Fig. 8 shown.

8 shows the functional units of the acceleration and deceleration differentiating circuits in the form of a block diagram.

The acceleration differentiating circuit 22 includes a differentiating circuit 1t2c for selectively differentiating of the incoming signal H coupled to a positive slope detector 110e. This detector generates Output signals J and P when the signal H has a positive change value which corresponds to the extent of the Increase or acceleration of the variable direct current signal H represents. The signal J can preferably to any current receiving unit, for example can be applied to the acceleration-programmed oscillator 28 of the brake control system of FIG. That The output signal P is preferably sent to a voltage-sensitive signal to indicate an acceleration state of the vehicle wheels Circuit, for example, the acceleration switching unit 26 of the brake control system of Figure 1 coupled. The acceleration switching unit 26 supplies a first bias value V to the acceleration

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differentiating circuit 22 which selectively biases the positive slope detector 110c when the threshold value V _{1 is} reached. The threshold value V «. represents a first preselected acceleration value of the vehicle wheelsV

When the acceleration output signal P exceeds the threshold value V ^ reached, the acceleration switching unit 26 supplies the signal Q to the hysteresis circuit 114c, which the necessary Provides bias for detector 110c. That supplied by hysteresis circuit 114c to detector 110c Bias causes an increase in the rate of change of the output signal P, which on the other hand indicates that the threshold value V ^ has been reached. The value of the signal P is preferably increased so that it is improved, faster and more sensitive Output signal depending on the variable input signal H is achieved. The indication that a a predetermined acceleration value of the vehicle wheels has been reached is a critical consideration of the anti-slip brake control system of Fig. 1.

The delay differentiating circuit 20 includes a differentiating circuit 102c, the ε £ η a negative Inclination detector 100c is coupled, which in turn is connected to a hysteresis circuit 104c. A second signal G from DC value detector and zero speed switching unit 16 drives the Wheel speed of the vehicle; it is typically a variable DC signal. The differentiating circuit 102c selectively differentiates the incoming signal G, and it couples the differentiated Signal to the negative inclination detector 100c, which is sensitive to a negative rate of change, i.e. on

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the size of the decrease in the incoming signal G is responsive. If the incoming signal G has a negative rate of change, the detector 10oc provides an output signal 0 which is the mathematical differential of the incoming signal G and which represents a deceleration state of the vehicle wheels. Hysteresis circuit 104c is coupled to detector 100c and monitors delay signal 0 so that detector 100c is selectively biased when delay signal 0 reaches a second selected threshold value. The threshold variable delay switching unit 24 selectively provides the second selected threshold V ₂ , which serves as a threshold for the 0 signal. The threshold value Vp represents a preselected deceleration value of the wheels of the vehicle. After the occurrence of the condition that the deceleration signal 0 exceeds the threshold value V _? reached, the delay switching unit 24 delivers a switching signal K ^! to hysteresis circuit 104c which then selectively biases detector 100c to indicate that threshold V has been reached.

Upon receipt of the bias signal from the hysteresis circuit 104c, the negative slope detector 100c indicates that the threshold V has been exceeded, preferably by increasing the rate of change of the output signal 0, which typically clamps the signal 0 at a low V / er. The indication that the deceleration signal 0 has reached the threshold value V ₂ , which means that the deceleration of the wheels has reached a preselected deceleration value, is thus an essential aspect of the anti-skid brake control system shown in FIG.

If the incoming signal H has a negative rate of change having a delay state

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indicates, then the positive slope detector delivers 110c as the output signal P a constant voltage value which indicates the "no response" state of the H signal. In the same way, the negative inclination detector 100c generates the occurrence of a signal G with a positive rate of change, which indicates the acceleration state of Vehicle wheels indicates an output signal 0 with a constant voltage value, which indicates the state "no response" of the signal G.

The threshold values V ^ and Vp are supplied in a selected manner such that the threshold value V- represents a first threshold value for a state of the signal P and a second threshold value for a second state of the signal P. In the same way, the threshold value V ₂ forms a first threshold value for a state of the signal O and a second threshold value for a second state of the signal 0.

The brake control logic circuit 18 includes a reset logic unit 64, a ramp logic unit 66, an output logic unit 68 and an oscillator logic unit The input signals of the brake control logic circuit 18 are the slip switching signal D, the zero speed switching signal I, the deceleration switching signal K, the duty cycle switching signal M, the acceleration switching signal Q, the reset switching signal V and the output switching signal W; the output signals of the brake control logic circuit 18 are the output logic signal E, the Rampon logic signal N, the ramp logic signal S and the Reset logic signal T.

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The oscillator logic unit 70 of the brake control logic circuit 18 generates in response to the zero speed switching signal I from the zero speed switching unit 58, from the delay switching signal K, from the delay switching unit 24 with variable threshold value and the duty cycle switching signal M from the pulse generator 32 with fixed threshold value and variable duty cycle, the oscillator logic signal R, which is sent to both the ramp logic unit 66 as well as to the output logic unit. An acceleration programmed oscillator and a pulse generator with a fixed threshold value and a variable duty cycle are shown in more detail in FIG shown.

According to Fig. 9, speed monitoring circuits generate Differentiating circuits and voltage threshold circuits when the deceleration value of the vehicle wheels exceeds a preselected value, another signal K, which indicates the state that the deceleration of the vehicle wheel has exceeded a predetermined value. This means that the deceleration value of the vehicle wheels has exceeded a safe threshold with respect to the vehicle speed and that a slip imminent.

The acceleration programmed oscillator 28 speaks responsive to a signal J representing acceleration conditions of the vehicle wheels, and generates a first one Vibration signal L, one of which is dependent on signal J and, accordingly, on the acceleration conditions of the wheels Has oscillation frequency. The oscillating output signal L typically has a sawtooth shape, and the sawtooth pulses of the signal L preferably have

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variable amplitudes, so that a frequency-variable signal is generated. That means the length of time each The pulse is all the more 3-fold and therefore the frequency of the output signal The higher the amplitude of each pulse, the lower L is.

According to FIG. 9, the acceleration-programmed oscillator 28 also responds to the signal K, which has a high delay value represents the vehicle wheels. The signal K causes a blocking of the oscillating signal L in the Condition that the acceleration has exceeded the preselected value. Thus the signal contains L periods variable frequency indicative of signal J and periods indicative of signal K in which it is im essentially has the frequency 0. Although the use of the signal K in the acceleration-programmed oscillator 28 leads to advantageous results, this is not a decisive feature of the brake control system described here, as will be explained in more detail below.

The first oscillating signal L, the areas with sawtooth oscillations with variable amplitudes is provided by a pulse generator 32 with a fixed threshold value and variable duty cycle monitored so that this generates a second oscillating signal M. The second The oscillating signal M preferably consists of a selected sequence of pulses corresponding to the oscillations of the signal L. The pulses of the signal M preferably have a size and a duration. By adding & s signal L actuates the pulse generator 32 at different frequencies, the output signal M is a pulse train with variable duty cycle. It should be noted that the term "duty cycle" means the percentage

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of a cycle in which the signal M is in a logic state. It is therefore easy to see that signal M has a programmable duty cycle which is determined by the frequency of signal L and ranges from 0% to 10%. A pulse duty factor of 100% is indicated by a signal M, which remains in a logical state during the entire cycle. The period of time between the leading edges of pulses of the acceleration signal J is typically regarded as the cycle.

The oscillator logic unit 70 is also shown in FIG. those corresponding to the second vibration signal, the signal K and that of the zero speed wheel speed Signal I is working. The oscillator logic unit generates a third oscillation signal R, which with the help of the logical equation R = M. K. T can be described mathematically.

As already mentioned above, the use of the signal K in the brake control system described above not a critical feature; however, it is advantageous. The use of the K signal results in an R output signal with an additional pulse that occurs immediately after the state in which the vehicle wheel acceleration has elapsed exceeded the selected value. This additional impulse is selected in a way by locked to a zero speed wheel speed condition indicated by signal I. Every impulse in the pulse train of the signal R causes a selective actuation of the vehicle braking system, thereby the Speed is reduced. The signal R thus applies the brakes in a pumping manner during the The wheels, and it "pumps" the brake once,

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after the deceleration of the wheels is no longer above the selected value. Both states are the Subject to the condition that the wheel speed is not substantially zero.

The acceleration programmed oscillator 28 includes an oscillation frequency programming unit 100b which receives the signals J and K and to a frequency-dependent Oscillator 100b is coupled, which supplies the first oscillation signal L. The frequency programming unit 100b programs the oscillator 102b in proportion to the signal J (acceleration states of the wheels). As has already been mentioned above, the signal K causes an adjustment of the oscillation frequency of the oscillator 102b, which essentially has the value 0. It can be seen, however, that the wheels are not accelerating at the same time and can delay so that the signals J and K are mutually exclusive. The signal J actuates the Oscillator only during one acceleration state of the wheels, and it generates preferentially during all others Periods an oscillation frequency with the value 0. The observation of this fact makes it possible as Input signal of the oscillation frequency programming unit 100b to use only the signal J, which of course the advantageous use of the special pulse in the output signal R according to the state of the Signal K no longer allows.

The fixed threshold, variable duty cycle pulse generator 32 includes a level detector iO4b for monitoring the first oscillation signal L, which provides an input signal for a flip-flop circuit 106b, which the signal M preferably with one of two logical Supplies signal values. When the signal L is less than the

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Level of the level detector 104b, then the toggle * circuit 106b sends the signal M with one logical signal value, while it sends the signal M with the other logical value Provides signal value when the signal L exceeds the level of the level detector 104 b.

According to Figure 9, the flip-flop 106b with the frequency-dependent Oscillator 102b connected so that the signal L is generated entirely dependent on the signals J and K.

In addition to the signal R, the ramp logic unit 66 is also from the zero speed switching signal I, from the duty cycle switching signal M and from the acceleration switching signal Q controlled; in response, the ramp logic unit 66 generates the ramp logic signal N and the ramp logic signal S, both of which are applied to ramp signal generator 52 to set that generator. That Ramp logic signal N is also applied to reset logic unit 64.

The reset logic unit 64 receives both the ramp logic signal N as well as the output drive signal W in order to generate the reset signal T which corresponds to the reset timing control and reset switch unit 30 is supplied.

The reset time control and switching unit 30 includes a reset time control unit 60 and a reset switch unit 62. The reset signal I is fed to the reset time control unit 60, which in response to it with a reset time cycle begins, at the end of which a reset time control signal U is generated and sent to the reset switching unit 62 is applied. The reset switching unit also receives the threshold acceleration signal Q,

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and in response to the reset timing control signal U and the threshold acceleration signal Q, it generates the reset switching signal V which is applied to the output logic unit 68. In response to receiving the slip switch signal D _{f of} the oscillator signal R and the reset switch signal V, the output logic unit generates the output signal E, which is coupled to the output driver circuit 34 for generating the two module output signals F and W.

As has been stated above in connection with Fig. 1, the output driver circuit 34 generates both the output signal F as well as the output signal W. The output signal F is coupled to the error monitoring circuit 36, while the output signal W in addition to the fault monitoring circuit 36 is also coupled to the reset logic unit 64. The output signal W sets the reset logic unit 64 in an operating state for a subsequent brake control cycle.

The fault monitoring circuit 36 includes an overcurrent detector 72 (Failure Protection I), a power failure detector 74 (error protection II), a sensor interruption detector 76 (error protection III), a Magnetic interruption detector 78 (error protection IV) and an error switching unit 80. As already mentioned, the error monitoring circuit 36 monitors the operation of the brake control module r and ßie generates signals that a Control display device such as a lamp or a buzzer and / or the supply energy by burning out disconnect a fuse or open a switch, so that a visible or audible indication of a module or Brake system failure and / or disconnection of the

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supply energy is caused by the module to prevent further destruction.

The fault protection I is an overcurrent detector that does the Receives output signal W and monitors whether there are overcurrent conditions in the brake control module. If that If the output signal W indicates an overcurrent condition in the brake control module, the error protection device I generates a pulse-shaped one Monitor signal X1 coupled to fuse blow circuit 84.

Failure protection II is a power failure detector, which monitors the controller 42 to determine whether or not supply energy is being supplied to the brake control module. If the supply energy of the brake control module fails, the fault protection II determines this state, and it generates a pulse-shaped monitor signal X2 which is coupled to the lamp driver 88.

The fault protection III is a sensor interruption detector, which receives the signal A coming from the speed sensor and determines whether there are 10 signals from the speed sensor generated and applied to the brake control module. If the speed signal fails to appear, the fault protection III fixes this state, and it generates a pulse-shaped monitor signal X3, which is coupled to the error switching unit 80 will.

The error protection IV is a magnetic interrupt detector, which the output signal. F receives from the output driver circuit 34 so that it can be determined whether the brake control solenoid is working properly or not.

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If the brake control solenoid is malfunctioning, i. E. is interrupted, the error control IV determines this state, and it generates a pulse-shaped monitor signal X4, which is also coupled to the fault switching unit 80.

The output signal generated by the output driver circuit 3 ^ F is also coupled to the error switching unit 80, which together with the monitor signals X3 and X4 two pulse-shaped error switching signals Y1 and Y2 are generated. In addition, the fault switching unit 80 monitors the brake switch of the vehicle and the actuation switch the brake control module of the brake control system to determine whether these switches are operated when the land vehicle brakes and the brake control system works.

The lamp drive circuit 40 includes a time delay circuit 86 and the lamp driver 88. In response to receipt of the error switch signal Y2 the time delay circuit 86 delays this signal by a preselected amount of time and sets the delayed Error switching signal Z2 to lamp driver 88 and to fuse blow circuit 38. If the Energy failure detector 74 of the fail safe ΣΙ has detected a power failure, and the monitor signal X2 has been generated and coupled to the lamp driver 88, then the delayed error switching signal Z2 is also applied to the lamp driver 88, which is then operated so that a light is switched on or a buzzer to Response is brought, whereby the driver of the land vehicle is warned that the brake control system is not working properly is working.

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The fuse blow circuit 38 includes “fuse blow logic 82 and a fuse blowing unit In response to receiving the false switch signals Y1 and of the delayed fault switching signal Z2, the fuse blow logic 82 generates a fuse blow pulse signal Z1, which is applied to the fuse blow unit 84. If there is an overcurrent condition in the brake control system, detected by the overcurrent detector 72 of the fault fuse I. is then the monitor signal X1 is generated and applied to the fuse blow unit 84, which together With the application of the fuse blown pulse signal Z1, the blowing of a fuse (or the opening of a Switch). The brake control system is therefore separated from the supply energy, i.e. from the controller 42, since an overcurrent condition is most likely to destroy the brake control module and the disconnection the supply energy from the module is an effective way of preventing further destruction of the brake control system.

The fault switching unit 80 also monitors whether the speed sensor is interrupted (error protection III), or whether the brake control magnet is interrupted (error protection IV). If the monitor signal X3 and / or the monitor signal X4 are applied to the fault switching unit 80, this becomes Error switch signal Y2 is generated and sent to the time delay circuit 86 applied so that the time-delayed signal Z2 is generated and the lamp driver 88 is actuated so that the driver of the land vehicle is again indicated that the braking system of his vehicle is not working properly.

Operating conditions;

Basically, the anti-slip brake control module described here generates the following eight control signals:

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1. The generator and comparison circuit 14 for slip and Ramp signal generates a slip control signal D, which controls the switching on and off of the module output signal, whereby the braking system of the land vehicle is selectively locked and can selectively operate in the normal manner.

2. The variable threshold delay switching unit 24 generates a delay control signal K, which programs the acceleration programmed oscillator 28.

3. Fixed threshold pulse generator 32 and variable duty cycle generates the duty cycle control signal M, which the oscillator logic unit 70 of the brake control logic circuit 18 controls.

4. The variable threshold acceleration switching unit 26 generates the acceleration control signal Q, which controls the slow ramp behavior of the ramp logic unit 66 of the brake control logic circuit 18 and the reset time control - and reset switching unit 30 sets.

5. The DC value detector and zero speed switching unit 16 generates the zero speed control signal I, which also has the slow ramp behavior of the Programmed ramp logic unit 66 of the brake control logic circuit 18 and the duty cycle control signal M on it prevents the oscillator logic unit 70 of the brake control logic circuit 18 from controlling.

6. The reset logic unit 64 of the brake control logic circuit generates a reset control signal T in response to receipt of that generated by the output driver circuit 34

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Output signal ¥, and it effects control or Resetting the reset time control and reset switch unit 30th

7. The oscillator logic unit 70 of the brake control logic circuit 18 generates an oscillator logic control signal R, which switches off the output signal of the control module, i.e. that it is the slip control signal D and the Ruckste11οgiksteuersignal T overdriven; the control signal R programs the rapid ramp behavior of the ramp logic unit 66 of FIG Brake control logic circuit 18.

8. The reset time control and reset switch unit generates a reset control signal V in response to receipt of the reset logic control signal T and switches the output signal of the control module during the time period in which the acceleration control signal Q is turned on is.

Time TO :

At time TO, the land vehicle is working normally Operating state in which the brake system is released. The vehicle wheel speed is as shown in Figure 3A is, and the other starting conditions of the other units of the control module described here are in the The curve diagrams of FIG. 3 are given by way of example.

Point in time T1

Process 1; The deceleration value of the wheel speed of the land vehicle exceeds the deceleration threshold value set by the deceleration switching unit 24, such as by the variable DC signals B, G and H

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is specified.

Operation 2: The DC value detector zero speed switching unit 16 generates the variable DC signals G and H which follow the variable DC signal B until the signal B goes below the level set by the DC value detector 56.

Operation 3 t The delay differentiating circuit 20 generates the delay differentiating signal O which is proportional to the delay value of the variable direct current signal G.

Process 4: If the delay differentiating signal 0 of the delay differentiating circuit 20 exceeds the voltage threshold value set by the delay switching unit 24, then this switching unit generates the delay switching signal K.

Process 5 t The delay switching signal K of the delay switching unit 24 programs the acceleration-programmed oscillator 28, and it switches the acceleration oscillator signal L to the low state.

Operation 6: When the acceleration oscillator signal L of the acceleration programmed oscillator 28 is switched to the low state, the pulse generator with fixed threshold value and variable duty cycle is switched on, whereupon the duty cycle control signal M goes to its high state, while the ramp logic signal N goes to its high state and the ramp logic signal S goes low.

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Process 7; The ramp logic signal N of the ramp logic unit 66 controls the edge signal generator 52 so that the ramp signal C no longer follows the variable direct current signal B of the frequency converter 12.

Time T2

Process 1; The variable direct current signal B from the frequency converter 12 falls below the voltage value of the ramp signal C from the ramp signal generator 52, which is now in the hold state.

Process 2: When the variable direct current signal B falls below the voltage value of the ramp signal C, the comparison signal D of the comparison circuit 54 is switched to its high state.

Operation 3: The comparison signal D drives the output logic unit 68, and it causes the output signal E generated by that unit to go low.

Process 4; When the output signal E changes to its low state, it drives the output driver circuit, so that the transition of the output signal F generated by this output driver circuit 34 into its high state is caused.

Process 5: When the output signal F goes high, the braking system of the land vehicle (via the brake control magnet) is locked or released.

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Time T5

Process 1; The wheel speed deceleration value falls below the deceleration threshold value set by the deceleration switching unit 24, as indicated by the variable direct current signals B, G and H.

Operation 2: The delay differentiating signal 0 from the delay differentiating circuit 20 decreases in proportion to the size of the decrease in the direct current signal G from the direct current value detector 56.

Process 5; When the delay differentiating signal 0 falls below the voltage threshold value set by the delay switching unit 24, the delay control signal K changes to its low state.

Process 4; When the deceleration control signal K from the deceleration switching unit 24 changes to the low state, the acceleration oscillator signal L from the acceleration-programmed oscillator 28 changes to the high state at a preselected rate of change.

Operation 5: The control signal R from the oscillator logic unit 70 changes to the high state when the delay control signal K from the delay switching unit 24 changes to its low state.

Process 6: The control signal R from the oscillator logic unit 70 controls the output logic unit 68, and it causes its output signal E to go high.

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Process 7: The output signal E of the output logic unit controls the output driver circuit, and it causes the pulse-shaped output signal F

this output driver circuit goes low, thereby causing the braking system of the land vehicle pressurized again.

Time T4

Procedure 1 : If the acceleration oscillator signal L from the acceleration-programmed oscillator 28 exceeds the threshold value set by the pulse generator 32 with fixed threshold value and variable duty cycle, then the duty cycle control signal M generated by this pulse generator changes to the low state.

Operation 2: When the duty cycle control signal M goes low, the control signal R also goes low, and it causes the "ramp signal N, the output signal E and the driver output signal F to go low, respectively .

Operation 5: When the ramp signal N transitions to its low state, it switches the ramp signal generator out of a hold state so that it can begin another discharge.

Operation 5: When the ramp signal N goes low and the output drive signal F goes high, then the reset control signal T from the reset logic unit 64 goes high.

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During the time Τ4 there are a finite number of occurrences second order. These are the following processes:

Process 1; The wheels of the land vehicle begin to accelerate as indicated by the variable DC signals B, G and H.

Process 2; The acceleration differentiating signals J and P from the acceleration differentiating circuit 22 are proportional to the acceleration value of the vehicle wheel speed.

Process 3 t The acceleration control signal Q switches to a high state.

Process 4; The ramp logic unit 66 is programmed to the low state by the acceleration control signal Q from the acceleration switching unit 26.

Time T5

Procedure 1: The acceleration-programmed oscillator 28 switches to its low state when the acceleration oscillator signal L generated by it reaches the analog voltage value indicated by the acceleration differentiating signal J from the acceleration differentiating circuit 22.

Process 2: When the acceleration signal L falls below the voltage threshold value set by the pulse generator 32, the duty cycle control signal M generated by the pulse generator 32 switches to the high state.

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Procedure 3: When the reset timing signal U switches to the high state, the control signal R goes to the high state.

Process 4; That . Ramp logic signal S and the output signal E follow the control signal R.

Event 5; When the output signal E goes high, the output drive signal F goes low.

Process 6; The reset logic control signal T follows the output driver signal F.

Please note the following: Between times T4 and T5 the voltage value of the reset time control signal U increases for the period in which the reset control signal T is in the high state, slowly increases linearly.

Time T6

Process 1: That. Ramp signal C drops to a voltage value below the voltage value of the variable direct current signal B from frequency converter 12.

Process Zi The comparison signal D switches to the low state.

Process 3; The output drive signal F remains in its low state.

Process 4; The output signal E remains in its high state.

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Note the following: The comparison signal D and the reset control signal are the only control signals of the control module, which can switch on or reactivate the braking system of the land vehicle.

The following should also be noted: The acceleration oscillator signal L, the duty cycle control signal M, the oscillator logic signal R and the ramp logic signal S switch or continue to oscillate with a duty cycle that depends on the acceleration value of the direct current value signal H (see T6 to T8).

• Time T7

Process 1: The acceleration value of the direct current value signal H falls below the acceleration threshold value which is set by the variable threshold value acceleration switching unit 26.

Operation 2: The acceleration differentiating signal P falls below the threshold voltage set by the acceleration switching unit 26, and the acceleration control signal Q generated by the acceleration switching unit 26 changes to the low state.

Operation 3: The ramp logic signal S remains high in response to the acceleration control signal Q if the oscillator logic signal Rim is high.

Time T8

At this point in time, the same seven processes take place as in point in time T1.

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Time T9

At this point in time, the same five events take place as at point in time T2.

Time T10

Operation 1t The variable DC signal B falls below the value set by the DC value detector 56 (see signals G and H).

Process 2; The variable direct current signals G and H are clamped at a preset direct current value.

Operation 5: The DC value detector 56 generates a DC value signal 11 which is an analog representation of the variable DC signal B when it falls below the threshold value set by the DC value detector 56.

Process 4; The zero speed control signal I switches to its high state and prevents the oscillator unit 70 from generating the oscillator signal R.

Operation 5: The delay differentiating signal 0 from the delay differentiating circuit 20 decreases in proportion to the delay value of the direct current signal G from the direct current value detector 56.

Process 6; When the delay differentiating signal is 0 among those set by the delay switching unit 24

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The voltage threshold drops, then the delay control signal goes K about to its low state.

Operation 7: When the deceleration control signal K from the deceleration switching unit 24 changes to its low state, the acceleration oscillator signal L from the acceleration programmed oscillator 28 changes to the high state at a preselected rate of change.

The following should be noted: In the course of process 6, the oscillator signal R is blocked, in contrast to his Transition to the high state at time T3.

Time T 11

Process 1; The acceleration oscillator signal L exceeds the fixed threshold value set by the pulse generator 32, and the duty cycle control signal M switches to its low state.

Process 2; The edge logic signal N switches to the low state.

Curtain 3; The reset logic control signal T follows the output driver signal F, which means that it switches to the high state.

Process 4: The reset time control signal U changes in a substantially constant amount in the positive direction.

Time T12

Process 1 ; The variable direct current signal B rises to a direct current value which is above that of the

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DC value detector 56 is set DC value, which means that the vehicle wheels with a accelerate low value.

Process 2; The DC value signal 11 reaches a DC value which turns off the zero speed switching unit 58, whereupon the zero speed control signal I changes to its low state.

Process 5: The voltage values of the acceleration differentiating signals J and P transition to positive values at a speed proportional to the change in the variable direct current signal F.

Operation 4: When the acceleration differentiating signal P exceeds a preselected DC voltage value, the acceleration control signal Q switches to the high state.

Process 5: The acceleration oscillator signal L changes to the low state depending on the acceleration differentiating signal J.

Operation 6: The duty cycle control signal M switches to the high state when the acceleration oscillator signal L switches to the low value.

Process 7: The oscillator logic signal R, the output signal E and the ramp logic signal S each switch to the high state.

Operation 8: When the oscillator logic signal R goes high, the reset logic control signal T goes low.

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Operation 91 When the output signal E goes high, the output drive signal F goes low or off.

Operation 10: When the output drive signal F switches to the low state, the reset timing control signal U begins to slowly change in the negative direction.

Process 11; When the ramp logic signal S switches to the high state, the ramp signal C switches from its slow ramp state to its fast ramp state.

Time T13

Process 1; The ramp signal C falls below the voltage value of the signal B from the frequency converter.

Process 2: The comparison signal D switches to the low state or to the shutdown state.

The following should be noted: Between the times T12 and T13 reaches the reset timing control signal U den DC voltage value set by the reset time control unit 60, and it switches to a low one in s State to, whereby the reset unit 62 opens and the switching of the reset signal V to the high state is initiated. The reset signal V causes the output signal E to switch high and it holds the output driver circuit 34 in the on state, except when the oscillator logic signal R is low.

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Time T14

At this point in time, the same six processes take place as in point in time T5.

Time T15

Process 1; The acceleration-programmed oscillator switches to the high state when the acceleration oscillator signal L generated by it falls below the analog voltage indicated by the acceleration differentiating signal J from the acceleration differentiating circuit 22.

Process 2; When the acceleration oscillator signal L rises above the voltage threshold value set by the pulse generator 32, the duty cycle control signal M generated by this pulse generator 32 switches to the low state.

Operation 3: When the reset timing control signal U switches to the low state, the oscillator logic signal R also switches to the low state.

Process 4t The ramp logic signal S and the output signal E follow the oscillator logic signal R.

Operation 5: When the output signal E switches to its low state, the output drive signal F goes high.

Process 6: The reset logic control signal T follows the output driver signal F.

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Time T16

At this point, the same six operations occur as in time T15.

Time T17

Process 1; The acceleration value of the wheels of the land vehicle falls below the threshold value set by the acceleration switching unit 26.

Process 2 ; The acceleration differentiating signal P falls below the voltage threshold value set by the acceleration switching unit 26.

Operation 3: The acceleration control signal Q switches to its low state.

Process 4 : The ramp logic signal S switches to the high state, while the reset signal V switches to its low state.

Process 5; In response to the reset signal V, the output signal E goes high, while the output drive signal F goes low.

There now follows a description of Figures 4A to 4D, in which a circuit diagram of an embodiment of a Anti-slip brake control module is shown. As can be seen, the voltage regulator 42 generates positive Regulated DC voltages, for example voltage B (for example + 8V) on line 90 and voltage B +

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(e.g. + 13V) on line 92. The voltage regulator 42 is connected via terminal 75 to the battery of the land vehicle from which it is fed. The example a satisfactorily working voltage regulator for the embodiment of the brake control module described here is described in the aforementioned patent application P21 16 303.1. Line 92 is used to drive the transistors used in the output logic unit 68 and in the output driver circuit 34, while the line 90 to the Control of the transistors of the remaining circuit parts the embodiment of the brake control module described here is used.

As already indicated above in connection with FIGS has been, the frequency converter 12 receives at the terminals 77 signals with variable frequency either from a wheel speed sensor as described in the patent application mentioned P 21 16 303.1 is described, or by a (not shown) drive shaft sensor, and he sets this Signals with variable frequency in the in Fig.3B variable direct current signals. The variable direct current signal B appears at terminal 80a, and it is sent via the line 81 to the slip signal generator 50, via the lines 94 and 95 to the comparison circuit 54 and coupled to the direct current value detector 56 via the line 94. The frequency converter 12 also generates a Output signal B1, which via line 96 to the DC value detector 56 is coupled.

The slip signal generator 50 receives the variable direct current signal B via the line 81 and the Voltage divider circuit made up of resistors R1, R2, R3

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and R5, which divides signal B. The variable DC signal B is then coupled via line 98 to a differential amplifier which includes transistors T1 and T2. The collectors of the transistors T1 and T2 of the differential amplifier are connected to current source transistors T4 and T5, the emitters of which are connected to the B supply line 91 via emitter bias resistors R.6 and R7, respectively; the base connections of the transistors T4 and T5 are connected to one another. The base terminal of the current source transistor Τ4 is connected to its collector. The output signal of the differential amplifier (transistors T1 and T2) is taken from the collector of the transistor T2 via an output transistor T3, the collector of which is connected to the B supply line 91 via a load resistor R9, while its emitter is connected to the base terminal of the transistor T2. The emitters of the transistors T1 and T2 are connected to one another; they are also connected to switching transistor T6 through an emitter bias resistor R8. The emitter of the switching transistor T6 is grounded and its base terminal is connected to the B supply line 91 via the base bias resistor R10. Parallel to the base-emitter path of the switching transistor T6 is an inverting amplifier transistor T8, the collector of which is connected to the base terminal of the switching transistor T7, while its emitter is connected to ground, and its base terminal is connected to the cathodes of input diodes D2 and D3 via a limiting resistor R30 is. YJenn the edge logic signal N has high Fourth, as it prevents, during the time between times T1 and T4 is the case of the slip signal generator 52 to the capacitor C1 from moving ^to the transistor T19

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, as shown by the edge signal C of FIG. 3 discharged. The switching transistor T7 is also provided for resetting the slip signal generator 50. The collector of the switching transistor T7 is connected to the B supply line 98 via the bridge resistor R4, while its collector is connected to ground and its base connection is connected to the reset time control unit 60 via a limiting resistor R5 and a line 106. When the reset time control signal U2 turns on, it controls the base terminal of the switching transistor T7 to a low value, so that the transistor T7 goes into the conductive state, which causes a change in the slip signal divider circuit consisting of the resistors R1, R2, R3 and R4. This means that the divider resistor R4 of the circuit for resetting the slip signal generator 50 is connected in parallel to the divider resistor R2.

The '. In addition to the discharge transistor T9, the ramp signal generator 52 contains current source transistors T10, T11 and T13 for setting the bias current for the discharge transistor T9. Collectors of the current source transistors T10, T11 are connected to each other and to the B supply line 90 through the collector bias resistor R12, while their emitters are grounded through the emitter bias resistors R13 and R14, respectively. The base of the current source transistor T10 is connected to the base of the discharge transistor C9, and the collector of the current source transistor T10 is returned to its base. The collector of the current source transistor T13 is connected to the B supply line 90 through the collector bias resistor R15, and its emitter is grounded through the emitter bias resistor R16, while

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its base is connected to the base of the current source transistor T11. The collector of the current source transistor T13 is coupled back to its base. A switching transistor T12 is in parallel with the emitter bias resistor R14 of the current source transistor T11. That is to say that the collector of the transistor T12 is connected to the emitter of the transistor T11 and that the emitter of the transistor T11 is connected to ground, while its base is connected to the cathode of the diode D1 is connected, the anode of which is connected to the output of the ramp logic unit 66 via a line 103. Of the Transistor T14 is parallel to current source transistor T13. That is to say that the collector of the transistor T14 is connected to the collector of the current source transistor T13 while its emitter is grounded and its base connected to the B supply line through base bias resistor R17 90 communicates; furthermore, its base is connected to the ramp logic unit via line 98. if the transistor T12 is switched on, the Ramp signal generator 52 in a hold state. That is, the current source transistor T11 is substantially the entire Pulls current through collector bias resistor R12, so that the current through the EntMetransistor T9 and the current source transistor T10 essentially approaches zero goes, because here these two transistors are in a very weakly conductive state, so that a discharge of the capacitor C1 via the discharge

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transistor T9 is changed. So when the ramp logic signal N is high, so that the diode D1 is forward biased, and the transistor T12 is put into its highly conductive state, this has for the time between the times T1 and T4 from Ramp signal generator 52 generated ramp signal C an essentially flat profile. If the Transistor T14 is in a highly conductive state, it essentially connects the base terminals of the current source transistors T10 and T11 to ground. The current source transistor In this case, T10 draws a current that essentially has the value 0; he is so in a very weakly conductive state. As a result, there are the discharge transistor T9 and the current "~ source transistor T10 in their highly conductive states, in which they draw a maximum current. This allows the capacitor C1 to move through the discharge transistor T9 unload at high speed. So when the "ramp logic signal S has a high value, so that the Transistor T14 in its conductive state is switched, the ramp signal C generated by the ramp signal generator 52 falls rapidly, as in time is shown between times T4 and T6.

The comparison circuit 54 contains a differential amplifier with transistors T15, T16 and T17, output transistors T18, T19 and T21, a switching transistor T20 and current source transistors T22 and T23. The differential amplifier transistors T15 and T17 are with their emitters commonly connected to the collector of transistor T16, which in turn is connected to the collector of the current source transistor T22. The collectors of the Transistors T15 and T17 are across collector bias resistors R18 or R19 connected to the cash register, during the

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Emitter of transistor T16 is directly connected to ground. The emitters of the current source transistors T22 and T23 are connected to the B supply line 90 via emitter bias resistors R26 and E27, while their base terminals are connected to one another. The collector of the current source transistor T23 is on the one hand connected to ground via the collector bias resistor R28 and on the other hand is fed back to its base. The collector of the output transistor T18 is connected to the B supply line 90 via a load resistor R25, and its emitter is connected to ground, while its base is connected to the collector of the transistor T17 via a limiting resistor R21. The base of the inverting transistor T21 is connected to the collector of the transistor T18, and its emitter is connected to ground, while its collector is connected to the B supply line 90 via a load resistor R29. The output signal of the comparison circuit 54 · is generated at the load resistor R29; it is coupled to the output logic unit 68 via a diode D12. The collector of the output transistor T19 is connected to the base of the transistor T17 via a limiting resistor R22, its base is connected to the collector of the transistor T17 via a limiting resistor R20 and its emitter is connected Dimensions. The transistor T20 and the limiting resistor R23 are parallel to the output transistor T19 and the limiting resistor R22, the collector of the transistor T20 being connected to the base of the transistor T17 via the limiting resistor R23, while its emitter is connected to ground and its base is connected to a limiting resistor R23 ¹ and is connected to the reset time control unit 60 via line 106.

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The input signals of the comparison circuit 54 are grounded at the terminals 93 via a line 95 '(ramp signal C) and received via a line 95 and a limiting resistor R24 (variable direct current signal B). The output signal D of the comparison circuit 54 is via a line 100, the diode D3 and a limiting resistor R30 fed back to the inverting transistor T8. The resistors R22, R23 and R24 form a current dividing circuit for resetting the comparison circuit 54. That is to say that when the reset signal U2 den Transistor T20 drives into its highly conductive on state, transistor T20 drives the current divider from the resistors R22, R23 and R24 changed and thereby the comparison circuit 54 resets.

ttr DC value detector 56 contains a differential amplifier with transistors T24 and T25 and an output transistor T26. The collector of transistor T24 is connected to the B supply line 90, while the collector of transistor T25 is connected via a collector bias resistor R33 is in connection with the B supply line. The emitters of the differential amplifier transistors T24 and T25 are grounded through an emitter bias resistor R32. The base of the transistor T24 is connected to line 94 through resistor R31 and the base of transistor T25 is direct connected to line 96. The emitter of the output transistor T26 is connected to B supply line 90 through an emitter bias resistor R34 Connection, its collector is connected to ground and its base is connected to the emitters of transistors T24 and T25. Between the ground and the base of the transistor T24 there is a capacitor C2, the connection point between the capacitor and the base of the transistor T24 is connected to ground via a bias resistor R35.

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This RC circuit prevents any AC components from which can be generated by the differential amplifier transistors T24 and T25, at a coupling to the output transistor T26. The output transistor T26 is connected in an emitter follower circuit so that no amplification when generating the DC value signal G arises, which is connected to the delay differentiating circuit via a limiting resistor R37 and a coupling capacitor C3 20 is coupled.

The zero speed switching unit 58 contains an output transistor T27, the emitter of which is directly connected to the B supply line 90, the base of which is connected to the B supply line 90 through a base bias resistor 33 and its collector is connected to ground via a test resistor R36. The zero speed control signal I is generated at the load resistor R36, and it is fed to the via a line 110 and a diode D11 Oscillator logic unit 70 and coupled to the ramp logic unit 66 via a diode D6. Generated in this way the zero speed switching unit 58 effectively provides the zero speed switching signal I as a function of the output signal of the direct current value detector 56, which is applied to the load resistor R33 of the differential amplifier transistor T25 is generated.

The delay differentiating circuit 20 includes differentiating transistors T28 and T29. The collector of the transistor T28 is connected to the B supply line via a load resistor R38 90 connected and its base is through a base Xfr voltage resistor R39 is connected to the B supply line 39, while its emitter is connected to the coupling capacitor C3 is connected. The collector of transistor T29 is connected to the base of transistor T28, its base is connected to the emitter of transistor T28 and his

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The emitter is grounded. Thus, when the DC value signal G is applied to the delay differentiating circuit 20, it is differentiated by the differentiating circuit described above so that the delay -r differentiating signal 0 is generated which is coupled to the variable threshold delay switching unit 24. The differentiated output signal of the delay differentiating circuit 20 is generated at an RC element made up of a capacitor C4 and a resistor R40 in connection with a transistor T30 ^f . The output terminal of the delay differentiating circuit 20 is connected to ground via the capacitor C4, and it is connected to the collector-emitter path of the transistor T30 ¹ via the resistor R40. The base of the transistor T30 ^{1 is} connected to ground via a base bias resistor R46.

The variable threshold delay switching unit 24 includes a differential amplifier (transistors T30, T31), a complementary emitter follower circuit (transistors T32, T33) and an output circuit (transistor T34). The collector of the differential amplifier transistor T30 is is connected to the B supply line 90, and its base is connected to the collector of the output transistor T28. The collector of the differential amplifier transistor T31 is connected to the B supply line via a load resistor R42 90 connected. The emitters of the two differential amplifier transistors T30 and T31 are connected via an emitter bias resistor R41 connected to earth. The base of the differential amplifier transistor T31 is over a coupling capacitor C5 and a base bias resistor R43 connected to the B supply line 90. The collector of transistor T32 of the emitter follower circuit is connected to the B supply line 90 while the collector of transistor T33 of the one-follower circuit is on

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Mass lies. The emitter and base connections of the complementary Emitter follower transistors T32 and T33 are with each other connected, their bases connected to the collector of the output transistor T28 and their Emitter terminals are connected to the junction of voltage divider resistors R43 and R44, which in turn between ground and the B-supply line 90 lie. The emitter of the output transistor T34 is connected to the B supply line 90, its collector is connected to ground via a resistor R47 and its base is connected to the load resistor R42. The voltage divider resistor R.45 lies between the collector of the output transistor T34 and the voltage divider resistor R46.

The acceleration differentiating circuit 22 includes one Differentiating amplifier for differentiating the DC voltage value signal H to generate the acceleration differentiating signals J and P; it contains the transistors T35, T36 and T37. The base of transistor T35 is on the base of the transistor T36 is connected, and the emitter of the transistor T35 is connected through a limiting resistor R48, a coupling capacitor C6 and a limiting resistor R46 with the DC value detector 56 connected. The collector of the Trar & stors T35 is for coupling the acceleration differentiating signal J to the input terminal of the programmed acceleration Oscillator 28 connected. The collector of the transistor T36 is connected to an RC element made up of the capacitor C7 and the Collector bias resistor R50 to ground; its basis is on the one hand a bias resistor R52 connected to ground and, on the other hand, directly to the collector of transistor T37; its emitter is over one Limiting resistor R51 to the base of transistor T37 tied together. The emitter of the transistor T37 is connected to the B supply line 90, its collector is

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Connected to ground via the bias resistor R52 and its base is at the connection point between the coupling capacitor C6 and the limiting resistor R49 connected. When the DC signal H to the acceleration differentiating circuit 22 is coupled, the acceleration differential signal J is thus generated in the collector circuit of the transistor T35 and sent to the acceleration programmed oscillator 28 coupled, while the acceleration differentiation signal P from RC element made up of capacitor C7 and resistor R50 is generated and coupled to the acceleration switching unit 26 with a variable threshold value.

The threshold variable acceleration switching unit 26 includes a complementary emitter follower circuit (Transistors 38, 39), a differential amplifier circuit (transistors T40, T41 and T42) and an output amplifier circuit (transistor T43). The collectors of the complementary emitter follower transistors T38 and T39 are connected to the B supply line 90 and to ground, respectively, while their emitter connections and their base outputs are connected to each other are. Their connected base connections are connected in such a way that they receive that of the acceleration differentiating circuit 22 generated acceleration differentiation signal P received while the connected emitter terminals at. the base of the differential amplifier transistor T41 are connected. The complementary emitter follower transistors T38 and T39 control the base of the differential amplifier transistor T41 in such a way that this is the base of the Differential amplifier transistor T40 plus or minus a diode voltage drop follows. Of the The emitter of the transistor T40 is connected to the B supply line 90 via a load resistor R53,

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while its collector is grounded through a collector bias resistor R64. The emitter of the transistor T41 is also connected to B supply line 90 through load resistor R43, and its collector is directly due to mass. The oasis of transistor 41 is connected to the base bias resistor R55 B supply line 90 and connected to ground via an RC element made up of a capacitor C8 and a resistor R56. The collector of the transistor T42 is connected to the B supply line 90 via a load resistor R57, its emitter is connected directly to ground and its base is connected to load resistor R54. Of the The collector of the output transistor T43 is connected to the B supply line 90, its base is connected to the load resistor R57, while its emitter is connected to the isolating resistor R58, the is inserted between the emitters of the transistors T42 and T43. The acceleration control signal Q on the acceleration switching unit with variable threshold value is generated at the load resistor R57, amplified by the transistor T43 and finally via a line 114 on the one hand via a diode D5 of the ramp control unit 66 and, on the other hand, fed to the reset switching unit 62 via a limiting resistor R83.

The accelerator programmed oscillator 28 contains a logic circuit (transistor T44), a power source circuit (transistors T45, T47) and an oscillator circuit (Transistors T46, T48 and T49). The transistor T44 receives at a base via a blocking diode D3 and a limiting resistor R60 the delay control signal K. The emitter of the traiB istors T44 is connected to ground, and its collector is connected to the B supply line 90 through a load resistor R62. The transistors T45 and T47 ensure that the collector circuit of transistor T46 is activated, and they transfer its voltage

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the load resistance R.62. The transistor T47 receives has the acceleration differentiating signal J at its collector, and its emitter is across the emitter bias resistor R63 connected to ground. Its base is connected to its collector and to the base of transistor T45, whose emitter is connected to ground via an emitter bias resistor R61 and whose collector is connected to the Kol3äctor of the transistor T44 and on the other hand via the Load resistor R62 is connected to the B supply line 90. The collector of the oscillator transistor T46 has a collector connected to the B supply line 90 through the load resistor R62, while being The emitter is directly connected to ground and its base with the connection point between a limiting nv / idorstand R64 and the collector-emitter path of the oscillator transistor T48 is connected. The emitter-base path of the oscillator transistor T48 lies between the collector of the oscillator transistor T46 and B supply line 90 through emitter bias resistor R65 while its collector so although to the base of the oscillator transistor T46 as well as to the collector of the oscillator transistor T49 is connected via the limiting resistor R64. The emitter of the oscillator transistor T49 is directly connected Ground, and its base is connected to the connection point of the voltage divider composed of resistors R71 and R72. An RC series circuit for generating the acceleration oscillator signal L is inserted between the B-supply, line 90 and ground "it contains resistor R65 and capacitor C10. The acceleration oscillator signal L is generated on capacitor C10, and it is sent to pulse generator 32 with fixed Threshold and variable duty cycle applied. In this way, the capacitor 10 charges

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to a voltage value via the Ilder stand Rö5, which is equal to that set at the collector of the oscillator transistor T46 by the transistors T45 and T47 Voltage value is. When this occurs, the oscillator transistor T48 becomes conductive offset so that the capacitor C10 via the Oscillator transistors T46 and T49 discharges. Thus it depends on the acceleration programmed oscillator 48 generated frequency from the oscillator of the transistor T46 from the transistors T45 and T44 set voltage value.

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. This means that the frequency depends on the acceleration differentiating signal J generated by the acceleration differentiating circuit 22, which is coupled to the current source transistor T4-7, which in turn controls the collector circuit of the oscillator transistor T46.

The fixed threshold, variable duty cycle pulse generator 32 includes a differential amplifier circuit (Transistors T50, T51) and an output amplifier circuit (transistor T52). The emitter the transistors T50, T51 are connected to one another and to ground through an emitter bias resistor R67; the base of the transistor T50 is connected in such a way that it receives the signal L from the acceleration-programmed oscillator receives, and the base of transistor T51 is connected to the voltage divider from resistors R.68 and R.69 connected. The collector of the transistor T50 is connected to the B supply line 90, during the The collector of the transistor T51 is connected to the B supply line 90 via the load resistor R66. The voltage divider from the resistors R68 and R69 is connected between the B supply line 90 and ground. The base of the output transistor T52 is at the connection point between the load resistor R66 and the collector of transistor T51 while its emitter is directly connected to B supply line 90; its collector is connected to ground via load resistor R70. Between the collector of the output transistor T52 and the voltage divider resistor R71 are connected to an isolating diode D15. The duty cycle control signal M is on

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Load resistance R70 is generated, and it is connected via a line 112 and a limiting resistor R95 the oscillator logic unit 70 is coupled. It is also via line 112 and a limiting resistor R77 coupled to the reset logic unit 64. So if the voltage on capacitor C10 is below that of the voltage value set for the voltage divider resistors R68 and R69 drops, the output transistor T52 placed in the conductive state so that it generates the duty cycle control signal M.

The reset logic unit 64 includes two transistors T53 and T54; the collector of transistor T53 is over a load resistor R75 is connected to the B supply line 90 while its emitter is grounded and its Base is connected to the connection point between the limiting resistors R73 and R74. The two Limiting resistors are in turn in series between ground and the collector of transistor T65 of the output logic unit 68 switched. The transistor T53 is from the presence of the comparison signal D or des Reset signal V via the OR element diodes D12 and D13 switched or put in the conductive state. The reset logic unit 64 generates the reset logic control signal T which is fed to the reset time control unit will. When the transistor T54 is switched by the duty cycle control signal M or put into the conductive state is, the reset logic unit 64 generates a positive pulse, i.e. that the reset logic control signal T in passes the high state, as shown in the time segment between times TtI and T12.

309882/1135

The reset time control unit 60 includes an inverting amplifier (transistor T55), a logic circuit (transistor T56) and a flip-flop circuit (transistors T57 and T58). The transistor T55, which forms the inverting amplifier, has its collector connected on the one hand to the B supply line via a load resistor R78 and on the other hand to the blocking diode D4; its emitter is grounded and its base is connected to load resistor R75 of reset logic unit 64 and to the collector of transistor T56. The emitter of the transistor T56 is connected to ground, and its base is connected to the edge logic unit 66 via a limiting resistor R80. The cathode of the blocking diode D4 is connected to ground via the 1-adecondensator C11, and it is also connected to the emitter of the transistor T57 via the limiting resistor R79. The base of transistor T57 is connected to B supply line 90 through base bias resistor C52; it is also connected to the collector of transistor T58. The collector of the transistor T57 is connected on the one hand to the base of the transistor T58 via the load resistor R81 and on the other hand to the slip signal generator 50 via the line 106 and the limiting resistor R5. When the voltage across the capacitor C11 reaches the ^{voltage value set by the resistors R32 and R82 1} , the two transistors T57 and T58 are driven to the on state, whereupon the reset time control signal U1 assumes a low value, while the reset time control signal U2 assumes a high value. Furthermore, the output transistor T59 of the reset switching unit 62 generates the reset signal V, which is in the high state, the voltage on the capacitor C11 runs off from the resistors R82

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and R82 ^{1 reached the} set voltage value. The emitter of the output transistor T59 of the reset switching unit 62 is connected to ground, and its collector is connected to the ramp logic unit 62 via the blocking diode D5 and to the output logic unit 68 via the blocking diode D13.

The ramp logic unit 66 contains three logic circuits with transistors T60, T61 and T62. The emitter of transistor T60 is connected to ground, its base is connected to the Junction of resistors R84 and R85 connected and its collector is connected so that it is across the Terminal 112 and resistor R86 receive the duty cycle control signal M. The emitter of transistor T61 is grounded, its base is with the Sferbindpunkt of resistors R88 and R91 and its collector is connected to resistor R87 and the anode of blocking diode D8 tied together. The emitter of the transistor T62 is at ground * its base is with the connection point of the resistors R89 and R90 and connected to the cathode of the limiting diode D8 and its collector is connected to the line 98 connected to the ramp signal generator 52. The transistor T6o is controlled by the acceleration control signal Q while the transistor T61 is controlled by the oscillator logic signal R, so that the acceleration control signal Q the diode D8 ■ can bias him 'in the forward direction, and that thereby the transistor T62 is controlled in its conducting state. The transistor T62 generates the ramp control signal S when the transistor T61 is in its conductive state State is prestressed; this is the case when the oscillator slip signal R is high, and when the ramp logic signal N in its high state forward biases diode D9. Thus is the ramp logic signal N, which is generated as a function of the acceleration control signal, is sent to the slip signal generator 50.

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couples, and it biases diode D9, but it works. Ramp logic signal S not in its high State over until the oscillator logic signal R is at its high level.

The oscillator logic unit 70 contains a transistor T63, deseen emitter connected to ground, the base of which is connected to the Connection point of the resistors R92 and R93 is connected and its collector is connected so that it receives the duty cycle control signal M through resistor R95. The resistors R93 and R94 are with one End together to earth; the other end of resistor R94 is connected to resistor R95 while the the other end of the resistor R93 is connected to the base of the transistor T63. The resistor R92 is with the connection point of the cathodes of diodes D10 and D11 connected, the anodes of which are connected so that they receive the delay control signal K from the delay switching unit 24 with a variable threshold value or the zero speed control signal I from the zero speed switching unit 58 received. The output signal of the oscillator logic unit 70 is via the limiting diode D14 coupled to output logic circuit 68.

The output logic circuit 68 includes two transistors T64 and T65. The emitter of transistor T64 is connected to ground; its collector is connected to resistor R101. The other end of resistor 101 is across the capacitor CI5 connected to ground. The base of the transistor T64 is connected to diode D12 via the series circuit made up of resistors R96 and R97. The emitter of the

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Transistor T55 is grounded, its collector is on Connection point of resistors R96, R97 and R98 connected and its base is connected to the connection point of resistors R99 and R100. The other The end of resistor R99 is connected to the cathode of diode D14 connected while the other end of the resistor is grounded. The transistor T64 generates the output signal E when the comparison signal D or the reset signal V are coupled to the diodes D12 and D13, if the oscillator logic signal R is not coupled to diode D14 is. The transistor T65 generates the output signal F1, which is coupled to the base of the transistor T64 and prevents this transistor from being driven into its on state. The output signal F1 is coupled to reset logic unit 64 via resistor R73.

The output driver circuit 34 includes a current sensing transistor T66 and a power amplifier transistor T67. The emitter of transistor T66 is on the (B +) - supply line 92 is connected, its collector is connected to the anode of the diode D13 and its base is connected to the connection point between the resistor R106 and the diode D14. Of the The collector of the power amplifier transistor T67 is connected to the (B +) supply line 92, its emitter is connected to resistor R105 and its base is at the anode of the diode Di4. The base of the transistor T68 is connected to the resistor R103 the (B +) supply line 92 is connected and its collector is connected to resistor R105; its emitter is connected to the junction between resistor R106 and diode D14. The output driver signal F

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is then sent to the brake control magnet, to the magnet break detector 78 (error protection IV) and coupled to the error switching unit 80.

Another embodiment of a frequency converter 12 used in the fuel control system described herein can be, and is particularly suitable for the manufacture of an integrated circuit, is shown in FIGS. 5A and 5B. This circuit has the advantage that it allows wide tolerances and that it has a smaller one A number of input and output terminals for the integrated circuit requires a large number of external ones Capacitors is not required. This frequency-to-voltage converter also has the advantage that it can withstand major changes in environmental conditions.

5A shows a frequency-voltage converter, which is particularly advantageous for an embodiment in the form of a integrated circuit is suitable. A sensor signal, for example, the wheel speed in the above Described anti-slip brake control system, operates a square pulse shaper circuit 2a, so that a first pulse train A is generated from square pulses. The speed at which the pulses appear corresponds to the frequency of the sensor signal.

The pulse train A then controls a current source 6a and a dependent pulse generator 4a, which supplies the pulse train C together with the current source 6a. The frequency the pulse train C corresponds to the frequency of the sensor signal, and all pulses of the pulse train C are related their duration and their height are related to one another in such a way that in each impulse there is an essentially constant energy is maintained. This means that the power source 6a

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a first control signal C1 is generated with a predetermined current amplitude so that the pulse generator 4a is actuated and the pulse duration of the output pulse train C is controlled. The current source 6a also supplies a second control signal C2, the amplitude of which is that of the control signal C1
proportionally follows, so that the pulse amplitude of the
Output pulse train C is controlled. The energy in each of the current pulses of the pulse train C is determined by the relationship between the control signals C1 and C2. related to each other that a change in pulse duration
of a pulse of the pulse train C results in a corresponding and opposite change in the pulse amplitude of the pulse, so that the same energy is maintained in each pulse. The converter circuit described keeps the energy of the pulse essentially the same over a wide frequency range, which can be important in applications in which the system is exposed to variable environmental conditions. For example, the anti-skid brake control system mentioned above must be used in extreme temperatures and atmospheric conditions
Working climate conditions exactly.

The integration circuit 8a then generates through
Integrating the regulated pulse train C, the direct current output signal E. By generating a reference direct voltage V ^ gp for the output signal E, which corresponds to a zero frequency of the error signal, the
variable size of the output signal E above the
Reference value calibrated in such a way that it corresponds to the instantaneous frequency
is equivalent to. The higher the frequency of the input signal
is, the higher is the total energy per time period,
with which the integration circuit 8a is operated. The converter described here provides an exact DC current

3 0 9 8 B 2/1 1 3 5

23 3 Uδ4

Representation of a frequency over a broad frequency spectrum, the direct current representation being essentially is very linear from the frequency 0 on, which has not previously been achievable using conventional integrated circuits ttar.

Now let us consider the special design of the rectangular pulse shaper circuit 2a, the dependent pulse generator 4a, the current source 6a and the integration circuit 8a of the Frequency-voltage converter of Figure 5A described in more detail. The square pulse shaper circuit 2a typically includes a first differential amplifier 10a connected in series with a second differential amplifier 12a. A hysteresis circuit 14a provides feedback from the Amplifier 12a to amplifier 10a, thus between the switch-off threshold voltage values of the differential amplifier pair a hysteresis is generated. The square pulse tower circuit 2a works advantageously as a Schmitt trigger for generating the square-wave pulses.

The current source 6a contains current sources 30a and 32a, which generate the control currents C1 and. C2, the control current C2 follows the control current C1 proportionally in terms of amplitude. That means any disturbance or any change in a parameter that causes a fluctuation or a change in the control current C1 just as such a change in the control current C2 has the consequence. So if the control current C1 changes, so that the Pulse duration of the pulse train C is changed, then the control current C2 changes in a compensating manner, so that an inverse change in the pulse amplitude is brought about, the pulses with a substantially constant energy.

3 0 9 8 3 2/1135 ORIGINAL INSPECTED

233K84

The dependent pulse generator 4a includes a difference comparison circuit 18a which is responsive to the control current C1 and to a bias signal Vg. If the voltage of a signal D exceeds the set value _SS from the bias signal V B pulses are generated. A capacitor 16a charged and discharged in a controllable manner by the control current C1 supplies the signal D with a time-dependent amplitude. The pulse generator 4a also contains an exclusive OR circuit 20a for linking the pulse sequences A and B according to the exclusive OR function A Φ Β.

Furthermore, the pulse generator 4a contains a switch 22a which responds to the control current C2 and to the linked signal A Φ B responds in such a way that it generates the compensated pulse train C. The switch 22a preferably consists of one Switching unit in which the signal A Φ B as a switching signal for selective passage of an output signal with a amplitude controlled by the control current C2.

The positive and negative slopes of the signal D depend on the charging or charging. Discharge speed of the Capacitor I6aab, these speeds from Depend on control current C1. Each pulse of the signal D preferably has positive and negative slopes with one essentially the same size. If the voltage of the signal D exceeds the threshold value Vq, then generated the difference comparison circuit 18 the signal B. The pulse trains A and B are then in the exclusive circuit 20a linked so that the signal A Φ Β is generated; this means that a pulse train is generated, which contains pulses when the logic states of the pulse trains A and B are opposite are.

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The switch 22A is used to control the control current C2 to let through depending on the switching signal A Φ Β. The pulse train C consequently contains pulses with a duration controlled by the control current C1 and with a duration controlled by the control current C2 controlled amplitude.

The signal D is also responsive to the above-mentioned current change condition at. When the value of the control current C1 increases, the capacitor 16a charges and discharges with it increased speed. The output signal B of the difference comparison circuit is modified accordingly, where there is a pulse II on v / e which is offset in time with respect to an unmodified position. at the combination of the signals A and B in accordance with the non-equivalence function are therefore pulses of the signal A Φ B generated, which have a reduced duration and therefore a reduced energy.

The control current C2, however, increases in amplitude value as a function of the change, and so if the signal A does A Φ B switches the control current C2 via the switch 22a, the output signal C is generated with an increased amplitude.

The integration circuit 8a contains an arithmetic amplifier 26a with a filter 28a which feeds the signal E back to one of the amplifier input terminals. the other input terminal receives a reference signal Vorn? » which is set to have a DC output signal E is supplied, which corresponds to a frequency with the value 0, if the frequency of the sensor signal has the value 0. The integration circuit 8a further includes an integration capacitor 24a for integration of the compensated signal C.

J 0 9 8 S 2 i 1 1 3 5

733U8A

In Fig.5B is a second embodiment of a frequency converter shown in which a dependent pulse generator with adjustable or programmable monostable Circuits is used. The square-wave pulse shaping circuit 2a, the current source 6a and the integration circuit 8a are designed essentially in such a way as to be Connection with Fig.5A was described.

The pulse generator 4a, however, contains a first programmable one-shot circuit 40a and a second programmable one-shot circuit 42a, which operate as a function of the signal A and the inverted signal A, respectively. An inverter 44a generates the inverted signal A as an input signal füp the monostable circuit 42a. The current source CS1 controls the duration of the output pulse of each of the one-shot circuits 40a and 42a, while the signal A operates the one-shot circuits to provide the pulses. The output signals of the monostable circuits are then linked in the NOR element 46a. The output signal of the NOR element 46a is used to operate the switch 22a, as was described above in connection with FIG.

6 shows a combined differentiating circuit 20, and a combined threshold value switching unit 24, 26 for generating signals that are both acceleration and - Delay conditions in the anti-slip brake control system described here represent. These combined circuits have the advantage that the subsystems 20 and of Figure 1 and the subsystems 24 and 26 of Figure 1 are combined.

'J 0 9 8 R? / ■ 1 1 3 5

/. ο -'- ι -'t ο A

The combined acceleration-deceleration differentiating circuit 20, 22 contains a differentiating amplifier and switch unit 10b for receiving an input signal which is to be mathematically differentiated. In the anti-skid brake control system described in FIG. 1, the signal G is such an input signal, <& s selectively represents the vehicle wheel speed. The signal G v / e is typically in a fixed range of fixed magnitude when the wheel speed of the vehicle falls below a preselected threshold value. It has been shown that maintaining the input signal at a minimum value when operating the vehicle at low wheel speed has advantages when used in an anti-skid brake control system.

During low speed operation, electrical noise tends to disrupt circuit operation, and the pinned area prevents the operation from being interrupted by noise. The differentiating circuit 20, 22 also includes a clamping unit 18b for clamping an uncapped input signal, for example the signal G ^f . A signal B directly proportional to the wheel speed can be used as an input signal together with a bias signal B ¹ to set the minimum signal value below which the input signal B is separated from the differentiating amplifier 1OB or the differentiating amplifier 1OB itself is switched off. The differentiating amplifier and switch unit 10b generates output signals C and D which are dependent on positive and negative amplitude change states of the input signal of the differentiating amplifier 10b, respectively. The acceleration generator 10b works as a function of the signal C, which is a positive amplitude change

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ζ ο

speed, and it generates analog acceleration signals J and P which are proportional to the acceleration conditions of the vehicle wheels.

The delay generator 14b operates in an analogous manner as a function of the signal D, that of a negative rate of change in amplitude corresponds to, and it generates the delay differentiating signal 0 which corresponds to the delay states is proportional to the vehicle wheels.

The differentiating circuit 20, 22 also includes a Integration circuit 16b, which is coupled to the acceleration generator 12b and to the deceleration generator 14b is. The signals E and F corresponding to the acceleration and the deceleration are integrated so that a voltage signal A is generated, which is fed back as an input signal to the differentiating amplifier 10B will. The feedback loop from the integration circuit 16b and from the acceleration and deceleration generators 12b and 14b, respectively, tends to generate the voltage A so to provide that it is the same amplitude as the input signal B to v / e, that of the actual vehicle wheel speed is equivalent to. The generators 12b and 14b supply the integration circuit 16b with the current that is necessary so that the voltage signal A can follow the course of the input signal B. The one to the integration circuit The necessary electricity supplied is actually the amount that the mathematical desired Derivative of the input signal B is the same. The combined switching unit 24, 26 with a variable threshold value includes a dual voltage comparison circuit 20b and a variable reference generator 22b. The comparison circuit 20b monitors the fogging differentiating signal P and the delay differentiating signal 0, and they

3 0 9 8 fl? / 1 1 3 5

ORIGINAL INSPECTED

2 3 7. '.. 8 4

generates output signals that indicate the acceleration values and the deceleration values that one is selected Exceed the threshold voltage value. The reference generator 20b responds to the differential signals 0 and P in such a way that that it supplies the signal H which is used as a variable reference value. The generator 22b includes a memory circuit 23b, which generates the threshold value signal H, so that the comparison circuit 20b a variable threshold value in Dependent on the dynamic acceleration and deceleration input signals is made available. The output signals are generated under the condition that either the differentiating signal 0 or the differentiating signal P the value of the threshold value signal H, which is in the Memory circuit 23b is stored, exceeds. With a decrease in the value of the differentiating signals, the magnitude of the stored signal, the quantity present immediately before the voltage reduction. In general, the variable threshold is equal to the peak input signal minus an offset voltage. The storage of the Signal H and its proportionality to the differentiating signals result in the characteristic of the variable threshold value of the system described here, and allow a quick switching reaction to changed acceleration and Delay conditions.

The combined switching unit with a variable threshold value also includes a deceleration output circuit 24b and an acceleration output voltage 26b, the K signals and Q provide the delay and Display acceleration values that are variable as set by signal H. Exceed threshold.

3 0 9 8 B 7/1135

ORiGINAL INSPECTED

233H84

The combined switching unit 24, 26 with variable threshold value also contains a hysteresis circuit 28b, which couples the deceleration switching unit 24b and the acceleration switching unit 26b to the reference generator 22b. the Hysteresis circuit 28b selectively biases the variable reference generator 22b so that the H signal is included changed size is generated, which is the threshold voltage value the comparison circuit 20b (with generation of a hysteresis) is selectively lowered and a more positive switching effect results when one of the differentiating input signals exceeds the initial threshold voltage H.

From the above description it can be seen that here a control module for processing wheel speed signals has been created in an anti-slip brake control system. In particular, a control module is created has been, which generates a pumping or pulsating brake actuation in an anti-slip brake control system, which in advantageous Generates and processes vehicle speed signals, vehicle wheel speed signals and brake lock signals. In the anti-slip brake control system described, a frequency-voltage converter, a slip and ramp signal generator, a variable threshold value differentiator, and a monostable Frequency control circuit used. Thus, brake control signals are generated, de according to the Braking conditions such as the vehicle speed, the wheel speed, the condition of the road surface, Change the slip conditions of the vehicle wheel speed, etc.

Claims

8 8? / 1 1 3 5 '

Claims (1)

/ 33USA Claims 1 J braking control system for a vehicle for selectively controlling \ y of the depression and release of the brake system of the vehicle in accordance with the selected Bremsbedingunpn, characterized by comparing means (12, 14) generating in dependence on the vehicle speed and the vehicle wheel speed a first control signal when the Relationship between the vehicle speed and the vehicle wheel speed maintains a predetermined condition, detector means (24, 20, 26, 22, 16) for generating a second control signal when the vehicle wheel speed has a first value and for generating a third control signal when the vehicle wheel speed has a second value, signal generating means (28, 32) for generating a fourth control signal proportional to the selected conditions of the vehicle wheel speed after the first and second values have been reached, and a logic circuit (18) which selectively responds to the second, third and fourth Tax si The signal is responsive to release the vehicle brakes when the predetermined condition and the first value are reached and to sequentially engage and release the vehicle brakes when the predetermined condition and the second value are reached. 2. Brake control system according to claim 1, characterized in that the predetermined state is a selected differential speed is between the vehicle speed and the vehicle wheel speed. 3. Brake control system according to one of claims 1 or 2, characterized in that the first and second values are respectively selected deceleration and acceleration values of the vehicle wheels. 30 9882/1135 ο ο ι / ς /. ο ο ι 'τ ο -f Brake control system according to one of the preceding claims, characterized in that the selected states the Deceleration and acceleration values of the vehicle wheels are. 5. Brake control system according to one of the preceding claims, da & gek ,, that the comparison device has a first circuit arrangement (12) for generating one of the vehicle wheel speed proportional signal, a second circuit arrangement (50, 52) for generating one of the vehicle speed proportional signal and a comparison circuit (54) for comparing the vehicle wheel speed with the vehicle speed for generating the first control signal. 6. braking control system according to claim 5, characterized in that that the first circuit arrangement has a converter for converting signals of a first format which the Vehicle wheel speed are proportional, in signals of a second format that are proportional to the vehicle wheel speed are, contains, 7. Brake control system according to claim 6, characterized in that the converter is frequency-modulated signals in amplitude-modulated Converts signals. 8. Brake control system according to claim 7, characterized in that the converter has a square wave generator (44), a twofold Differentiating circuit (46) and an integration circuit (48). 9. Brake control system according to claim 7, characterized in that the converter has a rectangular pulse shape circuit (2a) 309882/1135 ο O O I / Q / which responds to the frequency-modulated signal so that it generates a first square pulse train, the frequency of which is related to the frequency of the frequency-modulated signal and its amplitude between first and second states switches that a pulse generator (4a) is provided, which generates a second pulse train the first pulse train responds, each pulse of the second pulse train from a change in state of the first Pulse sequence is determined, and has a selectively programmed duration that a first current generator arrangement (6a) a first signal to the pulse generator for controlling the pulse duration of the pulses emitted by this pulse generator and a second signal having an amplitude directly related to the first signal provides that a switching arrangement (22a) responsive to the second pulse train and to the second signal so that a third Pulse sequence is generated directly proportional to the frequency, the amplitude of the third pulse sequence being dynamic with the first signal related second signal is controlled so that a pulse duration change of the second Pulse train with an amplitude change in the third pulse train is offset so that all pulses of the third Pulse train are generated with an essentially equal energy, and that an integration arrangement (8a) is provided which is responsive to the third pulse train to provide a direct current signal whose Amplitude is related to the frequency of the frequency-modulated signal and is related to this frequency changes. 10.Brake control system according to claim 9, characterized in that that the pulse generator (4a) has a monostable generator circuit (40a) for generating pulses in response to 3 0 9 8 8 2/1135 233H84 contains a change in state of the first pulse train with a duration controlled by the first control signal. 11. Brake control system according to claim 10, characterized in that the pulse generator (4a) also has a circuit arrangement (44a) for inverting the first pulse train contains that a second monostable generator circuit (42a) is provided for generating second logic pulses as a function of the inverted first pulse sequence, and that a NOR gate (46a) is provided for combining the first and second logic pulses in accordance with the NOR function in order to generate the second pulse train. 12. Brake control system according to claims 9 to 11, characterized characterized in that the integration arrangement includes a capacitor (24a) derived from the second current source arrangement is selectively actuated, and that the integration arrangement has an arithmetic amplifier coupled to the capacitor for supplying the DC signal. 13. Brake control system according to claim 7, characterized in that that the converter contains a square-wave pulse shaping circuit (2a) which responds to the frequency-modulated signals responds so that it generates a first square pulse train having a time shift that corresponds to is related to the frequency of the frequency-modulated signal and has an amplitude that is between first and second states switches that a pulse generator (4a) responds to the first pulse train so that it generates a second pulse train, each pulse having a time shift that corresponds to a change in state is related to the first pulse train and 309882/1135 r "~> -j ι ■■ 'ο / , 1 O v- -t ■ -; has a selectively programmable pulse duration that a logic circuit arrangement (20a) is a link of the first and second pulse trains according to the non-equivalence function, so that a third pulse train is generated whose pulses one of the time difference between the first and second pulse trains determined Have duration, and that an integration arrangement (8a) is included, the third pulse train to one Integrated direct current signal, the amplitude of which is related to the frequency of the frequency-modulated signal and changes with frequency. 14. Brake control system according to claim 13, characterized in that the pulse generator (4a) has a memory device with a capacitor (i6a) containing a controlled Charging and discharging speed has that a differential comparison circuit (18a) for generating the second pulse train as a function of the relationship between the one predetermined threshold charge on the capacitor is provided that a Current source ("32a) provides an" output signal which is adapted to the size of the output signal of the first current source is that a switching unit (22a) as a function of the fourth pulse train switches the output signal of the second current source, so that a fifth pulse train is formed whose pulses are characterized by the pulse duration determined by the first current source, the amplitudes of these pulses being determined by the second current source, and that an integration arrangement (8a) with a capacitor as a function of Output signal of the second current source integrates the fifth pulse train and generates a direct current output signal, whose amplitude is related to the frequency of the frequency-modulated signal and is related to this frequency changes. 309882/1135 23 31 15. Brake control system according to one of claims 5 to 14, characterized in that the comparison circuit has one to the contains the first circuit arrangement (12) connected slip signal generator (50) which is based on the vehicle wheel speed proportional signal responds so that it selectively generates a slip signal proportional to this signal. 16. Brake control system according to one of claims 5 to 15 » characterized in that the second circuit arrangement includes a ramp signal generator (52) for generating a die Contains ramp signal representing wheel speed. 17. Brake control system according to claim 16, characterized in that the comparison circuit (54) to that of the wheel speed proportional signal generated by the first circuit arrangement (12) and the signal generated by the ramp signal generator (52) Generated ramp signal is responsive, and that the first control signal is a slip switch signal having a predetermined Relationship between vehicle wheel speed and vehicle speed and an activation of the brake control device to prevent the vehicle brake application causes. 18. Brake control system according to claim 17, characterized in that the predetermined relationship is the condition that the the size corresponding to the wheel speed is smaller than the size corresponding to the vehicle speed. 19. Brake control system according to claim 17 or 18, characterized in that the ramp signal generator (52) has a Latch means (122b) which selectively stores the slip signal that a charge control arrangement (124b, 126b) is responsive to a ramp stop signal indicative of a first condition of the vehicle wheels in which the deceleration value of the vehicle wheels is greater than a previous 3 0 9 8 8? / 1 1 3 5 2 3 3 U S fourth is selected so that the latch device can selectively discharge at controlled rates becomes when the delay value is less than the preselected value and that the discharge of the latch device selectively prevented when the delay value exceeds the preselected value. 20. Brake control system according to claim 19, characterized in that that the ramp signal generator (52) is responsive to a slow ramp signal indicative of a second condition of the vehicle wheels reproduces, in which the deceleration value of the vehicle wheels is smaller than the preselected value, so that the Latch device (122b) is discharged at a first controlled rate whereby the charge control arrangement (124b, 126b) blocks a discharge of the slip signal arrangement as a function of the ramp stop signal, discharging the storage device at a first controlled rate in response to the slow ramp signal and further discharges the storage device at a second controlled rate in the absence of the ramp hold signal and the slow ramp signal. 21. Brake control system according to claim 20, characterized in that the second state of the wheels is present when the Vehicle deceleration value is below a preselected value. 22. Brake control system according to claim 20 or 21, characterized in that the Lad3steuerungssystem a programmable Includes current generator (124b) that responds to the ramp hold signal and responsive to the slow ramp signal to generate the controlled discharge values, and that a ramp logic arrangement (126b) the slow ramp signal 3 0 9 8 8 2/1135 ORIGiNAL INSPECTED • J 87 - 233U84 and optionally to the power generator for dynamically programming the power generator into the couples these controlled discharge values resulting states. 23. Brake control system according to claims 5 to 22, characterized characterized in that the comparison circuit (54) includes hysteresis circuitry (36b) shown in Depending on the first signal, a first hysteresis signal proportional to the first signal, and that a differential amplifier (132b) is provided which is responsive to the first hysteresis signal and responsive to the ramp signal so that it compares these signals and selectively the slip switch signal generated. 24. Brake control system according to claims 15 to 22, characterized in that the slip signal generator (50) contains a slip logic (118b) which selectively generates a logic signal as a function of the 'slip switching signal and the ramp hold signal, and that a differential amplifier (116b ) selectively generates the slip signal as a function of the first signal and the logic signal, the slip signal logic biasing the second amplifier arrangement in a selected manner so that the slip signal is electrically isolated from the signal storage device. ¹ 25. Brake control system according to one of the preceding claims, characterized in that the detector devices a delay value device (20) for generating a contain the deceleration value of the vehicle wheels proportional signal that a Delay threshold device (24) is included, 309882/1135 which generates the second control signal when the deceleration value of the vehicle wheels reaches the first value, and that the Comparison circuit (12, 14) is dynamically controlled proportional to the deceleration value of the vehicle wheels, so that the selected ratio between the vehicle wheel speed and the vehicle speed as a function of the wheel speed acceleration value is controlled dynamically. 26. Brake control system according to one of the preceding claims, characterized in that the detector means a Acceleration value device (22) for generating a the acceleration value of the vehicle wheels proportional signal that in the detector devices Acceleration threshold means (26) included which generates the third control signal as a function of the acceleration value signal when the acceleration value of the vehicle wheels reaches the second value, and that the comparison circuit (12, 14) is dynamically controlled in proportion to the acceleration value of the vehicle wheels is so that the selected ratio between the vehicle wheel speed and the vehicle speed as a function is dynamically controlled by the wheel speed acceleration value. 27. Brake control system according to claim 25 or 26, characterized in that that the deceleration value and / or acceleration value devices (20, 22) have a differentiating circuit contain. 28. Brake control system according to claim 27, characterized in that the differentiating circuit circuit arrangements (102c, 100c, 112c, 110c) which, as a function of a signal representing the vehicle wheel speed, enter the Generate a signal representing the rate of change of the vehicle wheel speed, and that circuit arrangement * ^ 104c, ., J b B *, / I I J ü ORIGtNAL INSPECTED 114c,) are included that depend on the rate of change of the vehicle wheel speed signal representing the circuitry (102c, 10Oc, 112c, 110c) selectively control when the representing the rate of change of the vehicle wheel speed Signal reaches a selected fourth. 29. Brake control system according to claim 28, characterized in that the circuit arrangements (104c, 114c) the amplitude the speed of changing the vehicle wheels selectively change the representative signal. 30. Brake control system according to claim 28 or 29, characterized by a direct current value detector and speed switching unit (16), which represent a change speed of the vehicle wheels as a function of a Signal, a switching signal for the circuit arrangements (104c, 114c) and the selected value to the circuit arrangements Returns (102c, 100c, 112c, 110c). 31. Brake control system according to claims 28 to 30, characterized characterized in that the circuit arrangements (102c, 100c, 112c, 110c) are dependent on a specific rate of change of the vehicle wheel speed representing Signals selectively generate a signal consisting of a selected constant value. 32. Breras control system according to claim 31, characterized in that that the signal consisting of a selected constant value is the signal representing the rate of change of the vehicle wheels. 33. Brake control system according to one of claims 28 to 32, characterized in that the rate of change of the vehicle 30988 2/1135
- '-' i ''^; SO ORIGINAL INSPECTED wheel speed for an acceleration of the vehicle wheels is positive, the selected value representing a wheel acceleration having a predetermined value is present, and that the rate of change of the vehicle wheel speed with a deceleration of the vehicle wheels is negative, the selected value representing the deceleration of the wheels with a predetermined value. 34. Brake control system according to claim 33, characterized in that a positive inclination detector (110c) for Festetellen the positive inclination and a negative inclination detector (100c) are provided to determine the negative inclination. 35. Brake control system according to one of claims 28 to 33, characterized in that the signal representing the wheel speed of the vehicle is a variable DC signal is. 26. Brake control system according to one of claims 1 to 25, characterized in that the detector devices Contain differentiating circuits (20, 22) which respond to an input signal representing the vehicle wheel speed respond and deliver a first differentiating signal that reflects wheel acceleration conditions, and generate a second differentiating signal which Wheel deceleration conditions v / ieder, and that threshold circuits (24, 26) are provided which one have single variable threshold and respond to the differentiating signals so that they are in selectively provide first and second output signals when the differentiating signals are variable Exceed threshold value, the output signals generated at wheel acceleration and deceleration values 309832/1135 _0RIQWAL ".sPHCTSD 2 3 2 U £ 8 different from the value below which the signals are made inactive. 37.Brake control system according to claim 36, characterized in that that the output signals are activated at a lower acceleration and deceleration value than at the value at which they are made inactive. 38. .Brake control system according to claim 36 or 37, characterized characterized in that the differentiating circuits also generate a third differentiating signal whose current value represents the vehicle wheel acceleration. 39. ^Br 9msregelsystem according to claim 38, characterized in that the differentiating circuit (20, 22) contains a differentiating amplifier and switching arrangement (10b) which is dependent on a signal representing the vehicle wheel speed and on a feedback signal, the size of which reflects a value of the vehicle wheel speed which gradually approaches the value indicated by the input signal corresponding to the vehicle wheel speed, generates an acceleration differentiating signal and a deceleration differentiating signal that an acceleration current generator (12b) generates first and third differentiating signals corresponding to the vehicle wheel acceleration values in response to the acceleration differentiating signal, that a deceleration current generator (14b) as a function of the deceleration differentiating signal generates the second differentiating signal which corresponds to the vehicle wheel deceleration value, and that an integration circuit (16b) is dependent on the acceleration and deceleration current generators selectively the mathematical integral of the acceleration and deceleration differentiating 309882/1135 2 3 3 U S A delivers signals, thereby creating the feedback signal is produced. 40. Brake control system according to claim 39, characterized in that the differentiating circuit (20, 22) also contains a clamping circuit (18b) which, depending on a bias signal, makes the differentiating amplifier inactive in a selective manner with regard to the input signal when the size of the bias signal is the Exceeds the size of the input signal. 41. Brake control system according to .Anspruch 40, characterized in that that the selected inactive state is when the vehicle wheel speed falls below a preselected value sinks. 42. Brake control system according to one of claims 39 to 42, characterized in that the current generator is a positive generator means for generating a positive differentiating signal contains that the mathematical Derivation of the input signal indicates when the input signal has an increasing amount of change in amplitude has, and that the current generator has a negative generator device for generating a negative Contains differentiating signal that indicates the mathematical derivative of the input signal when the input signal has a decreasing amplitude change value, the positive and negative differentiators are connected to the integration circuit. 43. Brake control system according to one of claims 36 to 42, characterized in that the circuit unit with variable threshold value a voltage comparison 309882/1135 233U84 and switching unit (20b), the dependence on the acceleration and deceleration differentiating signals generates first and second output switching signals when the Acceleration and deceleration differentiating signals exceed the variable threshold that a variable threshold Reference generator (22b) responsive to the acceleration and deceleration differentiating signals Output means contains which supplies a reference signal to the voltage comparison and switching unit that the output hold signals are generated when the differentiating signals exceed the reference signal in terms of magnitude, and that a storage capacitor (23b) is connected to the Reference generator is coupled for storing the reference signal. 44. Brake control system according to claim 43, characterized in that the switching unit with a variable threshold value a delay output circuit (24b) which is dependent on the voltage comparison and switching unit supplies the first output signal, and that the switching unit with a variable threshold value an acceleration output circuit (26b), the function of the voltage comparison and switching unit provides the second output signal. 45. Brake control system according to claim 43 or 44, characterized characterized in that the threshold variable switching unit includes a hysteresis circuit (28b), which depends on the acceleration and deceleration output circuits selectively biases the variable reference generator to bias the reference signal and thereby the variable Reference value is lowered. 309882/1135 46. Brake control system according to one of claims 36 "to 46, characterized characterized in that the variable threshold switching unit is responsive to the differentiating signal responds to generate a differentiating switch signal ·. : is that the mathematical derivative of the variable Input signal exceeding the threshold value. 47. Brake control system according to one of the preceding claims, characterized in that the detector devices a DC value detector (16, 56) which generates two signals that correspond to the wheel speed signal at one preselected direct current value are proportional, whereby the direct current value detector undesired voltage curves of the wheel speed signals preventing them from reaching the Signal generating devices (28, 32) and the logic circuit ■ (18) arrive. 48. Brake control system according to one of the preceding claims, characterized in that the signal generating devices (28, 32) contain an oscillator circuit (28) for ₍ generating a signal proportional to the rate of change of the vehicle wheels, and that they contain a variable pulse generator (32) which one of the Change speed of the vehicle wheels proportional ratio signal generated. 49. Brake control system according to claim 48, characterized in that the oscillator circuit (28) is a programmable Has oscillation frequency that depends on an input signal that a certain state of the vehicle wheels indicates that a first vibration signal is generated, 3 0 9 8 8 2/1135 _omm M INSPECTED 2331 the frequency of which expresses the particular state, and that the pulse generator circuit (32) depending on the first oscillation signal, a second oscillation signal in a selected manner, generated, which a first pulse train and has a programmable duty cycle reflecting the first state, the second Vibration signal a selective actuation of the brake control system in repeated pulsating V / eise to Reduction of the vehicle wheel speed operated. 50. Brake control system according to claim 49, characterized in that the oscillator circuit (28) responds to a further input signal responds, which represents another state of the vehicle wheels, so that the oscillator circuit in selected Way blocked and essentially a zero frequency is generated during the other state. 51. Brake control system according to claim 50, characterized in that that the particular condition is the acceleration value exceeding a predetermined value and that the other State is the delay value that exceeds a predetermined value. 52. Brake control system according to claim 50 or 51, characterized in that the oscillator circuit (28) has a Oscillation frequency programming circuit (100b) contains, depending on the input signals of the oscillator circuit (28) in a selected manner a variable Provides bias signal, and that a value-dependent 0szillatorkreis (102b) is provided, whose Vibration frequency depends on the bias signal so that a first vibration signal is generated that indicates the acceleration value of the vehicle wheel speed. 30988 2/1135 233U84 53. Brake control system according to one of claims 50 to 52, characterized in that the pulse generator circuit (32) contains a voltage value detector (104b) which is dependent on the first oscillation signal supplies a detector signal in a selected manner, if the first oscillation signal exceeds a preselected threshold value, and that a flip-flop (106b) is provided, which delivers the second vibration signal depending on the detector signal, the one Contains a series of pulses indicating the acceleration, the flip-flop the second oscillation signal in one delivers first logic state when the first oscillation signal is less than the preselected fourth while it delivers the second oscillation signal in a second logic state when the first oscillation signal exceeds the preselected value. 54. Brake control system according to one of claims 50 to 53, characterized in that the signal generating devices (28, 32) contain logic circuits that are dependent on the second oscillation signal, the other Generate an input signal and a signal indicating the value zero of the wheel speed, a third vibration signal, that of the second vibration signal in the absence of actuation of the second input signal or in the case of one The signal indicating zero wheel speed is proportional, the third vibration signal being the selective Activation of the brake control device in a pulsating manner to reduce the vehicle wheel speed causes. 55. Brake control system according to claim 54, characterized in that that the third vibration signal in a selected way 309882/1135 233H84 contains second oscillation signal which has pulses, and that an additional pulse is provided which depends on the other state of the vehicle wheels. 56. Brake control system according to one of the preceding claims, characterized by resetting devices (30) for Generating a reset signal for resetting the vehicle brake control system when the relationship between the vehicle wheel speed reaches a second predetermined state. 57 · Brake control system according to claim 56, characterized in that that the first predetermined condition is reached when the vehicle wheel speed approaches zero and that the second predetermined state is reached when the vehicle wheel speed approaches the vehicle speed. 58. Brake control system according to one of the preceding claims, characterized by fault monitoring devices (36) to monitor the operation of the vehicle brake control system and to generate visual and audible indications of Errors in the system to prevent system damage from overcurrent. 59. Brake control system according to one of the preceding claims, characterized by an on the logic circuit (18) responsive output circuit (34) for selectively controlling the activation and the release of the braking system of the Vehicle corresponding to the predetermined state, the first and second fourth and the selected states. 60. Brake control system according to one of the preceding claims, characterized in that the logic circuit (18) controls the braking system during a deceleration of the vehicle wheels 309882/1135 233H34 triggers, and successively actuated and released again during the acceleration of the vehicle wheels. 61. Brake control system according to one of the preceding claims, characterized in that the logic circuit (18) has a Contains ramp logic arrangement (66) which generates signals as a function of the third and fourth control signals, the selected speed states of the vehicle wheels with respect to the vehicle speed for controlling the second signal devices represent. 62. Brake control system according to claim 21, characterized in that the logic circuit (18) has a reset logic arrangement (64) contains the dependent on the signals generated in the ramp logic arrangement and on the output signals of the system generates reset signals for resetting the system when the relationship between the Vehicle wheel speed and the vehicle speed reaches a predetermined value. 63. Brake control system according to one of the preceding claims, characterized in that the logic circuit is an oscillator logic arrangement (18), which generates signals as a function of the second and fourth control signals, which represent selected speed states of the vehicle wheels when the first and second values are reached are. 309882/1 135 Blank page