DE2325687C3 - Method and device for determining the order in which several requests of various types made by several units of a data processing system to a unit of the data processing system are processed by a queue control - Google Patents

Description

demands from both units the unit with the lower priority with the help of a first qualifier the allocation of a minimum amount of memory cycles at the expense of the unit with the higher Priority demands and the unit with the higher priority with the help of a second qualifier the Allocation of chained memory cycles at the expense of the lower priority unit requires that the queue control if there are requests from both units at the same time, a connection is established with the unit of lower priority if the first qualifier is zero and before one Traffic has occurred with the higher priority unit, this previous traffic being none has requested chained memory cycles and that queuing when there are requests of both units establishes a connection with the unit of higher priority if the first Qualifier is 1, or if the first qualifier is 0 and before that there is no communication with the unit higher Priority or communication with a chain request was given.

If the requirements are placed on an input-output processor, then the device according to the invention for carrying out the method is characterized by a queue control with a request decoder, which distinguishes between interrupt requests and data requests coming from the peripheral devices, with a first register for the interrupt requests a second register for the data requests, with a first mask register assigned to the first register, with a second mask register assigned to the second register, with a first and second coincidence circuit which only forwards the requests for which the assigned mask positions are set in the mask registers , with a logical network to which the interrupt requests and data requests selected by the mask register are fed and which interrupt requests and only in the event that no interrupt requests present, forwards data requests, with a priority network that selects a request from the number of interrupt requests or data requests, with a comparison circuit that compares the numbers of the connection points for the input-output commands with the numbers of the connection points of the requests selected by the priority network and at N <Ξ Pl emits a first signal and when N > P 1 a second signal and with a combinatorial network that emits a signal at a first output when mask commands are present, which at its second output when input-output commands are selected Outputs a signal which outputs a signal at a third output when interrupt requests are selected, and which outputs a signal at a fourth output when data requests are selected

Other developments of the invention emerge from the subclaims.

The invention is based on exemplary embodiments that are shown in the figures, on explained it shows

Fig. 1 is a block diagram of the processing units a data processing system,

F i g. 2 a queue control of the input-output processor,

F i g. Figure 3 is a work memory coordinator queue control.

1 shows an input-output processor EAP which, in the example, is connected to two external units PE1 and PE 2 and, on the other hand, is connected to a main memory coordinator AKO . The main memory coordinator A KO is on the other hand on a central processor ZP. It controls the traffic of the input-output processor EAP and the central processor ZP with a main memory / iSP. In Fig. 1, queues can arise in two places. The first position is the input-output processor EAP, which requests from the external devices PE1 and PE2 and, on the other hand, from the central processor ZP can be made. Another queue arises at the main memory coordinator AKO if there are requests from the central processor and the input-output processor at the same time.

In the following, the queue at the input-output processor will first be discussed.

Peripheral units make interruption and data requests to the input-output processor EA P. Both types of requests are aimed at the input-output processor, but logically means the interrupt request access to the central processor and the data request access to the main memory. This does not exclude the possibility of access to the main memory while an interrupt request is being processed. The total of the interrupt requests at the input-output processor EAP is, on average, significantly smaller than the total of the data requests. It is a prerequisite that the peripheral units work predominantly in block traffic.

It is determined that the interrupt requests should have a higher priority than the data requests. This ensures that interrupt requests are serviced more quickly than data requests. This favors the triggering of an alarm in the process computer in the central processor, facilitates the construction of large subscriber computer systems and also contributes to good utilization of the total data rate of the input-output processor. If control registers are kept in the main memory during data traffic, the processing time of an interrupt request is usually much shorter than that of a data request. Requests which are given by the central processor ZP to the input-output processor EAP are input-output commands for initiating block traffic and for data transmission in both directions. It should be possible that the data traffic is not only controlled peripherally, but can also be controlled centrally from the central processor. Commands to initiate traffic are similar to interrupt requests. In contrast, transfer commands for data transfers are related to data requests. The total number of initiate commands is, on average, equal to the total number of interrupt requests. The total number of transmit commands can at least sometimes be very much greater than the total number of interrupt requests, but still a great deal

less than the total number of data requests. Transmission commands are preferred for process computers in dealings with process controls.

On the basis of the foregoing, it is specified that input-output commands versus data requests how interrupt requests are handled. Furthermore, in the event of competition between input-output commands and requirements the command have priority at the same connection point. Input-output commands and interrupt requests Apart from the above-mentioned case, they are treated as requirements of the same type.

Thus, the requirements are not only based on the unit from which they are issued, but also rated and prioritized according to their type.

Furthermore, the queue control can be designed so that interruption and data requests can be masked separately.

In Fig. 2 shows an embodiment of a queue control of the input-output processor. PA denotes the peripheral connection point via which the data or interrupt requests from peripheral devices are sent to the queue control. The lines going out from the peripheral connection point PA are assigned to different channels of the input-output processor. The interface to the main memory coordinator AKO is denoted by SN.

Interrupt requests and data requests from peripheral devices are fed to a request decoder Dl. It determines the type of peripheral requests and feeds the requests either to a request register for interrupt requests AR1 or to a register for data requests AR1 . A mask register Ml or Ml is assigned to each request register AR 1 or AR 2. Requirements only become effective in the downstream circuits if the mask positions assigned to the requirements are set in the mask registers. This selection is made with the help of coincidence circuits t / l and Ul. Each mask register can be loaded by a specific mask instruction. Such a mask command is fed to the command register Bl and decoded in the command decoder Dl. The command decoder D1 emits signals D 21. D 22 which set the mask registers Ml and M 2. The setting of the mask registers Ml, M2 can be done by a system program, but it can also be carried out via a circuit arrangement in the input / output processor which set or not set certain positions in the mask registers AfI and Ml due to faulty peripheral devices.

A logical network of elements 1/3, i / 4, 01, 05, 06 ensures that data requests are only sent to the priority network Pi? be performed when there are no interrupt requests. By t / 3 and i / 4 conjunctions between the output signals of the coincidence circuits t / l or i / 2 and 505 or 505 or 505 are carried out, in 01 exclusive disjunctions of the output signals of 1/3 and 1/4. The priority network PR can be set up in a known manner. For example, the priorities of the individual peripheral devices can be defined among one another by the priority network PR. The only decisive factor is that a connection point is selected by the priority network PR. The output signal of the priority network Pi? is denoted by P1.

Input-output commands and mask commands are passed from the command register Bl to the downstream command decoder Dl . Each command names the number of the connection point at which the transmission is to take place in a number register NR. For this reason, signals D 23 and D 24 from the command decoder Dl are fed to the number register NR. The number register NR outputs the output signals N 1.

A comparator V1 provides the information as to whether the number of a connection point mentioned in the command is less than, equal to or greater than the number of the connection point with the highest priority peripheral request. A high number should correspond to a low priority. If the number of a connection point mentioned in the command is less than or equal to the number of the connection point via which the data or interrupt request comes (Nl Z. Pl), then the comparator V1 emits a signal at its first output. If, on the other hand, the number mentioned in the command is greater than the number of the connection point of the data or interrupt request (N 1 ~> P 1), a signal appears at the second output of the comparator V1.

The output signals of the comparator V1 are fed to a combinational network K. The combinational network also receives the signals D 21, D 22, D 23, D 24 and the output signals 505 and 506 of the elements 05 and 06. D 23, D 24 are output signals of the command decoder Dl when input-output commands are present. The combinatorial network K now decides which of the queued requests will be processed first. According to this decision, one of the outputs £ 1, El, El ·, E4 is activated. The queue control has thus determined which of the pending requests will be processed first by the input / output processor.

The decision of the combinatorial network K is based on the following criteria:

If there are mask commands, all other requests must wait. The combinatorial network K emits a signal at the output £ 1. It applies

Input-output commands prevail if there are no peripheral requests, or if the number Nl of the connection point mentioned in the command is less than or equal to the number of the connection point with the highest priority peripheral request, or if the aforementioned number relation is not met and only Pending data requests. It applies

E2 = (D23 + D24) (3Ü5-5Ü5)
+ (505 4- 506) (Nl <Pl)
+ 5Ü5-5O6- (JV1> P1).

Interrupt requests then prevail and at the output E3 of the combinatorial

609 653/275

Network K , a signal is emitted if £ 3 = (D 21 + D22 + D 23 + £> 24) 505 + (D23 + D24) 5Ό5 (/ V1> P1)

Data requests are only processed if applies

£ 4 = (D21 + D22 + Ü2i -t- ua4) ■ S65 ■ S06 Then a signal is given to £ 4.

selects - then a signal appears at the output Ml - or requests from the input-output processor - then a signal appears at the output ο iT ^Out g ^a "g MO a signal is then emitted if the memory coordinator has no request. In addition, there are two Flip-flops £ nn Γ provided. The flip-flop FFK is set when a request of the input Ä ^{e r0ZeSSOrS from} 8 ^eab * t has been made in the

Signals that occur at these outputs.

The combinatorial network could e.g. B. by a suitably masked, integrated read-only memory be realized.

Depending on whether a command or a request is being processed, the number of the connection point to be controlled results from a different register. When executing an instruction from the register NR, when executing a request from the priority network PR.

If requests are made to the main memory coordinator A KO by the central processor ZP and the input-output processor EAP , then the following applies:

Maintaining the simultaneous work between programs and input-output traffic and the Slight volatility of external data (punch card) requires the input-output processor to be preferred. The rapid servicing of vital alarms by the central processor demands one Central processor preference.

The requirements of the central processor and the input-output processor are therefore each identified by an additional qualifier (Q1, Q2) . These qualifiers are assigned the following meanings:

Ql = I: the central processor waits until the input-output processor EA P no longer uses any memory cycles.

Ql = O: the central processor demands the allocation of a minimum amount of memory cycles at the expense of the input-output processor EAP.

Q2 = 1: the input-output processor EAP requests chained memory cycles.

Q 2 = 0: the input-output processor EAP dispenses with chained memory cycles.

The central processor can easily derive the qualifier Q1 from the status flip-flops that are usually present anyway. The qualifier Q 2 is generated when the input-output processor EAP requires memory cycles in immediate succession.

An exemplary embodiment of the queue control of the main memory coordinator is shown in FIG. 3. The interface to the input / output processor is designated EAPS, the interface to the central processor is designated ZPS. A combinatorial network JCl, which z. B. can be designed as a read-only memory, the qualifier Q1 is fed from the interface ZPS, the qualifier Q 2 from the interface EAPS. The requirements A1 of the central processor or the requirements A1 of the input-output processor are fed to a register AB and from there to the read-only memory Kl.

rW "r, Ar · - gcMji / i, if an error

3, ^de _t ^S input c-output processor processed signal " ^Sl 8 ^nalef l ™ ^d ™ are control

The state of the outputs MO, Ml, M2 at Al, A2, Ql, Q2, K and V can be read from. The table has those in 7 ι } ^S P ^old - ¹ I of the first column are * o t 1 ° ν ^lh y merged ^through ™. In the second column

Point /? N Η ⁸⁶ ?, ^{The request} «" to A 1 at time N, in the third Snalt * H ₃ * presence of the ^A "

one

. - the eighth column of the

of _a n _O "κ ^from 8 ^to g ^e ^ O to M2, in the presence SpalteTef! Γ ⁶ ', ^A 8 ^to 8 ^s g ^rö SEN, in the ninth column of the state of the flip-flop FFA" at the time ^{υπ Α In the} tenth column, the state of the t-FV at time N is shown.

35

40

45

50

1 0 0 XXX

2 0 1 * 0 0

3 0 1 X 0 1

4 0 1 X 1 0

5 0 1 X 1 1

6 1 0 XX 0

7 1 0 XX 1

8 110 0 0

9 110 0 0

10 1 1 0 0 1

11 1 1 0

12 1 1 0
13th

1 1 0 1 ι
1 1 1

15 1 1 l

X X X

1
0
1

1 1
0 0
0 1
1

ο χ χ ι χ χ

M 0 0 0 M 2 0 1 M 2 0 1 MM

2 1 1 2 1 1 1 0 0

M 2 0 1 M 100 M 2 0 1 M 2 1 1 M 100 M

M M

2 1 1 2 0 1 2 1 1

60 —W, VYWJLlU JN.CXUC rtilJAJl-

haltnk _se "" ^ n? ^{2 to 5} g ^{zei en} <Ver Se-AuSabe'Pmt ^ request from Eingabenu7Se "AS ^Or ^ ¹¹⁶⁸ * - ^{the lines 6 u" d} 7 when Zä ΪΑSSVgJ g ^ntraI P-SSOR confess JZ- j ^{bK 15 'when} the Input-

-> r and from the central processor equal -'S ^{en an de} ° work memory coordination

ISS * t ™ ^{of column 81} ^ ^ab ^

which output MO to M2 activates, which find-

thus becomes nma ^ SS ? ^K ***? <** <& * & which requirements run SÄ ^ ^arbeltet ^ W, the type of Ao-

Whom? de? 7 ♦ Prehistory evaluates ^{the input process ^ ™ * pr (} ^ ^{processor Λλαά} the input output to successive Entecaei-

ZO DO /

Application times for a certain period of time always place requirements with the qualifications Ql and Ql - 0 at the same time, then alternate, controlled by one of the two status flip-flops, the memory allocations to the two units in a ratio of 1: 1. This ensures that the input-output traffic is not impaired too much or the central processor is not favored enough.

The method according to the invention has the following advantages: Incorrectly functioning peripheral units can be rendered ineffective without further damage to the data processing system if the assigned mask position is set accordingly in the mask register. This allows the Interrupt and data requests are no longer processed by the peripheral unit.

Maintenance on the running system is possible because the mask register allows for a check to be made Device the interruption and data requirements

can be suppressed. The setting of the mask register can be done by special instructions can be entered into the system on the operating sheet recorder.

Stop commands to the peripheral units are unnecessary, since again with the help of the mask register di < Interrupt and data requests from peripheral units can be suppressed.

The response time to peripheral interruption events is shortened because interruption requests are preferred over data requirements.

The degree of employment of the periphery and the utilization of the total data rate increase, since Be Missing and interrupt requests are preferred over data requests.

The reaction time to peripheral interruption events can be adjusted in certain central processor booths are guaranteed.

For this purpose 2 sheets of drawings

Claims (10)

Patent claims: 1. Procedure for determining the sequence, in which several of several units of a data processing system placed on a unit of the data processing system requests of different types are processed by a queue control, in which the unit that the requests are made is an "> input-output processor and the other units are peripheral devices and are a central processor and the requirements are mask commands, input-output commands, data and interrupt requests, ¹ S characterized in that the queue control, according to the type of request, first processes the mask commands, then the interrupt requests from the peripheral devices or the input Output commands and finally the data requests of the peripheral devices, and that if there are several requests of the same type, these requests are processed in a known manner according to the type of requesting unit. 2. A method for determining the order in which several of several units of a data processing system placed on a unit of the data processing system requests of different types are processed by a queue control, in which at least two units can make requests to a memory coordinator at the same time, characterized in that the queue control processed the requirements of the units according to the type of requirements previously completed and in a known manner according to the priorities of the units of defined qualifications (Q) . 3. The method according to claim 1, characterized in that the queue control the processing of input-output commands that carry data traffic via connection points request whose number is less than / equal to the number of the connection points of the interruption demanding peripheral units, initiated first. 4. The method according to claim 1 or 3, characterized in that the queue control with the help of mask commands, interrupt requests and data requests are suppressed. 5. The method according to claim 4, characterized in that the setting of the mask register is generated in an output processor by a circuit arrangement. 6. The method of claim 2, wherein two simultaneously requesting units are provided are, characterized in that when there are simultaneous requests from both Units the unit with the lower priority with the help of a first qualifier (Ql) the Allocation of a minimum amount of memory cycles at the expense of the unit with the higher Priority demands (Ql = 0) and the unit with the higher priority with the help of a second Qualifier (Q 2) lower the allocation of chained memory cycles at the expense of the unit Priority requires (Q2 = 1) that the queue control should be used at the same time Requests from both units establishes a connection with the unit of lower priority, if Ql = O and before there was traffic with the unit of higher priority, this previous traffic did not require chained memory cycles, and that the Queue control when there are requests from both units a connection with the unit of higher priority if Ql = I, or if Ql = O and there was previously no traffic with the unit of higher priority or traffic with chaining requests was. 7. The method according to claim 6, characterized in that the unit of higher priority is an input-output processor (EAP) and the unit of lower priority is a central processor (ZP) . 8. Apparatus for carrying out the method according to claim 7, characterized by a read-only memory (ZiI) which emits a signal at its first output (M 0) when there are no requests from the central processor (ZP) and input-output processor (EAP) , which at its second output (Ml) emits a connection establishment with the central processor (ZP) causing signal, which at its third output (M 2) generates a connection establishment with the input-output processor (EAP) signal, which to its fourth output emits a first flip-flop setting signal (K) when a chained memory cycle takes place, which emits a second flip-flop setting signal (V) at its fifth output when a request (A 2) from the input Output processor (EAP) runs and to which the qualifiers (Ql, Q2) and the requirements (A 1 or A 2) from the central processor (ZP) or from the input-output processor (EAP) are supplied and with the output of the first u nd of the second flip-flop is connected. 9. Apparatus for performing the method according to claim 5, characterized by a queue control with a request decoder (Dl), which distinguishes between interrupt requests coming from the peripheral devices and data requests, with a first register (AR 1) for the interrupt requests, with a second register (AR2) for the data requests, with a first mask register (Ml) assigned to the first register (AR 1), with a second mask register (Ml) assigned to the second register (AR 2), with a first and second coincidence circuit (i / l, i / 2), which only forwards the requests for which the assigned mask positions are set in the mask registers (Ml, Ml) , with a logical network (t / 3, i / 4, 05, 06, 01), the the interrupt requests and data requests selected by the mask register are supplied and the interrupt requests and only in the event that no interrupt requests there are no data requirements L / units formed - "" ^ T V ". -" 5 ^ "1IUIUCiUIi- ES is still hekamit. AnFm I κ? , f ^{() l} to arrange the queues and to process messages for the fifth in this order. ^{N Nummem of the} nature of the requesting entity and the AnfLe ^ ⁰ "* ^ ***** (™) type of request no consideration, requirements g (P 1) verg e - In this method, however, f ρ ™ is .cht and rather, all requirements are considered to be equivalent treated with a first signal when N <Ξ P 1 and treated with N > P 1
emits a second signal and with a combi- io It is' finally known the different natorÄchra. Network (K), which give different priorities to output (E 1) when mask commands are present on a first type of request. In this case, the different requirements ^ ^{1 P-8} I λ ^{'be a} "_ ^em ₄ ^zwe ith output a different weight to be assigned. The (E 2) for selecting input-output commands ER processing of the various requirements? ™ Τ · A ⁸ L, ^an rf ^{mem third output} g ^an i ¹ S then follows according to its weight, In the case of the (£ 3) with the selection of interrupt request, however, known method is not specified, rungen emits a signal, and that on a four - which type of request is the priority net zugeordten output (E4) when selecting Datenanfor- It also does not arise if the Abarbeiderungen emits a signal _{processing requests} not to others.. 10. The device according to claim 9, marked 20 criteria can be carried out characterized by a combinatorial network The object on which the invention is based (X) from a read-only memory. consists in providing procedures and devices give in which the order of processing of requests from units of a data server work system with simultaneous access to a unit of the data processing system is that the processing of the requirements takes place as quickly as possible. 30 In the event that the unit to which the requirements are made, the task is assigned an input The invention relates to a method and output processor is, and the other units Devices for determining the order in which peripheral devices and a central processor are woder several of several units of a data, when required, mask commands, input processing system to a unit of the data issuing commands, data and interrupt request processing system Different requirements are solved in that the queues Type controlled by a queue control according to the type of request will be working. first the processing of the mask commands, then If η units of a data processing system ßend the interrupt requests of the peri-simultaneous requests for access to a separate device or the input-output commands, then this and finally the data requests of the peri-service bottleneck arise. The unit / can arrange for a peripheral device, and that when there is time, the occupancy time, only one request from several requests of the same type is served, i.e. allocate a requesting unit occupancy work to these requests in a known manner. This is why the unit 1 receives a 45 according to the type of the requesting unit. Queue for requests and there is a The task will be in the event that at least Scheme necessary, according to which these requirements two units at the same time requirements for one can be edited. Provide working memory coordinator, thereby solved In the case of input-output traffic in a data that the queue control the requests processing system arise in two places, at the 50 of the units according to the type of input-output processor done beforehand and at the memory requests and in a known manner according to the coordinator, queues. At the input-output according to the priorities of the units defined quality processor can, for. B. A peripheral units edited on indicators. A connection points and a central processor will simultaneously make requests for access to a main memory coordinator. When requests are made, the requesting buffer coordinator can have access to the central processor units according to their priorities, qualifications and the input-output processor. gates are assigned through which the precedence of the So far, the requirements of z. B. π Ein requirements of the units can be specified. The units are written in η memory levels. Processing of the requests can still be done with an n-digit waiting queue of 0 -η places of the type of requests previously dealt with. This queue was made dependent on the condition. It can e.g. B. two of a hardwired priority network abear units can be provided. The unit with the height works, whereby the priorities can be given to the requesting ones. B. the input-output proportions were permanently assigned. Each new priority processor, the unit with the lower priority of the decision proceeded from one above all requirements 65 to be a central processor. newly formed queue. Are requirements of two entities to the However, this known method has the disadvantage that the working memory coordinator is provided, so it is preferable that the priorities of the requirements are based solely on the fact that if there are simultaneous requests