BE815352A - PROCEDURE FOR FIXING THE SUCCESSION OF PROCESSING OF REQUESTS SUBMITTED TO A DATA PROCESSING UNIT - Google Patents

PROCEDURE FOR FIXING THE SUCCESSION OF PROCESSING OF REQUESTS SUBMITTED TO A DATA PROCESSING UNIT

Info

Publication number
BE815352A
BE815352A BE144584A BE144584A BE815352A BE 815352 A BE815352 A BE 815352A BE 144584 A BE144584 A BE 144584A BE 144584 A BE144584 A BE 144584A BE 815352 A BE815352 A BE 815352A
Authority
BE
Belgium
Prior art keywords
succession
procedure
fixing
processing unit
data processing
Prior art date
Application number
BE144584A
Other languages
French (fr)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE19732325687 external-priority patent/DE2325687C3/en
Application filed filed Critical
Publication of BE815352A publication Critical patent/BE815352A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
BE144584A 1973-05-21 1974-05-21 PROCEDURE FOR FIXING THE SUCCESSION OF PROCESSING OF REQUESTS SUBMITTED TO A DATA PROCESSING UNIT BE815352A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19732325687 DE2325687C3 (en) 1973-05-21 Method and device for determining the order in which several requests of various types made by several units of a data processing system to a unit of the data processing system are processed by a queue control

Publications (1)

Publication Number Publication Date
BE815352A true BE815352A (en) 1974-11-21

Family

ID=5881596

Family Applications (1)

Application Number Title Priority Date Filing Date
BE144584A BE815352A (en) 1973-05-21 1974-05-21 PROCEDURE FOR FIXING THE SUCCESSION OF PROCESSING OF REQUESTS SUBMITTED TO A DATA PROCESSING UNIT

Country Status (5)

Country Link
BE (1) BE815352A (en)
FR (1) FR2231050B1 (en)
GB (1) GB1473581A (en)
IT (1) IT1012372B (en)
NL (1) NL7406760A (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4320456A (en) * 1980-01-18 1982-03-16 International Business Machines Corporation Control apparatus for virtual address translation unit
DE3570776D1 (en) * 1984-07-31 1989-07-06 Siemens Ag Circuit for telecommunication exchanges, in particular for telephone exchanges with centralized and/or partly centralized switching devices which can be connected to a data bus
DE3480962D1 (en) * 1984-10-31 1990-02-08 Ibm Deutschland METHOD AND DEVICE FOR CONTROLLING A BUS LINE.
US4788640A (en) * 1986-01-17 1988-11-29 Intel Corporation Priority logic system
US5115507A (en) * 1987-12-23 1992-05-19 U.S. Philips Corp. System for management of the priorities of access to a memory and its application
FR2625341A1 (en) * 1987-12-23 1989-06-30 Labo Electronique Physique SYSTEM FOR MANAGING MEMORY ACCESS PRIORITIES AND ITS APPLICATION
EP0324662A3 (en) * 1988-01-15 1990-01-17 EVANS & SUTHERLAND COMPUTER CORPORATION Crossbar system for controlled data transfer
US8490107B2 (en) 2011-08-08 2013-07-16 Arm Limited Processing resource allocation within an integrated circuit supporting transaction requests of different priority levels

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3492654A (en) * 1967-05-29 1970-01-27 Burroughs Corp High speed modular data processing system
FR2154968A5 (en) * 1971-10-01 1973-05-18 Telemecanique Electrique

Also Published As

Publication number Publication date
NL7406760A (en) 1974-11-25
FR2231050A1 (en) 1974-12-20
IT1012372B (en) 1977-03-10
GB1473581A (en) 1977-05-18
FR2231050B1 (en) 1979-03-09
DE2325687B2 (en) 1976-05-13
DE2325687A1 (en) 1974-12-12

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