DE2325140A1 - PROGRAM GENERATOR FOR A LIFT SYSTEM - Google Patents

Description

Munich ⁴ pieces

4f Munich, the IK. ^; - «- ^T i ^: 1973

2325H0

WESTINGHOUSE ELECTRIC CORPORATION
Pittsburgh. Pa. / V. St. A.

Program generator for an elevator system

The invention relates to a program generator for an elevator installation for generating a time-dependent speed signal with a limited change in acceleration.

For elevator systems with electromechanical control, no direct effect on the jerk that occurs when the acceleration changes via the speed program, but the freedom from jolts is brought about by other factors. The dynamic control of the cabin run is a compromise between different requirements and properties, such as response speed of the system, braking effect and deceleration value during deceleration. When installing the elevator system, this is done carefully adjusted so that no excessive jerk occurs, which again compromises between various factors such as overshoot the deceleration, landing and speed fluctuations when accelerating. Further the freedom from jolts must usually be restored at certain

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be established when the parameters of the dynamic system change as a result of aging, temperature and wear and tear.

In elevator systems with contactless control, the maximum Change in acceleration must be built into the speed program itself. For example, U.S. Patent 3,523,232 a time-dependent setpoint generator for the distance that generates an acceleration signal and then by means of an integrator this acceleration signal is a jerk limitation signal superimposed. This jerk-limited acceleration signal is then integrated twice, depending on the setpoint of the to get from the time. Xn of U.S. Patents 3,35o, 6i2 a capacitor is used to smooth the transitions between the different sections of a setpoint signal.

The invention specified in claim 1 is based on the object of such a contactless setpoint generator for a speed program to incorporate the jerk limitation in an improved manner directly into the program.

The measure according to the invention has the advantage that the maximum Change in acceleration of the cabin is controlled directly and is easily adjustable. Regardless of the speed of response of the speed controller, the preset maximum acceleration jerk cannot be exceeded will.

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Advantageous further developments are given in the subclaims. In particular, depending on the operating state of the elevator, one of the two values of the square-wave signal is selected in order to adapt the maximum jerk to the respective operating conditions the control system is switched back and forth between its two values ₉ so that the acceleration jerk receives the mean value zero _o

In Aufzu'gsanlagen relatively low speed, the time-dependent speed program for full control "of the cabin barrel _o In elevator systems with higher speeds sufficient, the seitabhängige Geschwindigkeitsprogrannra be used for certain phases of the cabin run while it is in other phases replaced by path-dependent desired values _a example, the Time-dependent speed program can be used for acceleration and for running at full speed, while after reaching the maximum deceleration when braking, a switch is made to a distance-dependent deceleration signal.

In the program generator according to the invention, the maximum value is the acceleration jolt independent of the transition functions of the system; there will be no adjustment or readjustment required on the spot and since no change

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There is an effect between jerk control and other parameters, the other parameters can be optimized independently of the jerk limitation.

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An example of implementation of the invention is given below with reference to described in the drawing. Here are:

Fig. 1 shows an overview of an elevator system in to which the invention is applicable;

Fig. 2 is a block diagram of a floor selector

3 is a more detailed block diagram of the same;

FIG. K shows a graph of the time profile of various clock signals in the floor selector for sampling position 0 of the sampling counter; FIG.

Fig. 5 and 6 Sehaltbilder different levels of the stick » factory selector according to Fig. 3 »

FIG. 7 shows a graph of the time course of various signals in the floor selector according to FIG. 3 for a thirty story building;

FIGS. 8 to Vo are circuit diagrams of further stages of the floor selector according to FIG. 3; '

11 shows a diagram of the bar position; which landing calls an elevator can take into account when it

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upward or downward travel set

T2 is a block diagram of a speed programmer, which can be used in the elevator system according to FIG. 1 J?

13 and 14 circuit diagrams of individual stages of the programmer according to Fig. 12;

Fig. 15 .ej.n. Graph to explain the voltage curve , - ;. at, different points of the ramp generator

-.- ■ .-.,. V- ... according to FIG. 14;

1> 6 shows a graph to explain the time-dependent signals for change in acceleration, acceleration and speed in the programmer according to FIG. 12; . ·. ,.

17 and 18 are schematic circuit diagrams of further stages the programmer according to FIG. 12;

FIG · 19 DLE representation of an apparatus for generating a predetermined velocity profile for the delay in approaching a Endstock- ■: factory; - - ■: · ■■ - "-. ■ - ■ _. -. -. .. _; .. .. ... ..... · .-.

Fig. 2oA and 2OB are diagrams for explaining the working ^iy, the Verzögeruragsschaltung of Fig * 18 and

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Pig. 21 a schematic circuit diagram of a driver stage for the programmer according to Fig. 12.

The individual figures will now be described in turn.

Figure 1

The illustrated elevator installation 19 contains at least one elevator car 12 which is suspended in a shaft 13 of a building] k. For example, the building has 30 floors, with only the first, second and thirtieth floors indicated. The cabin 12 is suspended from a rope 16 which runs over a drive pulley 18. The drive motor 2o is designed, for example, as a direct current motor with a Ward-Leonard drive. At the other end of the cable 16 there is a counterweight 22. A control cable 2k attached to the ceiling and floor of the cabin 12 is guided over a transmitter disk 26 located at the highest point of the shaft 13 and a roller 28 located at the lowest point of the shaft. The encoder disk 26 has holes or projections 26A, the passage of which is perceived by a pickup 30. For example, every centimeter of the trajectory results in an impulse. The pulses supplied by the optical or magnetic pick-up 3o are fed to a pulse detector 32 which generates distance pulses for a floor selector 3k «

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The car calls accepted by a row of buttons 36 in the car 12 are registered in a car call control stage 38 and converted into serial signals, and this information is fed to the floor selector 3k.

Call buttons ko _t k2 _t kk (last right for up and down travel) are installed on the individual floors. The landing calls received there are registered in the landing call control stage k6 and converted into serial signals. The corresponding information is also fed to the landing selector 3k.

The floor selector 3 ^ derives information about the position of the elevator car 12 in the elevator shaft 13 from the distance pulses from the pulse detector J2 and transmits these further processed distance pulses to a programmer 48, which generates a speed setpoint for a travel switch 5o, which in turn provides the drive voltage for the motor 2o supplies.

The floor selector 3k tracks the path of the elevator car 12 and the handling of the calls through it, supplies the acceleration signal and the deceleration signal for the programmer k8 at the correct times and the stop signal at a certain floor for which a call is registered. The floor selector 3k also provides signals for the control of auxiliary equipment "such as the door operating stage 52, the indicator lamps ^ k , etc., and monitors the

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the S ^ eAxer ^ orrteJiifc ^ g ^ door StQekverksruf after these calls have been dealt with.

The stopping in visual crawl and the alignment of the car to the floor height is taken over by a converter device, which includes inductor plates 56 in the individual floors and a transducer 58 attached to the car 12 ·

The Fanrsclialter 5 ° contains a speed controller » in which the setpoint prescribed by the programmer 48 the driving speed is entered. The manipulated variable for

The speed can be derived from a comparison of the actual speed of the drive motor and the programmed target speed, for example by means of a drag magnet regulator according to ÜS-PS 3.2o7 _t 265 *

Too high a speed near the upper and lower end storeys is detected by a sensor 60 in combination with a delay plate 62 . One of these components is attached to the car, the other to the two end floors. The retardation plate has individual peripheral recesses similar to a toothed edge, the teeth being spaced apart such that pulses are generated in the transducer 60 when there is relative movement between them. These pulses are processed further in the pulse detector 64 and fed to the programmer 48, where they are used to determine if the speed is too high.

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Figure 2!

Fig. 2 is a B2; a <ifcs; circuit diagram of the ^: basic structure 'of the station selector 3 &' The distance pulses from the pulse detector J2 are given by a reversible counter ψα , which * starts on the lowest floor (1st floor) with Ö and goes up - counts when the cabin starts moving, counts down when the cabin moves down. The counter 7 ° is automatically reset to Θ even if it deviates by a few counting pulses, and can also be based on the dem The number assigned to the top floor can be reset when it arrives at this floor in order to correct any counting errors. The counter 7o is preferably a binary counter whose capacity is sufficient to count the binary number that is the elementary length between two pulses and the distance between depends on the outermost floors.

The counter? O is designed so that it outputs a binary number, which changes steadily as the elevator car moves moved in their shaft, all the more so constantly the forward car position display · This cabin position is brought forward the place at which the occupied booth after expiry a predetermined delay program from your current one Speed could be brought to a halt. The cab position, which is constantly moved forward, is in fast moving Elevators are more important than the actual position of the car, as several floors are generally required to reach the Cab without unnecessary burdens for the passengers at one

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bring smooth stopping.

The cab position, which is constantly moved forward, is generated directly in the reversible counter 7ο by generating pulses have twice the frequency of the distance pulses, however, when the car accelerates it becomes the same Frequency like the distance pulses if the The cabin moves at a constant speed. When a delay is initiated, the count of the distance imptiles interrupted, so that when the elevator stops, the number in the counter reflects the actual position of the car.

A second reversible counter supplies a signal that shows the car position that has been moved forward by leaps and bounds in the form of a floor number indicates. The counter 72 is also preferably a binary counter, the capacity of which is sufficient to provide a binary word for the top floor as well. The counter 72 can be set aside in one or both end floors are and will be incremented up or down as required, when the steadily advanced car position changes.

When addressed by the binary word of the counter 72, which represents the car position that has been moved forward in leaps and bounds with a floor number, a fixed memory 'Jh supplies a binary word, the length of which is sufficient for the exact position of this

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To describe the first floor of the building with a resolution of the same step length as for the ¥ egimpulsen, ie one centimeter here. The fixed memory is preferably represented by a diode matrix in which the fuses of individual diodes are blown in order to obtain the desired step distribution. The presence of a diode corresponds to a logic one, while a missing or disconnected diode represents a logic zero. The fixed memory is set to the number of floors of the respective building during installation. After being called up by a word from the counter 72, which contains the number of bits required to describe the number of floors, the memory JK outputs a word, the length of which is used to precisely describe the location of the floor in question in the building with the same resolution as in the counter 7o is sufficient to describe the cab position that is constantly moved forward. For example, a five-bit word indicating a floor number can trigger a word up to 16 bits describing the location of that floor in the building. .

A bit-by-bit comparing comparator 76 compares these binary words output by the counter 7o and the memory 7 ^. If the two words are the same, the comparator 76 outputs an equality signal EQ2. So when the car goes up and the binary words from the counter 7o and the memory 7 ^ are equal, the equality signal EQ2 is generated.

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The equilibrium signal EQ2 means delayed, but must be initiated at this moment * or the car cannot stop at the discrete car position moved forward. If no acceleration is carried out at this point, the counter 7o continues its counting according to the distance pulses, the binary word in the counter 7o exceeds the binary word in the memory Jk and the comparator 76 supplies a signal for the index level 78. The index level 78 supplies a Signal for counter 72 * that causes it to output the binary word for the next higher floor.,

If the car travels downwards and the binary word of the counter 7o becomes the same as the binary word of the memory 7 ^, the equality signal EQ2 is generated again, if no delay is initiated at this point in time. the counter 7 continues its downward counting and as soon as the word contained in it is smaller than the binary word of the memory 7k ., the comparator 76 supplies a signal for the index level 78, whereby the counter 72 is set back by one number to get the floor number of the to indicate the next lower floor. The output of the memory 7 ^ is switched to the address of this floor.

A third counter 80 is a continuous sampling counter, preferably of the binary type, which starts at 0 _s in a predetermined time period up to a predetermined one. Counts the binary number and then the next time period starts again at 0 _β Da-

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by dividing each of these successive time periods into a plurality of time intervals. The location of a certain interval in the successive time periods is thus expressed by the same binary number. The number of intervals of each sampling period is determined by the number of floors in the building and is at least as large as this number of floors. For example, a five-bit sample counter gives 32 intervals before automatic reset to 0 and the start of the next sample period. If the number of floors is greater than 32, a counter with six bits must be used, which supplies 6k intervals, etc. The length of each interval is determined by the speed with which the call information can be obtained from the pushbuttons in the car and on the floors; this speed is limited by the noise of the sensor for the rotating rope. A time interval of two milliseconds was found to be satisfactory. Thus, for a five-bit sample counter, a sample period is 32 χ or 6 milliseconds long, with each of the 32 intervals taking up two milliseconds. The sample counter 8o is monitored by a master clock.

A second bit-by-bit comparator compares the binary output word of the counter 72, which is the floor number describes the car position moving forward by leaps and bounds, with the binary output of the scanning counter 8o. The comparator 82 outputs a signal EQ1Z 'during each sampling period if the binary number of the sampling position of the counter 8o is equal to that

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Binary word of the counter 72 is. The signal EQ1Z can thus be used as serially leading car position signal are referred to because, it is the leading car position in the relevant sampling interval, which is the floor of the leading car position is assigned, locates.

Logic 84 receives the landing and car calls, where these calls, divided into car calls, up calls and down calls of the floors, each available in serial form synchronized with the sampling counter. A car call for a certain floor thus appears in the sampling interval for this floor as indicated by the sample counter. The same is true for the other calls that logic 84 judges the coincidence of the calls present, which the elevator is set to handle, with the floor of the preceding one Cabin position. If the elevator is set to travel upwards, car and floor calls are taken into account for Floors in the direction of travel are registered. The elevator handles all calls in the upward direction one after the other in front of him. The elevator takes care of all the upward travel requirements in the direction of travel. If none of these are left, the logic ensures that the elevator to the top registered call for downward travel and then one after the other dealt with all requests that go down to lead. If these are done, he goes back to the bottom Call that aims upwards, etc.

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The coincidence signal EQ1Z is stored in the logic 84 and when the equality signal EQ2 arrives, the delay is initiated immediately, whereby the counter 7o is prevented from counting further distance pulses. This means that the counter 72 is not incremented and if the car stops on the floor for which a need was registered, the car position advancing abruptly and the continuously advancing car position coincide with the actual car position. If no coincidence of a call with the floor of the stepwise leading car position is determined before the equality signal EQ2 is emitted by the comparator 76, the next distance pulse causes the comparator to generate a signal for the index stage 78, whereby the counter 72 is incremented by one digit and so indicates the number of the next floor where the elevator can stop.

Figure 3

Fig. 3 shows again the block diagram of the floor selector 3 ^, but with more details and additions with regard to a particular embodiment.

Thus, in Fig. 3, a jerk sub-step 86 is shown, which an output signal LOADN for the counters under control by the unit sensors on the top and bottom floors 7o and 72 gives up. Controlled from the floor in question Memories deliver a binary word that indicates the location, i.e.

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describes the floor number in question. This word is entered into the counters Jo and 72 and serves as the starting point for counting the distance and floor pulses.

A min / max decoder 88 represents the arrival of the steadily leading Cabin position on the top and bottom floor and initiates the braking for the with a TDS signal End floor on, if the serial leading car position signal EQ1Z does not coincide with a call for the approached one End floor shows before the equality signal EQ2 occurs.

A fixed memory 9ö is used to identify those Sampling intervals that are not assigned to floors and those intervals at which there are no upward and downward calls can occur, i.e. top and bottom floors *

The logic 8k contains a call selector 92, a synchronization stage 8k and a logic stage 96. The call selector 92 receives the serial leading car position signal EQTZ and determines a coincidence between EQ1Z and the serial floor calls up and down or car calls 1Z, 2Z and 3Z. If the coincidence is established, a coincidence signal EIX occurs which, after synchronization in the logic 96, is fed to the synchronization stage 94 as signal EI. The Synchronisiersinife determines from the request on

to stop

Floor of the forward signal Eü / before the occurrence of the equality signal EQ2 is present. If the signal EI from the

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Synchronization stage 94 received before the equality signal EQ2, a signal DEC requesting the delay is output, which in logic 96 becomes a signal ACCX for the Programmer 48 is being processed. When the equality signal EQ2 occurs, there is still no signal EI present, the comparator 76 provides a signal for the Index level 78, which then sends an incremental pulse PU or PD generated up or down for the counter 72. The other Signals shown in Fig. 3 will be described later.

Figure 4

Before describing embodiments of the individual stages of the floor selector 34 will be explained different clock signals for the operation of the same. Fig. 4 shows those Signals that are zero in the sampling interval (here with 00 designated) of the scanning counter 80 in FIG. 2 can be generated. The sampling interval is e.g. 2 milliseconds long. The main clock signal is a pulse K32 with a frequency of 32 kHz. The other clock signals are derived from this. The signals KI6, Ko4, Ko2, Κ0Ι and KP5 are square-wave pulses with the frequencies 16, 8, 4, 2, 1 and 0.5 kHz by frequency division of the main clock signal K32 can be generated in a binary counter.

The clock signals K08S and Ko2S are shifted by the Clock signals K08 and Ko2 generated by 9o. The clock signal STC is made by reversing the clock signals Ko1 and KP5 and using the same generated as inputs of a NAND gate (STC = K01

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The clock signals S1 to Sk are produced every sampling interval in the first, .zweiten, third and fourth quadrants, signal S1 = K01 "KP5" KO2S and have the signals S2 to Sk similar, k in Fig. Mentioned compositions "

All of these signals are generated in every sampling interval, i.e. in every position of the sampling counter x 8. In contrast, the clock signals S1oo, S2oo and S300 are only generated in the sampling interval 00, with signal SI 00 = 00 * S1 _s, signal S2oo s OQ * S2 and signal S300 = 00 * S3.

The following is a list of the signals generated by the different levels and circles of the system and their functions, except the clock signals that are explained inFig "k".

Signal function

Accelerate the cabin or with maximum

drive speed

Request ACCX acceleration

AVP0-AVP4 leading cabin position in binary dar

position

BTTM cabin k $ cm from the lowest floor

removed

BYPS - elevator does not answer floor calls

CA call above the floor of the preceding one

Cabin position

CB call below the floor of the preceding one

Cabin position

CCY serial car calls

CEN; Enable reputation

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CFLY call ve »floor in the first sampling interval

vall

Enable DCE Waist Call

DCL doors closed

DCY serial down calls

Request DEC delay

DECS synchronized delay request

DGD actuation signal for step-down relay

DGU actuation signal for up relay

DL2 actuation signal for floor relay

DO enable door opening command

DOR door open command

Delete DORR door open command

DOWN Elevator set to go down

DPL distance pulses

DNRZ delete serial floor call downwards

DSAN speed program for deceleration

DSSW actuation signal for DSAN contactor

D45 actuation for main door relay

E1 call in forward cabin position

E1X hold command

EQ1Z serial cabin position

EQ2 "leading cabin position same floor

factory height

PSC first sampling interval

Actuate HLD indicator lights for downward travel

HLU indicator lamps for upward travel be

make

Press the HLX indicator lamp

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HT1 ΗΤΑΝ HIS IDLE LAZQ LOAD N MAIN ΜΙΝΑ MTOO MT01 MXVM NC

NCS NLC NL1-NL12 NL16 PCR

PD

PLSDP PtJ

SAC SBC

SDT SPSL SPSV Signal from position sensor in shaft Signal from position sensor circuit Actuation signal for HTAN switch Elevator is ready to drive Car 25 cm from floor height Car position counter set car k $ cm from main floor maximum delay

Memory signal

Memory signal

Maximum speed

logic zero when no calls are present logic zero when no calls are present input pulses for counters distance signals for counter cabin ko cm from floor level

forward cabin position has changed

Keep the leading cabin position back one floor

Impulse for final floor delay

Keep the leading cabin position one floor ahead

Scanning above the leading cabin position

Scanning below the leading cabin position

Set selector to downward travel. Speed selector switch

Exceeding the speed limit in the area of a terminal floor

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SPS1 SPS2 SRAT

BEGIN

SUT SOS-S ^ S TDS TOP

TOVSP

TSAN

TSD

TRAN TRSW UCE UCY UP UPRZ

UPTR Z02

Item 2Z 3Z

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Speed no. 1 choose speed No. 2 select

programmed speed signal for motor switch

Start signal when an acceleration request arrives

Set selector to travel upwards. Scanning signals

Stop signal in the end floor

- Cabin k5 em removed from the upper end floor

excessive speeding in the end floor area

Alternatively, the speed program used for braking in the auxiliary floor

Deceleration on the end floor, if logical O

Time-dependent speed program actuation signal from TRAN Up calls enable serial floor calls to the top. Elevator set to go up

delete serial floor signal upwards ^

Await drive

Cabin 5 cm from floor height

serial floor calls up serial floor calls down serial car calls

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Pig. 5 shows a preferred embodiment of the stages 7 © »72, - 7k, 76, 78 and 88 on the left side of the Pig« ₃₀

The counter 5o contains a plurality of synchronously operated binary counters with four bits ₉ each, of which four counters I00, 1o2, 1o4 and I06 are shown. the su chosen distance impulses.

The data supplied by the monitoring disc 26 and from the pulse detector 32 in Pig. 1 to the; Logic adapted distance impulses DPL should, as mentioned above _β generated during the acceleration of the elevator car with double frequency _c 12m the steadily advancing car position out te 11 esa ₉ then after reaching the maximum speed with normal frequency - be counted and finally suppressed when braking Depending on the direction of travel, the DPL pulses must be fed to one of the two inputs "Up and Down" of the counter 7. The programmer 48 must always receive the distance pulses during the car movement at the frequency that actually occurs. All these functions are effected by the counter 70. This contains two flip-flops I08 and ΙΙ0 of the type D, which are actuated by the rising frequency of the pulses, and a flip-flop 112 of cross-connected NAND gates, seven NAND gates 114-124 'and 134 and seven negation elements (inverter) 125 to 133 and 135 "- 2k -

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The distance pulses DPL are fed to the terminal of the same name, which is connected to input D of flip-flop 1o8.

At the input C of the same are via the negation element 125

clock signals K08 is on. The output Q of the flip-flop 108 / with the Input D of the flip-flop "Mo" and one input of the NAND gate 114 connected. The output Q of the flip-flop_I08 is on an input of the NAND gate 116 is performed. The clock signals K08S are applied to input C of flip-flop 14. The inputs Q and Q of the same are connected to the inputs of the NAND gates 116 and 114 respectively. The input terminal MVXM is with connected to an input of the NAND gate 116. -The signal MVXM is generated by the programmer 48 and takes the value 0 when the elevator reaches its maximum speed.

The output of the NAND gate 114 is connected to an input of the NAND gate 134 and via the negation gate I26 to an output terminal NLC tied together. This terminal supplies distance pulses NLC with the same frequency as the distance pulses DGL. The output of the NAND gate 116 is with the other input of the NAND gate 134 connected. The outcome of the latter is connected to the inputs of the two NAND gates 118 and 12o,

The flip-flop 112 indicates the direction of travel. Its set input S is via the negation element 133 with the input terminal UP and the reset input via the negation element 135 with the

DOWN
Entrance gills / connected. The signal UP has the logical one

Value one if the elevator is going up; corresponding

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applies to the AB signal. The output signal DN of the flip-flop 112 becomes an input of the NAND gate 118 and via the negation gate 128 is fed to an input of the NAND gate 12o.

An input terminal ACC is connected to the remaining inputs of the two NAND gates 118 and 12o. The signal ACC from the program generator 32 has the logic value one when the brake relay is activated for the drive motor, and the logical value when the deceleration of the car is initiated to zero, - ■

The output of the NAND gate 118 is via the inverter 13 © connected to an input of the NAND gate 122. Likewise is the Output of the NAND gate 12o via the inverter 132 with the Input of the NAND gate 124 connected. The other inputs of the NAND gates 122 and 124 are connected to the MAX and MIN outputs of the decoder 88 connected. The MAX and MIN signals take the logical value zero if the output word is the continuously leading Car position (counter 7 <>) is equal to the binary word, that describes the upper or lower end floor.

For the functional description of the counter 7 ° it is assumed that the elevator is set to ascend and is just starting. The input signal UP is equal to one and the input signal DOWN is equal to zero, as a result of which flip-flop 112 is set. The output signal DN has the value one, so that the NAND gate 12o a zero comes, which blocks it. When the brake relay to release the brake is applied, signal ACC takes the

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Value one. Thus, a pulse at the output of the NAND gate 13 ^ bring the output of the NAND gate 118 to zero and A one arrives at the input via the negation element I30

1 of the link 122. As long as the constantly advancing cabin position does not coincide with the upper end piece, MAX has the Value one, so that a zero occurs every time at the output of 122, when the output of the NAND gate 13 ^ becomes zero. Of the The output of the NAND gate 122 is connected to the input "counting up" of the counter I00 connected.

The NAND gate 13 ^ is operated by the combination of the flip-flops and Ho and the NAND gates Mk and 1 16 in such a way that it emits twice as many pulses as distance pulses are received until the elevator reaches its maximum speed, which is indicated by the value Zero of the MXVM signal is displayed. The output Q of the flip-flop I08 sends pulses at the frequency of the distance pulses DPL supplied to it to the NAND gate 114 and this supplies the NAND gate 13 * 1 and the output terminal NLC at the same rate as the pulses DPL arrive.

The output pulses from flip-flop I08 also reach the Input D of flip-flop Mo, which, however, receives a clock pulse shifted by 9o against flip-flop I08. Through this Flip-flop II0 switches the clock pulses 90 ° later than flip-flop I08 with 8 kHz, whereby the Output Q of the flip-flop I08 and the output Q of the flip-flop lic, both of which assume the value one at 9o, the output

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of the NAND element 1i4 each for 90 ° to the value zero. These Overlap occurs at the beginning of the positive output pulse Q from flip-flop 1ö8 and at the end of the positive pulse Q from Flip-flop 11o on «This creates an impulse in the area where it rises of the pulse DPIr.

This overlap of the logical states of the value one occurs but also between the output signals Q and Q of flip-flops 1o8 and 11o at the end of the output signal Q from flip-flop 11o and at the beginning of the output signal Q from flip-flop 1o8, whereby a pulse at the output of NAND gate Ί16 is close to the End of a pulse DPL results. So this impulse has one Distance from that occurring at the output of the NAND gate 114, Pulse triggered by the same pulse DPL.

Since the outputs of the NAND gates 114 and 116 are high have until this drops near the beginning or the end of a pulse DPL, the output of the NAND gate 134 for each Impulse DPL positive twice and results in this way. Input pulses for the counter 1oo with twice the frequency of the pulse DPL, while at the output terminal NLC pulses with the same frequency how the pulse DPL occur.

When the elevator reaches its maximum speed, it takes the signal MVXM has the value zero and thereby blocks the NAND gate 116. -The input of the counter 1oo then receives pulses with the same frequency as the incoming distance pulses DPL. When braking of the elevator is initiated,

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The signal ACG disappears, whereby the NAND gate 118 is blocked and no more pulses at all to the input counter 1oo.

If the elevator goes down, the NAND gate 118 is from Flip-flop 112 blocked and NAND gate 12o open, see above that the output of the NAND gate 134 via the NAND gate 124 reaches the input of the counter loo for counting down, as long as the MIN signal has the value one.

The min / max decoder 88 forces the car to brake when the steadily advancing car position according to the status of the counter 7 o reaches one of the two end floors, and also blocks the counter 7 o in this case against the registration of further distance pulses. The output MAX of the decoder 88 depends on a plurality of diodes 138 which are connected to the output of the counter 7o and which assume the logical value one if the continuously leading cabin position is equal to the binary word which describes the position of the upper end floor . When the cathodes of all these diodes are connected to a logical one, the input of a negator i4o connected to the anodes of the diodes goes high and the output thereof goes to zero, so as to produce the signal MAX.

Likewise, the output MIN of the decoder 88 depends on a plurality of diodes 142, the cathodes of which with the outputs of the counter

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7o are connected, while the anodes are connected to a negation member 144 lie. The diodes 142 are preceded by negation members. As a result, they speak on that binary word in the counter that corresponds to the lowest floor.

The output signals MIN and MAX are used to terminate the count of the counter 7o in the manner described above and further "to initiate the braking deceleration via the circle with the Input terminals BTTM, TOP, UP and DOWN, the negation elements 1 46 to 15 °, the NAND elements 152 to · i6o and the output terminal TDS.

The input terminals BTTM and TOP are equipped with limit switches in Elevator shaft connected, which respond if the elevator is still 45 cm from the end floors is “The NAND links and 15V are therefore open as long as the cabin is not inside this is 45 cm. The NAND gates 156 and 158 are alternate open when the elevator is moving downwards or upwards is set «,

To explain the function it is assumed that “the car is moving upwards. The signals MIN and MAX both have the logical value one, as does the complement of the signals BTTM and-TOP after the negation gates 146 and 148 _O. Thus, the output signals of the NAND gates 152 and 154 have the. logical value zero, the output signals of the NAND gates 156 and 158 have the value one, the NAND gate 160 has the logical value zero and appears at the output of the negative element 150

309848/055 1

- 3ο -

a logical one which results in a false signal TDS. If the binary word for the top floor appears at the counter Jo, the MAX signal becomes zero, the output of NAND element 15k is high, that of NAND element 158 is low, that of 160 is high and the output of negation element 150 is closed Zero, ie the delay signal TDS for a terminal floor is generated. It is fed to the synchronization stage Sk in a manner which will be explained later. The same applies when the elevator travels downwards and the MIN signal becomes zero, because the steadily advancing car position has reached the lower end floor.

The commercially available plague memory 7k is set when the elevator installation is set up in such a way that it outputs a binary number which expresses the exact binary address of the individual floors in the same key as the counter 72.

Per comparator 76 contains a plurality of bit-by-bit comparing comparison stages I62 to I68 and has an input for the "A" location, which is connected to the outputs of the counters I00, 1o2, 1 ok and I06, and an input for the word "B"", which is connected to the output of the memory 74. The comparator 76 has three outputs, namely an output A <\ B, which assumes the value one if the word is A \ B, an output A = B, which assumes the value when the words are equal, and an output A / * B, which is one if the word is A ^ B. The output A / * B is connected to the input, B of a flip-flop 172 of the B »type which is toggled by the rising edge

- 31 -

309848 / 055Ί

2325U0

verbumden, the output A = B with the input D of the flip-flop 17 ^ and the output A.> B with the input D of the flip-flop I7o. The clock inputs of these Flip-Flops receive the clock signal K32 via a negation element 176. The outputs Q of the flip-flop I70 and 172 are connected to index level 78, while the output Q of the flip-flop 174 via a negation element I78 at the Output 6terminal EQ2 is present. The output terminal EQ2 provides this Equality signal EQ2, if, the steadily leading cabin position arrives at the floor height of the leaping car position.

For the functional description it is assumed that the elevator is after drives up. Word A is smaller than word B and the output A <^ B has the value one, while the other outputs have the value Have value zero. Flip-flop 172 thus inputs. Signal of value One off while the outputs of flip-flops I70 and 174 are on Are zero. If the words A and B match, the output A = B goes to one, flip-flop 174 emits a one and a signal EQ2 receives the goods value zero. A delay is then initiated to move the car on the floor of the leap forward To bring the cabin position to a halt, the ACC signal disappears and the counter 7o remains at the level of the jump leading car position, so that word A continues to be equal to word B until the car has stopped and then again is approached. If, on the other hand, no delay is introduced when the signal A = B occurs, the first distance pulse causes it after equality has occurred that output A / B denotes Receives the value one and the flip-flop I70 outputs a one.

309 84 8 / 05bΊ.

2325 UO

The index stage 78 slides under the influence of the flip-flops 17ο and 172 continue the leap forward cabin position, to show the next floor on which the elevator is located can stop. It contains the NAND elements 182 to 188, the negation elements 1 ° -o and 192 and has the input terminals UP, DOWN, ACC and SI00. It is also connected to the output terminals PU and PD and the synchronization stage 94 connected. The inputs of the NAND gates 182 and 184 are connected on the one hand to the input terminal UP or DOWN and on the other hand to the input terminal ACC connected. So if the elevator goes up and is not braked, the NAND gate 182 is a Zero, the NAND element after reversal in the negation element 19o 186 opens. The NAND element 184 outputs a one which, after reversal in the negation element 192, blocks the NAND element 188. at Conversely, downward travel is blocked NAND element 186 and NAND element 188 open. When traveling upwards, the output signal A ^ B of the comparator 76 and the associated flip-flop have 172 has no effect because NAND gate 188 is blocked. As soon A ^> B, flip-flop is flipped 17o and the pulse SI00, which is only occurs in the sampling interval OO of the sampling counter 80, makes the output of the NAND gate 186 to zero, i.e. the signal PU becomes generated. This signal switches the counter 72 to the display next higher floor number, whereby the memory 74 is switched to the address of this floor. These The number is again higher than the constantly advancing cabin position.

If the elevator goes down, NAND element 186 is blocked and NAND gate 188 open. ¥ ¥ ¥ after equality has occurred

. - 33 -

■■ 3098 A8 / OSbI

2325H0

of words A and B is not initiated, the counter 7o continues the downward counting and as soon as the output AS B receives the value 1, flip-flop 172 is toggled and the output of NAND element 188 goes to zero if the pulse occurs in time interval 00 S1oo arrives. This generates the signal ED which resets the counter 72 by one binary level in order to indicate the next lower floor. If the counter 72 is incremented, the comparator f6 again outputs a logical one at the output A ^ B and the above sequence of functions is repeated. ,.

Figure 6

Fig. 6 shows the embodiment for the counter 72, the reset stage 86 and the comparator 82 in Figure 3 _e, "

The counter 72 contains the necessary number of synchronously controlled binary four-bit counters in a cascade circuit that is required to represent the number of floors in the building concerned. Two such partial counters 194 and 196 are indicated. The inputs of the counter 19 ^ for counting up and counting down are with; connected to terminals PU or PD. The output of the counter 72 is connected to the memory Jh and to an input of the comparator 82 via the output terminals AVPÖ, AVP1, AVP2 and AVP3. The comparator 82 compares bit by bit; its other input is connected to the sample counter 80. It has three outputs for A <B, AsB and A> B, similar to counter 76.. ·,

309848/0551.

7 ■

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The outputs of the comparator 82 are used to generate the serial leading cabin position signal EQ1Z, the signals SBC and SAC for scanning below and above the jump ^ wise leading cabin position. These signals are developed by a circuit that includes the input terminals STG and PCR, the NAND gates 198, 2oo and 2o2, the negation terms 2o ^, 2o6 and 2o8 and the output terminals SBC, EQ1Z and SAC.

When the sampling counter 8o samples (counts) below the floor of the car position advancing by leaps and bounds, the output signal A <B is high and opens the NAND gate 198, which is acted upon by the signal STC during each sampling interval, in order to generate an output zero which In-. Negation member 2o k is reversed, resulting in the signal STC of the value one.

In the same way, the signal EQ1Z occurs when A = B, as long as the counter 72 from a non-zero signal PCR is opened (counter 72 not incremented). The signal EQ1Z is therefore in the correct sampling interval of the sampling counter 8o generated. If the sampling counter 8o counts over the

to one-way leading cabin position, the output A> B / and the NAND gate 2o2 outputs a logic zero when the opening signal STC becomes one during each sampling interval. The output signal from NAND gate 2o2, which goes to zero, becomes reversed in the negation element 2o8 and thus delivers a strong signal SAC, which is a sample above the abruptly running signal Indicates cabin position. - 35 -

■ 3098 48/0 55 1

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The reset stage 86 resets the two reversible counters 7o and 72 in the end floors to the correct starting numbers before the elevator car can start the next trip to an intermediate floor _{or the like}

The inputs of the NAND element 21 o in the reset stage 86 are connected to the input terminals DL2 and Z02, DL2 being generated by the programmer k8 when the elevator is to stop. If DL2 has the value zero, this corresponds to the "drive" command, while the value one corresponds to the "hold" command. The signal Z02 is issued by a limit switch in the elevator shaft when the car is still 5 cm from the floor level. The signals TOP, BTTM and MAIN are generated by switches in the elevator shaft if the car is at a distance of 4 5 cm from the top, bottom and main floor. If the lowest floor is the main floor, the input terminal MAIN and the NAND element 21 k can be omitted. The input terminal S1oo receives the clock pulses S1oo, which only occur in the 00 sampling interval. The output of the NAND-Oliedes 218 is connected on the one hand to the counter 72, on the other hand to the output terminal LOAD ^ N, which leads to the counter 7o (see FIG. 5).

A read-only memory 222 is used to output the binary floor number for the floor that controls the memory. For example, when the output of the NAND gate 212 goes to zero, the memory 222 returns that associated with the lowest floor Binary number, which should be 00001 here. If the output of the NAND gate 216 becomes zero, the read-only memory 222 outputs

309848/0551 '. " ³⁶ "

" ³ " 2325H0

the number of the top floor, which in this example with 3o floors has the value 1111ο.

If the elevator car is on an intermediate floor, the inputs of the NAND element 22o are all equal to one and its output becomes zero, whereby the NAND element 218 is blocked. If the car arrives at one of the end floors, the NAND element 11o opens the NAND gates 212, 21 k and 216 and depending on which end floor it is, one of these NAND gates addresses the memory 222 and opens NAND gate 22o. If the clock signal Sloo arrives in the sampling interval OO, it can pass through the NAND gate 218, as a result of which the correct floor number is input into the counter 72. The counter 72 is thus compulsorily set to the correct floor number. and this number is used to control the correct address of the memory "Jh. Speicher 7 ^ provides the exact location of the relevant floor with regard to the building in the form of a multiple of the elementary length. The output of the memory 7 ^ is not only used by the comparator J6 , but is also connected to the preset input of the counter 7o, as shown in Fig. 5. The signal LOAD N from the reset stage 86 is connected to the input LOAD N of the end floor 7o and when this signal becomes zero, the output of the memory 7k is in The counter 7o is entered so that it starts with the correct counting result on each preferred floor

309848/0551

.2325UO

Operation, which means a loss of payment of the meter, the mode of operation can be continued normally after the return of the power if the elevator car was previously moved manually to one of the reset floors _P

Figure 7

Fig. 7 shows the time sequence for a building with 30 floors with reference to the successive sampling intervals of the sampling counter 80. This has five bits- ₉ which results in 32 intervals. Since each interval should last two milliseconds, the total sampling period is 64 milliseconds «,

The car calls 3Z are synchronized serially connected to the scan counter 80 so that they appear in the one sampling interval, that the corresponding to destination floor is assigned to _e example, is connected to each Kabxnendruckknopf via a wire to a gate circuit and this torso conversations are successively opened from the output of the sampling counter, so that the Äfotastintervall OO opens the gate circuit assigned to the first floor, etc. The outputs of these gate circuits are combined in order to display the car call information in serial form. In the operational example of FIG. 7, it is assumed that the elevator is traveling downwards, that the car position (signal EQ1Z) in 20. Floor is and that car calls (signal 3Z) for the 19th, 15 · Ί1. » 1o. and 3 · floor are present.

309848/0551

2325U0

The up calls 1Z and the down calls 2Z are from floors similarly shown in series and synchronized with those sampling intervals that correspond to the floor numbers in question assigned. So in Fig. 7 up calls for the 1o. and 13 · floor, as well as down calls for the 7th and Floor.

The signals MTOO and MT01 are stored in the read-only memory 90 in FIG. and serve as opening signals to ensure that the. Sampling intervals that are not used to represent floors are also ignored, as is the sampling intervals for the top and bottom floors when comparing the up calls and the down calls. Thus is the signal

Opening the
MTOO for the / Auf was t sruf e 1Z a logic one for the sampling intervals 00 to 28 (floors 1 to 29) and a logic zero for the sampling intervals 29, 3o and 31. The signal MT01 for the opening of the down calls 2Z is a logic one One for the sampling intervals 01 to 29 (floors 2 to 3o) and a logical zero for the sampling intervals 00, "} o and 31 ·

The Signa ^ EN is a call opening signal for the car calls, which is also supplied by the memory 9o or another storage track. The CEN signal can simply be used to determine that the sampling intervals not used to represent floors in the call memory circuits remain unconsidered. Instead, a dealt with signal CEN in FIG. 7 can also be used for the control to prevent certain floors in the event of a car call,

309848/0551 " ³⁹ -

ζ. B. the floors 15 »2o and 3o«

The other plotted in Fig. 7 clock signals have already been described in connection with FIG, K.

In the example shown in FIG. 7, the downward moving elevator stops on the floors for which car calls yz are registered and on the 70th floor to handle the downward call 2Z stored there. If the elevator made its last call in the downward direction, it travels to the lowest registered up call and then takes care of all other up calls. Once this has happened, the elevator moves to the highest registered down call * The switching means used for this are described below »

Figure 8,

Fig. 8 is the schematic circuit diagram of an embodiment of the call selector 92 of Fig. 3. The primary function of the call selector 92 lies in the determination of a coincidence between the signal EQ1Z, which indicates the abruptly leading cabin position, and an elevator request for the floor in question, to generate a hold command signal EIX when a such coincidence occurs. Auxiliary tasks of the dialer 92 are the resetting of the landing calls, the control of the indicator lamps, the generation of the door opening command and the Detection of a call on the floor from which the elevator is currently leaving.

■ "- ko -

30984 8/0551

'- ^4o -. 2325U0

The input terminals of the call selector 92 are the call signal terminals TzV 2Z "t 5z, the storage signal terminals MTOO, MT01 and IC, the terminals UCE and DCE for receiving the call release signals up and down from the logic 96, the terminals DLC, DO and DORR for the Signals "door closed", "release of door opening" and "delete door signal ¹ ·, the input terminal UPTR, which receives a signal from the logic 96 regarding the direction of travel, the input terminal FSC, which receives a signal from the logic 96 if the first Sampling is initiated at the beginning of a journey, and the input terminal S4 for receiving clock pulses during each sampling interval.

The serial signal EQ1Z of the forward car position appears at the input EQ1Z in the sampling interval that is assigned to the floor position in question and is from the clock signal S4 scanned by means of the NAND gate 24o and reversed by the negation gate 242 so that it is at the inputs of the NAND gates 244, 246 and 248 with the logical one appear.

The serial floor calls occurring at input 1Z after above are reversed in the negation element 250, from the storage signal MTOO screened by means of the NAND element 252, reversed again in the negation element 25 ^ and each to one input of the NAND gates 244 and 256, as well as a further negation element 258 on the output terminal UCY. The latter delivers that is, the serial landing calls screened by the memory signal MTOO.

- 41 -

3Q98487055 1

"^" 2325H0 "

Similarly, those arriving at the entrance gill 2Z Floor calls in downlink 2Z from the memory signal MTO1 after. Reversal in negation element 260 by means of the NAND element 2Ö2 screened and arrive via negation element 264 to the NAND- * elements 246 and 266, as well as via the rest of the way Negation element 268 "to the output terminal DCY.

The serial car calls at the terminal yi are reversed in the negation element 270 and given to the NAND elements 272 and 248. The car call release signal GEN is reversed in the negation element 274 and applied to a further input of the NAND elements 272 and 248. The car calls for floors for which a release is present _s appear at the output of the NAND gate 272 and at the output terminal ₀ CCY

When the enable signal coming from the UCE for up calls ₈ by logic 96, logic ΐ / ert one has, the NAND gates ₉₂₅₆ and 2kk 276 are .geöffnet. At the same time, the release signal DCE for down calls' is at the logic value zero, so that the NAND gates 246, 266 and 278 are blocked, and vice versa

The outputs of NAND gates 244, 246 and 248 are normal on the logical value one if there is no coincidence of the car position leaps forward and a call for this floor is determined «Since these. exits all are connected to the input of a NAND gate 280, the latter outputs a logic zero if there is no coincidence,

- 42 -

3 0 9 8 4 8/0881

which is converted into a logical one by the negation element 282. The output signal IT _f, which represents the hold command, is therefore incorrect if there is a lack of coincidence, ie at the logical value one.

If, on the other hand, a floor or car call is registered for the floor of the car position advancing in leaps and bounds, the signal EIX to zero, i.e. made true, in the following manner.

If it is a floor call up and the car is set to handle up calls, then have the input signals of the NAND gate 244, i.e. UCE, EQ1Z and TJCX, all the logic value one during the sampling interval corresponding to the floor of the leap ahead

Cabin position is assigned _o As a result, the output of the NAND element element 244 is zero, the output of /. 28o becomes one and the output signal EIX becomes zero because of the negation element 282.

Is it the coincidence with a floor call down and the elevator is on the handling of down calls set, the input signals of the NAND gate 246 are all simultaneously during the sampling interval, that is assigned to the floor of the car layer that is leaping forward, on the logical one

Value one, whereby a logic zero occurs at the output of the NAND gate 246, which is a corresponding zero at the Causes output terminal EIX.

- 43 309848/0551

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If it is the coincidence with a car call, then the output of the NAND gate 248 is raised in the same way Zero controls and thereby blocks the NAND gate 28o, whereby the output signal EIX again becomes zero »

At the start of the journey, the logic provides 96 during the first complete When the sample counter 80 passes a true, i.e. zero, PSC which begins with the clock signal S2oo and ends with the clock signal SI00 and to the terminal PSC in FIG. 8 is created. In the call selector 92 it is reversed by means of the negation element 284 and gives a logical one to one Input of the NAND element 286. At the start of the journey, the actual position of the elevator car and the car position that is advancing in leaps and bounds coincide, the signal EQ1Z appears in the sampling interval that is assigned to the location of the cabin. If there is a floor call to the top on this floor, then a floor signal UCX is an input of the NAND element 256 supplied. Is the elevator for handling up calls enabled, then signal UCE is available and if the elevator is set for upward travel, it also has a signal UPTR the logic value one, whereby a zero occurs at the output of the NAND gate 256. '

Likewise, the output of NAND gate 266 goes to zero when a down call is registered in the living floor of the car (signal DCX), the car to handle Calling down is enabled (signal DCU) and the elevator is on

- kk -

30984 8/0551

- ^kk - 2325HO

Downward travel is set (signal UPTR).

The outputs of NAND gates 256 and 266 are to the NAND gate 288 led. At the output of the same, a logical zero occurs if there is no floor call at the location of the approaching cabin is present. If, on the other hand, the output signal of one of the NAND gates 256 and 266 is equal to zero, this gives NAND gate 288 from a logical one. If this case occurs in the first sampling period (FSC), the NAND gate gives 286 from a zero, which is reversed in the negation element 29o and is applied to the NAND gate 292 as a logical one. The other input of the NAND gate 292 is with the clock signal S4 applied, which thus scans the call from the floor and a corresponding output signal CFLY that indicates a call on this floor. Furthermore, the output signal of the NAND gate 292 is sent to a set input a door flip-flop 294 given. The latter consists, for example, of the cross-connected NAND elements 295 and 297.

Further set inputs of the door flip-flop 294, i.e. the inputs of the NAND gate 295 are connected to the outputs of the NAND gates 244, 246 and 248. Thus a reputation results in stays Floor or a stop command because of a car or Floor call a set pulse for the door flip-flop 294, whereby at the output of the NAND gate 295 and at the input of the NAND gate 296 a logic zero occurs. The other input of the NAND gate 296 is connected to the input terminal DO

- ■ 45 -

309848/0561

connected, which is at the logical value one, if the Door open command is released. Is 296 as a NAND element opened by the signal DO and set flip-flop 294, see above

a

/ second flip-flop 298 is also set. The flip-flop 298 can also consist of cross-connected NAND gates 299 and 301. NAND element 299 supplies a logic one at its output, which is reversed in negation element 3oo and applied to output terminal DOR. A signal DOR with the value zero means a command ₈ to open the elevator doors; This command is given to the door operating device 52 according to FIG Limit switch mounted on the elevator doors generates and resets the first door flip-flop 294 _{or the like}

The second door flip-flop 298 can also be used to generate a Door open command from the delay signal TSD for a End floor can be set. The braking effected by the programmer 48 when approaching an end floor leads also for opening the elevator doors "

The output of the nagging member 300 is in a Negation element 3o2 again reversed and to the inputs the NAND gates 276 and 278 given, which also have the Release signals DCE or UCE are fed. If so

3 09848/0551 "^ ⁶ "

- hey - .

2325 HO

the elevator is released for handling up calls and a door open command is generated, the exit goes of the NAND gate 276 to zero and this signal is im Negation element 3o4 reversed and to an input of the NAND element 3o6 given. Another input of the NAND gate 3o6 is with the serial leading cabin position signal EQ1Z tied together. If this assumes the value one, the output signal becomes from NAND gate 3o6 to zero and this output signal goes to the output terminal HLU for the purpose of actuating the indicator lamp for upward travel on the floor of the forward car position and to the output terminal UPRZ for the purpose of resetting the push button for upward travel on the floor concerned.

In the same way, when a door open command occurs and release of the elevator to handle downward calls, the NAND gate 278 opens and opens via the negation gate 3o8 the NAND gate 31o when the signal EQ1Z occurs, so much the actuation signals HLD and DNRZ for indicator lamp and Resetting of the floor push button for downward travel closed produce. .

Figure 9

FIG. 9 is a schematic illustration of an exemplary embodiment of the logic 96 according to FIG. 3t, which is used ^to form the signals UCE, DCE, UPTR, HLX, FSC, HCCX and EI.

The serial call signals UGY, DCY and CCY are determined

- 47 309848/0 55 1

2325U0

The serial car calls CCY are applied to all three NAND elements, the serial up calls UCY to the NAND elements 322 and 324 and the serial down calls DCY to the NAND elements 32o and 324 _o Only if there is no call at all are the outputs of all three NAND elements at the logical value zero. The outputs of these NAND gates are connected to certain inputs of NAND gates 326 to 332, namely the output of NAND gate 32o goes to an input of NAND gate 33o, the output of NAND gate 322 to an input of NAND Element 328 and the output of NAND element 324 to one input each of NAND elements 326 and 332.

Another input Mes NAND gate 326 is connected to the input terminal SAC connected, which receives a signal of the logic value one from the comparator 82 when the sample counter 8o is above of the floor of the serially advancing car layer scans.

Further inputs of the NAND element 228 are connected to the clock signal terminal Sk (FIG. 7), the input terminal EQIZ from the comparator 82 and the output of the NAND element 374 via the negation element 323. The output of the negation element 323 is at the value one when there is an acceleration command for the elevator, as will be explained later.

Further inputs of the NAND gate 33o are connected to the output of the negation element 323, as well as with the input terminals EQ1Z

3098 4 8 / 05S1 -48-

2325H0

and Sk connected. Another input of the NAND element 332 is connected to the terminal SBC, to which a signal is applied when the comparator 82 indicates that the scanning counter 80 is scanning below the floor of the serially leading car position.

\ "

The outputs of the NAND gates 326 to 332 are selected with Inputs of two flip-flops 333 and 335 connected. The flip-flop 333 for calls above consists of the two NAND gates 334 and 336, the outputs of the NAND gates 326 and to the NAND gate 334 are performed. One output of the NAND gate 336 is connected via the negation element 342 to the input terminal S300, which the flip-flop 33 ° during the sampling interval 00 of the sample counter 80 resets.

The flip-flop 335 for calls below consists exclusively of two cross-connected NAND gates 338 and 34o ₉ wherein the input gears ¹ of the NAND gate 338 to the NAND gates 33o and are connected 332nd The reset input of the NAND element is also connected to the output of the negation element 342.

When the sample counter 80 is above the floor of the serial scans the leading car position and detects a call there, the output of the NAND gate 326 becomes zero and sets the flip-flop 333 »whereby a signal CA appears at the output of the NAND gate 334. At the same time, the starting

- 49 -

309648/0551

"■ _ 2325H0

signal CA of NAND gate 336 to zero. The flip-flop 333 is also set when the output of the NAND gate 328 goes to zero, i.e. there is an acceleration command and a car call or an up call in the whereabouts of the Car occurs. The flipped state of the flip-flop 333 is indicated by the signal S3oo in the next sampling interval 00 canceled again.

The flip-flop 335 for calls down is set when the sampling counter 8o scans below the serially leading cabin position and detects a call there. In this case, the output of the NAND element 332 becomes zero and the signals CB and CB to _o Furthermore, the flip-flop 335 is set when the output of the NAND element 23o becomes zero and thereby indicates that an acceleration command is present and at the same time a call down or a car call is present in the location of the elevator car.

The output signals CA and CB are to a NAND gate and the output signals CA and CB to a NAND gate 346 given. Both NAND gates are also the clock signal S2oo and the signal ID supplied; the latter has the logical one It returns one if there is no command to open the elevator door. So if there's a call above the elevator, don't but there is below the elevator and the elevator is ready to leave, the output of the NAND element 3 ^^ closes. zero made when the clock signal S2oo occurs in the sampling interval 00

- 5o -

309848/0 551

- 5ο -

occurs. The same applies to the NAND gate 346 if there is a call only below the elevator location and the elevator is ready to drive or drives. If, on the other hand, calls occur simultaneously above and below the elevator location, both remain NAND gates 344 and 346 blocked because the signals CB and CA are equal to zero.

The outputs of NAND gates 344 and 346 are to selected ones Inputs of a direction flip-flop 35o placed. This includes cross-connected NAND gates 352 and 354. An the NAND gate 352 is performed while the NAND gate 344

346
the NAND gate / is led to the NAND gate 354. Further inputs of the NAND gate 352 are connected to the terminals SUT and BTTM. A guard can manually command an upward journey via the SUT terminal. The BTTM signal indicates that the elevator is approaching the lowest floor. A negation element 356 reverses the signal BTTM before it is fed to the NAND element 352.

Next ^ inputs of the NAND gate 354 are connected to the terminals SDT and TOP connected. The SDT terminal is used to manually input a downward travel signal by a guard, while the end signal TOP is reversed in a negation element 358 will.

The output of the NAND gate 352 is a signal 81U, the is fed to an input of a NAND gate 360. The other The input of the same is connected to the output of the negation element 35 &

309848/0551

2325U0

tied together. The output signal of the NAND gate i6o, which with UPTR is designated, is reversed in negation element 362 and fed to the output terminal UPTR «, so this has the logical value one if upward travel is desired, and the logical value zero if descent is desired.

In normal operation, the signal 81U has the value, one, when the output of the NAND gate 344 goes to zero, and the value zero when the output of the NAND gate 346 goes to zero. On the other hand, calls both below and above of the car location or a call at this point is detected during the first sampling period, then one of the two NAND gates 344 and 346 can emit a negative pulse, since QÄ and CB have the logic value zero. In this case, the direction of travel flip-flop 350 is not tilted and the elevator maintains the previously chosen direction of travel. Signal TOP toggles flip-flop 350 and the output of NAND gate 360 becomes positive). The latter even occurs if, for whatever reason, the flip-flop 350 does not respond, since an input of the NAND element 360 is directly connected to the input terminal TOP via the negation element 358. If the car is not on the top floor and there are no further calls to be made above it, but calls below, the output of the NAND gate 346 goes to zero and toggles flip-flop 350, so that the signal 81U assumes a low value and the The output of the NAND gate 360 results in a logic one.

30984870551 - 52 -

"'2325 HO

The same applies if the elevator is set to travel downwards is; however, the terminal BTTM is not directly connected to the input of the NAND gate 360. Are no more calls underneath the elevator going down and has to do

this has not yet reached the lower end floor ^ while at the same time Calls are registered above the elevator, so the output of the NAND gate 344 goes to zero and toggles flip-flop 350, so that a true signal 81U occurs, which is the output of the NAND gate 360 makes zero.

The NAND elements 364 and 366 and the negation elements 368 and 370 are provided for the floor call release. These components are acted upon by a BYPS signal, which depends on the car load. When the load exceeds a certain maximum value, the BYPS signal goes to zero. This signal applies to one input of the NAND elements 364 and 366. Another input of the NAND element 364 is connected to the output terminal UPTR, while an input of the NAND element 366 is connected to the output terminal UPTR of the NAND element 360 .. If the cabin load is below the permissible limit and the signal UPTR has the value one, a logic zero occurs at the output of the NAND element 364 _t which is reversed by the negation element 368 and fed as a true signal of the logic value one to the output terminal UCE. This means that the elevator is released to receive calls to the upper floor. Likewise, the occurrence of an output signal DCE means that the elevator is released to receive floor calls downwards,

30984 87 0551 - 53 -

232514b

because the cabin load is within the specified limits holds and the signal TJPTE is true, i.e. equal to zero.

If the cabin load exceeds the prescribed value, so the BYPS signal goes low and both NAND gates 364 and 366 are disabled, i.e. take the output signals UCE and DCE the value zero. These signals are sent to the paging dialer 92 in Fig. fed. .

When the elevator is ready to run in the waiting position, a call triggers an ACCX acceleration command in the direction that prescribed by the direction change just described will. The flip-flops serve to form the ACCX signal 380 - 384, the NAND elements 374 and 386 - 394, as well as the negation elements 396-400.

The flip-flop 380 with the NAND gates 402 and 404 receives the Inputs of the NAND gate 402, the output signals CA "and CB of the Flip-flops 333 and 335 for call up and call down. Furthermore is a Input of the NAND gate 402 to the output of the NAND gate 391 connected. The latter is with its one entrance to the Terminal EQJ Z and the other input is connected to the input terminal "CEN. Each call sets flip-flop 380 so that one logic one occurs at the output of NAND gate 402; this output signal is called NCS. Since furthermore the signal CEN for a floor for which the elevator is not approved,

- 54. 309848 / OS S Γ

^"54 ~ 2325H0

represents a logical one, means the coincidence of the Floor of the serial leading car position (signal EQ1Z) with a floor for which the elevator is not released, that there is a call in the system, which is why flip-flop 380 also ' is set. This prevents the elevator from accidentally stopping on a floor for which it is not approved. The flip-flop 380 is reset during the sampling interval 00 by the clock signal S300, which is applied to an input of the NAND gate 404 is performed.

The output signal NCS of the NAND gate 402 goes to the inputs the NAND gates 386 and 392. The output of the NAND gate 404 is connected to an input of the NAND gate 388. When a call is detected in the system and the flip-flop 380 is set is, the true signal NCS becomes 00 during the sample interval by the clock signal S200, which is connected to the other input of the NAND gate 386, passed through this NAND gate. Of the The output of NAND gate 386 goes low when clock pulse S200 is received, thereby toggling flip-flop 382 so that it emits a signal NC of the logic value one at the output of the NAND gate 406. The reset input of flip-flop 382, i. an input terminal of the NAND gate 408 is connected to the output of the NAND gate 388. The inputs of the NAND gate 388 are with the output of the NAND gate 404 of the flip-flop 380, with between input terminal S200 and input terminal DOR. The latter results in the absence of an opening command for the Elevator doors have a high voltage. Thus, flip-flop 382 is from

30984 8/0551 "55-

NAND gate 388 reset if no door opening signal DOl is present, but not before flip-flop 380 by the clock signal S300 has been postponed. ■

The output NC of the flip-flop 382 is connected to an input of a NAND element 410 in a flip-flop 384, with an input of the NAND gate 309 and with one input of a NAND gate 414 tied together. The latter will be considered later. If the signal NC assumes a high value when the clock signal S200 occurs, it opens the flip-flop 384 and the NAND gate 390. Another input of the NAND gate 390 is connected to the input terminal S100, to receive a corresponding opening impulse. That Clock signal S100, whose occurrence by a full sampling period is shifted by the clock signal S200 after the flip-flop 382 is toggled, the NAND gate 390 trips to a low output signal to generate, whereby the flip-flop 384 is in turn toggled and thereby the output signal RUN of the NAHD element 410 to zero, as well as the output signal RUN of the NAND gate 412 to

a high voltage. The output signal RUN is fed to an input of the NAND gate 414, while the output signal RUN is led to an input of the NAND gate 392.

Flip-flop 380 is _{not reset by the clock pulse S300 (} because there is a call in the system. Thus, the input NCS of the NAND gate 392 is at a high value when the output RUN of the flip-flop 384 receives a high value at the time S100.

- 56 309848/0551 ■ "■

^'56 2325U0

Further inputs of the NAND gate 392 are connected to the input terminals S100 and IDLE connected. So if the signals NCS, RUN and SIOO are all high, while the elevator is out of work, the output of NAND gate 392 goes low and drives the Output of NAND gate 394 up; this becomes in the negation term 298 is reversed and gives a low or true signal ACCX. The ACCX signal means an acceleration command and is given to the program generator 48.

The output of the NAND gate 394 is also connected to an input of the NAND gate 374 and its output is also connected to connected to an input of the NAND gate 394 and provides a disappearing output signal ACCY of the NAND gate 374, if a DEC delay command is not available. Thus, the NAND gate 374 holds the ACCX signal at the logic value zero through the Sipaal DEC disappears, although the NAND element 392 is terminated of the clock pulse S100 emits a positive output signal.

The signal FSC for the first sampling period appears during the entire sampling period with which a journey begins, shortly before the driving flip-flop 384 is set. If the output NC of the flip-flop 382 becomes positive and the driving flip-flop releases 384, that is Signal RUN strongly positive. This signal goes to an input terminal of the NAND gate 414 and there it is also positive Signal NC is present at an input of the NAND gate 414, the signal FSC appearing at its output is immediately low and remains so from the clock signal S200, which flipped the flip-flop 382,

309848/0551 - 57 _

2325H0

until the clock signal SIOO, which flips the driving flip-flop 384 and this controls the RUN signal down and the FSC signal up. At the clock signal S200, flip-flop 382 is activated by the NAND gate 388 and in turn sets flip-flop 384 return. ,. .

The signal EI shows a call in the floor of the serial leading Car position when a hold command EIX generated by the call selector 92 will. The flip-flops 420 - 424 are used to generate the signal EI, the negation elements 400, 426-430 and the NAND element 432. The flip-flop 420 contains the NAND elements 434 which are connected crosswise and 436, one input of the NAEfD element 434 being connected to the input terminal EIX. Furthermore, an input terminal of the NAND gate 434 connected to the output of NAND gate 432. One input of the NAND gate 436 is via the negation gate 426 connected to input terminal S200. Another input of the NAND gate 436 is connected to the flip-flop 424.

The flip-flop 422 is of the JK type, the input J being connected to the output of the NAND element 436 via the negation element 428. The clock input C receives the clock signals SLOO, the input K is grounded and the output "Q" is connected to the output terminal EI via the negation element 430.

The flip-flop 424 consists of cross-connected NAND gates 438 and 440, in which an input of the NAND gate 438 with the Input terminal 'PCR, one input of the NAND gate 440 with the

309.848 / 0551 - 58 -

2325H0

is

v erb
Input terminal DECSK The output of the NAND gate 438 is connected to the clear input of the flip-flop 422 and an input of the NAND gate 436 in the flip-flop 42Ό. ,

The inputs of the NAND gate 432 are connected to the output RUN of the Flip-flops 384, the input terminal EQ1Z, the input terminal S4 and the input terminal CEN via the negation element 400. For example, a true RUN signal, which coincides with a high serial leading cabin position signal EQ1Z, causes a Floor on which the elevator is enabled (CEN = 1) that when the clock signal S4 occurs, the output of the NAND element 432 goes to zero. This output is connected to an input of the NAND gate 434 of the flip-flop 420.

When the input terminal EIX assumes a low value, flip-flop 420 is set and generates a logic one at the output of the negation element 428 and at the input J of the flip-flop 422. When the clock signal S100, the output is <? of flip-flop 422, low and negator 430 reverses this low signal to a high or true signal EI. This signal EI is sent to the synchronization stage 94.

The Rüc.kstellflipflop 424, the cross-coupled NAND element

-vZjirück ' 438 and 440, sets flip-flops 420 and 422V when on Command occurs to decelerate the car, i.e. signal DECS goes low. The reset flip-flop 424 is reset when the

- 59 309848/0551

Floor of the serially advancing car position is changed, which is indicated by a low signal PCE. That Flip-flop 420 can also be reset by the clock signal S200 will.

In addition to a hold signal EIX, the flip-flop 420 can also use this be set that the output of the NAND gate 432 assumes a low value. This happens when there is an The RUN signal coincides with the serial leading car position signal for a floor and the elevator car is released is.

A preparation signal HLX for the indicator lamps is in the NAND gates 441 - 447 formed. The inputs of the NAND gate 441 are connected to the output of the NAND gate 324 “the output of the NAND gate 360 and the input SBC connected The output of the NAND gate 441 and that of the NAND gate 443 are to the Inputs of the NAND gate 445 led «At the inputs of the NAND gate 443 is the output of NAND gate 324, the output signal. UPTE and the input signal SAC. The exit of 443 is connected to the input of a NAND gate 440. the Inputs of the NAND gate 447 are connected to the output of the NAND gate 445 and the input terminal DÜE. The exit of the NAND gate 447 is led to the output terminal HLX.

- 60 309848/055 1

2325H0

If no calls are registered, the output of NAND gate 324 is low and NAND gates 441 and 443 give Ones off. As a result, NAND gate 445 is downdriven and NAND gate 447 driven up, so that a signal HLX of the value One occurs that can be used to lock the lamp circuits. If, on the other hand, a call is registered, the NAND element 324 outputs the signal one from and opens the NAND gate 441 or 443, depending on whether the sample counter is below "the preceding The car position is scanned and whether the elevator is set to travel downwards, or the scanning of the one set to travel upwards Lift takes place above the car position «This blocks NAND element 445 and opens NAND element 447, if there is no door opening command (DOR = one). So results HLX is zero so that the indicator lights can be activated.

Figure 1o

FIG. 1o shows the schematic representation of an exemplary embodiment for the synchronization stage 94 in FIG. 3. It is used in addition, the signals EI from logic 9-6 and EQ2 from the comparator. 76 (Fig. 5) to bring in a temporal relationship. Will the signal EQ2 (leading car position = floor height) received and if no call is registered for this floor (EI = zero), EQ2 blocks an EI that occurs later. The elevator sets thus its journey continues at undiminished speed and the index level 78 emits a progress pulse PU or PD for the counter 72 and the synchronization stage 94. If there-

309848/05 Br

- 6i -

If, on the other hand, a signal EI is registered when the pulse EQ2 occurs, the braking command DEC is derived from the synchronization stage.

In detail, when the equality signal EQ2 occurs, a single pulse E2 is generated. This takes place in the NAND gates k5o and 452 and the flip-flops 454, 456 and 458. Each flip-flop consists of two cross-connected NAND gates 46o to 47o.

The signal EQ2 is each input of the NAND gates 45o and 462 supplied. The output of the NAND gate 45o is with connected to the input of the NAND gate 46o. Lines lead from the NAND gate 462 to the NAND gates 466 and 452. The The output of the flip-flop 456 is also connected to the NAND gate 452 connected, its output in turn to the NAND gate leads in flip-flop 458. Another input of the NAND gate 47o receives a DECS signal expressing the delay command. The output of flip flop 458 is with the inputs of NAND gates 43o, 464 and 453 are connected. On one Another input of NAND-Glled 453 is the DECS signal at. The NAND gate 453 delivers the pulse E2 when the equality signal EQ2 is received,

Flip-flop 458 is controlled by one of the two via an AND gate 472 End delay signals TDS and TSD reset. Further it can be reset by a signal PU or PD. The reset circuit in question contains a flip-flop 482 the NAND gates 486 and 488, and a NAND gate 484 and

"309848/0551 - 62 -

2325H0

the negation terms 476, 478 and 48ο.

One input of NAND gate 488 in flip-flop 482 is over NAND gate 476 connected to the clock signal input terminal S2oo. The signals PU and PD are present at the inputs of the NAND element 486. The output of the NAND gate 486 of the flip

482
flops / leads to the input of the NAND element 484 and via the negation element 48o to the output terminal PCR. Since PU or PD occur in the sampling interval of the clock pulse S1oo in order to set the flip-flop 482, and the clock pulse S2oo resets the flip-flop 482, the signal PCR is true, ie low, as long as the index level 78 supplies an incremental pulse, namely it lasts from the clock pulse S1oo to the clock pulse S2oo.

An input of the NAND element 484 is also connected to the input signal SI00 via the negation element 478. The output of NAND gate 484 leads to the input of the NAND gate 468 in flip-flop 458.

The logical values indicated in FIG. 1o correspond to this. those shortly before receiving a true, i.e. vanishing Signals EQ2. When EQ2 goes down, it becomes a NAND gate 450 blocked and results in a one at the output, causing flip-flop 454 is flipped and stores the pulse EQ2. The NAND element 462 then outputs a logical one, the flip-flop 456 flips and sets the output of the NAND gate * £> 2 to zero. This toggles flip 458 and sets the output of the NAND gate 468 to zero. Thus appears at the output of the NAND

^: 3 O 9 8 4 8 / O 5 b 1

. 2325H0

Element 453 a one, i.e. the signal E2 becomes true. Furthermore, the zero at the output of the flip-flop 458 flips the flip-flop 456 and thus the state of the flip-flop 458 is saved. and thereby NAND gate 452 is opened and enables flip-flop 458. The low output of flip-flop 458 also blocks NAND gate 45o.

If a delay is required, the input signal DECS of the NAND gate 4? O disappears, so that flip-flop 458 cannot be reset. If no acceleration is desired, EQ2 goes back to the value one. When the clock pulse Si00 occurs, a true _t ie zero signal PU or PD is generated and flip-flop 482 is set, as a result of which a logic one occurs at the output of the NAND gate 486. NAND gate 484 is thus blocked at the end of the clock pulse SI00, whereby flip-flop 458 is reset and. the output signal E2 of the NAND gate 453 back to the value zero

returns. The same goes for the delay when approaching one
at / end floor.

When flip-flop 458 flips back, there is also flip-flop 456 free and since EQ2 is again at the logical value one, becomes NAND gate 45o opened by the input signal from flip-flop 458. This resets flip-flop 454, which in turn Flip-flop 456 resets, making a logical one is maintained at the output of NAND gate 452 since the The input of the flip-flop 454 is now at the zero level.

Flip-flop 482 flips back on clock pulse S2oo and ends

- 64 -

3098Α8 / 05 & Ί

- 6k -

the true signal PCR. The circuit is now in its original state again and awaits a further signal EQ2.

The circuit in the is used to generate the DECS signal, as well as the DEC brake command and the door opening release signal DO

en
upper part of Fig. 1o, the / structure emerges from the figure.

The logical values specified there correspond to an elevator in motion immediately before the occurrence of the signals EQ2 and EI. When signal EI becomes true, d «, h. _o assumes the value one before signal EQ2 becomes true, ie assumes the value zero, the NAND gate 5 °° is opened and holds the NAND gate 5 ° 2 in its blocked state. The NAND element 5 ° 6 is blocked by the signal EI formed in the negation element 5 ″ Io and thus supplies a high input signal for the NAND element 5o4.

If now the signal E2 'by the occurrence of the equality signal EQ2 assumes the value one, all inputs of the NAND gate A-96 are at a high level, whereby NAND gate 508 is blocked and emits an output signal DEC with the value one, which represents the braking or deceleration command. Furthermore, the output signal from NAND gate 508 is sent to NAND gate 498 given and when the clock pulse SI00 arrives, is NAND gate 498 from a zero, which flip-flop 492 toggles. This provides a true DECS output signal and a true output signal DO what the synchronized delay and Represent door opening release commands. The elevator stops and opens its doors in response to the deceleration command

- 65 -

309848 / .OBSI

" ⁶⁵ " ■ 2325H0

and the door opening command ₉ as takes the input signal has the value one and if the waiting time has elapsed and signal D ^ 5 assumes the value one, _e h _o d the door to be closed Soll ₉ are NAND gate 49 * 4- a signal of the value Zero from "which the. Flip-flop ^ 92 reset

__ e in true, however, the signal EQ2 / {before signal EI occurs, then the pulse E2 from the logic one value to the inputs of the NAND gates 5o2 _a $ ok and KS6 applied NAND gate 5 © 2 is opened and locks the NAND elements 49 & and 500ο If signal EI would occur in the *) short interval between the Tg.ktsignals SI00 and S2oo (the index level J8 responds to S2oo if there is no signal EI at the time of SI00) _s would have this has no effect on circuit ₀ because the NAND gates 500 and k <$ 6 are blocked _o .

If a call is registered in the location of the elevator "Xiährend same the first scan before starting running ₉ then signal CELY true 'and this serves to prevent an acceleration and to form a -Türöffnungsbefehls in a circle with the Eüpflop k9o ₀ The vanishing signal CELY sets flip ^ 9o and are vFlipflop ^ 92 free ₉ by the output of the NAND gate = assumes the value one K9K | further NAND gate 5 ° 8 is locked so that _t as before the signals DEC ₀ DECS and DO are true ₀

66

2325 HO

Fig. 1 1 shows which floor calls from floor selector 3 ^ - are taken into account, the floor calls are on the left and down direction for one set to go down Elevator car 53 ° indicated, 'on the right the landing calls in

on
Downward and upward direction for a / upward travel set cabin 53® '· In both cases, the leading cabin position should have reached the 17th interconnection «

Driving the car 53o down (UPTR = zero) can be considered down to the 1st floor of the elevator down calls in 17 · floor and below until 2 Stoäk and up demands from i6 ₀ floor. The boxes concerned are ticked. The car 53o answers all down calls in its direction of travel; when there are no more down calls, it moves to the lowest registered up call.

If the elevator goes up 53 °, it takes all of them into account Upward calls in front of him, including the floor in front of him, that is from the 17th to the 29th floor, and if so these are dealt with, he drives to the topmost registered down call and begins these down calls to deal with «the same can be between the 18th and 30th floors.

Figure 12

FIG. 12 is a block diagram of an exemplary embodiment of the programmer 48 in FIG. 1. The programmer provides k8

309048/0551 _ _6? _

■■ - 67 -

a signal for the travel switch 5 © ₅ which controls the speed of the drive motor 2o ixnd thus the travel speed of the elevator 12.

The progressive generator shown is built without an electromechanical model of the lift system and regulates the lift to the optimum travel time ₉ d ₀ h _o the time interval between the beginning and the end of a journey reaches a minimum with direct regulation of the change in acceleration (jerk) and taking into account prescribed maximum values for acceleration and driving speed, _etc.

The programmer 48 receives the signals ACCX and TJPTR from Floor selector 3 ^ »which the acceleration command nxnd the Express the direction of travel command. These signals are in the Logic 5 ^ 0 for actuation signals DGU and DGD for the travel direction relay, an acceleration signal ACC, speed signals SPSI or SPS2 for a ramp generator 5 ^ 2 and a start signal START for a driver stage 552 processed.

The ramp generator 5 ^ 2 supplies a side-dependent signal TRAN, which can be used for elevator systems with a maximum travel speed of up to about 150 m / min to control the acceleration, the travel speed _s, the deceleration and the Abbrenasimg of an elevator. In the case of lift systems with a higher travel speed, the setpoint signal TRAN mzr is used for the acceleration phase, the phase of full travel and the over-

- 68 -

3098 48 / OB 51

2325H0

The gear phase between full speed and maximum deceleration is used, while the program generator k8 automatically switches to distance- dependent signals for the phases of maximum deceleration and braking until stop.

A reversible counter % kh receives the distance pulses NLC from the counter 7 o in Fig. 5 «The counter 5 ^ 4 is from a signal MXVM of the ramp generator, which assumes the value zero ₈ when the full driving speed is reached; and controlled by a signal ACC of the logic 5 ^ o, which assumes the vert zero if a deceleration is desired. These signals program the counter 544 so that it counts up during the acceleration of the elevator car according to the pulses NLC, at maximum speed (MXVM = Zero) stops counting and thus saves the distance to be traveled to a stop, and counts down when the deceleration “is initiated (ACC = zero).

The counter 544 operates on a distance delay circuit 546 which generates a speed setpoint signal DSAN proportional to the square root of the distance from the stop. The square root of the distance from the stop results in a constant delay of the elevator car ₉ , the switchover from the time-dependent signal TRAN to the distance-dependent signal DSAN by means of the switches 548 and and the driver stage 552

55o / is carried out, the switching signals at the right time TRSW and DSSW for operating switches 548 and delivers 55 °. Switching between the different

- 69 -

309848/0551

2325 HO

Speed ^ target signals is happening immediately and completely ,, In reality, however, preferably used a gradual transition from one signal to another, _o in order to cause no shocks and jerks An apparatus for carrying out such a smooth transition is, for example, in the British _o PS 1 _s 293 described O97 _P ,, located at the elevator in a predetermined distance from the stopping floor (ZOB _o 20 cm) j, it shall be given a signal HT1 of a shaft mounted in the converter -a switching device 55 ^ _B also. Fahrtrich-foungssignale-TJP and DOTiM receives _o The switching device 55 ^ outputs a speed setpoint signal HTAN to a switch 55 ^ ₉ which receives a switching signal HIS at the right time from the driver stage 522 ₉ whereby it depends on the independent speed = setpoint signal DSAW also, this transition is also switched to the distance-dependent speed = Soll = ΗΤΑΝ signal _o is preferably done gradually ,, the generation of the transducer is described igsmls HTl zobo in US PS 3 = ₉ 2o7 ₉₂₆₅

The pulse detector 6k in FIG _o 1 generates pulses "that of a pickup derived So on the elevator car and of Induktorblechen 62 in the elevator shaft in the vicinity of the end floors of meeting _o These pulses TLSDP together with a signal from a tachometer on the drive = motor 2o on an end floor delay circuit 4.58 ge = given ₀ The latter monitors the elevator speed in the vicinity of an end floor and if too high a speed is determined, it delivers a speed S = ■

, 309848/0881. ■ - 70 -

. , " ⁷ °" 2325 HO

Reference signal TSAN to stop the elevator on the end floor it is approaching »The signal TSAN is from a changeover switch 560 switched on, the sin switching signal 'TSD from driver stage 552. If the from level 558 the determined speed exceeds a certain value, a signal TOVSP is generated, which is given to an emergency braking device, not shown.

The signals emitted by the analog switches are applied to an adding amplifier 5 ^ 2, which is a speed reference signal SRAT generated for the travel switch 5 ° in FIG. 1; the latter can be constructed in a known manner.

Figure 13

Fig. 13 is a schematic representation of an execution .beispiels for the logic $ ko _o in Figure 12, "You receive besides the already mentioned input signals and UPTR ACCX nor the input signals A and SPSL. The acceleration signal ACCX becomes zero as soon as the Breras relay A (not shown) is released, and remains the same as Muli; ₉ when the brake is applied and equal to one when the brake is released ". The speed s-selection signal SPSL can be set manually or automatically to a certain maximum speed. For example, the relevant selector switch is in one position for full travel and for a Crawl speed before

309848 / OSSI

2325U0

Stopping in a second position _{or similar}

The input terminal UPTR is connected directly to an input of the NAND element 164 and via the negation element 568 to an input of the NAHB element 566. The input terminal ACCX is connected via the negation element 522. the input of the NAND elements 56 ^ 5 566 toid 57o The terminal A is connected via negation element 574 to the NAND element 57o «The outputs of the NAND elements 564 _s 566 and 57 ° are connected to the output terminals DGU, DGD and ACC connected _o The input terminal SPL is connected to input D of the flip-flop 580; the latter can be designed as a D flip-flop , which is toggled by the positive rising edge of a pulse. "The clock input of the flip-flop 58O is connected to the ACC output stick . 578 led »The output terminal ACC is also connected to the inputs of AND gates 576 and 578 ,,

When the logic 54o is in operation, a signal UPTR of the value one (upward travel) releases the NAND element 564 ρ while a signal UPTR of the value zero (downward movement) releases the NAND element 566. When an acceleration _{command occurs D} , the ACCX signal becomes zero and is sent by the. Negation circuit 572 conversely ₉ so that either NAND Glied.564 or NAND gate 566 are (depending on the direction of travel) a logical zero on the relevant output terminal _o If z _e as the lift is set to upward travel, UPTR is equal to one and NAND -Ground 564 open * If the acceleration command occurs5. Gives NAND element. 564 a logic zero on the output terminal BGU "that relay

309848/0551 - 72 -

2325U0

energized, which sets the drive motor to travel upwards.

When the floor selector 3k requests the elevator to start and accelerate, signal ACCX becomes zero and when brake A is applied, signal A is also zero. The negation elements 522 and 524 apply the reciprocal values of the signals ACCX and A to the NAND element 57o, so that the latter emits a logic zero which, via the negation element 575, makes the output signal ACCX to one. This indicates that an acceleration command has been issued and that the elevator is available, ie is ready to travel with the brake applied.

The signal ACC opens the AND gates 576 and 578 and switches the setting indicated by the speed selection signal SP.SL to the outputs of the flip-flop 580, which stores the selected speed. If the output Q delivers a one, there is the AND gate 576 from a signal SPSi of the value one. Is against the output of Q equals one, the AND gate results 578 a true output signal at terminal SPS2.

The output terminal START of the logic 580 is connected to the output of the negation element 572. If the output signal START assumes the value one, this means that the command has been issued to start the elevator, the signal START ₉ which is identical to the signal ACCX ₅ is applied to driver stage 552.

- 73 -

309848/0551

Figure 14

FIG. 14 is the schematic representation of an exemplary embodiment for the ramp generator 542 in FIG. ₀ 12 _O This stage

supplies the speed = setpoint values for the acceleration phase and the phase of full travel; In elevator systems with a relatively low maximum speed, it can be used to deliver the target speeds for a complete journey _o ,

The change in acceleration (jerk) is immediately limited to a maximum value; regardless of how quickly the elevator reacts to the speed setpoint signal ₉ , the speed jerk can never exceed the specified maximum value

The speed = setpoint value is flown by double integration of a current _B which itself is an image of the jerk _o This means that the acceleration changes that are felt by the passengers more than the acceleration or the speed j are directly controlled and are not inaccuracies due to tolerances The acceleration is indirectly controlled by integrating the jerk signal and the travel speed of the elevator is also indirectly controlled by integrating the footing signal ₉ because small deviations in acceleration and speed from the prescribed values are not perceived as uncomfortable by the passengers

309848/06 51 = 74-

- ^7k ". ■ 2325U0

like error in the jerk control.

The measure of the jerk for acceleration and deceleration is provided by positive and negative currents, these currents being controlled by an analog switch that is switched under control by a negative feedback circuit. The negative feedback depends on the maximum acceleration and deceleration as well as the maximum speed _# The switching speed of the analog switch after reaching the maximum acceleration or the maximum speed is so fast that the elevator cannot respond to it. As a result, the mean value of the switched voltages is formed in these periods, which is equal to zero »This means that the jerk in these periods is also zero«. During the transition periods between zero speed and maximum acceleration, between maximum acceleration and maximum speed ₍ between the maximum speed and the maximum delay, as well as between the maximum delay and the speed zero, the analog _{switch is set by the negative feedback signal so that it switches the positive or negative StTOm 9} without su, to the first integrator _s to during these transition periods to form a speed setpoint in which the desired maximum jerk is directly entered by means of the strength of the positive and negative currents »

The input terminals SPS1, SPS2 and ACC of the ramp generator are connected to the logic 5 ^ 0. The output terminal TRAN

- 75 3Q984S / 05S1

-75- 23,251

supplies at least the sections for acceleration and full driving speed of the speed program for the drive switch The output terminal MINA supplies a true signal (logical value zero) during the maximum deceleration and is connected to the driver stage 552. The output terminal MXVM ₉ which supplies a true signal ₉ when the velocity has its maximum value _s is to the counters 5 ^ 4 and 7 ° · - connected (see Figure 5 _o)

The ramp generator 542 includes a stage 582 for direct

Setpoint representation of the / speed change o This consists of adjustable positive and negative voltage sources 584 and 586 and an analog switch 587 <> The positive voltage source 584 is connected via the switch 587 and a resistor 589 to a terminal 588; to which the negative voltage source 586 is connected a resistor 591 liegte strength and direction of the current at terminal 588 can thus be changed by opening and closing the switch 587 _o the operation of the switch 587 is controlled by a feedback 59 ° ", the switch · 587 ₉ closes when on the feedback line 59 ° to the logic value one prevailed, and opens ₉ when the feedback line 59o den. logical value zero leads _o

The current strength at point-588 is a direct representation of the acceleration jolt and since this current intensity is given by the adjustable voltage sources 584 and 586 ₉ the acceleration jolt in the developing speed setpoint program cannot exceed the preset maximum value,

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The terminal 588 is connected to a first integrator 592, which preferably consists of an operational amplifier with capacitor 593 in the negative feedback circuit. When using such Operational amplifier, the terminal 588 is connected to its inverting input, while the non-inverting input is grounded. Since the integral of the acceleration jerk is the acceleration or deceleration, the output signal represents of the first integrator 592 at terminal 59 ^ the acceleration or delay.

The terminal 59 ^ is connected to a second integrator 596, which also consist of an operational amplifier with capacitive negative feedback 595 and a resistor 597 connected upstream can. The non-inverting input is grounded again. At the exit 59s of this second integrator can be the speed setpoint be removed; accordingly this output is connected to the output terminal TRAN.

To limit the acceleration, the deceleration and the Speed to certain maximum values, negative feedback stages are provided that control the switching of the Switch 587 are involved.

The speed negative feedback compares the signal of the output terminal 598 of the second integrator 596 with a Reference signal. To do this, the removed from terminal 598 Speed signal reversed in a negation element 600; this consists e.g. of an operational amplifier with ohmsclier Negative coupling 606. Terminal 598 is via resistor bo8

309848/06 51 ''_'77

. - 77 - 2325UO.

connected to the inverting input of this operational amplifier; the non-inverting input is through resistor 6o4 grounded. The negative feedback and input resistors 606 and 608 have the same value so that the amplifier has a gain factor of minus 1 «

The output terminal 6o2 of the negation element 600 is connected to a comparator 6I0, which can consist of an operational amplifier; the output terminal 6o2 is connected to the inverting input of the operational amplifier. The non-inverting input is connected via a NOT gate 612, a speed selector H '61 and an analog switch 616 connected to a reference voltage + V.

The analog switch 616 includes two switches 618 and 620 which are operated by input signals SPS1 and SPS2. These signals are provided by the logic $ ko . The outputs of these two switches are connected to selected inputs of the speed selector -614, which consists of resistors 622 and 624 of different sizes connected in parallel. The other ends of these resistors, including a conductor 62 6 without additional resistance, which represents the maximum selectable speed, are jointly connected to the output terminal 628 of the speed selector 6 \ k . This output terminal is connected to the input of the negation element 612 via a resistor 632. The negation element 6.12 again consists of an operational amplifier with ohmic negative feedback 630 * The reversing input of the same is grounded via the resistor 63h * PÄ ^e resistors 630 and, 632 have the

309S4B / OSS1 - 78 -

same values. The output signal of the negation element 612 is taken from a terminal 636 via a resistor & yf . Terminal 636 is connected to the non-reversing input of comparator 6I0. If the speed signal from terminal 6o2 to comparator 6I0 is less than the setpoint value at input terminal 636, there is a positive output signal from comparator 6To, which is reversed in negation element 638 in order to appear as a logic zero at terminal 64o. Conversely, if the speed input to comparator 6I0 exceeds the reference set point at terminal 636, the output voltage of comparator 6I0 is negative and is reversed by negator 638 to appear at terminal 64o at a logic one level. At terminal 64o there is a logical one if the input speed exceeds the setpoint speed, and a logical zero if the reference speed exceeds the input speed.

The acceleration feedback from terminal 59 ^ consists of two separate loops for acceleration and deceleration. The loop for acceleration contains the negation term 642 with ohmic negative feedback 646 and input resistors 648 'and 650, as well as the comparator 644. The resistors 646 and 648 have the same value to give a gain of -1.

The output terminal 652 of the negation element 642 is via a Resistor 653 with the inverting input of the negation element 600 connected. Resistor 653 is large compared to the value of the

- 79 -

30964870551

" ⁷⁹ " .. 232SU0.

Resistor 608 (e.g. _a B _o ten times as large) _o Consequently sind./ the feedback circuits for the acceleration and speed meshed with each other and the value of the bridging resistor 653 is selected so 'that a temporary maximum speed during the transition from Maximalbe = exceeded acceleration to vanishing Acceleration and maximum speed is prevented _o

The output terminal 652 is the negation gate 642 "connected to the input of the! Comparator 644. ₉ whose inverting input connected to the ¥ ählarm 65 ^ a recap · = is connected nigungswählers 656 _o ¥ ählarm 654 is with a specific resistance of Beschieunigungswalilers" with the non-inverting S ₀ B _{0 connected to} a resistor 658. The resistance value of the same results in the desired acceleration, If the acceleration value at the input of the! Comparator 644 from the terminal 652 exceeds the _set value from the acceleration selector 656 s the output signal of the! Comparator 644 is positive _o It is from the Negations = element 660 reversed and appears as a logic zero at terminal 662. In the reverse case ₀ d _o h _o if the acceleration obtained from the integration exceeds the setpoint value, a logic zero occurs axa of terminal 662 _o

The terminals 64o and 662 ₉ of the speed or _o acceleration corresponding currents lead, a NAND gate 664 is * connected to the inputs, connected "Sox-Zohl the speed and the acceleration can therefore by the occurrence of a logical zero the output of the NAND gate 664

, - 80 -

'309848/0551

- 8ο -

"bring to the logic one value, the output signal of the NAND gate 66k is connected to an input of the NAND gate 666, whose other .Eingang is connected to the output of the delay loop _o The output of the NAND gate 666 is lungs line with the rear Kopp - 590 connected so that the switching of the NAND gate 666 controls the state of the analog switch 582 "

The feedback loop for the delay contains a comparator 668, which here consists of an operational amplifier " whose non-inverting input is connected to terminal 59 ^ and whose inverting input is connected to the selector arm 6 ^ h of the acceleration selector 656" So also in the delay phase controls the setting of the acceleration selector 656, the maximum delay "the output signal of the comparator 668 is then placed inverted by the NOT gate 670 and to a terminal 672 which is connected to an input of the NAND gate and to the output terminal MINA _o the signal MINA is true, ie, equal Nuil ₉ during the maximum deceleration «,

The output signal of the comparator 668 is positive _? if the delay value supplied by terminal 59 ^ exceeds the setpoint value, and negative ₂ if the setpoint value exceeds the delay value obtained through integration- _{o In} the latter case, terminal 672 carries a logic one and ± n the former case a logic zero ₀ Outside the delay phase takes the terminal 672 the value one, as will be explained _o In these times wiikt so the NAND gate 666 as a negation

_ 81 - '

309848/0561

2325U0

element for the output of the NAND element 664 “where the acceleration = nigunfs = or speed input of the NAND gate 664 die Switching of the analog switch 587 controlled In the delay = tion phase, however, the output of the NAND gate 664 is at the value one and is NAND gate 666 free, so that this from the delay feedback at terminal 672

As will be explained xiirdj, the output of the! Comparator 61 switches ο during the phases maximum speed rapidly back and _o To generate forth a defined signal indicative of the phase of maximum speed of the speed command signal indicative of _s is a memory stage 673 ₉ is provided with the Input = terminal ACC and terminals 662 and 6ko is connected _o The storage stage 673 supplies the signal MXVM ₅ which only assumes the true value during the phase of maximum speed of the speed setpoint TRAN _o

The memory 673 includes a NAND gate 672 _ύ one input via NOT gate 674 to terminal 64o 'is connected, while the other Eingang- via a NOT gate 678 to the output of a flip-flop 676' to the cross-coupled NAND Gliedern680 and 682 anscMiessqEin input "of the NAND gate

is
680 / with the terminal 662 and an input of the NAND gate 682

connected to the ACC input terminal

_{The output of the NAND gate} 672 leads to a flip-flop 684 ΰ which is here of the JK type «. With positive logic this results

309848/0551

. - 82 -

2325.H0

Flip-flop a logic one at the terminal Q with a low input at the terminal PRESET and a logic zero at the terminal, Q with a low input at the terminal CLEAR ₀

The output of the NAND element 672 is connected to the input PRESET _B the input terminal ACC is connected to the input CLEAR, the inputs J ₅ C and K are grounded and the output Q is guided via negation element 688 to the output terminal MXVM. Memory level 6j $ is written after an overview of the entire operation of the ramp generator has been given,

Figure 15

15 9 consisting. from FIGS _o 1 ^ A and if ^ Bs is a graph for explaining the flow = and voltage course at various locations of the ramp generator according to Figo 14 _O To explain the operation thereof was first assumed that .the elevator is at rest and there is no need is logged in o Thus the signals SPSI ₈ SPS2 and ACC are on the logical. Value Nuil ₀ both at the input and at the output of the operational amplifier 612 prevails the voltage value Nuil ₉ as shown in FIG _o 1 5B "indicated at 689 is the switch 587 open (690 in Figo I-5A) ρ a current flows from the inverting input thereof of the first integrator 592 and the output to be positive, "as indicated at 692 in Figure 1 _o 5 & Thereby, the output of the second integrator 596 is negative ;, as point 69k of the curve 596 shows ₀ the output of the Operations begins ·

. 83 -

3098 48/0581

" ⁸³ '* ■? 325148

Amplifier 600 goes; therefore in the positive (see point 696 of curve 600) ο This output signal is given to the inverting input of the comparator 6I0 (Fig. I5B) and compared with the input signal at the non-inverting input of the amplifier 612 ₉ which is equal to zero ₀ Since the Gesclrwimdigkeitssignal vom Operational amplifier 600 exceeds the setpoint signal from operational amplifier 612, the output of! Comparator 61 is ο negative5 as indicated at 698 in curve 6I0 »The negative output signal is reversed by negation element 638 (digit 7oo from the value one) and then to an input of the NAND- Link 664 given _o

The acceleration selector 656 supplies a positive voltage at the inputs of the comparators 668 and 644 _o Since there is no acceleration or deceleration ₉ the setpoint voltage exceeds the acceleration and deceleration signals and the output signals of the comparators 668 and 644 are negative, as in Jo2. and 7 ° 4 indicated in the corresponding curves _o The. negative output signals of the comparators 668 and 644 are converted into logical ones by the negation elements 67p and 660, as the positions 706 and 708 show, the output signal of the negation element 660 goes to the other input of the NAND -Glecte 664 and the output signal of the negation = element 670 to an input of the NAND element 666 _O

So if the elevator is at rest and switch 587 is open, both inputs of the NAND gate 664 go high.! so that its Output from the logic state one (place 71o) in the closed =

. - 84 -

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2325U0

was zero (position 712) passes _o As a result, the output of the NAND element 666 ' goes from state zero (position 714) to state one (position 716) via “This causes a closing command for the analog switch via the feedback line 59o 587s as shown at 718 in Figure 15A

When the switch 5 ^ 7 closes _s flows corresponding to a maximum jerk current into the inverting input of the first integrator 59.2 ₉ so that its output (point 72o) is negative "The output of the second integrator begins to be due to its positive (position 722) and the output of the operational amplifier 6oo becomes negative (point 724) "The reversing input of the speed comparator 6io thus receives less than the input signal zero from the setpoint circuit at the non-reversing input and its output becomes positive (point 726 in FIG. 15B)" This corresponds to a signal from the value zero at the output of the negation element 638 (position 728) and the outputs of the NAND elements 664 and 666 are set to one (position 73o)

zero
■ bzw7v (point 732) placed _s why analog switch 587 opens again (position 734 in Figure "15A) ₀ This game is repeated at very high speed ₉ which depends on the threshold of! Comparators 6I0 and the characteristics of the integrators 592 and 596" The Switching speed _p, which will generally be greater than 10 kHz, is much too high for the elevator to be able to follow it, so that it does not "interfere with the movement of the elevator". The rapid switching of switch 587 is shown in FIG. , I5A and 15B are shown much too long in relation to the effect of the switchover

_ 85 - '

309848/055 1.

■ - 2325H0

the switch 587 to the various circuit elements to ζ own _o

The rapid changeover of the analog switch 587 continues thanks to the speed feedback and the! Comparator 61 ο as long as the elevator is at rest and no acceleration command is received _o This phase is indicated in Fig. 15- & as phase Σ

The phase II ₉ starts when an acceleration command arrives _s is expressed by ₅ that ACC and pass PLC1 or PLC2 of logic .NULL to the logical value one (point 736) o Here arrived ₉ that the speed ~ selector SPSL- (Figure is ₀ I3) is set to _s that SPS1 ACC zusammenfälltο Bas signal SPS1 closes the analog switch 618p so that the output of the operational amplifier 612 at 73-8 is negatively _o (Fig ₀ 15 ^) Because the output of operational amplifier 600 is almost at "zero _{s it} is more positive than the negative output of the operational amplifier 612 and the output of the comparator 6I0 becomes negative (position 7 ^ q) ₀ This means a logic one at the output of the negation element 638 (place 7 ^ s) ₅ a logic zero behind the NAND Element 66k (position 7kk) and a logical one behind the NAND element 666 (position 746) _o This closes analog switch 587 (position 748 in Fig. 1

~ 86

309848 / 0Β5Ϊ

. - 86 - ■

The quick toggling of the analog switch 587, the brought the mean jerk value to zero and also the acceleration and speed values to full, is now over and the Switch 587 'remains closed until the selected setpoint of Acceleration is achieved. Closing switch 587 causes the output of operational amplifier 592 to become negative a slope 750, which is determined by the preset size of the jerk value »This gives the output signal of the Operational amplifier 592, i.e. »the first integral of the jerk value, the acceleration program, the rate of change of which cannot exceed the preset value »

The linearly decreasing output voltage of the operational amplifier 592 is integrated again by the second integrator 596 and thus results in a smooth, curved transition 751 from zero a predetermined speed “when the maximum acceleration is reached »

The operational amplifier 642 inverts the output of the first Integrator 592 and applies a positive signal 752 to the non-inverting input of! Comparator 644o The increasing Size of the same with the constant positive acceleration setpoint compared to the one at the other input of the! Comparator-644 is applied; when the acceleration signal 752 is the acceleration setpoint at point .754, the comparator 644 switches from the negative voltage value 704 to a positive one

. _ 87 -

309848/0551

Voltage value 756 to "membered The negation 660 Switching an thereupon by the logiscnen one (point 708) for logically Mull - (point 758) _O Thus, the output of the NAND gate 664 receives the I * 7ert one at (point 76o) _5, the output of the NAND element 666 takes on the value zero (position 762) and the switch 587 opens at 764o This ends phase II and phase III begins »

In phase III, the acceleration is kept at a constant value by rapidly changing over the switch 587 under the control of the comparator 644, ie the output signal of the first integrator 592 fluctuates only slightly around a mean value (point 766) and at such a high frequency that this Fluctuation has no influence on the travel behavior of the elevator ο The travel speed increases continuously, according to the fact _p that the acceleration signal, which is constant in mean value, is integrated in the second integrator 596 and thus results in a mean value linear increase in speed (position 768) a more negative going input signal 770 to the comparator 610 "If this reaches the negative speed setpoint _p 771 on 'other input of the! comparator 610 it switches at 772 from a negative to a positive value to" so the negation element 638 is obtained at the output 744 is a logical zero, the output of the NAND element 664 becomes one at 676 and that of NAND element 676 becomes zero at 778 and the analog switch 587 opens at 780 _o This ends phase III »

~ 88 ~

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~ ⁸⁸ - 2325H0

The positive input of negator 600 in the speed coupling circuit from the second integrator 596 is in phase III by the positive output of the negation element 642 in the acceleration coupling circuit "supported .. This interaction of the two feedback loops causes the output of the negation element 600 reaches the speed setpoint at 771 somewhat faster than without this interaction. Through this if the prescribed target speed is exceeded somewhat, but an overrun of the speed program 596 becomes progressive during the transition from the period Driving speed prevented during the period of constant driving speed in phase IV.

When switch 587 opens at 780 to end phase III and to begin phase IV, the output voltage of the first takes off Integrator 592 increases linearly along line 782 from the constant negative value 766. The slope of the line 782 and with it the merging speed of the acceleration is determined by the. Presetting of the jerk value determined.

The second integrator 596 provides a smooth curved one Transition 784 "© m linearly increasing section 768 to a constant section 786 »To the extent that the output voltage of the second integrator 596 expires flat, the element on the negation is 600 incoming support from the negation element 642, the extent of which is determined by the resistor 653, to zero on the Line 788 reduced. This can reduce the output voltage of the

- 89 -

309848/0551

Negation element 600, which exceeds the speed setpoint to the setpoint given by the speed selector 656 return when the speed program 596 arrives at the level of the speed setpoint «So it is in phase IV the section 790 of the output voltage of the negation element 600 still slightly below the setpoint ". When this tension is on the When the size of the setpoint increases, the! Comparator 610 switches at 792 from a positive to a negative starting value, which in turn the negation element 638 to the value one, the NAND element 664 switches to the value zero and the NAND gate 666 switches to the value one. As a result, switch 587 closes and phase IV ends will.

Phase V is the output voltage of the second integrator to keep · 596 constant at the level 786 "When switch 587 closes at the beginning of the phase V of a rapid switching of the analog switch 587 under the control of the comparator 61O _5, the output voltage of the first integrator is 592 negative, that of the second integrator 596 more positive and that of the negation element 600 more negative and when the speed setpoint is reached, the output of the comparator 610 becomes positive, whereby the negation element 638 generates a logic zero which is transmitted via the NAND elements 664 and 666, as well as the feedback line "590 causes an opening pulse for the switch 587 at the point 796 <,. This in turn leads to the closure of the switch 587 in the manner described several times, so that in phase V the analog switch 587

309848/0581

constantly opens and closes and thus keeps the travel speed of the elevator at a constant value «,

Phase V is ended when the floor selector gives the command to bring the elevator car to a stop on the floor of the leading car layer. This is expressed in that the signals ACC and SPS1 at position 800 assume the logical value zero. This initiates phase VI, which represents a smooth transition from maximum, constant driving speed to maximum deceleration. When SPS1 goes to zero, the speed setpoint at the input of operational amplifier 612 becomes zero, which is why the output of the same switches from level 738 at 802 to zero positive and makes the output of negation gate 638 at 806 zero and that of NAND gate 664 at 808 one. The other input value of the NAND element 666 from the feedback circuit for the delay is still at one, which is why the NAND element 666 goes to zero at 810 and opens the switch 587 at 812.

This opening increases the output voltage of the first Integrator 592 linearly from zero along a curve 814, whose Slope is determined by the set jerk value. The output voltage of the second integrator 596 falls in one smooth curve 816 from the maximum speed value 786 away. If the deceleration on line 814 exceeds the deceleration target

- "91 -

3 0 984 8/0551

2325H0

value has reached, the comparator 668 switches its output voltage from a negative value 702 to a positive value 818 “The negation element 670 switches to the logic value zero at 820, which is why the output value of the NAND element 666 goes high at 822 and the switch 587 at 824, “This ends phase VI and begins phase VII ₅ which means a constant travel deceleration ο

By closing the switch 587, the output voltage of the first integrator 592 drops and when it has fallen below the reference value of the delay, the output of the comparator 668 switches to a negative voltage, the negation element 670 goes to one and the NAND element 666 to NuIl ₅ doh "Switch 587 opens" This starts the chain again, which leads to the renewed closing of the switch 587 and switch 587 now again continuously carries out rapid switchovers in order to keep the output voltage of the first integrator at the preselected maximum positive value 826 “As a result of this constant positive output voltage of the first integrator, the output voltage of the third integrator 596 decreases linearly along a curve 828 and the negation element 600 shows an increasing tendency towards Mull. . The -increase of the output voltage of the negation member 600 along the curved section 830 is controlled by the negative section supports 832 deir output voltage of the negation member 642 _s so that the cam 830 reaches the level zero before the output voltage of the second integrator 596 and thereby exceeding the speed

- 92 309848 / OBSI

Program beyond the setpoint in the same way as in phase IV. When the curve section 8 30 reaches the response threshold of the comparator 610 at the point 834, it switches from a positive to a negative value at 836, the negation element 638 goes to one at 838, the NAND element to zero at 840 and the NAND element Member 666 at 842 to one, so that switch 587 closes at 844 and thus ends phase VII and initiates phase VIII.

Phase VIII represents the transition from maximum deceleration to zero speed. When switch 587 closes at the beginning of phase VIII, the output voltage of the first integrator 592 decreases along curve 846 with the set constant slope, the second integrator provides a smooth curved transition from last speed reached to zero speed and the combination of the output voltages of the second integrator and operational amplifier 642 (the latter rises to zero along curve 850) prevents operational amplifier 600 from returning to the setpoint before the elevator gently stops at 852. When the elevator car stops, phase VIII ends and phase I begins again »

The storage stage 673 supplies a false (high) signal MXVM, until the comparator 610 indicates that the maximum speed has been reached. At this point in time, as in Fig. 15 B \ indicated, signal MXVM at position 854 at zero. Is the

- 93 309848 / Q551 * "

- ■ '' '■ "■ 2325HO

If the elevator is at rest, the output voltage of the negation element 660 is high, as a result of which flip-flop 676 is enabled. Since signal ACC is equal to zero, flip-flop 676 results in a logic one , which results in a zero in 4-segment element 678. "'NAND element 672 therefore outputs a one to input PSESET of flip-flop 684 = the ACC signal supplied at input CLEAR with a value of zero yields a logic zero at the output Q of flip-flop 684 which provides at the output terminal MXVM -a logical one "If desired, an acceleration signal ACC so.geht by one and thereby the flip-flop 676 and 684 freely ₀ is the maximum acceleration is reached, the hegation element 660 goes to zero at 758 and toggles flip-flop 676 so that the negation element now outputs a logic one to an input of the NAND element 672 the negation elements 638 and 674 apply a logic one to the other input of the NAND element 672, so that this is opened and flip-flop 684 toggles “which as a result a signal of the value Ei ns at the output Q “which after reversal in the negation element 686 generates a true signal MXVM of the value zero. If the signal ACC goes to zero, then the elipflop 676 is toggled again and causes the NAND element 672 to output a logical one; the logic zero at the input of flip-flop CLEAR tilts 684 to generate an output value from the Q value of one, which, after inversion, a high signal MXVM (value one) yields _r as in 856 in Fig 15B _o ο shown ''.

= 94 - '

309848/055 1

2325H0

Figure 16

Figure 16 is a diagram of the driving behavior of the elevator car, thus corresponds to the curves for R uckwert, acceleration and speed in Fig. 15 without the rapid switchovers which do not affect the behavior of the elevator itself. The curve of the jerk value represents the input voltage of the first integrator 592 at terminal 588. During the rapid changeover, the jerk mean value is equal to zero. When the switch is closed, a positive setpoint value for the jerk is prescribed; a negative jerk value is specified when the switch is closed.

The speed curve, i.e. the output voltage of the 'second Integrators 596, as mentioned, can be used for elevator systems with relatively low maximum speed can be used for full drive control. At very high speeds over about 150 m / min, that would be the time-dependent The ramp generator-provided speed program is not accurate enough to stop the elevator car exactly at floor level to enable. Therefore, according to FIG. 12, the programmer 48 contains, in addition to the ramp generator 542, a path-dependent one Delay circuit 546 and a position sensing circuit 554. According to FIG. 16, the program signal SRAT for this case is composed of a section 860 from the ramp generator, which includes phases I - VI, a section 862

"95 _

30 9848/0551

from the path-dependent delay circuit 546 for phase VII and a section 864 of position sensor circuit 554 for phase VIII,

Figure 17

j

17 shows a schematic representation of an embodiment of the reversible counter 544 and the path-dependent delay circuit 546 in FIG. 1 1 ₀ The delay circuit 546 is able to bring the elevator car into the stop zone with precision regardless of long-term changes in the circuit constants. The driver stage 552 switches the speed program from the time-dependent ramp generator 542 to the path-dependent delay circuit 546 when the signal MINA goes to zero "and thus indicates that the maximum delay has been reached At this point in time , but with regard to the measure "which corresponds to the point / which the car would be when switching from the delay circuit to the position sensor circuit" This is the only point for which the greatest accuracy is required this specific distance from the floor in question immediately before the use of this circle, the circuit does not need to be constructed over a long period of time, "which makes it much cheaper"

309848/0 55

- -96 -

2325U0

The reversible counter 544 in FIG. 17 has input terminals IDLE, MXVM, ACC and WLC. The importance of the fed there Signals was explained earlier. It should be remembered that the distance pulses which e.g. specify an elevator travel of one centimeter each.

The number of (preferably binary) counter stages 8 70 in the Counter 544 should be sufficient to determine the maximum distance over which the elevator is accelerated, measured by the distance pulses, to count. In the example shown, three synchronous counter stages 872 - 876 are connected in cascade. So it turns out a twelve-part counter, the one at the specified measuring length is sufficient to count a distance of about 40 m. The reset inputs CL of the three counters are connected to the input terminal IDLE. The inputs UP and DN of the first counter 872 receive the distance pulses NLC via a circuit that consists of the NAND gates 906-912 and the negation gates 902 and 904 exists. The connection between them and with the other entrance gill MXVM is from the drawing evident.

The four outputs A, B, C and D of each counter are each connected to an input of a total of twelve NAND gates 878-900. Furthermore, the outputs B, C and D of the counter 874 and the outputs A, B, C and D of the counter 876 are via negation elements 95O - 956 connected to the inputs of a NAND gate 948,

- 97 309848/0551

· * 97 ~

2325U0

whose output leads to an output terminal NL, 16 »

Bin-further input of each NAND element 878-900-is with the Output terminal 999 of a circuit connected to the negation elements 914 and 916, the AND element 918, the NAND element 920 and the monostable multivibrator 922 includes «the inputs of the AND element 918, the signal ACC reversed in negation element 914 and the carry signal from last counter 876 become fed *

The outputs of the NAND elements 878-900 are connected to output terminals NL1-NL12 via negation elements 924-946; however, the negation elements 928 and 934 are designed as NAND elements, the second input of which is connected to point 999 is"

For the functional description of the counter 544 it is assumed that, that the elevator is ready to run; in this case the input signal IDLE occurs and represents the twelve outputs of the Counter 870 back to zero »When an acceleration command arrives, the Sigial IDLE goes to zero and returns the counter 870 free while the acceleration signal ACC goes to one and the ramp generator 542 provides the speed program, which initiates the movement of the elevator car “If the elevator starts up, a pulse NLC is emitted for every one centimeter of distance., The input signal MXVM has the value one,

309848 / Q551

2325 UO

since the elevator has not yet reached its maximum speed

^ wplementjir_e_
has reached "The ^v about carry output B of the counter 876 is as long as a signal from the value one from when this counter is not full. The two NAND gates 906 and 908 are thus opened by the pulses NLC. At the output of NAND element 906, with each pulse NLC, a zero occurs, which sets a one to the input of counter 872 via NAND element 910. The negation element 904 ensures that the ACC signal blocks the NAND element 912. When the elevator has reached its maximum speed, the MXVM signal goes to zero, so that the NAND gate 906 is blocked and the NLC pulses can no longer reach the counter'870. The counter reading remains at the last value reached.

When signal ACC goes to zero because a delay is required, signal MXVM goes back to one, but MAND-Glled 910 is now locked / errted by the ACC signal that has disappeared. The negation element 904, however, opens the NAND element 912, so that the pulses NLC on the down-counting input of the Tough 872 arrive. The number in the counter 870 now gives constantly the distance from the holding floor. The counter registers when the acceleration and deceleration values are the same exactly the distance from the floor of the leading car position when the ACC signal goes to zero, since this distance always with that of the departure floor during the acceleration phase for matching speeds matches. . 99 _

3 0 9848/056 1

When the countdown has reached 32, d <, h. the elevator is still 32 cm away from the stopping floor. so the outputs B, C and D of the "counter 874 and the outputs A ₉ B ₉ C" and D of the counter 876 have the logical value NuIl ₀ These zeros) are reversed by the negation elements 950-956 so that NAND element is opened and a signal NL16 of the value zero äSsfibt _ff which indicated the mentioned distance from the stopping floor

When the delay has been initiated, the path-dependent delay circuit 146 in FIG. 17 supplies a speed program which is proportional to the square root of the distance from the stopping mechanism happens in Fig. 12. The output of the counter 870 is used first when the delay is initiated, until the speed program switches from the delay circuit 546 to the position sensor circuit 554 "In order to ensure a smooth stop during this transition!" Circuit for the formation of the square root in the circle 546 have an accuracy of - 0.05 % - Such a circuit

loo

3 0 9 8 U 8 / UB b 1

2325U0

would be quite expensive to manufacture. Therefore, a different approach has been taken in designing the circuit of Figure 17 so that an operational amplifier with a simple analog multiplier can be used in the feedback loop to form the square root. Such a device maintains its calibration during the time interval that is required to decelerate the elevator car and bring it to a stop to provide a relatively simple delay circuit that provides the desired accuracy of 0.05% at the transition point.

For this purpose, the reversible counter 544 is designed in such a way that that before the start of the delay phase he has the binary number 10100, i.e. the number 20, which corresponds to the switching point mentioned, shows at its output, and only then on the display of its actual counter status toggles when the delay command arrives.

When the ACC signal is zero, the AND gate 918 has

two input signals with the value one, namely one from the negative carry output B of the counter 876 and one from the input terminal ACC via the negation element 914. The output Tj of the commercially available monostable multivibrator 922 is connected to an input of the NAND element 920 and thus provides an output signal with the logical value one.

3098-48 / 055 1 - 101 -

This gives a logical one at the output of the NAND element 920, which is negotiated into a logical one by the negation element 916. In the idle state, terminal 999 is at the logical value one, which enables the NAND elements 873 = 90O ₅ AND 928 and • »

The acceleration command is expressed by the value of one of the signal ACC ,, As a result, the AND gate 918 disabled NAND gate 920 is "a .Eins '', and a Nuil appears at terminal 999 ₀ The NAND gates 878-900 all emit a logical one, so that _{logical zeros occur at the outputs NLi 11} NL2, NL5 and NL7 NL12 ,, The NAND gates 928 and 932, on the other hand, provide output signals with the value one ,, Thus the output terminals NL1 - NL12 represent the binary number 10100 which corresponds to the number 20 in the decimal system »If the ACC signal returns to zero at the beginning of the delay phase, the output of the AND element 918 goes high again, as a result of which the multivibrator 922 emits a negative pulse of a predetermined duration of the NAND gate 920 at the value one and the terminal 999 at the value zero

If for any reason the counter 870 is already at zero ' have counted down before reaching the switching point, so the delay circle 546 would take the square root of zero, which is equal to zero, "That would be that. Velocity =

completed '
program ^v and the elevator would already be shut down

- 102 '' 3 0 9 8 A 8 / ü 5 5 1

the negative carry output of the counter 876 is fed to the AND gate 918, the output of the counter 544 is forcibly set to the number 20 when the counter 820 has counted down to zero. Has not yet reached the cm distant by 20 from the stop ümschaltstelle in this time of the elevator, then a non-zero output voltage of the delay results in ögerungslcrei ses through which the elevator is further guided in its direction of travel, _n until the changeover point is reached. The negative carry of counter 876 is zero when the counter has counted down to zero. This initiates the same process as when the ACC signal goes to zero.

Delay circuit 546 in Fig. 17 includes a digital to analog converter 960, a negation term 962, a square root. 964, negation elements 966 and 968 and a sample and hold stage 970.

The converter 960 is a linear converter which outputs a predetermined DC voltage, Venn its input terminals to NL1 NL12 all at the logic value one are, and gradually lower voltages corresponding to the down-counting of the binary number supplies.

The output voltage of the converter 960 is applied to the negation element 962, here from an operational amplifier with ohmic Feedback 972 exists. At the entrances are the

- 103 309848/0 551 '

Resistors 973 and 974 inserted around the delay properties to be able to choose is at the output of the operational amplifier 962 a "selector switch 976 with a selector arm 978 and several optionally switchable resistors 980 provided

Analog stages for the formation of a square root are known "Here the square root stage 964 consists, for example, of an operational amplifier 982 with an analog multiplier 984 and a resistor 986 in the feedback loop voltage source 988 connected is ο thus, if the voltage source 988 is set to zero, are in the absence of voltage from the operational amplifier 962, the output voltages of the amplifier 982 and the multiplier 984'gleich Nuil ₀ Mimmt the output voltage of the negation member 962 from zero to -X volts so. is the output voltage of the multiplier 984 + X volts and to bring about an adjustment of the inputs of the operational amplifier, the signal "Vx volts" must appear at the input of the multiplier 984. If the voltage source 988 is not set to zero, the output voltage of the operational amplifier is 982 proportional to the square root of the input voltage from the operational amplifier 962, increased by a constant value "which depends on the setting of the voltage source 988"

/ ■ - 10 4-

309848 / Ü5S1

The output signal of the operational amplifier 982 is via "the Resistor 98 9 given to a negation member 966, which again as an operational amplifier with ohmic feedback 990 and Input resistance 992 is formed at the other input. The output of the latter is switched to another via a resistor 994 Negation element 968, which is again designed as an operational amplifier with ohmic feedback 998 and input resistor 996 is «The output of the operational amplifier 968 supplies the output voltage DSAN representing the speed program during the deceleration »

A selector switch 1000 is optionally provided to provide a bias to the input of the operational amplifier 968 and thus set various delay properties. The selector switch 1000 has a switch arm 1006 through which. a DC voltage 1002 optionally via various resistors 1004 can be applied to the operational amplifier 968.

The sample and hold circuit 970 includes a comparator 1008, which preferably.from an operational amplifier with Zener diodes 1010 exists in the feedback loop. The reversing entrance the same is with a reference voltage 101.2 via a voltage divider 1014 connected. The reference voltage is equal to the nominal value of the output voltage DSAN if the counter reading of the counter 544 reaches the value that corresponds to the switching distance from the stopping floor (here 20 cm). The non-inverting input of the

- 105 309-84 8/055 V

- 105 -. 2325 HO

Operational amplifier 1 008 is connected to the resistor 1016 Output terminal DSAN connected to provide the required information with regard to the value of the signal DSAN,

Any deviation of the output voltage DSAN from the reference voltage at the voltage divider 1O14 causes a polarity change at the output of the operational amplifier 1008 in such a way that the control deviation is corrected scan full 'ride ο In this time interval appears at the output of the counter 544 by the decimal number 20 corresponding to binary number "corresponding to the UmschaItabstand entspricht- In this time interval is developed the voltage and stored, for calibration, i.e.," h _o for the correction of the output voltage DSAN to the reference voltage is required »Immediately before the counter 544 switches over from the constant output value to the actual count, the feedback part of the sample and hold circuit is separated from the memory part so that the calibration voltage for the switchover point can be held during the delay process, without e to be influenced by the variable count of the counter 544. This calibration voltage has no disruptive influence on the operation of the elevator, while it suffers a delay from its maximum speed to the switchover point, since its value is irrelevant _f as long as the number in counter 544 is relatively high, "

- 106 3 0 9 8 4 8/0651

The calibration voltage only becomes important when the count has reached the Switching distance is approaching; then it creates a seamless Transition between the delay signals and the position sensor signals.

Correct coordination of the sample and hold circuit 970 with the output values of the counter 544 can be caused by an acceleration signal ACC of the value Bins for activation the sample and hold circuit is used; the feedback loop the same is separated from the memory section when the ACC signal assumes the value "zero" because a delay is required will. The monostable multivibrator 922 is given its purpose here, since it enables the counter 544 to be switched by one delayed sufficient time to open circuit 970.

The sample and hold circuit 970 contains in the illustrated embodiment a negation element 1018, a PNP * transistor. 1020, an NPN ~ Translstor 1022, two field effect transistors 1024 and 1026 and a capacitor 1028 which is included in the Drawing visible manner with each other and with the resistors 1030-1038 are connected.

If the input signal ACC assumes the value one, the counter 544 switches to its fixed output value and the input signal blocks after reversal in the negation element 10i8 via the resistor ^; 1O3Ö the transistors 1020 and 1022, so that the voltage 'zero between the current supply electrode and the:

3098 48/0 56 1 - ■ ■ ■■ " ¹ O ₇ _

Control electrode of transistor 1024 results in "and the current path of transistor 1024 assumes a low impedance »As a result the output voltage of the! Comparator 1008, the assumes the value that is required to adjust its input terminals, connected to the charging capacitor 1028 » The one with the current removal electrode D of the transistor 1024 and charging capacitor 1028 connected to the control electrode G of transistor 1026 and grounded at one end causes transistor 1026 according to the charging of the capacitor 1028 begins to conduct and a calibration voltage is applied to the reversing input of the

Op amp 968 there. If the output voltage of this amplifier is equal to the reference voltage at the inverting input of the comparator 1008, the charge of the capacitor 1028 is stabilized and the same applies to the voltage applied to the input of the operational amplifier 968 «

If the ACC signal takes on the value zero due to a delay requirement, the negation element 1018 applies a positive voltage to the transistor 102O _9, which causes it to start conducting and provides a base bias for the transistor 1022. The transistor 1022 is also conductive and connects the control electrode G of the field effect transistor 1024 with a negative DC voltage sourcei 033 »This blocks the transistor 1024 and separates the output of the! Comparator 1008 from the capacitor 1028» The monostable multivibrator 922 keeps the counter 544 at its fixed level long enough to disconnect the capacitor 1028

309848/0561 -108-

- 108 - 2325H0

from the output of the! Comparator 1008., The capacitor 1.028 remains charged during the delay process and suffers very little charge loss because of the high input impedance of transistor 1026, whereby transistor .1026 so biased "that this delivers the calibration voltage necessary for the adjustment the output voltage of the operational amplifier 968 to the output voltage of the position sensor circuit at the switching point is required ο

This recalibration of the delay circuit before each deceleration process of the elevator car enables the use of an inexpensive square root step 964 _S, since the constantly renewed recalibration eliminates the signs of wear and tear of simpler square root steps. These simple square root steps are very stable during short time intervals, as they are required here to decelerate an elevator. The calibration is also carried out in the lower range of the output voltage, which is the least accurate range for a square root analog computer »

Thanks to the repeated verification, the Accuracy of the analog-to-digital converter 960 can be selected to be lower «. With the larger signal values, the fault of the converter becomes 960 roughly halved by extracting the square root of its output signal and at low levels The recalibration compensates for any fluctuations in the signal values

- 109. 30984'8 / 05 & 1.

73251

_Τ 09-

of the converter ,, A special recalibration of the delay circuit 546 for maintenance is unnecessary, since it is carried out automatically during every trip of the elevator takes place »

Figure 18

Elevator safety regulations require that a additional independent device for braking the elevator car near the end floors can be provided got to. This delay device monitors the control and in the event of a fault it supplies an auxiliary program Control of the travel switch that brings the elevator to a stop - The known devices of this type are generally used two rows of ICurface actuated switches, one of which one line on the selector slide and the 'other on' the elevator car sits »when the elevator car. is one end floor approaches, a curved surface fixed in the shaft opens the Switches on the cabin one after the other <, the selector slide moves in the normal way, the corresponding ones close there. Contacts «If the voter sled gets stuck, so a monitoring circuit initiates the braking of the elevator. An auxiliary braking program is run by one on top attached to the elevator car, operated by a curved surface Distance sensor initiated »This familiar arrangement is effective, but requires very precise adjustment of the Curved surface, which the switches and distance sensors on the Cabin activated »The deflection of the feeler arms is very little

'30984-8 / 0561 - no _

- no - 2325 UO

in comparison with the very long Spreading of the lift _s so that in some elevator systems high speed zwei'JCurven-.flächen and two sensors are required "

18 schematically shows the circuit diagram of a delay stage 558 for the end floors, which for the corresponding step in Fig »12 can be used and the known series of

Switches and distance sensors avoids “The delay circuit 548 in Fig. ₀ 18 works together with notched strips, which are installed in the elevator shaft near the two end stops. Such notched strips are shown at 62 in FIG. 1 and on a larger scale at 1040 in FIG. 19. The strip 1040 has a series of quenchers or notches 1042 ₅ are distributed so that 'a mounted on the elevator car photoelectric or magnetic sensor to determine their presence and can produce pulses ₅ supplied to the delay circuit 558th The recesses 1042 are distributed in such a way that when the elevator is decelerated with a constant degree of deceleration, the time elapsing from one recess to the other remains constant. If the elevator is not delayed or deviates the degree of deceleration by more than a certain threshold from the given delay from _s so is the time between the detection of two successive * folgender.Ausnehmungen shorter than normal and a Überwaclnmgsstufe in the delay circuit 558 detects this excessive speed and ldits the deceleration of the elevator

-f

cabin a.

--11T-

30 98 Λ S / ÖS St

4 yrs IO £. \ J i

The same bar 1040, which is used to determine an excessive speed, is also used to generate the auxiliary program for this case _o The difference between the frequency with which the pulses are generated when the sensor passes the bar 1040, and a predetermined one Frequency, which corresponds to the maximum permissible deceleration, results in the speed deviation "The distribution of the recesses in the bar determines the prescribed degree of deceleration, each deviation from this automatically disturbs the equilibrium, and a deviation signal causes a 'speed deviation signal always running in the same direction is converted "This deviation signal can be used directly to supply the motorized drive switch" Instead, the speed deviation can be superimposed on the actual speed of the elevator "measured by a normal speedometer, for example, to create a speed program that can be used directly to replace the normal speed program,

It is true that the delay bar 1040 is preferably in the shaft and the transducer attached to the elevator car, but it T7S, 3? e also possible to proceed in reverse "

The sensor 1044 for determining the recesses 1042 is designed, for example, as a photoelectric device and comprises a light source 1046 and one opposite it

- 1/12 309 8-4 8/0561

2325U0

Light receiver "1048, which can be covered by the dark parts of the strip 1 between the recesses 1042nd The light source 1046 is Z ₀ as a light emitting diode""is and the light receiver 1048 ζ" an incandescent lamp, a neon lamp or the like Β a phototransistor. ,, a photodiode , a photoresistor or the like. The transducer 1Ο44 can also be magnetic or "inductive, which can be done with a single or with two windings"

The light receiver 1Ο48 generates pulses when the discontinuities of the bar 1040 are shifted relative to it «These pulses appear at the input terminal PLSDP of the delay circuit 558«. At the output of the same a series of pulses of constant width appear, the spacing of which corresponds to the pulses received by the amplifier 1050. These impulses are used to operate a switch IO53, one side of which is connected to a positive DC voltage source 1Ο55 via a resistor 1Ο57 and the other side to earth. The switch IO53 is, for example, a transistor or the like. A low-pass amplifier 1054 is connected to the connection point 1051 between the switch 1053 and the resistor 1057. This is Z ₉ as an operational amplifier whose inverting input is performed via resistor 1059 at the joint 1051 "is the non-inverting input via a potentiometer 1063 Roit a positive DC voltage source" In the Eückkopplungsschleife

309848/0551 " ¹¹³ "

325K0

of the operational amplifier is the parallel connection of one Capacitor 1065 and a resistor 1O67 "

If the monostable multivibrator 1052 does not emit a pulse, switch 1053 is open and the positive voltage source 1055 is connected to the reversing input of the low-pass filter 1054. If a pulse PLSDP is received, switch 1053 closes and connects the reversing input of the low-pass filter 1054 with earth » \ Jenn the deceleration of the elevator is normal _p the: low-pass amplifier delivers a constant output DC voltage, which is corrected to zero, since there is no speed error given pulse frequency, whereby the relative time span during which the switch IO53 is grounded is increased. This makes the effective input voltage less positive and the output voltage of the low-pass filter 1054 more positive

The output of the low-pass filter 1054 goes to the non-inverting input of an operational amplifier 1O560 serving as a comparator. At the inverting input of the same, a direct voltage Y _{1 is} fed which is derived from a voltage source 1058 via a voltage divider 1060 »The magnitude of the direct voltage V ₁ is equal to that which is emitted by the low-pass when the elevator car with a predetermined maximum

- 114 _ '·' 30 9141/0511

-.114 -

speed the end floor approaches "If the output voltage of the low-pass filter 1054 is below this reference voltage V ₁ j the output voltage of the operational amplifier 1056 is negative5 d« h «a logical zero«, in the other case it is positive, doh, a logical one »This output voltage becomes in the NOT gate 1049 vice versa, so that a low or true signal at the output terminal SPSXf returns "This terminal is' connected to the driver stage 552 in FIG _o 12 a true signal SPSW shows an excessive speed to near a Endstockwerk.

The output of the low-pass filter 1054 is also connected to the non-inverting input of a second operational amplifier 1062, which also serves as a comparator "The inverting input is again above a voltage divider 1066 to a DC voltage 1Q6O" so that the input voltage of the! Comparator has the value V ₂ ' . The voltage V "is higher than the voltage V ₁ and its size is chosen so that it represents the elevator speed _f at which an emergency stop of the elevator car should be made. In the event of an emergency stop, the elevator should only be able to start moving again, when a maintenance service has the opportunity to check the installation «If the comparator 1062 has therefore been switched to a positive output voltage ₈ because the output voltage of the low-pass filter 1054 reaches the reference voltage of the comparator 1062, a storage stage 1O7O can be triggered to maintain the emergency stop signal, until it is reset by trained personnel.

390848 / ÖSI1 '- 115 -

The storage stage is _/ Z ₀ B ₀ from the flip-flop 1070 with cross-coupled NAND gates TO72 and 1074, a NOT gate 1076 and a normally open reset button 1O82o The output of the! Comparators 1062 passes through a NOT gate 1076 to the input of the NAND gate 1072 The MAND element 1072 is connected to an output IcI emme TOVSP, which leads to an emergency stop device, and an input of the NAND element 1074 is connected to earth 1080 via the push button 1082.

Under normal conditions, the flip-flop 1070 is open because a logic one occurs at the input of the NAND gate 1074 because the push button 1082 is open and the output of the. ! Comparators 1062 outputs a logical one to the input of the NAND element 1072 via the negation element IO760. The output • terminal TOVSP is thus at the logical value zero Έβπα. an overspeed is detected by the comparator 1062 so that its output 'is positive or hcSi is _f the flip-flop 1070 is toggled and delivers a true (or high) signal to the output terminal TOVSP ₀ The flip-flop remains in this state until the push button 1082 of Hand operated "to reset the flip-flop 1070"

Figure 2OA and 2OB * are graphs of voltage versus time for explaining the operation of the circuit 558 at a normal approach to a Enästockwerk or "when approaching at high speed" in FIG 20A ₀

309848 / 0BS1 '" ^l16 "

2325U0

The square wave pulse 1084, which represents the complement of the output voltage of the monostable multivibrator 1052, is generated by it with a constant frequency and delivers after the passage through the low-pass filter 1054 a DC voltage 1086, the magnitude of which is essentially zero volts. The reference voltages V ₁ and V ₂ , which are applied to the comparators 1056 and 1062, are shown, but with normal 'delay' the voltage 1086 remains below these reference values. ■

In contrast, FIG. 20B shows the situation when the speed is exceeded near the end floor. The pulses PLSDP are generated here with a frequency greater than that

SOCBT

predetermined constant pulse frequency or ^ unimmune, so that a square-wave voltage 1084 'results at the input of the low-pass filter, the zero value of which increases successively. This results in a lower mean value of the input voltage, so that the output voltage of the low-pass amplifier I.O54 increases along the curve 1086 '. If the speed is exceeded, is compared in 1040 (Fig. 19) with the built-speed profile 1043 of the delay block is large enough, the output voltage that is the speed deviation ^V _SE "reaches the low pass filter 1054, the reference voltage V _1, whereby the signal SPSW occurs and the driver stage 552 supplied will. The grows

- 117 3098A8 / 0551

5140

Exceeding the speed even further, so that the speed _{deviation V gE reaches} the reference voltage V ₂ , then the emergency signal TOVSP also becomes one and initiates an emergency stop of the elevator car _{or the like}

An important feature of the delay circuit 558 is the fact that the same bar 104O ₁ , the. is used to monitor and determine if the speed limit is exceeded near the end floor, also to generate the auxiliary driving program in the event that the "speed limit determination is used"

thereof independently developed an auxiliary program signal TSAN in which the Geschwindiglceitsabweichung V _gE is added to a voltage ₅ which the actual speed is of the elevator "This Sann the off transition voltage of a tachometer be ,, referred to herein with ^v rp _ACH" Since the If the speed deviation is equal to the target speed and if the actual speed is reduced, the auxiliary signal can. for the speed setpoint can be formed by adding the voltage V _gE to the voltage »

This addition is shown in FIG. 18 by means of an adding amplifier 1090., Here it consists of an operational amplifier "Whose non-inverting input via resistor 1092

. - 118 -

2 3 25 U O

is grounded and whose inverting input is connected to the voltages V _s "and V _T " _e "via resistors" 1094 and 1096 "The voltage V _TACi . is supplied by a rectifier 1098, which converts the alternating voltage generated by the tachometer into a direct voltage" which can be added to the direct voltage Vg ". The direct voltage ^V _TÄCH is negative, which is taken from the negative pole of the rectifier 1098 (for example, a bridge circuit). The speed _{deviation V gE} can never exceed the actual speed, so that the output signal TSAN is always positive »

Figure 21

FIG. 21 is the schematic representation of an exemplary embodiment for the driver stage 552 in FIG of the temporary solution when switching between two program signals according to the aforementioned British patent Ί 293 097 apart from that, since this is not absolutely necessary * there, where an ipuck-free transition is most noticeable, namely when approaching a stop slowly, the The elevator system described here achieves the adaptation of the two signals before and after the switchover in a different way.

The importance of the various input signals of the driver stage 552 is repeated shortly "That, signal NL16 from reversible Zäkler544 equals Muil ₉ d 'Ii. true if the elevator car

309848/0681. - π 9 -

= 119 = 232514Ö

30 cm away from a stop is »The LAZO signal from a converter in the shaft is true, if the elevator is 20 cm away from a stop. The signal MI ¥ A from the lamp generator 542 goes to NuIl ₅ . when the elevator reaches its maximum deceleration value. The START signal from the Logiis 4O _5, which is identical to ACCX, goes to one / when the elevator is "to be accelerated, and remains true until a stop command is received." The TOP and BTTM signals come from switches in the shaft that are attached in this way are that these signals go to zero when the .Aufzug 45 cm from the upper and lower Endstockwerk is removed. the signal from the SPSW Endstockwerks-Veraögerungs · = circle 558 goes to zero when a speeding is estgestellt ^p near a Endstockwerk. the Signal DCL from limit switches on the building doors is equal to one when all doors are closed »

The driver stage 5 $ B- derives the output signals DL2, TRSW, DSSW, SI and TSD from these input signals. The signal DL2 is zero when the elevator is running and one when the elevator is in the landing zone, ie less than 20 cm from the stop. The signals Tllf, DSlf and HIS are used to actuate the analog switches 548, 550 or 556 in FIG. 12 at the correct times in order to switch over the individual phases of a barrel. The signal TSD is equal to NuIl ₅ when an overspeed occurs nmke a terminal floor. It is on the analog switch 560 in Fig. 12 and on

- 120 -

309848 / 0B61

_ _ia0 _ 2325H0

various previously described positions in the floor selector given.

The driver stage 552 consists of the. NAND links 1102 - 1116, the negation elements 1118 - 1128 and the flip-flops 1130, 1132 and 1134. The latter again preferably consist of two cross-connected NAND elements 1136 - 1146. These components are in the manner evident from the drawing and the following functional description in one another and with connected to the input and output terminals.

The elevator is on the lower final floor with closed Doors in rest position * The signals NET!?, LAZO, STAET, and BTTM are then zero and the signals MINA, TOP, SPSW and DCL equals one. At the output of the NAND gate 1138 of the Flip-flops 1130 then occur a zero, which is reversed by the negation element 1124 to a signal DL2 of the value one. The NAND gate 1146 of the flip-flop 1134 also has the output signal Zero and the NAND gate 1140 of flip-flop 1132 has the output signal one, so that a signal TSD from Value one results. The combination of these output values of the flip-flops 11.30, 1132 and 1134 in the NAND gates 1112, 1114 and 1116 results in only NAND gate 1116 having two high Has input signals. Thus, the signals TRSW and DSSW are equal to one and signal IiIS is equal to zero, i.e. true. The speed program is thus under control of the in the shaft

- 121 309848/0661

located converter as it is required when the elevator is on one floor.

When an acceleration command occurs, the ACCX signal from the floor selector 34 goes down and the logic 540 generates a start signal of the value one »This switches NAND gate 1108 to the output signal zero and laps flip-flop 1130 so that the signal DL2 has the value zero assumes what corresponds to the move command EUN »Furthermore, the NAND element 1110 is opened and flip-flop 1134 flips so that a one occurs at the output of the HAND element 1146. The inputs of the NAND element 1112 are now all at one, so that the signal TRSW becomes zero, while the NAND element 1116 now has a low input signal because of the negation element 1124, so that the signal HIS assumes the value one. By changing the signals TESW and HIS, the analogsets 548 and 556 are operated in opposite directions, whereby the speed program of. the inductor control 554 is switched to the ramp generator 542 o.

The elevator thus departs from the lowest floor and the signals NL16, LAZO and BTTM assume the value one. If the floor selector now issues a stop command, the ACCX signal becomes one and the START signal becomes _zero. The NAND gates 1108 and 1110 take a high output voltage and enable flip-flops 1130 and 1134, signal TRSW remains zero as the initial deceleration of the elevator from maximum speed to maximum deceleration under the control of the

09848 / 0S51

- 122

-m-: '2325H0

time-dependent campaign generator remains.

When the maximum delay is reached, the MINA signal supplied by the ramp generator goes down and flips that Flip-flop 1134 so that NAND gate 1146 has a low output voltage has, the NAND gate 1112 upwards and NAND gate 1114 drives down. This will make the analog switches 548 and 550 in Fig. 12 are actuated to enter the speed program from the time-dependent ramp generator 542 to the path-dependent delay circuit 546.

When the elevator reaches a point 32 cm from its stop, signal NL16 goes down and if the cabin is still 20 cm from the. Stop is away, signal LAZO is also zero, so that NAND gate 1102 a Emits zero and flip-flop 1130 toggles to a zero at the output of the NAND element 1138 to be delivered. This turns signal DL2 to One, which corresponds to the hold signal, and the NAND gates 1114 and 1116 provide high and low outputs, respectively. The corresponding output signals DSSW and HIS operate the Analog switches 550 and 556 such that the signal HTAN supplied by the transducer in the shaft is fed to the adder circuit 562 and the elevator leads to the stop.

If an over speeding is detected near a terminal floor, the delay circuit 558 outputs

- 123 309848/0551

2325H0

the signal SPSW from ₉ the flip-flop 1132 toggles so that a low output signal occurs at the output of the NAND gate 1140 the driving program is switched from the normal control "to the auxiliary signal TSAN, which is supplied by the delay circuit 558.

848/0861

Claims (8)

«PL-feg. 8. Wa 41 Munich, the * '· - ■ W.584-Dr.Hk/rie WESTINGHOUSE ELECTRIC CORPORATION Pittsburgh. Pa. / V.St.A. Claims 1. Programmer for an elevator system to generate a time-dependent speed signal with limited change in acceleration, characterized by a voltage source (582), which is a switchable between two values, the maximum change in acceleration (jerk value) provides a representative square wave signal, a first integrator (592) for the square wave signal to form a Acceleration signal, a second integrator (596) for the acceleration signal to form a speed ssignals and a feedback (59o) from the two integrators to control the switching of the square wave signal depending on the acceleration ^ - and 'dem Speed signals 2, programmer according to claim 1, characterized in that the feedback the square wave signal during predetermined transition phases between sections of constant speed and constant acceleration of the speed _ 2 - ■ 309848/0551 Program to one of its two values and in the sections constant speed and constant Accelerating constantly between these two. Xiert forward and switch ο., 3. Programmer according to claim 1 or 2, characterized in that the two ¥ erte of the RechtecMgnals are represented by currents in opposite directions _o 4. Programmer according to claim 3s> characterized ₀ that in the program sections at constant speed the mean value formed by switching the square-wave signal back and forth is equal to zero ₀ , 5 x programmer according to any one of claims 1 to k _g characterized, in _t that the feedback from an acceleration-dependent, dependent on the first integrator (592) derived Re = coupling loop (642s 6kk) and a geschxtfindigkeits · = derived from the second integrator (596) Feedback loop (6oop 6io) exists o 6. Programmer according to claim 5 »characterized: in ₀ that the acceleration loop and the velocity loop are such intermeshed ,, that the signal in the Beschletmigungsschleif e hi * the signal of the speed loop ° a Ruckwert.begrenzung imposed _o 3 - 7. Programmer according to claim 6, characterized by setpoint generator (6i4, 656) in the acceleration loop and the speed loop and comparators (644, 6I0) to compare the feedback signals with the relevant Setpoints, as well as a connection (653) of the acceleration loop with the speed loop in such a way that the Time until the setpoint of the speed feedback signal is reached is reduced. 8. Programmer according to claim 7 »characterized in that the setpoint generators can be switched to different setpoints are and that the comparators work via logic switching means (664, 666) on a changeover switch (587) that this in the transition phases (il, IV, VI, VIII) between Periods of constant speed and constant acceleration occupies one of its two positions and thereby one supplies the two values of the voltage source (582) to the first integrator (592) to limit the jerk value, and that in the periods of constant velocity (l, V) and constant acceleration (ill, VIl) the switches (587) is switched back and forth at a frequency that exceeds the response time of the elevator « 9. Programmer according to one of claims 6 to 8 "characterized in that that the connection between the acceleration loop and the speed loop is such that ■ formed that a jerk-limited transition from one phase constant acceleration to a phase of constant 309848/0551 speed without overshooting the speed ο 1Oo programmer according to claim 8 or ^ _9, characterized in that the acceleration signal in the acceleration 'phase of the elevator has one polarity and in the deceleration phase the opposite polarity and that a second acceleration comparator (668) in the acceleration loop the deceleration signal with the The acceleration value is compared and the comparison result is fed to the logic (66k " 666) ο program generator according to one of claims 7 to 1o ₀ thereby characterized ρ that the speed program is initiated by a ■ change (736) of the speed = setpoint (SPSi) from one variable to another variable _o 12o programmer according to claim 11, characterized _s that the deceleration phase of the speed program by a change (8oo) of the velocity command value is passed to its original size _o 13o programmer according to one of claims 7 to 12 ₀ characterized = denotes _B that the speed program has a phase (j) for the speed NuIl ₁ , a transition phase (ll) regulated to the jerk value and a phase (ill) of constant acceleration Transition phase initiated by a jump (736) of the speed = setpoint (SPS1) and by the acceleration = comparator (642.) 309848/0661 '- 5 - 2325U0 German is ended when the acceleration signal exceeds the acceleration setpoint achieved. 1 k, programmer according to claim 13, characterized in that the speed program has a second transition phase (iv) regulated to the jerk value and a phase (v) of constant speed and that the influence of the speed signal by the acceleration signal (comparator 600) has a more rapid increase of the speed signal brings about the setpoint speed as without this influencing, so that the second transition phase connects the phases of constant acceleration and constant speed without overshoot. Program generator according to claim ik _s characterized by a third transition phase (vi) regulated to the jerk value and a phase of constant deceleration (VIl), the third transition phase being initiated and then ended by a jump (800) in the speed setpoint (SPSi) when the acceleration signal reaches the negative value of the target acceleration «, 16. Programmer according to claim 15 ν, characterized in that the speed program has a regulated on the jerk value fourth transition phase (viii) to a phase (l) with the speed zero, in which the speed ssignal is influenced by the acceleration signal in such a way that the speed Setpoint is reached earlier, 3098 487 05 b 1 - ^s ~ ". 2325H0 ■ ■. . . .ill » so that the phases of constant deceleration and vanishing speed are smoothly connected with each other » 09848 / 0SS 1 Empty soap