DE2324279B2 - Method and circuit arrangement for the exchange of information in an integrated PCM telecommunications network - Google Patents

Description

The invention relates to a method and a circuit arrangement for exchanging information in an integrated PCM telecommunications network. The development of digital controls and the possibility of using With PCM technology, the implementation of transmission systems also has to represent voice signals in digital form in which both the information to be transmitted (e.g. language) and that for the control The signals required for transmission are passed on in digital form.

A well-known transmission system (DE-OS

21 21 660) contains several incoming and several outgoing PCM lines and devices, that buffer the incoming information and transfer it to the actual one at the right time Bring the transmission path or distribute it to the outgoing lines. Which are connected to such a system Requirement of speed transparency for bit streams of a certain transmission speed requires the insertion of additional bits ("stuffing") into the bit stream to be transmitted. The information will therefore transmitted asynchronously.

In the course of the advancing development of PCM switching technology and the resulting Conversion of exchanges to this technology, it is desirable to already have existing ones PCM transmission links to be included in a future integrated telecommunications network in order to achieve the To be able to continue using facilities of the transmission path (e.g. amplifier).

However, the switching technology makes different demands than those which the development of the Underlying transmission system. In particular, there is now a synchronous transmission of information required. To an independent PCM transmission system of the type mentioned above in an integrated Telecommunication network / u can use that for the same number of channels and the same information transmission speed is designed, a considerable adjustment effort is required because the transmission system by inserting additional bits an overall higher transmission speed used than is necessary for operation between exchanges of an integrated network. One of The bit stream coming from the exchange, which is to use the transmission link of the independent transmission system, must first enter the facilities (e.g. multiplexer, clock adjustments) of the system are processed and at the end of the transmission path the corresponding devices are re-entered run through in reverse order before it is switched through in the following exchange can be.

In a likewise known PCM time division multiplex telecommunications network (DE-AS 22 21 217), two exchanges which operate at different operating frequencies are connected to one another via a transmission link. Each exchange has a buffer memory on the receiving side. The bits transmitted from the PCM exchange VSt 1 to the PCM exchange KSi 2 are written into the buffer memory P2 with the bit frequency f \ of the exchange VSt 1 and read out from this buffer memory with the bit frequency Fl of the PCM exchange VStI, while the bits transmitted from the PCM exchange VSi 2 to the PCM exchange VS / 1 are written with the bit frequency f2 into the buffer memory P1 and read out from it with the bit frequency / 1. The writing in a buffer memory is done with the so-called external information bit rate on the PCM receive time division multiplex line leading to it, and reading from the buffer memory with the so-called internal information bit rate of the associated PCM time division multiplex exchange. This time division multiplex telecommunications network is therefore not transparent to bit streams of a certain transmission speed. Should existing transmission links in this telecommunications network

are used, a high level of adaptation is also required.

The invention is based on the problem of using existing PCM transmission links in an integrated telecommunications network with little adjustment effort. These The object is achieved according to the invention by the method characterized in claim 1.

Jas provides an advantageous further development of the invention in the method characterized in claim 2 represents, while a circuit arrangement suitable for performing this method is in the claim 3 is marked.

The method according to the invention thus allows the direct, synchronous transmission of information on the existing PCM transmission link; it has another advantage: the transmission path becomes initially operated independently; should at a later time through the extensive expansion of the integrated Network the information lines of the transmission system also in there: integrated telecommunication network included, parts of the facilities of the originally existing transmission system be removed and possibly reused elsewhere, without the inventive Procedure is not possible.

The invention is illustrated below with the aid of a · - in the Drawings illustrated embodiment explained, the numerical data being a 120-channel PCM system is based. It shows

F i g. 1 the block diagram of a transmission link, which is also used between PCM exchanges;

F i g. 2 shows a basic circuit diagram of the additional devices of a PCM exchange;

F i g. 3 an illustration of the processes described.

F i g. 1 shows the transmission link UeS, which is equipped with line terminals LE and repeaters R in a known manner. The device M of the transmission system (multiplexer, demultiplexer, stuffing logic, clock adjustment) handles the stringing together of the incoming information in the connected PCM lines G (or their distribution to the outgoing lines G) and the clock-correct information transmission with the addition of the additional bits already mentioned. The PCM switching centers VST contain devices C which add a number of additional bits to the bit stream to be transmitted or split them off again, and enable the required increase in the transmission rate from 8.192 to 8.448 MBd. The optional switchover to operation between the

'■'

PCM exchanges are symbolically represented by coupled switches A uid ^.

F i g. Figure 2 shows the additional facilities C of the exchanges according to the invention. The processing and switching of the received bit stream takes place in the exchange in a known manner.

In the transmit mode, the clock derivation stage TAS receives the switching clock VT of 8.192 MHz and uses it to generate an 8.448 MHz transmission clock UeT (em speaking the 8.448 MBd of the transmitted bit stream). A channel counter KZ is thus incremented, which runs from 1 to 132 and, by passing on the channel number , causes the reading AL of the information in the corresponding line of a voice memory of the exchange. The increase in the number of channels on the channel counter is proportional to the increase in the transmission speed. If the channel counter KZ switches to certain channel numbers stored in a channel number memory KNS , a comparator VG responds, which causes SAL to block the reading of information from the voice memory.

In reception mode, the arrangement works in a similar way, apart from the necessary synchronization SYN; the transmission clock UeT of 8.448 MBd controls the reading ES of the received bit streams into the voice memory of the exchange via the channel counter KZ. If the line counter LZ shows one of the specified channel numbers (that is, when additional bits arrive), the comparator VG causes the SES to be blocked and possibly initiates other switching operations. The bit streams can then be forwarded again at the transmission speed of the integrated network (8.192 M Bd).

F i g. 3 shows a possible chronological sequence of the arrival of bit streams (line clock LT) and their transmission (transmission clock UeT), the channel numbers 129, 130, 131, 132 being noted in the channel number memory KNS. The bit streams meet with the line clock LTein (Sa). The channel counter KZ reaches the channel number 129, the recording of the bit stream is prevented by the comparator VG (SES). Only when the channel counter is switched to 1 by the line clock L7 "is the bit information of the first channel recorded in the switching memory. This occurs with all channels up to and including channel 128.

Correspondingly, in the sending switching center (3tyd the channels 129 to 132 are empty channels; while it is their turn, no switched information is sent out (SAL).

For this purpose 2 sheets of drawings

Claims (3)

Patent claims: 1. A method for exchanging information in an integrated PCM telecommunications network with PCM transmission links between PCM exchanges, characterized in that the PCM transmission links (UeS) of a PCM transmission system (M, UeS, M) operated at a certain transmission rate, with an unchanged transmission rate if necessary between the PCM communication points CVSi; that in the PCM exchanges a number of additional bits is added to the bit stream to be transmitted at predetermined points, and that these additional bits are split off again when received in the PCM exchanges at these locations, the number of additional bits being determined by the difference between the Transmission speed of the PCM transmission path (UeS) used and the switching cycle of the integrated PCM telecommunications network is determined. 2. The method according to claim 1, characterized in that a transmission rate corresponding to the transmission rate (UeT) is generated in the PCM switching center by devices (C) from the switching cycle (VT) of the integrated telecommunications network, which the reading (transmission mode) or the writing (receiving operation) of the binary information in a voice memory of the PCM switching center controls, with certain, predetermined channel numbers reading or writing is interrupted and additional bits are sent out or split off. 3. Arrangement for performing the method according to claim 2, characterized by a clock derivation stage (TAS) for generating the transmission clock (UeT) from the switching clock (VT), the output of which is connected to the input of a channel counter (KZ) , the number of channels within a frame according to the higher transmission rate is greater than the number of useful channels and the output of which forwards the channel number for the voice storage of the exchange, and through a comparator (VG), the inputs of which are connected to a channel number memory (KNS) that contains the channel numbers from which the readout or Writing is to be interrupted, and the output of the channel counter (KZ) are connected, and whose output signal interrupts the reading out or writing into a voice memory via the voice memory control.