DE2319986C3 - Digital-to-analog converter - Google Patents

Description

35

The invention relates to a digital-to-analog converter for converting digital information signals with several digits with different Place value in an analog information signal with a control logic that does not overlap in time Evaluation signals are generated with a duration assigned to one of the priority values, which is shorter than the duration of the associated digital information signal, a logic circuit that each Evaluation signal conjunctively linked to the associated digital information signal, and one am Output of the logic circuit connected integration circuit.

In a known digital-to-analog converter with the features specified above, the Evaluation signals have a fixed duration, each of which is assigned a value of the digital information signals to be converted. Because the duration of the evaluation signals is invariable, the known digital-to-analog converter can only perform a certain conversion function be achieved. A variable conversion function adapted to the respective circumstances is, however, not possible.

The invention is based on the object of providing a digital analog converter of the type specified at the beginning Type to be designed in such a way that, with a simple structure, different types of implementation functions are possible Will,

According to the invention, this object is achieved in that the control logic for generating the evaluation signals contains a gate network whose linking function to change the individual places ^ Values assigned duration of the evaluation signals by means of control signals applied to the gate network is changeable

In the converter according to the invention, it is possible to change the duration of the evaluation signals so that this can be used to determine how strong the individual points of the digital information signals to be converted go into the analog information signal to be generated. By selecting the respective duration of the Any conversion functions can be set for evaluation signals. For example, a logarithmic dependency between the digital and the analog information signal can be achieved, which is particularly advantageous if the digital-to-analog converter according to the invention is used instead a non-linear potentiometer for the physiologically correct volume or brightness setting in to be used with a television receiver. An advantageous development of the invention consists in that the control signals applied to the gate network are the digital information signals. This training enables the conversion function in Control yourself depending on the digital information to be converted.

Advantageously, it can also be provided that for linking further digital information signals with the evaluation signals emitted by the control logic, further logic circuits and others Integration circuits are connected to the control logic. By means of this configuration, you can simultaneously several digital information signals using the same evaluation signals into analog information signals implemented.

An embodiment of the invention is shown in the drawing. In it shows

F i g. 1 shows a block diagram of the digital-to-analog converter according to the invention and

FIG. 2 is a timing diagram for explaining the operation of the FIG. I shown converter.

The in F i g. 1 shown Dibital-Airsiog converter contains a control unit 10, whose outputs 12.1, 12.2 ... 12.77 with the corresponding inputs 14.1, 14.2 ... 14./J a logic circuit 16 connected are. Further inputs 18.1,18.2 ... 18./J of the logic circuit 16 are connected to outputs of a source 20 of the digital information.

The logic circuit 16 contains AND gates 22.1, 22.2 ... 22.n, each of which has two inputs exhibit. An input of this AND gate 22.1,22.2 ... 22.Π is connected to the corresponding input 14.1, 14.2 ... 14.Π of the logic circuit 16, while the other input with the corresponding input 18.1, 18.2 ... 18.n of the logic circuit 16 is connected. The outputs of the AND gates 22.1, 22.2, ... 22.77 are connected to the inputs of one in the Logic circuit 16 contained OR gate, the output 26 of which is connected to an integration circuit 28. The output 30 of the Integration circuit 28 represents the output for the analog information signal.

The control logic 10 contains a dual counter 32 controlled by a clock generator 11, which is made up of several stages. The outputs of the individual stages are connected to the inputs of a gate network 36, whose outputs are the outputs 12.1,12.2. . 12.77 of the control logic 10.

The Gatterrtetzwefk 36 has an input 38 on a control signal for setting the linkage

function of the gate generator can be created.

The source 20 of the digital information supplies a binary number, with a binary number for each digit Output is provided, which is connected to the respectively assigned input 18.1, 18.2,.,. 18./j the logic circuit 16 connected isL If a position is occupied, the source 20 connects to the corresponding output Information signal in the form of a DC voltage signal with the signal value 1, while unoccupied Place an equal signal with the signal value 0 is created.

The description of the operation of the digital-to-analog converter of FIG. 1 takes place under the Assume that the dual counter 32 has four stages and that the source 20 is a four-digit binary number in the form of four information signals with different values, of which the one at the input 18.1 the logic circuit 16 applied signal has the lowest value. To facilitate the Assignment of the circuit shown in FIG. Signals appearing in FIG. 1 are those in the timing diagram of FIG. 2 signals shown with the reference numerals of the outputs and inputs at which they are in the Circuit of FIG. 1 occur.

The dual counter 32 generates a square-wave signal with a pulse duration T and a at its output 34.1 Duty cycle of 1: 2. Square-wave signals are generated at the outputs 34.2, 343 and 34.4 of the dual counter output whose repetition frequency is halved in each case

The rights clcsigna-Ie issued by the dual counter 32 are fed to the gate network 36, which links them with one another in such a way that at the outputs 12.1 to 12.4 pulses with the duration T, 27 * 4T or. ST appear when the gate network 36 is set by a control signal at the input 38 so that a linear conversion is to be achieved. As shown in FIG. 2, the pulses emitted at the outputs 12.1 to 12.4 are offset from one another in such a way that they immediately follow one another in time without overlapping.

If the source 20 of the digital information now, for example, a digital information signal with the Returns the value 13 in dual-coded form, then it is on Input 18.1 the signal value 1, at input 1JL2 the signal value 0, at input 18.3 the signal value 1 and at Input 18.4 has the signal value 1. This is in the left part of FIG. 2 with the numbers 18.1-18.4 Signals shown.

During the counting cycle of the dual counter 32, the signals present at the inputs of the logic circuit 16 are now linked to one another in the AND gates 22.1 to 22.4. The evaluation signal present at input 14-1 is conjunctively linked in AND gate 22.1 with the digital information signal present at input 18.1, so that a pulse with duration T is emitted at the output of AND gate 22.1 because the one present at input 18.1 Evaluation signal the duration That Then the evaluation signal present at the input 14.2 of the logic circuit 16 is combined in the AND gate 22.2 with the digital information signal present at the input 18.2, and there is no output pulse at the output of this AND gate, since the digital information signal has the signal value 0 The AND gate 223 links the digital information signal at the input 18.3 of the logic circuit 16 with the evaluation signal at the input 143, so that at the output of this AND gate a pulse with the duration 47 * is created

Subsequent linking of the information signal at input 18.4 with the evaluation signal at input 14.4 results in a pulse with a duration of 8 T at the output of AND gate 22.4, which immediately follows the pulse at the output of AND gate 223. The outputs of the AND gates 01/22 to 04/22 are fed to an OR gate 24, * emits at its output a pulse of duration T and a pulse duration 127, so that a total duration of 13 T yields that the reacted digital information with the value 13 corresponds to the signal denoted by 26 in FIG. 2, this relationship can be recognized.

The output 26 of the AND gate 24 signal is applied to the integration circuit 28, in which a Averaging of the applied signal takes place The averaging is used as analog information delivered at the output 30 of the integration circuit 28.

In the simplest case, the integration circuit can consist of a capacitor and a resistor; the charging voltage of the capacitor ate''it then the represents analog information corresponding to the digital information.

As a further example, FIG. 2 shows the implementation of digitized information with the value 7, which is present in dual-coded form with the signal values 1.1 »1 and 0 at the corresponding inputs of the logic circuit 16. As can be seen from FIG. 2, the pulse emitted when converting the value 7 at the output 26 of the logic circuit has the total duration 7 T, which determines the value of the analog signal emitted by the integration circuit.

As already mentioned, a linear conversion function has been assumed in the examples described, in which the duration of the evaluation signals is proportional to the value of the digital information signal to be linked to the evaluation signal. If the digital information is to be converted, for example, into analog information for physiologically correct volume control, then a resolution function must be used which produces an approximately logarithmic dependence between the digital information and the analog information. In the case of the in FIG. 1, this can be achieved simply by applying a corresponding control signal to the input 38 of the gate network 36 so that the logic of the gate network is changed so that the duration of the evaluation signal assigned to the higher-order digits of the digital information is reduced. The more significant digits of the digital information thus contribute to a small extent to Ents'ehi ^- the analog information at .g, so that the duration of the assessment signals yields the desired logarithmic dependence in a corresponding determination.

In the described. Embodiment could, for example, the proportional transfer function be changed so that the evaluation signal emitted at the output 12.4 of the control logic is not the Duration 87 * but only the duration 67 * hai, so that the The highest digit of the digital information contributes less to the generation of the analog information

The control signal fed to the gate network 36 for switching over its linking logic can also be the digital information signal itself, so that it is possible to have the conversion function in dependence

set from the digital information itself.

In FIG. 1 it is also indicated how the digital-to-analog converter described here can be expanded in a simple manner for the simultaneous conversion of a plurality of digital information. For this purpose, other similarly structured logic circuits 16 'can be connected to the outputs of the control logic, in which further digitate information signals from sources 20' can be linked with the evaluation signals from control logic 16, which are then sent to outputs 30 'from integration circuits "Ά 'appear as analog information signals

For this purpose 2 sheets of drawings

Claims (3)

Patent claims: 1. Digital-to-analog converter for converting digital information signals with several digits with different value in an analog information signal, with a control logic that is timed non-overlapping evaluation signals with one assigned to one of the priority values Generated duration that is less than the duration of the associated digital information signal, one Combination circuit, which each evaluation signal with the associated digital information signal conjunctively linked, and an integration circuit connected to the output of the logic circuit, characterized in that the control logic (10) for generating the evaluation signals contains a gate network (36), its linking function for changing the duration of the individual priority values Evaluation signals is variable by means of control signals applied to the gate network. 2. Digital-to-analog converter according to claim i, characterized in that the to the Gatternetzweik (36) applied control signals are the digital information signals. 3. Digital-to-analog converter according to claim 1 or 2, characterized in that .daß for linking further digital information signals with the evaluation signals emitted by the control logic (10) further logic circuits (16 ') and further integration circuits (28 ') are connected to the control logic (10).