DE2319986B2 - Digital-to-analog converter - Google Patents

Description

35

The invention relates to a digital-to-analog converter for converting digital information signals with several digits with different Place value, in an analog information signal, \ with a control logic that does not overlap in time Evaluation signals are generated with a duration assigned to one of the priority values, which is shorter than the duration of the associated digital information signal, a logic circuit that each Evaluation signal conjunctively linked to the associated digital information signal, and one am Output of the logic circuit connected integration circuit.

In a known digital-to-analog converter with the features specified above, the Evaluation signals have a fixed duration, each with a value of the digital information signals to be converted assigned. Since the duration of the evaluation signals cannot be changed, the known « Digital-to-analog converter only a certain conversion function can be achieved. One to respective A variable implementation function that is adapted to the circumstances is, however, not possible.

The invention is based on the object of a £> o Design digital-to-analog converter of the type specified in such a way that with a simple structure various implementation functions are made possible.

According to the invention, this object is achieved in that the control logic for generating the evaluation signals contains a gate network whose linking function is used to change the individual values associated duration of the evaluation signals by means of control signals applied to the gate network is changeable.

In the converter according to the invention, it is possible to change the duration of the evaluation signals so that it can thus be determined how strong the individual digits of the digital information signals to be implemented are go into the analog information signal to be generated. By selecting the respective duration of the Any conversion functions can be set for evaluation signals. For example, a logarithmic dependency between the digital and the analog information signal can be achieved, which is particularly advantageous if the digital-to-analog converter according to the invention is used instead a non-linear potentiometer for the physiologically correct volume or brightness setting in to be used with a television receiver. An advantageous development of the invention consists in that the control signals applied to the gate network are the digital information signals. This hamlet formation enables the conversion function depending on the digital information to be converted to control yourself.

Advantageously, it can also be provided that for linking further digital information signals with the evaluation signals emitted by the control logic further logic circuits and others Integration circuits are connected to the control logic. By means of this configuration, you can simultaneously multiple digital information signals into analog information signals using the same evaluation signals implemented.

An embodiment of the invention is shown in the drawing. In it shows

1 shows a block diagram of the digital-to-analog converter according to the invention and

F i g. FIG. 2 is a timing diagram to explain the operation of the FIG. 1 shown converter.

The digital-to-analog converter shown in Fig. 1 contains a control logic 10, the outputs 12.1, 12.2 ... 12.n with the corresponding inputs 14.i, 14.2 ... 14.n a logic circuit 16 connected are. Further inputs 18.1, 18.2 ... 18.Π of the logic circuit 16 are connected to outputs of a source 20 of the digital information.

The logic circuit 16 contains AND gates 22.1, 22.2 ... 22.n, each of which has two inputs. One input of these AND gates 22.1, 22.2 ... 22.Π is connected to the corresponding input 14.1, 14.2 ... 14.Π of the logic circuit 16, while the other input is connected to the corresponding input 18.1, 18.2 ... 18 ./? the logic circuit 16 is connected. The outputs of the AND gates 22.1, 22.2, ... 22./? are connected to the inputs of an OR gate contained in the logic circuit 16, the output 26 of which is connected to an integration circuit 28. The output 30 of the integration circuit 28 represents the output for the analog information signal.

In the control logic 10 there is a clock generator 11 Contained controlled dual counter 32, which is constructed from several stages. The outputs of the individual stages are connected to the inputs of a gate network 36, the outputs of which the outputs 12.1, 12.2 ... 12.n the control logic 10 form.

The gate network 36 has an input 38 to which a control signal for setting the linkage

function of the gate network can be created.

The source 20 of the digital information provides one Dual number, with an output being provided for each digit of this dual number, which is associated with the respectively assigned Input 18.1, 18.2, ... 18.n of the logic circuit 16 is connected. When a position is occupied, the source 20 puts on the corresponding output Information signal in the form of a DC voltage signal with the signal value 1, while unoccupied Place a DC voltage signal with the signal value 0 is applied.

The description of the operation of the digital-to-analog converter of FIG. 1 takes place on the assumption that the dual counter 32 has four stages and that the source 20 emits a four-digit binary number in the form of four information signals with different values, of which the one at the input 18.1 the logic circuit 16 applied signal has the lowest value. To facilitate the assignment of the in the circuit of Fi ₀ '. 1, the signals shown in the pulse diagram of FIG. 2 are identified by the reference numbers of the outputs and inputs at which they are used in the circuit of FIG. 1 occur.

The dual counter 32 generates a square-wave signal with a pulse duration Γ and einf m at its output 34.1 Duty cycle of 1: 2. Square-wave signals are generated at outputs 34.2, 34.3 and 34.4 of the dual counter output whose repetition frequency is halved in each case.

The square-wave signals emitted by the dual counter 32- Ji) Ie are fed to the gate network 36, which links them to one another in such a way that at the outputs 12.1 to 12.4 pulses with the duration T 27 * 4T or 87 " appear when the gate network 36 is set by a control signal at the input 38 so that a linear implementation is to be achieved. As shown in FIG. 2 are those at outputs 12.1 to 12.4 given impulses are offset against each other in such a way that they are immediately timed without overlapping connect to each other.

If the source 20 of the digital information now, for example, a digital information signal with the If the value 13 outputs in dual-coded form, then the signal value I is at the input 18.1 and the signal value I is at the input 18.2 Signal value 0, signal value 1 at input 18.3 and signal value 1 at input 18.4. This is in the left part of Figure 2 with those labeled 18.1-18.4 Signals shown.

During the counting cycle of the dual counter 32, the signals present at the inputs of the logic circuit 16 are now linked to one another in the AND gates 22.1 to 22.4. The evaluation signal present at input 14-1 is conjunctively linked in AND gate 22.1 with the digital information signal present at input 18.1, so that a pulse with duration T is emitted at the output of AND gate 22.1 because the one present at input 18.1 Evaluation signal the duration That. Then the evaluation signal present at input 14.2 of logic circuit 16 is combined in AND gate 22.2 with the digital information signal present at e> o input 18.2, and there is no output pulse at the output of this AND gate, since the digital information signal has the signal value 0. The AND gate 22.3 links the digital information signal at the input 18.3 of the logic circuit 16 with the evaluation signal at the input 14.3, so that a pulse with a duration of 4 7 * is produced at the output of this AND gate. The subsequent combination of the information signal at input 18.4 with the evaluation signal at input 14.4 results in a pulse with a duration of 87 at the output of AND gate 22.4; which immediately follows the pulse at the output of the AND gate 22.3. The output signals of the AND gates 22.1 to 22.4 are fed to an OR gate 24, which emits a pulse of duration Γ and a pulse of duration 12Γ at its output, so that a total duration of 137 * results, that of the digital information to be converted corresponds to the value 13. The signal denoted by 26 in FIG. 2 reveals this relationship.

The output 26 of the And-Gaüers 24 signal is applied to the integration circuit 28, in which one Averaging of the applied signal takes place. The calculated mean value is used as analog information delivered at the output 30 of the integration circuit 28.

In the simplest case, the integration circuit can consist of a capacitor and a resistor; the charging voltage of the capacitor then represents the analogue corresponding to the digital information Information.

As a further example, the implementation of digital information with the value 7 is shown in FIG. in dual-coded form with the signal values 1,1,1 and 0 at the corresponding inputs of the logic circuit 16 is present. As can be seen from FIG. 2, the has the value 7 at the output when it is implemented 26 of the logic circuit emitted pulse the total duration 77 "which is the value of the integration circuit output analog signal determined.

As already mentioned, a linear conversion function is assumed in the examples described been, in which the duration of the evaluation signals each the significance of the with the evaluation signal to be linked digital information signal is proportional. For example, if the digital information is to be converted into analog information for the physiologically correct volume control, then must a conversion function can be used that has an approximately logarithmic dependence between the digital information and the analog information generated. In the circuit shown in Fig. 1 can this can be achieved simply by applying a corresponding control signal to the Input 38 of the gate network 36, the logic of the gate network is changed so that the The duration of the evaluation signal assigned to the more significant digits of the digital information is reduced will. The higher-value parts of the digital information thus contribute to a lesser extent Origin of the analog information, so that with a corresponding definition of the duration of the Evaluation signals result in the desired logarithmic dependence.

In the exemplary embodiment described, the proportional transfer function could, for example, thereby be changed so that the evaluation signal emitted at the output 12.4 of the control logic is not the Duration 87 * but only has duration 67 *, so that the most significant digit of the digital information is less contributes to the generation of the analog information.

The control signal fed to the gate network 36 for switching over its combination logic can also be the digital information signal itself, so that it is possible to have the conversion function in dependence

of the digital information itself.

In Fig. 1 it is also indicated how the digital-to-analog converter described here in a simple manner Way can be expanded to the simultaneous implementation of multiple digital information. To this For this purpose, further similarly structured logic circuits 16 'can be connected to the outputs of the control logic. are connected, in which further digital information signals from sources 20 'with the evaluation signals can be linked from the control logic 16, which then appear at outputs 30 'of integration circuits 28' as analog information signals

For this purpose 2 sheets of drawings

Claims (3)

Patent claims: 1. Digital-to-analog converter for converting digital information signals with several digits with different value in an analog information signal, with a control logic that is timed non-overlapping evaluation signals with one assigned to one of the priority values Generated duration that is less than the duration of the associated digital information signal, a ι ο Combination circuit, which each evaluation signal with the associated digital information signal conjunctively linked, and an integration circuit connected to the output of the logic circuit, characterized in that the control logic (10) for generating the evaluation signals contains a gate network (36), its linking function for changing the duration of the individual priority values Evaluation signals is variable by means of control signals applied to the gate network. 2. Digital-to-analog converter according to claim 1, characterized in that the to the gate network (36) applied control signals are the digital information signals. 3. digital-to-analog converter according to claim 1 or 2, characterized in that for linking further digital information signals with the evaluation signals emitted by the control logic (10) further logic circuits (16 ') and further integration circuits (28 ') are connected to the control logic (10).